Analog Devices AD7713EB, AD7713SQ, AD7713AR, AD7713AQ, AD7713AN Datasheet
AD7713
AIN2(+)
AIN2(–)
AIN3
STANDBY
CLOCK
GENERATION
SERIAL INTERFACE
CONTROL
REGISTER
OUTPUT
REGISTER
CHARGING BALANCING A/D
CONVERTER
AUTO-ZEROED
∑ − ∆
MODULATOR
DIGITAL
FILTER
AGND DGND MODE SDATA SCLK A0
MCLK
OUT
MCLK
IN
AIN1(+)
AIN1(–)
REF
IN(–)
REF
IN(+)
AV
DD
DV
DD
AV
DD
1µA
A = 1 – 128
AV
DD
200µA
V
BIAS
SYNC
DRDYTFSRFS
RTD2
PGA
200µA
RTD1
INPUT
SCALING
M
U
X
LC2MOS
a
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes
60.0015% Nonlinearity
Three-Channel Programmable Gain Front End
Gains from 1 to 128
Two Differential Inputs
One Single Ended High Voltage Input
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Single Supply Operation
Low Power (3.5 mW typ) with Power-Down Mode
(150 mW typ)
APPLICATIONS
Loop Powered (Smart) Transmitters
RTD Transducers
Process Control
Portable Industrial Instruments
Loop-Powered Signal Conditioning ADC
AD7713*
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7713 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer or high level signals (4 × V
REF
) and
outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes
performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator.
The modulator output is processed by an on-chip digital filter.
The first notch of this digital filter can be programmed via the
on-chip control register allowing adjustment of the filter cutoff
and settling time.
The part features two differential analog inputs and one singleended high level analog input as well as a differential reference
input. It can be operated from a single supply (AV
and DV
DD
at +5 V). The part provides two current sources which can be
used to provide excitation in three-wire and four-wire RTD configurations. The AD7713 thus performs all signal conditioning
and conversion for a single, dual or three-channel system.
The AD7713 is ideal for use in smart, microcontroller-based
systems. Gain settings, signal polarity and RTD current control
can be configured in software using the bidirectional serial port.
The AD7713 contains self-calibration, system calibration and
background calibration options and also allows the user to read
and to write the on-chip calibration registers.
*Protected by U.S. Patent No. 5,134,401.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DD
CMOS construction ensures low power dissipation and a hardware programmable power-down mode reduces the standby
power consumption to only 150 µW typical. The part is avail-
able in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line
package (DIP) as well as a 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
1. The AD7713 consumes less than 1 mA in total supply current, making it ideal for use in loop-powered systems.
2. The two programmable gain channels allow the AD7713 to
accept input signals directly from a transducer removing a
considerable amount of signal conditioning. To maximize the
flexibility of the part, the high level analog input accepts
4 × V
signals. On-chip current sources provide excitation
REF
for three-wire and four-wire RTD configurations.
3. No Missing Codes ensures true, usable, 24-bit dynamic
range coupled with excellent ±0.0015% accuracy. The effects
of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
4. The AD7713 is ideal for microcontroller or DSP processor
applications with an on-chip control register which allows
control over filter cutoff, input gain, signal polarity and calibration modes. The AD7713 allows the user to read and
write the on-chip calibration registers.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD7713–SPECIFICATIONS
MCLK IN = 2 MHz unless otherwise noted. All specifications T
(AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; REF IN(+) = +2.5 V; REF IN(–) = AGND;
to T
MIN
unless otherwise noted.)
MAX
Parameter A, S Versions1Units Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 12 Hz
22 Bits min For Filter Notch = 20 Hz
18 Bits min For Filter Notch = 50 Hz
15 Bits min For Filter Notch = 100 Hz
12 Bits min For Filter Notch = 200 Hz
Output Noise See Tables I & II Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity ± 0.0015 % of FSR max Filter Notches ≤ 12 Hz; Typically ± 0.0003%
Positive Full-Scale Error
Full-Scale Drift
Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
Bipolar Zero Drift
2, 3
5
2
5
2
5
See Note 4
1 µV/°C typ For Gains of 1, 2
0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
See Note 4
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
See Note 4
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Gain Drift 2 ppm/°C typ
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
2
5
±0.004 % of FSR max Typically ±0.0006%
1 µV/°C typ For Gains of 1, 2
0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS
Input Sampling Rate, f
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
AIN1, AIN2
7
Input Voltage Range
S
6
6
8
Common-Mode Rejection (CMR) 100 dB min At DC
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range
10
See Table III
100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 × f
For Normal Operation. Depends on Gain Selected.
REF
REF
9
V max Unipolar Input Range (B/U Bit of Control Register = 1)
V max Bipolar Input Range (B/U Bit of Control Register = 0)
0 to +V
±V
6
150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
6
150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 × f
AGND to AVDDV min to V max
NOTCH
NOTCH
NOTCH
NOTCH
DC Input Leakage Current @ +25°C 10 pA max
T
to T
MIN
Sampling Capacitance
MAX
6
1 nA max
20 pF max
AIN3
Input Voltage Range 0 to + 4 × V
Gain Error
Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator
Offset Error
11
11
±0.05 % typ Additional Error Contributed by Resistor Attenuator
4 mV max Additional Error Contributed by Resistor Attenuator
V max For Normal Operation. Depends on Gain Selected
REF
Input Impedance 30 kΩ min
NOTES
1
Temperature range is as follows: A Version, –40°C to +85°C; S Version, –55°C to +125°C.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
The AIN1 and AIN2 analog inputs presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum
recommended source resistance depends on the selected gain.
8
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2 (–) inputs. The input
voltage range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than A VDD + 30 mV or
more negative than AGND – 30 mV.
9
V
= REF IN(+) – REF IN(–).
REF
10
This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed A VDD + 30 mV and AGND – 30 mV.
11
This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section.
–2– REV. C
AD7713
Parameter A, S Versions
1
Units Conditions/Comments
REFERENCE INPUT
REF IN(+) – REF IN(–) Voltage +2.5 to AVDD/1.8 V min to V max For Specified Performance. Part Is Functional with Lower
V
Voltages
Input Sampling Rate, f
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
Common-Mode Rejection (CMR) 100 dB min At DC
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range
S
6
6
6
6
10
DC Input Leakage Current @ +25°C 10 pA max
T
to T
MIN
MAX
f
/512
CLK IN
100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 × f
150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 × f
AGND to AV
DD
V min to V max
1 nA max
REF
NOTCH
NOTCH
NOTCH
NOTCH
LOGIC INPUTS
Input Current ± 10 µA max
All Inputs Except MCLK IN
V
, Input Low Voltage 0.8 V max
INL
V
, Input High Voltage 2.0 V min
INH
MCLK IN Only
V
, Input Low Voltage 0.8 V max
INL
V
, Input High Voltage 3.5 V min
INH
LOGIC OUTPUTS
VOL, Output Low Voltage 0.4 V max I
VOH, Output High Voltage 4.0 V min I
Floating State Leakage Current ±10 µA max
= 1.6 mA
SINK
SOURCE
= 100 µA
Floating State Output Capacitance129 pF typ
TRANSDUCER BURN-OUT
Current 1 µA nom
Initial Tolerance @ +25°C ±10 % typ
Drift 0.1 %/°C typ
RTD EXCITATION CURRENTS
(RTD1, RTD2)
Output Current 200 µA nom
Initial Tolerance @ +25°C ±20 % max
Drift 20 ppm/°C typ
Initial Matching @ +25°C ± 1 % max Matching Between RTD1 and RTD2 Currents
Drift Matching 3 ppm/°C typ Matching Between RTD1 and RTD2 Current Drift
Line Regulation (AVDD) 200 nA/V max AVDD = +5 V
Load Regulation 200 nA/V max
SYSTEM CALIBRATION
AIN1, AIN2
Positive Full-Scale Calibration Limit13+(1.05 × V
Negative Full-Scale Calibration Limit13–(1.05 × V
Offset Calibration Limit
Input Span
14
14, 15
–(1.05 × V
+0.8 × V
+(2.1 × V
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
AIN3
Positive Full-Scale Calibration Limit13+(4.2 × V
Offset Calibration Limit
15
0 to V
Input Span +3.2 × V
+(4.2 × V
NOTES
12
Guaranteed by design, not production tested.
13
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
14
These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV
than AGND – 30 mV.
15
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)
REF
+ 30 mV or go more negative
DD
REV. C
–3–
AD7713–SPECIFICATIONS
Parameter A, S Versions
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage +5 to +10 V nom ±5% for Specified Performance
DVDD Voltage
Power Supply Currents
AVDD Current 0.6 mA max AVDD = +5 V
DV
DD
Power Supply Rejection
(AVDD and DVDD) See Note 18 dB typ
Power Dissipation
Normal Mode 5.5 mW max AVDD = DVDD = +5 V, f
Standby (Power-Down) Mode 300 µW max AV
NOTES
16
The ±5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.
17
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz or 60 Hz.
18
PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.
16
Current 0.5 mA max f
17
+5 V nom ±5% for Specified Performance
0.7 mA max AVDD = +10 V
1 mA max f
1
Units Conditions/Comments
= 1 MHz. Digital Inputs 0 V to DV
CLK IN
= 2 MHz. Digital Inputs 0 V to DV
CLK IN
Rejection w.r.t. AGND
= DV
DD
= +5 V, Typically 150 µW
DD
DD
DD
= 1 MHz; Typically 3.5 mW
CLK IN
(DVDD = +5 V ± 5%; AVDD = +5 V or +10 V ± 5%; AGND = DGND = 0 V; f
TIMING CHARACTERISTICS
Limit at T
1, 2
Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
, T
MIN
MAX
Parameter (A, S Versions) Units Conditions/Comments
3, 4
f
CLK IN
400 kHz min Master Clock Frequency: Crystal Oscillator or
2 MHz max Externally Supplied for Specified Performance
t
CLK IN LO
t
CLK IN HI
5
t
r
5
t
f
t
1
0.4 × t
0.4 × t
CLK IN
CLK IN
ns min Master Clock Input Low Time; t
ns min Master Clock Input High Time
50 ns max Digital Output Rise Time; Typically 20 ns
50 ns max Digital Output Fall Time; Typically 20 ns
1000 ns min SYNC Pulse Width
Self-Clocking Mode
t
2
t
3
t
4
t
5
t
6
6
t
7
6
t
8
t
9
t
10
t
14
t
15
t
16
t
17
t
18
t
19
0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 × t
CLK IN
ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 × t
4 × t
t
CLK IN
t
CLK IN/2
t
CLK IN
3 × t
+ 20 ns max RFS Low to SCLK Falling Edge
CLK IN
+20 ns max Data Access Time (RFS Low to Data Valid)
CLK IN
/2 ns min SCLK Falling Edge to Data Valid Delay
+ 30 ns max
/2 ns nom SCLK High Pulse Width
/2 ns nom SCLK Low Pulse Width
CLK IN
50 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 × t
4 × t
+ 20 ns max TFS to SCLK Falling Edge Delay Time
CLK IN
CLK IN
ns min TFS to SCLK Falling Edge Hold Time
0 ns min Data Valid to SCLK Setup Time
10 ns min Data Valid to SCLK Hold Time
CLK IN
CLKIN
= 1/f
=2 MHz;
CLK IN
–4–
REV. C
AD7713
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Units Conditions/Comments
External-Clocking Mode
f
SCLK
t
20
t
21
t
22
t
23
6
t
24
6
t
25
t
26
t
27
t
28
7
t
29
t
30
7
t
31
t
32
t
33
t
34
t
35
t
36
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
4
The AD7713 is production tested with f
5
Specified using 10% and 90% points on waveform of interest.
6
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
7
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
f
/5 MHz max Serial Clock Input Frequency
CLK IN
0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 × t
CLK IN
ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 × t
CLK IN
ns max Data Access Time (RFS Low to Data Valid)
10 ns min SCLK Falling Edge to Data Valid Delay
2 × t
2 × t
2 × t
t
CLK IN
+ 20 ns max
CLK IN
CLK IN
CLK IN
ns min SCLK High Pulse Width
ns min SCLK Low Pulse Width
+ 10 ns max SCLK Falling Edge to DRDY High
10 ns min SCLK to Data Valid Hold Time
t
+ 10 ns max
CLK IN
10 ns min RFS/TFS to SCLK Falling Edge Hold Time
5 × t
/2 + 50 ns max RFS to Data Valid Hold Time
CLK IN
0 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 × t
2 × t
CLK IN
– SCLK High ns min Data Valid to SCLK Setup Time
CLK IN
ns min SCLK Falling Edge to TFS Hold Time
30 ns min Data Valid to SCLK Hold Time
at 2 MHz. It is guaranteed by characterization to operate at 400 kHz.
CLK IN
2
1.6mA
TO OUTPUT
PIN
100pF
200µA
+2.1V
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–5–REV. C
AD7713
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AV
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
DD
DV
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DD
DV
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AIN1, AIN2 Input Voltage
to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV
+ 0.3 V
DD
AIN3 Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +22 V
Reference Input Voltage to AGND . . – 0.3 V to AV
Digital Input Voltage to DGND . . . . – 0.3 V to AV
Digital Output Voltage to DGND . . . – 0.3 V to DV
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . . 450 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .105°C/W
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . .+260°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .70°C/W
JA
Lead Temperature, Soldering . . . . . . . . . . . . . . . . . . . +300°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .75°C/W
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Power Dissipation (Any Package) to +75°C . . . . . . . . . 450 mW
*Stresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V, which readily
accumulate on the human body and on test equipment, can discharge without detection. Although
devices feature proprietary ESD protection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic discharges. Therefore, proper precautions are
recommended to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Model Temperature Range Package Option*
AD7713AN –40°C to +85°C N-24
AD7713AR –40°C to +85°C R-24
AD7713AQ –40°C to +85°C Q-24
AD7713SQ –55°C to +125°C Q-24
EVAL-AD7713EB Evaluation Board
*N = Plastic DIP; Q = Cerdip; R = SOIC.
PIN CONFIGURATION
DIP AND SOIC
1
SCLK
MCLK IN
MCLK OUT
SYNC
MODE
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
STANDBY
AV
A0
DD
2
3
4
5
AD7713
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DGND
DV
DD
SDATA
DRDY
RFS
TFS
AGND
AIN3
RTD2
REF IN(+)
REF IN(–)
RTD1
–6–
REV. C
AD7713
PIN FUNCTION DESCRIPTION
Pin Mnemonic Function
1 SCLK Serial Clock. Logic input/output depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes
active when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7713 in smaller batches of data.
2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 2 MHz.
3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
4 A0 Address Input. With this input low, reading and writing to the device is to the control register. With this input
high, access is to either the data register or the calibration registers.
5
SYNC Logic Input which allows for synchronization of the digital filters when using a number of AD7713s. It resets
the nodes of the digital filter.
6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its
external clocking mode.
7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
is connected to an output current source which can be used to check that an external transducer has burnt out
or gone open circuit. This output current source can be turned on/off via the control register.
8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9 AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input.
10 AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input.
11
STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 50 µW.
12 AV
13 RTD1 Constant Current Output. A nominal 200 µA constant current is provided at this pin and this can be used
14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AVDD and AGND provided REF IN(+) is
15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).
16 RTD2 Constant Current Output. A nominal 200 µA constant current is provided at this pin and this can be used
17 AIN3 Analog Input Channel 3. High level analog input which accepts an analog input voltage range of
18 AGND Ground Reference Point for Analog Circuitry.
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
20
DD
RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
Analog Positive Supply Voltage, +5 V to +10 V.
as the excitation current for RTDs. This, current can be turned on or off via the control register.
greater than REF IN(–).
REF IN(+) can lie anywhere between AV
as the excitation current for RTDs. This, current can be turned on or off via the control register. This
second current can be used to eliminate lead resistanced errors in three-wire RTD configurations.
4 × V
0 to ±10 V.
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after
is written to the part.
self-clocking mode, the SCLK and SDATA lines both become active after
clocking mode, the SDATA line becomes active after RFS goes low.
RFS or TFS goes low and it goes high impedance when either RFS or TFS returns high or when
and AGND.
DD
/GAIN. At the nominal V
REF
TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data word
of +2.5 V and a gain of 1, the AIN3 input voltage range is
REF
RFS goes low. In the external
2
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AD7713
Pin Mnemonic Function
21 DRDY Logic output. A falling edge indicates that a new output word is available for transmission. The DRDY pin
will return high upon completion of transmission of a full output word.
when the AD7713 has completed its on-chip calibration sequence.
22 SDATA Serial Data. Input/Output with serial data being written to either the control register or the calibration
registers and serial data being accessed from the control register, calibration registers or the data register.
During an output data read operation, serial data becomes active after
low). During a write operation, valid serial data is expected on the rising edges of SCLK when
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
23 DV
DD
Digital Supply Voltage, +5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.
24 DGND Ground reference point for digital circuitry.
DRDY is also used to indicate
RFS goes low (provided DRDY is
TFS is low.
TERMINOLOGY
INTEGRAL NONLINEARITY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transition (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERROR
Positive full-scale error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal input full-scale
voltage. For AIN1(+) and AIN2(+), the ideal full-scale input
voltage is (AIN1(–) + V
/GAIN – 3/2 LSBs) where AIN(–) is
REF
either AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal
full-scale voltage is +4 × V
/GAIN – 3/2 LSBs. Positive full-
REF
scale error applies to both unipolar and bipolar analog input
ranges.
UNIPOLAR OFFSET ERROR
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+) and AIN2(+), the ideal
input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input
is 0.5 LSB when operating in the Unipolar Mode.
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 ...111
to 1000 . . . 000) from the ideal input voltage. For AIN1(+) and
AIN2(+), the ideal input voltage is (AIN1(–) – 0.5 LSB); AIN3
can only accommodate unipolar input ranges.
POSITIVE FULL-SCALE OVERRANGE
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) and AIN2(+) inputs
greater than (AIN1(–) + V
than +4 × V
/GAIN (for example, noise peaks or excess volt-
REF
/GAIN) or on AIN3 of greater
REF
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modulator or to overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages on
AIN1(+) and AIN2(+) below (AIN1(–) – V
/GAIN) without
REF
overloading the analog modulator or overflowing the digital filter.
OFFSET CALIBRATION RANGE
In the system calibration modes, the AD7713 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7713 can
accept and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7713 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7713’s analog input define the analog input range.
The input span specification defines the minimum and maximum input voltages from zero to full scale that the AD7713 can
accept and still calibrate gain accurately.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+) and AIN2(+), the ideal input voltage is (AIN1(–) – V
/GAIN + 0.5 LSB); AIN3 can only ac-
REF
commodate unipolar input ranges.
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REV. C
AD7713
CONTROL REGISTER (24 BITS)
A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24 bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12 bits of data into
the control register. If more than 24 clock pulses are provided before
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.
TFS returns high, then all clock pulses after the 24th clock
MSB
MD2 MD1 MD0 G2 G1 G0 CH1 CH0 WL RO BO B/U
FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
LSB
Operating Mode
MD2 MD1 MD0 Operating Mode
0 0 0 Normal Mode. This is the normal mode of operation of the device whereby a read to the device with A0
high accesses data from the data register. This is the default condition of these bits after the internal
power-on reset.
0 0 1 Activate Self-Calibration. This activates self-calibration on the channel selected by CH0 and CH1. This
is a one-step calibration sequence, and when complete, the part returns to Normal Mode (with MD2,
MD1, MD0 of the control registers returning to 0, 0, 0). The
calibration is complete. For this calibration type, the zero-scale calibration is done internally on shorted
(zeroed) inputs and the full-scale calibration is done on V
0 1 0 Activate System Calibration. This activates system calibration on the channel selected by CH0 and CH1.
This is a two-step calibration sequence, with the zero-scale calibration done first on the selected input
channel and
Mode at the end of this first step in the two-step sequence.
0 1 1 Activate System Calibration. This is the second step of the system calibration sequence with full-scale
calibration being performed on the selected input channel. Once again,
scale calibration is complete. When this calibration is complete, the part returns to Normal Mode.
1 0 0 Activate System Offset Calibration. This activates system offset calibration on the channel selected by
CH0 and CH1. This is a one-step calibration sequence and, when complete, the part returns to Normal
Mode with
the zero-scale calibration is done on the selected input channel and the full-scale calibration is done
internally on V
1 0 1 Activate Background Calibration. This activates background calibration on the channel selected by CH0
and CH1. If the background calibration mode is on, then the AD7713 provides continuous selfcalibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six. Its major
advantage is that the user does not have to worry about recalibrating the device when there is a change
in the ambient temperature. In this mode, the shorted (zeroed) inputs and V
input voltage, are continuously monitored and the calibration registers of the device are updated.
1 1 0 Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents
of the zero-scale calibration coefficients of the channel selected by CH0 and CH1. A write to the device
with A0 high writes data to the zero-scale calibration coefficients of the channel selected by CH0 and
CH1. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the
WL bit of the control register. Therefore, when writing to the calibration register, 24 bits of data must be
written, otherwise the new data will not be transferred to the calibration register.
1 1 1 Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of
the full-scale calibration coefficients of the channel selected by CH0 and CH1. A write to the device
with A0 high writes data to the full-scale calibration coefficients of the channel selected by CH0 and
CH1. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the
WL bit of the control register. Therefore, when writing to the calibration register, 24 bits of data must be
written, otherwise the new data will not be transferred to the calibration register.
DRDY indicating when this zero-scale calibration is complete. The part returns to Normal
DRDY indicating when this system offset calibration is complete. For this calibration type,
.
REF
DRDY output indicates when this self-
.
REF
DRDY indicates when the full-
, as well as the analog
REF
2
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