Analog Devices AD7712 f Datasheet

LC2MOS

Signal Conditioning ADC

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes

ⴞ0.0015% Nonlinearity
High Level and Low Level Analog Input Channels
Programmable Gain for Both Inputs

Gains from 1 to 128

Differential Input for Low Level Channel
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single- or Dual-Supply Operation
Low Power (25 mW typ) with Power-Down Mode

(100 ␮W typ)

APPLICATIONS
Process Control
Smart Transmitters
Portable Industrial Instruments

GENERAL DESCRIPTION

The AD7712 is a complete analog front end for low frequency
measurement applications. The device has two analog input
channels and accepts either low level signals directly from a trans­ducer or high level (±4 ⫻ V

) signals, and outputs a serial

REF

digital word. It employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The low
level input signal is applied to a proprietary programmable gain
front end based around an analog modulator. The high level
analog input is attenuated before being applied to the same
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be programmed
via the on-chip control register, allowing adjustment of the filter
cutoff and settling time.

Normally, one of the channels will be used as the main channel
with the second channel used as an auxiliary input to periodi­cally measure a second voltage. The part can be operated from a
single supply (by tying the V

pin to AGND), provided that the

SS

input signals on the low level analog input are more positive
than –30 mV. By taking the V
vert signals down to –V

REF

pin negative, the part can con-

SS

on this low level input. This low level
input, as well as the reference input, features differential input
capability.

The AD7712 is ideal for use in smart, microcontroller based
systems. Input channel selection, gain settings, and signal polar­ity can be configured in software using the bidirectional serial

*Protected by U.S. Patent No. 5,134,401.

AD7712

*

FUNCTIONAL BLOCK DIAGRAM

REF

AIN1(+)

AIN1(–)

AIN2

TP

AV

DD

AV

DD

VOLTAGE

ATTENUATION

AD7712

DGND

AGND

DV

DD

4.5␮A

M
U
X

V

REF

IN (–)

PGA

A = 1 – 128

SS

V

IN (+)

BIAS

CHARGE-BALANCING A/D

CONVERTER

AUTO-ZEROED

⌺–⌬

MODULATOR

SERIAL INTERFACE

CONTROL
REGISTER

MODE SDATA SCLK

TFSRFS

REF OUT

2.5V REFERENCE

DIGITAL

FILTER

CLOCK

GENERATION

OUTPUT

REGISTER

DRDY

A0

SYNC

STANDBY

MCLK
IN

MCLK
OUT

port. The AD7712 also contains self-calibration, system calibra­tion, and background calibration options, and allows the user to
read and to write the on-chip calibration registers.

CMOS construction ensures low power dissipation, and a hard­ware programmable power-down mode reduces the standby power
consumption to only 100 µW typical. The part is available in a
24-lead, 0.3 inch wide, plastic and hermetic dual-in-line pack­age (DIP), as well as a 24-lead small outline (SOIC) package.

PRODUCT HIGHLIGHTS

1. The low level analog input channel allows the AD7712 to
accept input signals directly from a strain gage or transducer,
removing a considerable amount of signal conditioning. To
maximize the flexibility of the part, the high level analog
input accepts signals of ±4 ⫻ V

REF

/GAIN.

2. The AD7712 is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity, and calibration modes.

3. The AD7712 allows the user to read and to write the on-chip
calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.

4. No missing codes ensures true, usable, 23-bit dynamic range
coupled with excellent ±0.0015% accuracy. The effects of
temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.

REV. F

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7712–SPECIFICATIONS

REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications T

Parameter A, S Versions

(AVDD = +5 V ⴞ 5%; DVDD = +5 V ⴞ 5%; VSS = 0 V or –5 V ⴞ 5%; REF IN(+) = +2.5 V;

to T

MIN

1

Unit Conditions/Comments

, unless otherwise noted.)

MAX

STATIC PERFORMANCE

No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 60 Hz

22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz

Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity @ 25°C ±0.0015 % FSR max Filter Notches ≤ 60 Hz

T

to T

MIN

Positive Full-Scale Error
Full-Scale Drift

Unipolar Offset Error
Unipolar Offset Drift

Bipolar Zero Error
Bipolar Zero Drift

MAX

5

2, 4

5

2, 4

5

2, 3, 4

±0.003 % FSR max Typically ±0.0003%

Excluding Reference

1 µV/°C typ Excluding Reference. For Gains of 1, 2

0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

0.5 µV/°C typ For Gains of 1, 2

0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128

0.5 µV/°C typ For Gains of 1, 2

0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128

Gain Drift 2 ppm/°C typ
Bipolar Negative Full-Scale Error2 @ 25°C ±0.003 % FSR max Excluding Reference

T

to T

MIN

Bipolar Negative Full-Scale Drift

MAX

5

±0.006 % FSR max Typically ±0.0006%
1 µV/°C typ Excluding Reference. For Gains of 1, 2

0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
AIN1/REF IN

DC Input Leakage Current @ 25°C
T

to T

MIN

MAX

Sampling Capacitance

6

6

6

6

100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ⫻ f
100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ⫻ f

10 pA max
1 nA max
20 pF max

NOTCH

NOTCH

Common-Mode Rejection (CMR) 100 dB min At dc and AVDD = 5 V

Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range

Analog Inputs

Input Sampling Rate, f

8

S

AIN1 Input Voltage Range

AIN2 Input Voltage Range

AIN2 DC Input Impedance 30 kΩ
AIN2 Gain Error
AIN2 Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator
AIN2 Offset Error

11

11

6

6

7

9

9

90 dB min At dc and AVDD = 10 V
150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ⫻ f
150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ⫻ f
VSS to AV

DD

V min to V max

NOTCH

NOTCH

See Table III

0 V to V

REF

±V

REF

0 V to 4 ⫻ V
±4 ⫻ V

REF

10

V max Unipolar Input Range (B/U Bit of Control Register = 1)
V max Bipolar Input Range (B/U Bit of Control Register = 0)

REF

10

V max Unipolar Input Range (B/U Bit of Control Register = 1)
V max Bipolar Input Range (B/U Bit of Control Register = 0)

For Normal Operation. Depends on Gain Selected

For Normal Operation. Depends on Gain Selected

±0.05 % typ Additional Error Contributed by Resistor Attenuator

10 mV max Additional Error Contributed by Resistor Attenuator

AIN2 Offset Drift 20 µV/°C typ

Reference Inputs

REF IN(+) – REF IN(–) Voltage

Input Sampling Rate, f

NOTES

1

Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.

2

Applies after calibration at the temperature of interest.

3

Positive full-scale error applies to both unipolar and bipolar input ranges.

4

These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.

5

Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

6

These numbers are guaranteed by design and/or characterization.

7

This common-mode voltage range is allowed, provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV

8

The AIN1 analog input presents a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).

9

The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AVDD + 30 mV or more negative than VSS – 30 mV.

10

V

= REF IN(+) – REF IN(–).

REF

11

This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the Static Performance section.

12

The reference input voltage range may be restricted by the input voltage range requirement on the V

S

12

2.5 to 5 V min to V max For Specified Performance. Part Is Functional with

f

CLK IN

/256

Lower V

input.

BIAS

Voltages

REF

+ 30 mV and VSS – 30 mV.

DD

REV. F–2–

AD7712

SPECIFICATIONS

Parameter A, S Versions

(continued)

1

Unit Conditions/Comments

REFERENCE OUTPUT

Output Voltage 2.5 V nom
Initial Tolerance ±1% max
Drift 20 ppm/°C typ
Output Noise 30 µV typ pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth
Line Regulation (AV
Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA

)1 mV/V max

DD

External Current 1 mA max

V

BIAS

Input Voltage Range AVDD – 0.85 ⫻ V

V

BIAS

13

INPUT

or AVDD – 3.5 V max Whichever Is Smaller: +5 V/–5 V or +10 V/0 V

REF

or AVDD – 2.1 V max Whichever Is Smaller: +5 V/0 V Nominal AVDD/V
VSS + 0.85 ⫻ V
or VSS + 3 V min Whichever Is Greater: +5 V/–5 V or +10 V/0 V

REF

or VSS + 2.1 V min Whichever Is Greater: +5 V/0 V Nominal AVDD/V

See V

Input Section

BIAS

Nominal AV

See V

Input Section

BIAS

Nominal AV

DD/VSS

DD/VSS

Rejection 65 to 85 dB typ Increasing with Gain

SS

SS

LOGIC INPUTS

Input Current ±10 µA max
All Inputs except MCLK IN

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 2.0 V min

INH

MCLK IN Only

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 3.5 V min

INH

LOGIC OUTPUTS

VOL, Output Low Voltage 0.4 V max I
VOH, Output High Voltage 4.0 V min I
Floating State Leakage Current ±10 µA max
Floating State Output Capacitance

14

9 pF typ

= 1.6 mA

SINK

SOURCE

= 100 µA

TRANSDUCER BURNOUT

Current 4.5 µA nom
Initial Tolerance ±10 % typ
Drift 0.1 %/°C typ

SYSTEM CALIBRATION

AIN1

Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span

15

16, 17

AIN2

Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span

NOTES

13

The AD7712 is tested with the following V
with AVDD = 5 V and VSS = –5 V, V

14

Guaranteed by design, not production tested.

15

After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.

16

These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AVDD + 30 mV or does not go more negative
than VSS – 30 mV.

17

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

15

17

BIAS

15

15

15

15

BIAS

= 0 V.

(1.05 ⫻ V
–(1.05 ⫻ V
–(1.05 ⫻ V

0.8 ⫻ V
(2.1 ⫻ V

(4.2 ⫻ V
–(4.2 ⫻ V
–(4.2 ⫻ V

3.2 ⫻ V
(8.4 ⫻ V

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

voltages. With AVDD = 5 V and VSS = 0 V, V

= 2.5 V; with AVDD = 10 V and VSS = 0 V, V

BIAS

= 5 V and

BIAS

REV. F

–3–

AD7712–SPECIFICATIONS

Parameter A, S Versions1Unit Conditions/Comments

POWER REQUIREMENTS

Power Supply Voltages

AVDD Voltage
DV

DD

AV

DD

Power Supply Currents

AV

Current 4 mA max

DD

DV

DD

V

Current 1.5 mA max VSS = –5 V

SS

Power Supply Rejection

Positive Supply (AV
Negative Supply (V

Power Dissipation

Normal Mode 45 mW max AV
Normal Mode 52.5 mW max AV

Standby (Power-Down) Mode

NOTES

18

The AD7712 is specified with a 10 MHz clock for AVDD voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less

than 10.5 V. Operating with AVDD voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0 ⬚C to 70⬚C temperature range.

19

The ± 5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.

20

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will

exceed 120 dB with filter notches of 10 Hz, 30 Hz, or 60 Hz.

21

PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. These numbers can be improved

(to 95 dB typ) by deriving the V

22

Using the hardware STANDBY pin. Standby power dissipation using the software standby bit (PD) of the Control Register is 8 mW typ.

Specifications subject to change without notice.

18

Voltage
– V

19

Voltage +10.5 V max For Specified Performance

SS

+5 to +10 V nom ±5% for Specified Performance
+5 V nom ± 5% for Specified Performance

Current 4.5 mA max

20

and DVDD)

DD

)90 dB typ

SS

voltage (via Zener diode or reference) from the AVDD supply.

BIAS

21

22

200 µW max AV

dB typ

Rejection w.r.t. AGND; Assumes V

= DVDD = +5 V, VSS = 0 V; Typically 25 mW

DD

DD

DD

= DV
= DV

= +5 V, VSS = –5 V; Typically 30 mW

DD

= +5 V, VSS = 0 V or –5 V; Typically 100 µW

DD

BIAS

Is Fixed

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

DD

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

V

SS

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

V

SS

AIN1 Input Voltage to AGND . . . V
Reference Input Voltage to AGND . . V

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

– 0.3 V to AVDD + 0.3 V

SS

– 0.3 V to AVDD + 0.3 V

SS

DD

ORDERING GUIDE

Model Temperature Range Package Options*

AD7712AN –40°C to +85°C N-24
AD7712AR –40°C to +85°C RW-24
AD7712AR-REEL –40°C to +85°C RW-24
AD7712AR-REEL7 –40°C to +85°C RW-24
AD7712AQ –40°C to +85°C Q-24
AD7712SQ –55°C to +125°C Q-24
EVAL-AD7712EB Evaluation Board

*N = PDIP, Q = CERDIP; RW = SOIC.

Digital Input Voltage to DGND . . . . . –0.3 V to AVDD + 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to DV

+ 0.3 V

DD

Operating Temperature Range

Commercial (A Version) . . . . . . . . . . . . . . .–40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C

Power Dissipation (Any Package) to 75°C . . . . . . . . . . 450 mW

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7712 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. F–4–

TIMING CHARACTERISTICS

(DVDD = +5 V ⴞ 5%; AVDD = +5 V or +10 V3 ⴞ 5%; VSS = 0 V or –5 V ⴞ 5%; AGND = DGND =

1, 2

0 V; f

=10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.)

CLKIN

AD7712

Limit at T

MIN

, T

MAX

Parameter (A, S Versions) Unit Conditions/Comments

4, 5

f

CLK IN

Master Clock Frequency: Crystal Oscillator or
Externally Supplied

400 kHz min AV

= 5 V ± 5%

DD

10 MHz max For Specified Performance

= 5.25 V to 10.5 V

DD

CLK IN

= 1/f

CLK IN

t

CLK IN LO

t

CLK IN HI

6

t

r

6

t

f

t

1

8 MHz AV

0.4 ⫻ t

0.4 ⫻ t

CLK IN

CLK IN

ns min Master Clock Input Low Time; t

ns min Master Clock Input High Time
50 ns max Digital Output Rise Time; Typically 20 ns
50 ns max Digital Output Fall Time; Typically 20 ns
1000 ns min SYNC Pulse Width

Self-Clocking Mode

t

2

t

3

t

4

t

5

t

6

7

t

7

7

t

8

t

9

t

10

t

14

t

15

t

16

t

17

t

18

t

19

NOTES

1

Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input
signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 11 to 14.

3

The AD7712 is specified with a 10 MHz clock for AVDD voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less
than 10.5 V.

4

CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.

5

The AD7712 is production tested with f

6

Specified using 10% and 90% points on waveform of interest.

7

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

0 ns min DRDY to RFS Setup Time; t
0 ns min DRDY to RFS Hold Time
2 ⫻ t

CLK IN

ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 ⫻ t
4 ⫻ t
t

CLK IN

t

CLK IN/2

t

CLK IN

3 ⫻ t

+ 20 ns max RFS Low to SCLK Falling Edge

CLK IN

+ 20 ns max Data Access Time (RFS Low to Data Valid)

CLK IN

/2 ns min SCLK Falling Edge to Data Valid Delay

+ 30 ns max

/2 ns nom SCLK High Pulse Width

/2 ns nom SCLK Low Pulse Width

CLK IN

50 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 ⫻ t
4 ⫻ t

+ 20 ns max TFS to SCLK Falling Edge Delay Time

CLK IN

CLK IN

ns min TFS to SCLK Falling Edge Hold Time
0 ns min Data Valid to SCLK Setup Time
10 ns min Data Valid to SCLK Hold Time

at 10 MHz (8 MHz for AVDD < 5.25 V). It is guaranteed by characterization to operate at 400 kHz.

CLK IN

CLK IN

= 1/f

CLK IN

REV. F

–5–

AD7712

TIMING CHARACTERISTICS

Limit at T

(continued)

, T

MIN

MAX

Parameter (A, S Versions) Unit Conditions/Comments

External Clocking Mode

f

f

SCLK

t

20

t

21

t

22

t

23

7

t

24

7

t

25

t

26

t

27

t

28

8

t

29

t

30

8

t

31

t

32

t

33

t

34

t

35

t

36

NOTES

8

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

Specifications subject to change without notice.

/5 MHz max Serial Clock Input Frequency

CLK IN

0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 ⫻ t

CLK IN

ns min A0 to RFS Setup Time

0 ns min A0 to RFS Hold Time
4 ⫻ t

CLK IN

ns max Data Access Time (RFS Low to Data Valid)

10 ns min SCLK Falling Edge to Data Valid Delay
2 ⫻ t
2 ⫻ t
2 ⫻ t
t

CLK IN

+ 20 ns max

CLK IN

CLK IN

CLK IN

ns min SCLK High Pulse Width
ns min SCLK Low Pulse Width

+ 10 ns max SCLK Falling Edge to DRDY High

10 ns min SCLK to Data Valid Hold Time

+ 10 ns max

t

CLK IN

10 ns min RFS/TFS to SCLK Falling Edge Hold Time
5 ⫻ t

/2 + 50 ns max RFS to Data Valid Hold Time

CLK IN

0 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 ⫻ t
2 ⫻ t

CLK IN

– SCLK High ns min Data Valid to SCLK Setup Time

CLK IN

ns min SCLK Falling Edge to TFS Hold Time

30 ns min Data Valid to SCLK Hold Time

1.6mA

TO OUTPUT

PIN

100pF

200␮A

2.1V

Figure 1. Load Circuit for Access Time and
Bus Relinquish Time

PIN CONFIGURATION

DIP and SOIC

SCLK

1

MCLK IN

MCLK OUT

STANDBY

A0

SYNC

MODE

AIN1(+)

AIN1(–)

TP

V

AV

DD

SS

2

3

4

5

AD7712

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

DGND

DV

DD

SDATA

DRDY

RFS

TFS

AGND

AIN2

REF OUT

REF IN(+)

REF IN(–)

V

BIAS

REV. F–6–

AD7712

PIN FUNCTION DESCRIPTION

Pin Mnemonic Function

1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the

device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes
active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7712 in smaller batches of data.

2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can

be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.

3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.

4A0Address Input. With this input low, reading and writing to the device is to the control register. With this input

high, access is to either the data register or the calibration registers.

5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7712s. It resets

the nodes of the digital filter.

6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its

external clocking mode.

7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input

is connected to an output current source that can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.

8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power

consumption to less than 50 µW.

10 TP Test Pin. Used when testing the device. Do not connect anything to this pin.

11 V

SS

12 AV

13 V

DD

BIAS

14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV

15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).

16 REF OUT Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output

17 AIN2 Analog Input Channel 2. High level analog input that accepts an analog input voltage range of ± 4 ⫻

18 AGND Ground Reference Point for Analog Circuitry.
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial

20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the

Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1
should not go > 30 mV negative w.r.t. V

for correct operation of the device.

SS

Analog Positive Supply Voltage, 5 V to 10 V.

Input Bias Voltage. This input voltage should be set such that V
⫻ V
and VSS. Thus, with AV
–5 V, it can be tied to AGND, while with AV

> VSS where V

REF

is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV

REF

= +5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and VSS =

DD

= +10 V, it can be tied to +5 V.

DD

+ 0.85 ⫻ V

BIAS

and VSS provided REF IN(+) is greater

DD

< AVDD and V

REF

BIAS

– 0.85

DD

than REF IN(–).

REF IN(+) can lie anywhere between AV

and VSS.

DD

that is referred to AGND.

V

/GAIN. At the nominal V

REF

of +2.5 V and a gain of 1, the AIN2 input voltage range is ±10 V.

REF

data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word
is written to the part.

self-clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external
clocking mode, the SDATA line becomes active after RFS goes low.

REV. F

–7–

AD7712

Pin Mnemonic Function

21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin

will return high upon completion of transmission of a full output word. DRDY is also used to indicate
when the AD7712 has completed its on-chip calibration sequence.

22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration

registers and serial data being accessed from the control register, calibration registers, or the data register.
During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is
low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low.
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.

23 DV

DD

24 DGND Ground Reference Point for Digital Circuitry.

Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end­points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi­tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 ...110 to 111 . . . 111). The
error is expressed as a percentage of full scale.

Positive Full-Scale Error

Positive full-scale error is the deviation of the last code transi­tion (111 . . . 110 to 111 ...111) from the ideal input full-scale
voltage. For AIN1(+), the ideal full-scale input voltage is
(AIN1(–) + V
scale voltage is +4 ⫻ V

/GAIN – 3/2 LSBs); for AIN2, the ideal full-

REF

/GAIN – 3/2 LSBs. Positive full-scale

REF

error applies to both unipolar and bipolar analog input ranges.

Unipolar Offset Error

Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+), the ideal input voltage is
(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB
when operating in the unipolar mode.

Bipolar Zero Error

This is the deviation of the midscale transition (0111 . . . 111
to 1000 ...000) from the ideal input voltage. For AIN1(+), the
ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal
input is –0.5 LSB when operating in the bipolar mode.

Bipolar Negative Full-Scale Error

This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+), the ideal input voltage is (AIN1(–)

/GAIN + 0.5 LSB); for AIN2, the ideal input voltage is

– V

REF

(–4 ⫻ V

/GAIN + 0.5 LSB) when operating in the bipolar

REF

mode.

Positive Full-Scale Overrange

Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) input greater than
(AIN1(–) + V

/GAIN (for example, noise peaks or excess voltages due to

V

REF

/GAIN) or on the AIN2 of greater than +4 ⫻

REF

system gain errors in system calibration routines) without intro­ducing errors due to overloading the analog modulator or to
overflowing the digital filter.

Negative Full-Scale Overrange

This is the amount of overhead available to handle voltages on
AIN1(+) below (AIN1(–) – V
–4 ⫻ V

/GAIN without overloading the analog modulator or

REF

/GAIN) or on AIN2 below

REF

overflowing the digital filter. Note that the analog input will
accept negative voltage peaks on AIN1(+) even in the unipolar
mode provided that AIN1(+) is greater than AIN1(–) and greater
than V

Offset Calibration Range

– 30 mV.

SS

In the system calibration modes, the AD7712 calibrates its
offset with respect to the analog input. The offset calibration
range specification defines the range of voltages that the AD7712
can accept and still accurately calibrate offset.

Full-Scale Calibration Range

This is the range of voltages that the AD7712 can accept in the
system calibration mode and still correctly calibrate full scale.

Input Span

In system calibration schemes, two voltages applied in sequence
to the AD7712’s analog input define the analog input range.
The input span specification defines the minimum and maxi­mum input voltages from zero to full scale that the AD7712 can
accept and still accurately calibrate gain.

REV. F–8–

AD7712

Control Register (24 Bits)

A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24 bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12 bits of data into
the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.

MSB

MD2 MD1 MD0 G2 G1 G0 CH PD WL X BO B/U

FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0

X = Don’t Care. LSB

Operating Mode

MD2 MD1 MD0 Operating Mode

000Normal Mode. This is the normal mode of operation of the device whereby a read to the device accesses

data from the data register. This is the default condition of these bits after the internal power-on reset.

001Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step

calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of
the control registers returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete.
For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs, and the
full-scale calibration is done on V

010Activate System Calibration. This activates system calibration on the channel selected by CH. This is a

two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and
DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the
end of this first step in the two-step sequence.

011Activate System Calibration. This is the second step of the system calibration sequence with full-scale

calibration being performed on the selected input channel. Once again, DRDY indicates when the full­scale calibration is complete. When this calibration is complete, the part returns to normal mode.

100Activate System Offset Calibration. This activates system offset calibration on the channel selected by

CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with
DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale
calibration is done on the selected input channel, and the full-scale calibration is done internally on V

101Activate Background Calibration. This activates background calibration on the channel selected by CH. If

the background calibration mode is on, then the AD7712 provides continuous self-calibration of the
reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence,
extending the conversion time and reducing the word rate by a factor of 6. Its major advantage is that
the user does not have to worry about recalibrating the device when there is a change in the ambient
temperature. In this mode, the shorted (zeroed) inputs and V
continuously monitored, and the calibration registers of the device are automatically updated.

110Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents

of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register, 24 bits of data must be written; otherwise the
new data will not be transferred to the calibration register.

111Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of

the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register, 24 bits of data must be written; otherwise the
new data will not be transferred to the calibration register.

REF

.

.

REF

, as well as the analog input voltage, are

REF

REV. F

–9–