Analog Devices AD7711AAR, AD7711ASQ Datasheet

LC2MOS Signal Conditioning ADC

a

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes
ⴞ0.0015% Nonlinearity

Two-Channel Programmable Gain Front End

Gains from 1 to 128

Differential Inputs
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single or Dual Supply Operation
Low Power (25 mW typ) with Power-Down Mode

(7 mW typ)

APPLICATIONS
RTD Transducers

GENERAL DESCRIPTION

The AD7711A is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer and outputs a serial digital word. It
employs a sigma-delta conversion technique to realize up to
24 bits of no missing codes performance. The input signal is
applied to a proprietary programmable gain front end based
around an analog modulator. The modulator output is pro­cessed by an on-chip digital filter. The first notch of this digital
filter can be programmed via the on-chip control register allow­ing adjustment of the filter cutoff and settling time.

The part features two differential analog inputs and a differen­tial reference input. Normally, one of the channels will be used
as the main channel with the second channel used as an auxil­iary input to periodically measure a second voltage. It can be
operated from a single supply (by tying the V
provided that the input signals on the analog inputs are more
positive than –30 mV. By taking the V
can convert signals down to –V

SS

on its inputs. The part also

REF

provides a 400 µA current source that can be used to provide

excitation for RTD transducers. The AD7711A thus performs
all signal conditioning and conversion for a single or dual chan­nel system.

The AD7711A is ideal for use in smart, microcontroller-based
systems. Input channel selection, gain settings and signal polar­ity can be configured in software using the bidirectional serial
port. The AD7711A contains self-calibration, system calibration
and background calibration options and also allows the user to
read and write the on-chip calibration registers.

*Protected by U.S. Patent No. 5,134,401.

pin to AGND)

SS

pin negative, the part

with RTD Current Source

AD7711A*

FUNCTIONAL BLOCK DIAGRAM

REF

AV

DD

AV

DD

AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)

AV

DD

RTD

CURRENT

AD7711A

AGND DGND MODE SDATA SCLK A0

CMOS construction ensures low power dissipation, and a soft­ware programmable power-down mode reduces the standby
power consumption to only 7 mW typical. The part is available
in a 24-lead, 0.3 inch-wide, hermetic dual-in-line package
(cerdip) as well as a 24-lead small outline (SOIC) package.

PRODUCT HIGHLIGHTS

1. The programmable gain front end allows the AD7711A
to accept input signals directly from an RTD transducer,
removing a considerable amount of signal conditioning. An
on-chip current source provides the excitation current for
the RTD.

2. The part features excellent static performance specifications

with 24-bit no missing codes, ±0.0015% accuracy and low

rms noise (<250 nV). Endpoint errors and the effects of
temperature drift are eliminated by on-chip calibration op­tions, which remove zero-scale and full-scale errors.

3. The AD7711A is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity, RTD current control and calibration modes.

4. The AD7711A allows the user to read and to write the
on-chip calibration registers. This means that the micro­controller has much greater control over the calibration
procedure.

DV

4.5mA

400mA

DD

M
U
X

V

SS

REF

IN (–)

PGA

A = 1 – 128

IN (+)

V

BIAS

CHARGE-BALANCING A/D

AUTO-ZEROED

MODULATOR

SERIAL INTERFACE

CONTROL
REGISTER

2.5V REFERENCE

CONVERTER

CLOCK

GENERATION

OUTPUT

REGISTER

REF OUT

DIGITAL

FILTER

DRDYTFSRFS

SYNC

MCLK
IN

MCLK
OUT

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7711A–SPECIFICATIONS

REF␣ IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise stated. All specifications T

Parameter A, S Versions

(AVDD = +5␣ V ⴞ 5%; DVDD = +5␣ V ⴞ 5%; VSS = 0 V or –5␣ V ⴞ 5%; REF IN(+) = +2.5␣ V;

to T

MIN

1

Units Conditions/Comments

unless otherwise noted.)

MAX

STATIC PERFORMANCE

No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 60 Hz

22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz

Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity @ +25°C ±0.0015 % FSR max Filter Notches ≤ 60 Hz

T

to T

MIN

Positive Full Scale Error
Full-Scale Drift

Unipolar Offset Error
Unipolar Offset Drift

Bipolar Zero Error
Bipolar Zero Drift

MAX

5

2

5

2

5

2, 3

0.003 % FSR max Typically ±0.0003%

See Note 4 Excluding Reference

1 µV/°C typ Excluding Reference. For Gains of 1, 2

0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

See Note 4

0.5 µV/°C typ For Gains of 1, 2

0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128

See Note 4

0.5 µV/°C typ For Gains of 1, 2

0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128

Gain Drift 2 ppm/°C typ

Bipolar Negative Full-Scale Error

Bipolar Negative Full-Scale Drift

T

to T

MIN

MAX

2

@ +25°C ±0.003 % FSR max Excluding Reference

5

±0.006 % FSR max Typically ±0.0006%
1 µV/°C typ Excluding Reference. For Gains of 1, 2

0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Common-Mode Rejection (CMR) 100 dB min At DC
Common-Mode Voltage Range
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
DC Input Leakage Current

T

to T

MIN

Sampling Capacitance
Analog Inputs

MAX

8

Input Voltage Range

Input Sampling Rate, f

Reference Inputs

REF IN(+) – REF IN(–) Voltage

Input Sampling Rate, f

6

7

7

7

7

7

@ +25°C 10 pA max

7

9

S

11

S

VSS to AV

DD

100 dB min For Filter Notches of 10, 25, 50 Hz, ±0.02 × f
100 dB min For Filter Notches of 10, 30, 60 Hz, ±0.02 × f
150 dB min For Filter Notches of 10, 25, 50 Hz, ±0.02 × f
150 dB min For Filter Notches of 10, 30, 60 Hz, ±0.02 × f

1 nA max
20 pF max

REF

REF

10

0 to +V

±V

See Table III

+2.5 to +5 V min to V max For Specified Performance. Part Functions with

f

/256

CLK IN

V min to V max

NOTCH

NOTCH

NOTCH

NOTCH

For Normal Operation. Depends on Gain Selected
nom Unipolar Input Range (B/U Bit of Control Register = 1)
nom Bipolar Input Range (B/U Bit of Control Register = 0)

Lower V

Voltages

REF

REFERENCE OUTPUT

Output Voltage 2.5 V nom

Initial Tolerance @ +25°C ±1 % max
Drift 20 ppm/°C typ
Output Noise 30 µV typ pk-pk Noise 0.1 Hz to 10 Hz Bandwidth

Line Regulation (AVDD) 1 mV/V max
Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA
External Current 1 mA max

NOTES

1

Temperature ranges are as follows: A Version, –40°C to +85°C; S Version, –55°C to +125°C.

2

Applies after calibration at the temperature of interest.

3

Positive full-scale error applies to both unipolar and bipolar input ranges.

4

These errors will be of the order of the output noise of the part as shown in Table I when using system calibration. These errors are 20 µV typical when using self­calibration or background calibration.

5

Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

6

This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed AV

7

These numbers are guaranteed by design and/or characterization.

8

The analog inputs present a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).

9

The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AVDD + 30 mV or go more negative than VSS – 30 mV.

10

V

= REF IN(+) – REF IN(–).

REF

11

The reference input voltage range may be restricted by the input voltage range requirement on the V

BIAS

input.

+ 30 mV and VSS – 30 mV.

DD

–2– REV. C

AD7711A

Parameter A, S Versions

INPUT

12

DD

V

BIAS

Input Voltage Range AV

1

– 0.85 × V

Units Conditions/Comments

REF

See V

BIAS

Input Section

or AVDD – 3.5 V max Whichever Is Smaller; +5 V/–5 V or +10 V/0 V

or AVDD – 2.1 V max Whichever Is Smaller; +5 V/0 V Nominal AVDD/V

Nominal AVDD/V

V

+ 0.85 × V

SS

REF

See V

BIAS

SS

SS

Input Section

or VSS + 3 V min Whichever Is Greater; +5 V/–5 V or +10 V/0 V

or VSS + 2.1 V min Whichever Is Greater; +5 V/0 V Nominal AVDD/V

Nominal AVDD/V

V

Rejection 65 to 85 dB typ Increasing with Gain

BIAS

SS

SS

LOGIC INPUTS

Input Current ±10 µA max

All Inputs except MCLK IN

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 2.0 V min

INH

MCLK IN Only

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 3.5 V min

INH

LOGIC OUTPUTS

VOL, Output Low Voltage 0.4 V max I
VOH, Output High Voltage DVDD – 1 V min I

Floating State Leakage Current ±10 µA max

Floating State Output Capacitance

13

9 pF typ

= 1.6 mA

SINK

SOURCE

= 100 µA

TRANSDUCER BURNOUT

Current 4.5 µA nom
Initial Tolerance @ +25°C ±10 % typ
Drift 0.1 %/°C typ

RTD EXCITATION CURRENT

Output Current 400 µA nom
Initial Tolerance @ +25°C ±20 % max
Drift 20 ppm/°C typ

Line Regulation (AVDD) 400 nA/V max AVDD = +5 V
Load Regulation 400 nA/V max
Output Compliance AVDD – 2 V max

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span

NOTES

12

The AD7711A is tested with the following V

with AVDD = +5 V and VSS = –5 V, V

13

Guaranteed by design, not production tested.

14

After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will

output all 0s.

15

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than VSS – 30 mV.

15

15

BIAS

14

14

= 0 V.

(1.05 × V
–(1.05 × V
–(1.05 × V

0.8 × V
(2.1 × V

voltages. With AVDD = +5 V and VSS = 0 V, V

BIAS

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

= +2.5 V, with AVDD = +10 V and VSS = 0 V, V

BIAS

= +5 V and

BIAS

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

REV. C

–3–

AD7711A–SPECIFICATIONS

Parameter A, S Versions Units Conditions/Comments

POWER REQUIREMENTS

Power Supply Voltages

AVDD Voltage
DVDD Voltage
AVDD–V

Power Supply Currents

AVDD Current 4 mA max
DV

DD

VSS Current 1.5 mA max VSS = –5 V

Power Supply Rejection

Positive Supply (AV
Negative Supply (VSS) 90 dB typ

Power Dissipation

Normal Mode 45 mW max AV
Normal Mode 52.5 mW max AV
Standby (Power-Down) Mode 15 mW max AV

NOTES

16

The AD7711A is specified with a 10 MHz clock for AV

than 10.5 V.

17

The ±5% tolerance on the DV

18

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed

120 dB with filter notches of 10 Hz, 30 Hz or 60 Hz.

19

PSRR depends on gain: Gain of 1: 70 dB typ; Gain of 2: 75 dB typ; Gain of 4: 80 dB typ; Gains of 8 to 128: 85 dB typ. These numbers can be improved (to 95 dB

typ) by deriving the V

Specifications subject to change without notice.

16

17

Voltage +10.5 V max For Specified Performance

SS

+5 to +10 V nom ±5% for Specified Performance
+5 V nom ±5% for Specified Performance

Current 4.5 mA max

18

and DVDD) See Note 19 dB typ

DD

voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AV

DD

input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.

DD

voltage (via Zener diode or reference) from the AVDD supply.

BIAS

Rejection w.r.t. AGND; Assumes V

= DV

DD

DD

DD

= +5␣ V, VSS = 0 V; Typically 25 mW

DD

= DV

= +5␣ V, VSS = –5 V; Typically 30 mW

DD

= DV

= +5␣ V, VSS = 0 V or –5 V; Typically 7 mW

DD

Is Fixed

BIAS

voltages greater than 5.25 V and less

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C, unless otherwise noted)

A

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

V

SS

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

V

SS

Analog Input Voltage to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . V

– 0.3 V to AVDD + 0.3 V

SS

Reference Input Voltage to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . V

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

– 0.3 V to AVDD + 0.3 V

SS

DD

Digital Input Voltage to DGND . . . . . –0.3 V to AVDD + 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV

+ 0.3 V

DD

Operating Temperature Range

Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Options*

AD7711AAR –40°C to +85°C R-24
AD7711ASQ –55°C to +125°CQ-24

*R = SOIC, Q = Cerdip.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7711A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. C

TIMING CHARACTERISTICS

AD7711A

(DVDD = +5␣ V ⴞ 5%; AVDD = +5␣ V or +10␣ V3, ⴞ 5%; VSS = 0 V or –5 V ⴞ 10%; AGND = DGND

1, 2

= 0 V; f

= 10␣ MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted)

CLKIN

Limit at T

MIN

, T

MAX

Parameter (A, S Versions) Units Conditions/Comments

4, 5

f

CLK IN

Master Clock Frequency: Crystal Oscillator or Externally

400 kHz min Supplied for Specified Performance

= +5 V ± 5%

DD

= +5.25 V to +10.5 V

DD

t

CLK IN LO

t

CLK IN HI

6

t

r

6

t

f

t

1

10 MHz max AV
8 MHz max AV

0.4 × t

0.4 × t

CLK IN

CLK IN

ns min Master Clock Input Low Time. t

ns min Master Clock Input High Time
50 ns max Digital Output Rise Time. Typically 20 ns
50 ns max Digital Output Fall Time. Typically 20 ns
1000 ns min SYNC Pulsewidth

Self-Clocking Mode

t

2

t

3

t

4

t

5

t

6

7

t

7

7

t

8

t

9

t

10

t

14

t

15

t

16

t

17

t

18

t

19

0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 × t

CLK IN

ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 × t
4 × t
t

CLK IN

t

CLK IN/2

t

CLK IN

3 × t

+ 20 ns max RFS Low to SCLK Falling Edge

CLK IN

+ 20 ns max Data Access Time (RFS Low to Data Valid)

CLK IN

/2 ns min SCLK Falling Edge to Data Valid Delay

+ 30 ns max

/2 ns nom SCLK High Pulsewidth

/2 ns nom SCLK Low Pulsewidth

CLK IN

50 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 × t
4 × t

+ 20 ns max TFS to SCLK Falling Edge Delay Time

CLK IN

CLK IN

ns min TFS to SCLK Falling Edge Hold Time
0 ns min Data Valid to SCLK Setup Time
10 ns min Data Valid to SCLK Hold Time

CLK IN

= 1/f

2

CLK IN

–5–REV. C

AD7711A

Limit at T

MIN

, T

MAX

Parameter (A, S Versions) Units Conditions/Comments

External Clocking Mode

f

SCLK

t

20

t

21

t

22

t

23

7

t

24

7

t

25

t

26

t

27

t

28

8

t

29

t

30

8

t

31

t

32

t

33

t

34

t

35

t

36

NOTES

1

Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 10 to 13.

3

The AD7711A is specified with a 10 MHz clock for AV
than 10.5 V.

4

CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.

5

The AD7711A is production tested with f

6

Specified using 10% and 90% points on waveform of interest.

7

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

8

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

f

/5 MHz max Serial Clock Input Frequency

CLK IN

0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 × t

CLK IN

ns min A0 to RFS Setup Time

0 ns min A0 to RFS Hold Time
4 × t

CLK IN

ns max Data Access Time (RFS Low to Data Valid)

10 ns min SCLK Falling Edge to Data Valid Delay

2 × t
2 × t
2 × t

t

CLK IN

+ 20 ns max

CLK IN

CLK IN

CLK IN

ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth

+ 10 ns max SCLK Falling Edge to DRDY High

10 ns min SCLK to Data Valid Hold Time

+ 10 ns max

t

CLK IN

10 ns min RFS/TFS to SCLK Falling Edge Hold Time
5 × t

/2 + 50 ns max RFS to Data Valid Hold Time

CLK IN

0 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 × t
2 × t

CLK IN

– SCLK High ns min Data Valid to SCLK Setup Time

CLK IN

ns min SCLK Falling Edge to TFS Hold Time

30 ns min Data Valid to SCLK Hold Time

voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AV

DD

at 10 MHz (8 MHz for AVDD > +5.25 V). It is guaranteed by characterization to operate at 400 kHz.

CLK IN

voltages greater than 5.25 V and less

DD

1.6mA

TO OUTPUT

PIN

100pF

200mA

+2.1V

Figure 1. Load Circuit for Access Time and Bus Relinquish
Time

–6–

PIN CONFIGURATION

DIP and SOIC

1

SCLK

2

MCLK IN

SYNC

MODE
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)

V

AV

A0

SS
DD

3
4
5

AD7711A

6

TOP VIEW

(Not to Scale)

7
8

9
10
11
12

MCLK OUT

24

DGND

23

DV

DD

22

SDATA

21

DRDY

20

RFS

19

TFS

18

AGND
RTD CURRENT

17
16

REF OUT

15

REF IN(+)

14

REF IN(–)

13

V

BIAS

REV. C

AD7711A

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 SCLK Serial Clock. Logic Input/Output depending on the status of the MODE pin. When MODE is high, the

device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes
active when RFS or TFS goes low and it goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7711A in smaller batches of data.

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can

be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.

3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.

4 A0 Address Input. With this input low, reading and writing to the device is to the control register. With this input

high, access is to either the data register or the calibration registers.

5 SYNC Logic Input which allows for synchronization of the digital filters when using a number of AD7711As. It resets

the nodes of the digital filter.

6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its

external clocking mode.

7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input

is connected to an output current source which can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.

8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input.

9 AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input.

10 AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input.

11 V

12 AV

13 V

SS

DD

BIAS

14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV

15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).

16 REF OUT Reference Output. The internal +2.5 V reference is provided at this pin. This is a single ended output

17 RTD CURRENT Constant Current Output. A nominal 400 µA constant current is provided at this pin, and this can be used

18 AGND Ground reference point for analog circuitry.

Analog Negative Supply, 0 V to –5 V. Tied to AGND for single supply operation. The input voltage on AIN1
or AIN2 should not go > 30 mV negative w.r.t. V

for correct operation of the device.

SS

Analog Positive Supply Voltage, +5 V to +10 V.

Input Bias Voltage. This input voltage should be set such that V

× V

REF >VSS

where V
and VSS. Thus with AV
–5 V, it can be tied to AGND while with AV

is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV

REF

= +5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and VSS =

DD

= +10 V, it can be tied to +5 V.

DD

+ 0.85 × V

BIAS

and VSS provided REF IN(+) is greater

DD

< AVDD and V

REF

BIAS

– 0.85

DD

than REF IN(–).

REF IN(+) can lie anywhere between AV

and VSS.

DD

which is referred to AGND. It is a buffered output which is capable of providing 1 mA to an external load.

as the excitation current for RTDs. This current can be turned on/off via the control register.

2

–7–REV. C

AD7711A

Pin Mnemonic Function

19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data

expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after
TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data word is written
to the part.

20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the

self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external
clocking mode, the SDATA line becomes active after RFS goes low.

21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin

will return high upon completion of transmission of a full output word. DRDY is also used to indicate when
the AD7711A has completed its on-chip calibration sequence.

22 SDATA Serial Data. Input /Output with serial data being written to either the control register or the calibration

registers and serial data being accessed from the control register, calibration registers or the data register.
During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low).
During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The
output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.

23 DV

DD

24 DGND Ground reference point for digital circuitry.

Digital Supply Voltage, +5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.

TERMINOLOGY

INTEGRAL NONLINEARITY

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end­points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi­tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.

POSITIVE FULL-SCALE ERROR

Positive Full-Scale Error is the deviation of the last code transi­tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + V

/GAIN – 3/2 LSBs). It applies to both unipolar

REF

and bipolar analog input ranges.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper­ating in the unipolar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–)
– 0.5 LSB) when operating in the bipolar mode.

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – V

/GAIN + 0.5␣ LSB), when oper-

REF

ating in the bipolar mode.

POSITIVE FULL-SCALE OVERRANGE

Positive Full-Scale Overrange is the amount of overhead avail­able to handle input voltages on AIN(+) input greater than
AIN(–) + V

/GAIN (for example, noise peaks or excess volt-

REF

ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu­lator or overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – V

/GAIN without overloading the

REF

analog modulator or overflowing the digital filter. Note that the
analog input will accept negative voltage peaks even in the uni­polar mode provided that AIN(+) is greater than AIN(–) and
greater than V

OFFSET CALIBRATION RANGE

– 30␣ mV.

SS

In the system calibration modes, the AD7711A calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages that the
AD7711A can accept and still accurately calibrate offset.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7711A can accept in
the system calibration mode and still correctly calibrate full-scale.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence
to the AD7711A’s analog input define the analog input range.
The input span specification defines the minimum and maxi­mum input voltages from zero to full-scale that the AD7711A
can accept and still calibrate accurately gain.

–8–

REV. C

AD7711A

CONTROL REGISTER (24 BITS)

A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24 bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12 bits of data into
the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.

MSB

MD2 MD1 MD0 G2 G1 G0 CH PD WL IO BO B/U

FS11* FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0

*Must always be 0 to ensure correct operation of the device.

LSB

2

Operating Mode

MD2 MD1 MD0 Operating Mode

0 0 0 Normal Mode. This is the normal mode of operation of the device whereby a read to the device with A0

high accesses data from the data register. This is the default condition of these bits after the internal
power on reset.

0 0 1 Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step

calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of
the control register returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete
and valid data is available in the output register. For this calibration type, the zero scale calibration is done
internally on shorted (zeroed) inputs and the full-scale calibration is done internally on V

REF

.

0 1 0 Activate System Calibration. This activates system calibration on the channel selected by CH. This is a

two-step calibration sequence, with the zero scale calibration done first on the selected input channel and
DRDY indicating when this zero scale calibration is complete. The part returns to normal mode at the
end of this first step in the two-step sequence.

0 1 1 Activate System Calibration. This is the second step of the system calibration sequence with full-scale

calibration being performed on the selected input channel. Once again, DRDY indicates when the full-
scale calibration is complete. When this calibration is complete, the part returns to normal mode.

1 0 0 Activate System Offset Calibration. This activates system offset calibration on the channel selected by

CH. This is a one-step calibration sequence and, when complete, the part returns to normal mode with
DRDY indicating when this system offset calibration is complete. For this calibration type, the zero scale
calibration is done on the selected input channel and the full-scale calibration is done internally on V

REF

.

1 0 1 Activate Background Calibration. This activates background calibration on the channel selected by CH. If

the background calibration mode is on, then the AD7711A provides continuous self-calibration of the
reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence,
extending the conversion time and reducing the word rate by a factor of six. Its major advantage is that
the user does not have to worry about recalibrating the device when there is a change in the ambient
temperature. In this mode, the shorted (zeroed) inputs and V

, as well as the analog input voltage, are

REF

continuously monitored and the calibration registers of the device are automatically updated.

1 1 0 Read/Write Zero Scale Calibration Coefficients. A read to the device with A0 high accesses the contents

of the zero scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register 24 bits of data must be written, otherwise the
new data will not be transferred to the calibration register.

1 1 1 Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of

the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register 24 bits of data must be written, otherwise the
new data will not be transferred to the calibration register.

–9–REV. C