Analog Devices AD7575KN, AD7575JR, AD7575JP, AD7575JN, AD7575BQ Datasheet

LC2MOS

TRACK

AND

HOLD

CLOCK

OSCILLATOR

DAC

SAR

COMP

CONTROL

LOGIC

LATCH AND

THREE STATE

OUTPUT DRIVERS

AD7575

V

DD

AIN

AGND

V

REF

CLK

CS
RD

TP

BUSY

DGND

DB7

DB0

a

FEATURES
Fast Conversion Time: 5 ␮s
On-Chip Track/Hold
Low Total Unadjusted Error: 1 LSB
Full Power Signal Bandwidth: 50 kHz
Single +5 V Supply
100 ns Data Access Time
Low Power (15 mW typ)
Low Cost
Standard 18-Lead DlPs or 20-Terminal

Surface Mount Packages

GENERAL DESCRIPTION

The AD7575 is a high speed 8-bit ADC with a built-in track/
hold function. The successive approximation conversion tech-

nique is used to achieve a fast conversion time of 5 µs, while the
built-in track/hold allows full-scale signals up to 50 kHz (386 mV/µs

slew rate) to be digitized. The AD7575 requires only a single +5 V
supply and a low cost, 1.23 V bandgap reference in order to convert
an input signal range of 0 to 2 V

The AD7575 is designed for easy interfacing to all popular 8-bit
microprocessors using standard microprocessor control signals
(

CS and RD) to control starting of the conversion and reading of
the data. The interface logic allows the AD7575 to be easily
configured as a memory mapped device, and the part can be
interfaced as SLOW-MEMORY or ROM. All data outputs of
the AD7575 are latched and three-state buffered to allow direct
connection to a microprocessor data bus or I/O port.

The AD7575 is fabricated in an advanced, all ion-implanted high
speed Linear Compatible CMOS (LC
available in a small, 0.3" wide, 18-lead DIP, 18-lead SOIC or in
other 20-terminal surface mount packages.

REF

.

2

MOS) process and is

5 ␮s 8-Bit ADC with Track/Hold

AD7575

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Fast Conversion Time/Low Power

The fast, 5 µs, conversion time of the AD7575 makes it

suitable for digitizing wideband signals at audio and ultra­sonic frequencies while retaining the advantage of low
CMOS power consumption.

2. On-Chip Track/Hold
The on-chip track/hold function is completely self-contained
and requires no external hold capacitor. Signals with slew

rates up to 386 mV/µs (e.g., 2.46 V peak-to-peak 50 kHz sine

waves) can be digitized with full accuracy.

3. Low Total Unadjusted Error
The zero, full-scale and linearity errors of the AD7575 are so
low that the total unadjusted error at any point on the trans­fer function is less than 1 LSB, and offset and gain adjust­ments are not required.

4. Single Supply Operation
Operation from a single +5 V supply with a low cost +1.23 V
bandgap reference allows the AD7575 to be used in 5 V
microprocessor systems without any additional power
supplies.

5. Fast Digital Interface
Fast interface timing allows the AD7575 to interface easily to
the fast versions of most popular microprocessors such as the
Z80H, 8085A-2, 6502B, 68B09 and the DSP processor, the
TMS32010.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7575–SPECIFICATIONS

(VDD = +5 V, V
all specifications T

= +1.23 V, AGND = DGND = 0 V; f

REF

to T

MIN

unless otherwise noted)

MAX

= 4 MHz external;

CLK

Parameter J, A Versions1K, B Versions S Version T Version Units Conditions/Comments

ACCURACY

Resolution 8 8 8 8 Bits

Total Unadjusted Error ±2 ±1 ±2 ±1 LSB max
Relative Accuracy ±1 ±1/2 ±1 ±1/2 LSB max

Minimum Resolution for Which

No Missing Codes Is Guaranteed 8 8 8 8 Bits max

Full-Scale Error

+25°C ±1 ±1 ±1 ±1 LSB max Full-Scale TC Is Typically 5 ppm/°C

T

to T

MIN

Offset Error

MAX

2

±1 ±1 ±1 ±1 LSB max

+25°C ±1/2 ±1/2 ±1/2 ±1/2 LSB max Offset TC Is Typically 5 ppm/°C

T

MIN

to T

MAX

±1/2 ±1/2 ±1/2 ±1/2 LSB max

ANALOG INPUT

Voltage Range 0 to 2 V

REF

0 to 2 V

REF

0 to 2 V

REF

0 to 2 V

Volts 1 LSB = 2 V

REF

/256; See Figure 16

REF

DC Input Impedance 10 10 10 10 MΩ min
Slew Rate, Tracking 0.386 0.386 0.386 0.386 V/µs max

3

SNR

45 45 45 45 dB min VIN = 2.46 V p-p @ 10 kHz; See Figure 11

REFERENCE INPUT

V

(For Specified Performance) 1.23 1.23 1.23 1.23 Volts ±5%

REF

I

REF

500 500 500 500 µA max

LOGIC INPUTS

CS, RD

V

, Input Low Voltage 0.8 0.8 0.8 0.8 V max

INL

V

, Input High Voltage 2.4 2.4 2.4 2.4 V min

INH

IIN, Input Current

+25°C ±1 ±1 ±1 ±1 µA max V

T

to T

MIN

MAX

CIN, Input Capacitance

3

±10 ±10 ±10 ±10 µA max V

10 10 10 10 pF max

= 0 or V

IN

= 0 or V

IN

DD

DD

CLK

V

, Input Low Voltage 0.8 0.8 0.8 0.8 V max

lNL

V

, Input High Voltage 2.4 2.4 2.4 2.4 V min

INH

I

, Input Low Current 700 700 800 800 µA max V

INL

I

, Input High Current 700 700 800 800 µA max V

INH

INL

INH

= 0 V

= V

DD

LOGIC OUTPUTS

BUSY, DB0 to DB7

VOL, Output Low Voltage 0.4 0.4 0.4 0.4 V max I
VOH, Output High Voltage 4.0 4.0 4.0 4.0 V min I

= 1.6 mA

SINK

SOURCE

= 40 µA

DB0 to DB7

Floating State Leakage Current ±1 ±1 ±10 ±10 µA max V

OUT

= 0 to V

DD

Floating State Output Capacitance310 10 10 10 pF max

CONVERSION TIME

With External Clock 5 5 5 5 µsf

With Internal Clock, T

4

= 4 MHz

= +25°C5 5 5 5 µs min Using Recommended Clock

A

CLK

15 15 15 15 µs max Components Shown in Figure 15

POWER REQUIREMENTS

V

DD

I

DD

5

+5 +5 +5 +5 Volts ±5% for Specified Performance

6 6 7 7 mA max Typically 3 mA with VDD = +5 V

Power Dissipation 15 15 15 15 mW typ

Power Supply Rejection ±1/4 ±1/4 ±1/4 ±1/4 LSB max 4.75 V ≤ VDD ≤ 5.25 V

NOTES

1

Temperature ranges are as follows:

J, K Versions; 0°C to +70°C
A, B Versions; –25°C to +85°C
S, T Versions; –55°C to +125°C

2

Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB.

3

Sample tested at +25°C to ensure compliance.

4

Accuracy may degrade at conversion times other than those specified.

5

Power supply current is measured when AD7575 is inactive i.e., when CS = RD = BUSY = logic HIGH.

Specifications subject to change without notice.

–2–

REV. B

AD7575

WARNING!

ESD SENSITIVE DEVICE

DGND

3kV 10pF

DBN

TIMING SPECIFICATIONS

Limit at +25ⴗC Limit at T

1

(VDD = +5 V, V

MIN

= +1.23 V, AGND = DGND = 0 V)

REF

, T

MAX

Limit at T

MIN

, T

MAX

Parameter (All Versions) (J, K, A, B Versions) (S, T Versions) Units Conditions/Comments

t

1

t

2

2

t

3

t

4

t

5

2

t

6

3

t

7

0 0 0 ns min CS to RD Setup Time
100 100 120 ns max RD to BUSY Propagation Delay
100 100 120 ns max Data Access Time after RD
100 100 120 ns min RD Pulse Width
0 0 0 ns min CS to RD Hold Time
80 80 100 ns max Data Access Time after BUSY
10 10 10 ns min Data Hold Time
80 80 100 ns max

t

8

NOTES

1

Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10% to 90% of +5 V)
and timed from a voltage level of 1.6 V.

2

t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

3

t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.

Specifications subject to change without notice.

0 0 0 ns min BUSY to CS Delay

Test Circuits

+5V

3kV

DBN

10pF

DGND

DBN

3kV 100pF

DGND

+5V

3kV

DBN

100pF

DGND

a. High-Z to V

OH

b High-Z to V

OL

a. VOH to High-Z b. VOL to High-Z

Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test

ABSOLUTE MAXIMUM RATINGS*

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

DD

Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V

Digital Output Voltage to DGND . . . . . . –0.3 V, V

CLK Input Voltage to DGND . . . . . . . . . –0.3 V, V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

V

REF

AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

+ 0.3 V

DD

+ 0.3 V

DD

DD

DD

Operating Temperature Range

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C

Industrial (A, B Versions) . . . . . . . . . . . . . –25°C to +85°C

Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7575 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

AD7575

PIN CONFIGURATIONS

LCCC

CS

RD

BUSY

CLK

DB7 (MSB)

DB6
DB5

DGND

TP

1

2

3

4

AD7575

5

TOP VIEW

(Not to Scale)

6

7

8

9

18

V

17

V

16

AIN

15

AGND

14

DB0 (LSB)

13

DB1

12

DB2

11

DB3

10

DB4

DD

REF

BUSY

CLK

DB7 (MSB)

DB6
DB5

NC = NO CONNECT

3

4
5
6

(Not to Scale)

7
8

9 10111213

TPRDCS

2

AD7575

TOP VIEW

DGND

ORDERING GUIDE

Relative
Temperature Accuracy Package
Range (LSB) Options

2

Model

1

AD7575JR 0°C to +70°C ±1 max R-18
AD7575JN 0°C to +70°C ±1 max N-18
AD7575KN 0°C to +70°C ±1/2 max N-18
AD7575JP 0°C to +70°C ±1 max P-20A
AD7575KP 0°C to +70°C ±1/2 max P-20A
AD7575AQ –25°C to +85°C ±1 max Q-18
AD7575BQ –25°C to +85°C ±1/2 max Q-18
AD7575SQ –55°C to +125°C ±1 max Q-18
AD7575TQ –55°C to +125°C ±1/2 max Q-18
AD7575SE –55°C to +125°C ±1 max E-20A
AD7575TE –55°C to +125°C ±1/2 max E-20A

NOTES

1

To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
Drawing (SMD), see DESC drawing #5962-87762.

2

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip, R = SOIC.

PLCCDIP/SOIC

NC

NC

20 191

VDDV

DB4

REF

DB3

18

AIN
AGND

17
16

DB0 (LSB)

15

DB1

14

DB2

4

TP

5

BUSY

6

CLK

DB6

7
8

DB7 (MSB)

NC = NO CONNECT

RDCSNC

3 2 1 20 19

AD7575

TOP VIEW

(Not to Scale)

9 10 11 12 13

DB5

DGND

VDDV

PIN 1
IDENTIFIER

NC

DB4

REF

DB3

18

AIN

17

AGND

16

DB0 (LSB)

15

DB1

14

DB2

TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)

An ADC with 8-bits resolution can resolve 1 part in 28 (i.e.,

256) of full scale. For the AD7575 with +2.46 V full-scale one
LSB is 9.61 mV.

TOTAL UNADJUSTED ERROR

This is a comprehensive specification that includes full-scale
error, relative accuracy and offset error.

RELATIVE ACCURACY

Relative Accuracy is the deviation of the ADC’s actual code
transition points from a straight line drawn between the devices
measured first LSB transition point and the measured full-scale
transition point.

SNR

Signal-to-Noise Ratio (SNR) is the ratio of the desired signal to
the noise produced in the sampled and digitized analog signal.
SNR is dependent on the number of quantization levels used in
the digitization process; the more levels, the smaller the quantiza­tion noise. The theoretical SNR for a sine wave input is given by

SNR = (6.02 N + 1.76) dB

where N is the number of bits in the ADC.

FULL-SCALE ERROR (GAIN ERROR)

The gain of a unipolar ADC is defined as the difference between
the analog input levels required to produce the first and the last
digital output code transitions. Gain error is a measure of the
deviation of the actual span from the ideal span of FS – 2 LSBs.

ANALOG INPUT RANGE

With V

= +1.23 V, the maximum analog input voltage range

REF

is 0 V to +2.46 V. The output data in LSBs is related to the
analog input voltage by the integer value of the following
expression:

Data (LSBs) =

256 AIN
2 V

REF

+ 0.5

SLEW RATE

Slew Rate is the maximum allowable rate of change of input
signal such that the digital sample values are not in error. Slew
Rate limitations may restrict the analog signal bandwidth for
full-scale analog signals below the bandwidth allowed from
sampling theorem considerations.

–4–

REV. B