Analog Devices AD7537 Datasheet
LC2MOS
a
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full temperature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1,
loaded to the input registers when
transfer this data to the DAC registers,
with
WR.
Added features on the AD7537 include an asynchronous
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
2
MOS) process. It is speed compatible with most
CS, WR and UPD. Data is
CS and WR are low. To
UPD must be taken low
CLR
(8+4) Loading Dual 12-Bit DAC
AD7537
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V V
tolerance on this nominal figure. All specifications are
guaranteed over this range.
, with ±10%
DD
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD7537–SPECIFICA TIONS
(VDD = +12 V to +15 V, 610%, V
I
= AGNDB = 0 V. All specifications T
OUTB
REFA
= V
= 10 V; I
REFB
to T
MIN
= AGND = 0 V,
OUTA
unless otherwise noted.)
MAX
Parameter Versions Versions Versions Version Version Version Units Test Conditions/Comments
J, A K, B L, C S T U
ACCURACY
Resolution 12 12 12 12 12 12 Bits
Relative Accuracy ±1 ±1/2 ±1/2 ± 1 ±1/2 ±1/2 LSB max
Differential Nonlinearity ±1 ±1 ±1 ±1 ±1 ±1 LSB max All grades guaranteed mono-
tonic over temperature.
Gain Error ±6 ±3 ±1 ±6 ±3 ±2 LSB max Measured using R
Both DAC registers loaded
Gain Temperature Coefficient
2
;
with all 1s.
FBA
, R
FBB
.
∆Gain/∆Temperature ±5 ±5 ±5 ±5 ±5 ±5 ppm/°C max Typical value is 1 ppm/°C
Output Leakage Current
I
OUTA
+25°C 10 10 10 10 10 10 nA max DAC A Register loaded
T
to T
MIN
MIN
to T
MAX
MAX
I
OUTB
+25°C 10 10 10 10 10 10 nA max DAC B Register loaded
T
150 150 150 250 250 250 nA max with all 0s
150 150 150 250 250 250 nA max with all 0s
REFERENCE INPUT
Input Resistance 999999kΩ min Typical Input Resistance = 14 kΩ
20 20 20 20 20 20 kΩ max
V
, V
REFA
REFB
Input Resistance Match ±3 ±3 ± 1 ±3 ±3 ±1 % max Typically ±0.5%
DIGITAL INPUTS
V
(lnput High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min
IH
V
(Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max
IIL
I
(Input Current)
IN
+25°C ±1 ±1 ±1 ±1 ±1 ±1 µA max V
T
to T
MIN
CIN (lnput Capacitance)
POWER SUPPLY
V
DD
I
DD
MAX
3
2
±10 ±10 ±10 ±10 ±10 ±10 µA max
10 10 10 10 10 10 pF max
10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max
222222mA max
IN
= V
DD
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(VDD = +12 V to +15 V; V
Parameter TA = +258CTA = T
Output Current Settling Time 1.5 µs max To 0.01% of full-scale range. I
Digital-to-Analog Glitch lmpulse 7 nV-s typ Measured with V
to I
to I
to I
to I
4
OUTA
OUTB
DD
OUTB
OUTA
AC Feedthrough
V
REFA
V
REFB
Power Supply Rejection
∆Gain/∆V
Output Capacitance
C
OUTA
C
OUTB
C
OUTA
C
OUTB
Channel-to-Channel Isolation
V
REFA
V
REFB
Digital Crosstalk 7 nV-s typ Measured for a Code Transition of all 0s to all 1s.
Output Noise Voltage Density 25 nV/√Hz typ Measured between R
(10 Hz–100 kHz) Frequency of measurement is 10 Hz–100 kHz.
Total Harmonic Distortion –82 dB typ VIN = 6 V rms, 1 kHz. Both DACs loaded with all 1s.
NOTES
1
Temperature range as follows: J, K, L Versions: –40°C to +85°C;
Specifications subject to change without notice.
= V
REFA
= +10 V; I
REFB
OUTA
–70 –65 dB max V
–70 –65 dB max DAC registers loaded with all 0s.
±0.01 ± 0.02 % per % max ∆VDD = VDD max – VDD min
70 70 pF max DAC A, DAC B loaded with all 0s
70 70 pF max
140 140 pF max DAC A, DAC B loaded with all 1s
140 140 pF max
–84 dB typ V
–84 dB typ V
A, B, C Versions: –40°C to +85°C;
S, T, U Versions: –55°C to +125°C
= AGNDA = 0 V, I
MIN
, T
Units Test Conditions/Comments
MAX
2
Sample tested at +25°C to ensure compliance.
3
Functional at VDD = 5 V, with degraded specifications.
4
Pin 12 (DGND) on ceramic DIPs is connected to lid.
= AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)
OUTB
load = 100 Ω, C
DAC output measured from falling edge of
OUT
WR.
EXT
Typical Value of Settling Time is 0.8 µs.
= V
FBA
REFB
and I
= 0 V. I
= 13 pF.
EXT
OUTA
C
= 13 pF. DAC registers alternately loaded with all 0s and all 1s.
EXT
, V
REFA
= 20 V p-p 10 kHz sine wave, V
REFA
Both DACs loaded with all 1s.
= 20 V p-p 10 kHz sine wave, V
REFB
Both DACs loaded with all 1s.
I
, I
OUTA
OUTB
REFA
= 20 V p-p 10 kHz sine wave.
REFB
load = 100 Ω, C
or R
OUTA
REFB
REFA
FBB
, I
OUTB
= 0 V.
= 0 V.
and I
load = 100 Ω,
OUTB.
= 13 pF.
–2–
REV. 0
AD7537
WARNING!
ESD SENSITIVE DEVICE
TIMING CHARACTERISTICS
(VDD = +10.8 V to +16.5 V, V
REFA
= V
= +10 V; I
REFB
= AGNDA = 0 V, I
OUTA
= AGNDB = 0 V.)
OUTB
Limit at Limit at
Limit at T
= –408CT
A
= +558C
A
Parameter TA = +258C to +858C to +1258C Units Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
V
, V
REFA
RFBA
, V
REFB
RFBB
V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
I
, I
OUTA
OUTB
AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
15 15 30 ns min Address Valid to Write Setup Time
15 15 25 ns min Address Valid to Write Hold Time
60 80 80 ns min Data Setup Time
25 25 25 ns min Data Hold Time
0 0 0 ns min Chip Select or Update to Write Setup Time
0 0 0 ns min Chip Select or Update to Write Hold Time
80 80 100 ns min Write Pulse Width
80 80 100 ns min Clear Pulse Width
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C
Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C
to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V
to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V
+0.3 V
DD
to DGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
+0.3 V
DD
Extended Hermetic (S, T, U Versions) . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7537 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
Figure 1. Timing Diagram
1
Model
ORDERING GUIDE
2
Temperature Relative Gain Package
Range Accuracy Error Option
AD7537JN –40°C to +85°C ±1 LSB ±6 LSB N-24
AD7537KN –40°C to +85°C ±1/2 LSB ±3 LSB N-24
AD7537LN –40°C to +85°C ±1/2 LSB ±1 LSB N-24
AD7537JP –40°C to +85°C ±1 LSB ±6 LSB P-28A
AD7537KP –40°C to +85°C ± 1/2 LSB ±3 LSB P-28A
AD7537LP –40°C to +85°C ±1/2 LSB ±1 LSB P-28A
AD7537AQ –40°C to +85°C ±1 LSB ±6 LSB Q-24
AD7537BQ –40°C to +85°C ±1/2 LSB ±3 LSB Q-24
AD7537CQ –40°C to +85°C ±1/2 LSB ±1 LSB Q-24
AD7537SQ –55°C to +125°C ±1 LSB ±6 LSB Q-24
AD7537TQ –55°C to +125°C ±1/2 LSB ±3 LSB Q-24
AD7537UQ –55°C to +125°C ±1/2 LSB ±2 LSB Q-24
AD7537SE –55°C to +125°C ± 1 LSB ±6 LSB E-28A
AD7537TE –55°C to +125°C ± 1/2 LSB ±3 LSB E-28A
AD7537UE –55°C to +125°C ±1/2 LSB ±2 LSB E-28A
NOTES
1
Analog Devices reserves the right to ship ceramic packages (D-24A) in lieu of
cerdip packages (Q-24).
2
To order MIL-STD-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
–3–
3
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