ANALOG DEVICES AD7533 Service Manual

CMOS Low Cost,

FEATURES

Low cost 10-bit DAC
Low cost AD7520 replacement
Linearity: ½ LSB, 1 LSB, or 2 LSB
Low power dissipation
Full 4-quadrant multiplying DAC
CMOS/TTL direct interface
Latch free (protection Schottky not required)
Endpoint linearity

APPLICATIONS

Digitally controlled attenuators
Programmable gain amplifiers
Function generation
Linear automatic gain controls

V

REF

20kΩ

S1 S2 S3 SN

BIT 1 (MSB) BIT 10 (LS B)

GENERAL DESCRIPTION

The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC
manufactured using an advanced thin-film-on-monolithic­CMOS wafer fabrication process.

Pin and function equivalent to the AD7520 industry standard,
the AD7533 is recommended as a lower cost alternative for old
AD7520 sockets or new 10-bit DAC designs.

AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on 5 V to 15 V power, and
provide proper binary scaling for reference inputs of either
positive or negative polarity.

FUNCTIONAL BLOCK DIAGRAM

10kΩ

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)

10kΩ 10kΩ

20kΩ 20kΩ 20k Ω

BIT 2 BIT 3

Figure 1.

10-Bit Multiplying DAC

AD7533

20kΩ

I

2

OUT

I

1

OUT

10kΩ

R

FB

01134-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD7533

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Te r mi n ol o g y ...................................................................................... 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

3/07—Rev. B to Rev. C

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Figure 13, Figure 14, and Figure 17 ........................... 9

Updated Outline Dimensions....................................................... 10

Changes to Ordering Guide.......................................................... 12

1/06—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings....................................... 4

Added Pin Configurations

and Function Descriptions Section................................................ 6

Updated Outline Dimensions....................................................... 10

Changes to Ordering Guide.......................................................... 12

Circuit Description............................................................................7

General Circuit Information........................................................7

Equivalent Circuit Analysis .........................................................7

Operation............................................................................................8

Unipolar Binary Code ..................................................................8

Bipolar (Offset Binary) Code.......................................................8

Applications........................................................................................9

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 12

3/04—Rev. 0 to Rev. A

Changes to Specifications.................................................................2

Changes to Absolute Maximum Ratings........................................3

Changes to Ordering Guide.............................................................3

Updated Outline Dimensions..........................................................7

Rev. C | Page 2 of 12

AD7533

SPECIFICATIONS

VDD = 15 V, V

Table 1.

Parameter TA = 25°C TA = Operating Range Test Conditions

STATIC ACCURACY

Resolution 10 Bits 10 Bits
Relative Accuracy

AD7533JN, AD7533AQ,
AD7533SQ, AD7533JP

AD7533KN, AD7533BQ,
AD7533KP, AD7533TE

AD7533LN, AD7533CQ, AD7533UQ ±0.05% FSR maximum ±0.05% FSR maximum
DNL ±1 LSB maximum ±1 LSB maximum
Gain Error

Supply Rejection

∆Gain/∆V

Output Leakage Current

I

1 ±5 nA maximum ±200 nA maximum Digital inputs = V

OUT

I

2 ±5 nA maximum ±200 nA maximum Digital inputs = V

OUT

DYNAMIC ACCURACY

Output Current Settling Time 600 ns maximum

Feedthrough Error ±0.05% FSR maximum

Propagation Delay 100 ns typical 100 ns typical
Glitch Impulse 100 nV-s typical 100 nV-s typical

REFERENCE INPUT

Input Resistance (VREF) 5 kΩ min, 20 kΩ maximum 5 kΩ min, 20 kΩ maximum611 kΩ nominal

ANALOG OUTPUTS

Output Capacitance

C

IOUT1

C

IOUT2

C

IOUT1

C

IOUT2

DIGITAL INPUTS

Input High Voltage (V
Input Low Voltage (V
Input Leakage Current (IIN) ±1 μA maximum ±1 μA maximum VIN = 0 V and V
Input Capacitance (CIN) 8 pF maximum

POWER REQUIREMENTS

V

DD

VDD Ranges
I

DD

25 μA maximum 50 μA maximum Digital inputs over V

1

FSR = full-scale range.

2

Full scale (FS) = V

3

Maximum gain change from TA = 25°C to T

4

AC parameter, sample tested to ensure specification compliance.

5

Guaranteed, not tested.

6

Absolute temperature coefficient is approximately −300 ppm/°C.

OUT

5

DD

2, 3

REF

1 = V

1

4

.

2 = 0 V, V

OUT

= 10 V, unless otherwise noted.

REF

±0.2% FSR maximum ±0.2% FSR maximum

±0.1% FSR maximum ±0.1% FSR maximum

±1% FS maximum ±1% FS maximum Digital input = V

0.001%/% maximum 0.001%/% maximum Digital inputs = V

4

50 pF maximum
20 pF maximum
30 pF maximum
50 pF maximum

) 2.4 V minimum 2.4 V minimum

INH

) 0.8 V maximum 0.8 V maximum

INL

5

5

5

5

5

800 ns5

5

±0.1% FSR maximum

100 pF maximum
35 pF maximum
35 pF maximum
100 pF maximum

8 pF maximum

5

5

5

5

5

5

15 V ± 10% 15 V ± 10% Rated accuracy
5 V to 16 V 5 V to 16 V Functionality with degraded performance
2 mA maximum 2 mA maximum Digital inputs = V

or T

MIN

is ±0.1% FSR.

MAX

INH

To 0.05% FSR; R
inputs = V

INH

LOAD

to V

Digital inputs = V
100 kHz sine wave

Digital inputs = V

Digital inputs = V

DD

, VDD = 14 V to 17 V

INH

, V

= ±10 V

INL

REF

, V

= ±10 V

INH

REF

= 100 Ω, digital

or V

INL

INH

INL

INL

, V

or V

IN

REF

to V

INL

INH

= ±10 V,

D

INH

INL

Rev. C | Page 3 of 12

AD7533

ABSOLUTE MAXIMUM RATINGS

TA = 25 °C unless otherwise noted.

Table 2.

Parameter Rating

VDD to GND −0.3 V, +17 V
RFB to GND ±25 V
V

to GND ±25 V

REF

Digital Input Voltage Range −0.3 V to VDD + 0.3 V
I

1, I

OUT

Power Dissipation (Any Package)

Operating Temperature Range

Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C

2 to GND −0.3 V to V

OUT

To 75°C 450 mW
Derates above 75°C by 6 mW/°C

Plastic (JN, JP, KN, KP, LN Versions) −40°C to +85°C
Hermetic (AQ, BQ, CQ Versions) −40°C to +85°C
Hermetic (SQ, TE, UQ Versions) −55°C to +125°C

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 4 of 12

AD7533

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for ideal zero and full scale and is expressed in % of
full-scale range or (sub) multiples of 1 LSB.

Resolution

Value of the LSB. For example, a unipolar converter with n bits
has a resolution of (2
a resolution of [2

–(n–1)

–n

) (V

). A bipolar converter of n bits has

REF

] (V

). Resolution in no way implies

REF

linearity.

Settling Time

Time required for the output function of the DAC to settle to
within ½ LSB for a given digital input stimulus, that is, 0 to
full scale.

Gain Error

Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error is adjusted out and is expressed in LSBs.
Gain error is adjustable to zero with an external potentiometer.

Feedthrough Error

Error caused by capacitive coupling from V

to output with all

REF

switches off.

Output Capacitance

Capacity from I

OUT

1 and I

2 terminals to ground.

OUT

Output Leakage Current

Current that appears on I
low or on I

2 terminal when all inputs are high.

OUT

1 terminal with all digital inputs

OUT

Rev. C | Page 5 of 12

AD7533

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

I

1

1

OUT

2

I

2

OUT

GND

3

AD7533

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

TOP VIEW

4

(Not to Scale)

5

6

7

8

Figure 2. 16-Lead PDIP Pin Configuration

I

1

1

OUT

2

I

2

OUT

3

GND

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

AD7533

4

TOP VIEW

(Not to Scale)

5

6

7

8

Figure 3. 16-Lead SOIC Pin Configuration

I

1 1

OUT

2

I

2

OUT

GND 3

BIT 1 (M SB) 4

BIT 2

BIT 3 6 BI T 811

BIT 4 7 BI T 710

BIT 5 8 BI T 69

AD7533

TOP VIEW

(Not to Scale)

5

Figure 4. 16-Lead CERDIP Pin Configuration

R

16

FB

V

15

REF

14

V

DD

13

BIT 10 (LSB)

BIT 9

12

BIT 8

11

10

BIT 7

BIT 6

9

01134-002

R

16

FB

15

V

REF

14

V

DD

BIT 10 (LSB)

13

BIT 9

12

11

BIT 8

BIT 7

10

9

BIT 6

01134-003

BIT 1 (MSB)

NC = NO CONNECT

BIT 1 (MSB)

R

16

FB

15

V

REF

V

14

DD

BIT 10 (LS B)13

12

BIT 9

01134-004

4

GND

5

6

NC

7

BIT 2

8

BIT 3

Figure 5. 20-Terminal LCC Pin Configuration

4

GND

5

6

NC

BIT 2

7

8

BIT 3

Figure 6. 20-Lead PLCC Pin Configuration

1

FB

OUT

OUT

R

I

I

3

19

20

1NC2

AD7533

TOP VIEW

(Not to Scale)

13

11NC10

BIT 59BIT 4

2

1

OUT

I

NC

1201923

PIN 1
INDENTFIER

AD7533

TOP VIEW

BIT 5NCBIT 6

FB

R

OUT

I

(Not to scale)

91011 12 13

BIT 4

NC = NO CONNECT

REF

V

BIT 712BIT 6

REF

V

BIT 7

18

V

DD

17

BIT 10 (LSB)

16

NC

15

BIT 9

14

BIT 8

18

V

DD

17

BIT 10 (LS B)

16

NC

BIT 9

15

14

BIT 8

01134-005

01134-006

Table 3. Pin Function Descriptions

Pin Number

16-Lead PDIP, SOIC, CERDIP 20-Lead LCC, PLCC Mnemonic Description

1 2 I
2 3 I

1 DAC Current Output.

OUT

OUT

2

DAC Analog Ground. This pin should normally be tied to the
analog ground of the system.

3 4 GND Ground.
4 to 13 5, 7 to 10, 12 to 15, 17 BIT 1 to BIT 10 MSB to LSB.
14 18 V

DD

Positive Power Supply Input. These parts can be operated from
a supply of 5 V to 16 V.

15 19 V
16 20 R

REF

FB

DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC

by connecting R

to external amplifier output.

FB

NA 1, 6, 11, 16 NC No Connect.

Rev. C | Page 6 of 12

AD7533

V

V

V

CIRCUIT DESCRIPTION

GENERAL CIRCUIT INFORMATION

The AD7533 is a 10-bit multiplying DAC that consists of a
highly stable thin-film R-2R ladder and ten CMOS current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.

The simplified D/A circuit is shown in
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the I
thus maintaining a constant current in each ladder leg
independent of the switch state.

V

REF

BIT 1 (MSB) BIT 10 (LS B)

10kΩ

20kΩ

S1 S2 S3 SN

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)

10kΩ 10k Ω

20kΩ 20kΩ 20kΩ

BIT 2 BIT 3

Figure 7. Functional Diagram

One of the CMOS current switches is shown in Figure 8. The
geometries of Device 1, Device 2, and Device 3 are optimized to
make the digital control inputs DTL/TTL/CMOS compatible
over the full military temperature range. The input stage drives
two inverters (Device 4, Device 5, Device 6, and Device 7),
which in turn drive the two output N channels. The on
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA,
and so on, thus maintaining a constant 10 mV drop across each
switch. It is essential that each switch voltage drop be equal if
the binarily weighted current division property of the ladder is
to be maintained.

Figure 7. An inverted

OUT

1 and I

2 bus lines,

OUT

10kΩ

20kΩ

I

I

R

OUT

OUT

2

1

FB

+

DTL/TTL/

CMOS
INPUT

250Ω

13

2

6

4

7

5

89

2

OUT

TO LADDER

I

1I

OUT

01134-007

Figure 8. CMOS Switch

EQUIVALENT CIRCUIT ANALYSIS

The equivalent circuits for all digital inputs high and digital
inputs low are shown in
all digital inputs low, the reference current is switched to I
The current source I
leakages to the substrate, while the I/1024 current source represents
a constant 1-bit current drain through the termination resistor
on the R-2R ladder. The on capacitance of the output N channel
switch is 100 pF, as shown on the I
capacitance is 35 pF, as shown on the I
the circuit for all digital inputs high, as shown in

01134-001

similar to
Ter m in a l I

Figure 9; however, the on switches are now on

1. Therefore, there is the 100 pF at that terminal.

OUT

R 10kΩ

I

REF

REF

R

Figure 9. Equivalent Circuit—All Digital Inputs Low

I

REF

REF

R

Figure 10. Equivalent Circuit—All Digital Inputs High

Figure 9 and Figure 10. In Figure 9 with

is composed of surface and junction

LEAKAGE

2 terminal. The off switch

OUT

1 terminal. Analysis of

OUT

Figure 10, is

R

I

I

R

I

I

FB

OUT

OUT

FB

OUT

OUT

I/1024

R 10kΩ

I/1024

I

LEAKAGE

I

LEAKAGE

I

LEAKAGE

I

LEAKAGE

R

35pF

100pF

R

100pF

35pF

2.

OUT

1

2

01134-008

1

2

01134-009

Rev. C | Page 7 of 12

AD7533

OPERATION

UNIPOLAR BINARY CODE

BIPOLAR (OFFSET BINARY) CODE

Table 4. Unipolar Binary Operation
(2-Quadrant Multiplication)

Digital Input Analog Output

MSB LSB (V

1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0

−

−

−

−

−

−

as shown in Figure 11)

OUT

1023

⎞

⎛

V

⎜

REF

⎝
⎛

V

⎜

REF

⎝

⎛

V

⎜

REF

⎝
⎛

V

⎜

REF

⎝
⎛

V

⎜

REF

⎝
⎛

V

⎜

REF

⎝

1024

513

1024

512

511

1024

1

1024

0

1024

⎟
⎠

⎞
⎟
⎠

⎛

⎞

=

⎜

⎟

⎝

⎠
⎞

⎟
⎠

⎞
⎟
⎠

⎞

0

=

⎟
⎠

V

⎞

REF

⎟

21024

⎠

Nominal LSB magnitude for the circuit of Figure 11 is given by

1

⎞

⎛

=

VLSB

⎜

REF

⎝

1024

⎟
⎠

BIPOLAR

ANALOG INP UT

±10V

R1

1kΩ

MSB

LSB

4

13

UNIPOLAR

DIGITAL

INPUT

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUST MENT IS REQUIRED.

2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.

V

15

AD7533

GND

REF

V

DD

R2

R

14

3

330Ω

FB

16

I

OUT

1

2

I

OUT

C1

1

V

OUT

2

Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)

Table 5. Unipolar Binary Operation
(4-Quadrant Multiplication)

Digital Input Analog Output

MSB LSB (V

1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 1

+

+

as shown in Figure 12)

OUT

511

⎞

⎛
⎜
⎝

⎛
⎜
⎝

512

1

512

⎟
⎠

⎞
⎟
⎠

V

REF

V

REF

1 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0

−

−

−

1

⎞

⎛
⎜
⎝

⎛
⎜
⎝

⎛
⎜
⎝

512

511

512

512
512

⎟
⎠

⎞
⎟
⎠

⎞
⎟
⎠

V

REF

V

REF

V

REF

Nominal LSB magnitude for the circuit of Figure 12 is given by

1

⎞

⎛

=

VLSB

REF

⎜
⎝

512

⎟
⎠

BIPOLAR

ANALOG I NPUT

V

±10V

DD

R1

1kΩ

V

REF

14

15

MSB

LSB

4

AD7533

13

3

GND

BIPOLAR

DIGI TAL

INPUT

NOTES

1. R3, R4 , AND R5 SELE CTED FOR M ATCHING A ND TRACKING .

2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

3. C1 PHASE COMPENSATION (5pF TO 15pF) M AY BE REQUIRED
WHEN USING HIG H SPEED AMPLIFIERS.

R2

330Ω

16

1

2

C1

I

1

OUT

I

2

OUT

Figure 12. Bipolar Operation (4-Quadrant Multiplication)

01134-010

R4

20kΩ

R3

10kΩ

A1

5kΩ

R5

20kΩ

A2

V

OUT

R6

01134-011

Rev. C | Page 8 of 12

AD7533

V

V

T

01134

015

APPLICATIONS

V

BIT 1

DIGITAL

INPUT

“D”

BIT 10

I

I

OUT

OUT

IN

2

1

MSB

LSB

2

1

R

FB

16

AD7533

3

GND

Figure 15. Divider (Digitally Controlled Gain)

REF

15

4

AD7533

13

3

GND

Figure 16. Modified Scale Factor and Offset

DIGITAL

INPUT

+15

14

15

+15V

14

MAGNITUDE
BITS

SIGN BIT

DIGITAL

FREQUENCY

CONTROL

WORD

MSB

4

LSB

13

V

REF

V

OUT

R

FB

16

I

OUT

1

2

I

OUT

V

OUT

where:

D= +

BIT 1
DIGITAL

INPUT
“D”

BIT 10

V

OUT

where:

0 < D ≤

1

2

= V

REF

BIT 1

2

0 < D ≤

1

ANALOG INPUT

MSB

LSB

13

CALIBRATE

MSB

4

LSB

13

–V

IN

=

D

BIT 1

D= +

1

2
1023
1024

R1

–V

R

= –

R1 + R

BIT 2

2

2
1023
1024

BIPOLAR

V

15

AD7533

REF

3

GND

V

DD

R

14

FB

16

I

1

OUT

1

2

I

2

OUT

OP97

±10V

4

Figure 13. 10-Bit and Sign Multiplying DAC

10V

15

+15V

V

V

REF

AD7533

3

GND

NC

DD

14

16

I

1

OUT

1

I

OUT

2

6.8V
(2)

2

1kΩ

10kΩ

1%

C

OP97

t

Figure 14. Programmable Function Generator

DIGITAL

INPUT

(TEST LIMIT)

BIT 10

BIT 2

+…

2

10

2

2

01134-014

.

V

OU

R2

REFD

R1D

2

R

+ R

2

1

2

BIT 10

+…

10

2

-

10kΩ

10kΩ

1/2 AD7512DIJN

V

5kΩ

OUT

OP97

4.7kΩ

1

tCt

10

REF

15

SQUARE
WAVE

TRIANGULAR
WAVE

)

+15V

AD7533

3

14

01134-013

TEST INPUT

(0 TO – V

REF

16

I

OUT

1

2

I

OUT

OP97

10kΩ

1%

f = N ( )

8

R

= 10kΩ

R

t

0 < N ≤ (1 2

V

MSB

4

LSB

13

GND

Figure 17. Digitally Programmable Limit Detector

01134-012

)

1

2

AD790
COMPARATOR

FAIL/PASS
TEST

01134-016

Rev. C | Page 9 of 12

AD7533

C

OUTLINE DIMENSIONS

0.800 (20.32)

0.790 (20.07)

0.780 (19.81)

16

1

0.100 (2.54)
BSC

0.210 (5.33)
MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

CONTROLL ING DIMENSIONS ARE IN INCHES; MI LLIME TER DIMENSI ONS
(IN PARENTHESES) ARE ROUNDED-O FF INCH E QUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROP RIATE FOR USE I N DESIGN.
CORNER LEADS M AY BE CONFIGURED AS WHOL E OR HALF L EADS.

Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP]

10.50 (0.4134)

10.10 (0.3976)

9

0.280 (7. 11)

0.250 (6.35)

0.240 (6.10)

8

0.060 (1.52)

0.015
(0.38)

0.015 (0.38)

MIN

SEATING
PLANE

0.005 (0.13)
MIN

COMPLIANT TO JEDEC STANDARDS MS-001-AB

GAUGE

PLANE

MAX

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

(N-16)

Dimensions shown in inches and (millimeters)

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

073106-B

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

0
0

.

7

.

2

5

(

0

5

(

0

.

0

2

9

5

)

0

0

9

8

)

.

1.27 (0.0500)

0.40 (0.0157)

45°

112906-B

0.30 (0.0 118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013- AA

Figure 19. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

Rev. C | Page 10 of 12

AD7533

0

0.005 (0.13) MIN

16

1

PIN 1

0.100 (2.54) BSC

0.840 (21.34) MAX

.200 (5.08)

MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.098 (2.49) MAX

9

0.310 (7.87)

0.220 (5.59)

8

0.070 (1.78)

0.030 (0.76)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Figure 20. 16-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-16)

Dimensions shown in inches and (millimeters)

20

1

VIEW

0.150 (3.81)
BSC

0.200 (5.08)
REF

0.100 (2.54) REF

0.015 (0.38)
MIN

3

4

0.028 (0.71)

0.022 (0.56)

0.050 (1.27)

8

BSC

9

45° TYP

0.100 (2.54)

0.064 (1.63)

0.358 (9.09)

0.342 (8.69)
SQ

0.088 (2.24)

0.054 (1.37)

0.358

(9.09)

MAX

SQ

0.075 (1.91)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075 (1.91)
REF

0.055 (1.40)

0.045 (1.14)

REF

19

18

14

13

BOTTOM

CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETE R DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

022106-A

Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-20-1)

Dimensions shown in inches and (millimeters)

BSC

0.180 (4.57)

0.165 (4.19)

0.120 (3.04)

0.090 (2.29)

(P-20)

0.20 (0.51)
MIN

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.045 (1.14)

0.025 (0.64)

0.020 (0.50)

0.330 (8.38)

0.290 (7.37)

R

R

BOTTOM

VIEW

(PINS UP)

0.048 (1.22)

0.042 (1.07)

0.020

(0.51)

0.048 (1.22 )

0.042 (1.07)

3

4

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

8

9

0.356 (9.04)

R

0.350 (8.89)

0.395 (10.03)

0.385 (9.78)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.056 (1.42)

0.042 (1.07)

19

18

0.050
(1.27)

14

13

SQ

SQ

COMPLIANT TO JEDEC STANDARDS MO-047-AA

Figure 22. 20-Lead Plastic Leaded Chip Carrier [PLCC]

Dimensions shown in inches and (millimeters)

Rev. C | Page 11 of 12

AD7533

ORDERING GUIDE

Nonlinearity

Model Temperature Range Package Description Package Option

AD7533ACHIPS DIE
AD7533JN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.2
AD7533JNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.2
AD7533KN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.1
AD7533KNZ

1

−40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.1
AD7533LN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.05
AD7533LNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.05
AD7533JP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JPZ
AD7533JPZ-REEL

1

−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2

1

−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533KP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KPZ

1

−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KPZ-REEL1−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KRZ

1

−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KRZ-REEL1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533AQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.2
AD7533BQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.1
AD7533CQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533SQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.2
AD7533UQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533UQ/883B −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533TE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1 ±0.1

1

Z = RoHS compliant part.

(% FSR max)

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01134-0-3/07(C)

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Rev. C | Page 12 of 12

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