ANALOG DEVICES AD7533 Service Manual

CMOS Low Cost,

FEATURES

Low cost 10-bit DAC
Low cost AD7520 replacement
Linearity: ½ LSB, 1 LSB, or 2 LSB
Low power dissipation
Full 4-quadrant multiplying DAC
CMOS/TTL direct interface
Latch free (protection Schottky not required)
Endpoint linearity

APPLICATIONS

Digitally controlled attenuators
Programmable gain amplifiers
Function generation
Linear automatic gain controls

V

REF

20kΩ

S1 S2 S3 SN

BIT 1 (MSB) BIT 10 (LS B)

GENERAL DESCRIPTION

The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC
manufactured using an advanced thin-film-on-monolithic­CMOS wafer fabrication process.

Pin and function equivalent to the AD7520 industry standard,
the AD7533 is recommended as a lower cost alternative for old
AD7520 sockets or new 10-bit DAC designs.

AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on 5 V to 15 V power, and
provide proper binary scaling for reference inputs of either
positive or negative polarity.

FUNCTIONAL BLOCK DIAGRAM

10kΩ

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)

10kΩ 10kΩ

20kΩ 20kΩ 20k Ω

BIT 2 BIT 3

Figure 1.

10-Bit Multiplying DAC

AD7533

20kΩ

I

2

OUT

I

1

OUT

10kΩ

R

FB

01134-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD7533

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Te r mi n ol o g y ...................................................................................... 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

3/07—Rev. B to Rev. C

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Figure 13, Figure 14, and Figure 17 ........................... 9

Updated Outline Dimensions....................................................... 10

Changes to Ordering Guide.......................................................... 12

1/06—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings....................................... 4

Added Pin Configurations

and Function Descriptions Section................................................ 6

Updated Outline Dimensions....................................................... 10

Changes to Ordering Guide.......................................................... 12

Circuit Description............................................................................7

General Circuit Information........................................................7

Equivalent Circuit Analysis .........................................................7

Operation............................................................................................8

Unipolar Binary Code ..................................................................8

Bipolar (Offset Binary) Code.......................................................8

Applications........................................................................................9

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 12

3/04—Rev. 0 to Rev. A

Changes to Specifications.................................................................2

Changes to Absolute Maximum Ratings........................................3

Changes to Ordering Guide.............................................................3

Updated Outline Dimensions..........................................................7

Rev. C | Page 2 of 12

AD7533

SPECIFICATIONS

VDD = 15 V, V

Table 1.

Parameter TA = 25°C TA = Operating Range Test Conditions

STATIC ACCURACY

Resolution 10 Bits 10 Bits
Relative Accuracy

AD7533JN, AD7533AQ,
AD7533SQ, AD7533JP

AD7533KN, AD7533BQ,
AD7533KP, AD7533TE

AD7533LN, AD7533CQ, AD7533UQ ±0.05% FSR maximum ±0.05% FSR maximum
DNL ±1 LSB maximum ±1 LSB maximum
Gain Error

Supply Rejection

∆Gain/∆V

Output Leakage Current

I

1 ±5 nA maximum ±200 nA maximum Digital inputs = V

OUT

I

2 ±5 nA maximum ±200 nA maximum Digital inputs = V

OUT

DYNAMIC ACCURACY

Output Current Settling Time 600 ns maximum

Feedthrough Error ±0.05% FSR maximum

Propagation Delay 100 ns typical 100 ns typical
Glitch Impulse 100 nV-s typical 100 nV-s typical

REFERENCE INPUT

Input Resistance (VREF) 5 kΩ min, 20 kΩ maximum 5 kΩ min, 20 kΩ maximum611 kΩ nominal

ANALOG OUTPUTS

Output Capacitance

C

IOUT1

C

IOUT2

C

IOUT1

C

IOUT2

DIGITAL INPUTS

Input High Voltage (V
Input Low Voltage (V
Input Leakage Current (IIN) ±1 μA maximum ±1 μA maximum VIN = 0 V and V
Input Capacitance (CIN) 8 pF maximum

POWER REQUIREMENTS

V

DD

VDD Ranges
I

DD

25 μA maximum 50 μA maximum Digital inputs over V

1

FSR = full-scale range.

2

Full scale (FS) = V

3

Maximum gain change from TA = 25°C to T

4

AC parameter, sample tested to ensure specification compliance.

5

Guaranteed, not tested.

6

Absolute temperature coefficient is approximately −300 ppm/°C.

OUT

5

DD

2, 3

REF

1 = V

1

4

.

2 = 0 V, V

OUT

= 10 V, unless otherwise noted.

REF

±0.2% FSR maximum ±0.2% FSR maximum

±0.1% FSR maximum ±0.1% FSR maximum

±1% FS maximum ±1% FS maximum Digital input = V

0.001%/% maximum 0.001%/% maximum Digital inputs = V

4

50 pF maximum
20 pF maximum
30 pF maximum
50 pF maximum

) 2.4 V minimum 2.4 V minimum

INH

) 0.8 V maximum 0.8 V maximum

INL

5

5

5

5

5

800 ns5

5

±0.1% FSR maximum

100 pF maximum
35 pF maximum
35 pF maximum
100 pF maximum

8 pF maximum

5

5

5

5

5

5

15 V ± 10% 15 V ± 10% Rated accuracy
5 V to 16 V 5 V to 16 V Functionality with degraded performance
2 mA maximum 2 mA maximum Digital inputs = V

or T

MIN

is ±0.1% FSR.

MAX

INH

To 0.05% FSR; R
inputs = V

INH

LOAD

to V

Digital inputs = V
100 kHz sine wave

Digital inputs = V

Digital inputs = V

DD

, VDD = 14 V to 17 V

INH

, V

= ±10 V

INL

REF

, V

= ±10 V

INH

REF

= 100 Ω, digital

or V

INL

INH

INL

INL

, V

or V

IN

REF

to V

INL

INH

= ±10 V,

D

INH

INL

Rev. C | Page 3 of 12

AD7533

ABSOLUTE MAXIMUM RATINGS

TA = 25 °C unless otherwise noted.

Table 2.

Parameter Rating

VDD to GND −0.3 V, +17 V
RFB to GND ±25 V
V

to GND ±25 V

REF

Digital Input Voltage Range −0.3 V to VDD + 0.3 V
I

1, I

OUT

Power Dissipation (Any Package)

Operating Temperature Range

Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C

2 to GND −0.3 V to V

OUT

To 75°C 450 mW
Derates above 75°C by 6 mW/°C

Plastic (JN, JP, KN, KP, LN Versions) −40°C to +85°C
Hermetic (AQ, BQ, CQ Versions) −40°C to +85°C
Hermetic (SQ, TE, UQ Versions) −55°C to +125°C

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 4 of 12