Analog Devices AD7528 b Datasheet

CMOS Dual 8-Bit

V

REF

A

AD7528

V

REF

B

R

FB

B

AGND

V

DD

DB0

DB7

DATA

INPUTS

DAC A/

DAC B

CS

WR

DGND

CONTROL

LOGIC

INPUT

BUFFER

LATCH

LATCH

OUT B

OUT A

DAC B

DAC A

RFB A

a

Buffered Multiplying DAC

AD7528

FEATURES
On-Chip Latches for Both DACs
+5 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible
Latch Free (Protection Schottkys not Required)

APPLICATIONS
Digital Control of:

Gain/Attenuation
Filter Parameters
Stereo Audio Circuits
X-Y Graphics

GENERAL DESCRIPTION

The AD7528 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount
packages.

Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.

Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control
input DAC A/DAC B determines which DAC is to be loaded.
The AD7528’s load cycle is similar to the write cycle of a ran­dom access memory and the device is bus compatible with most
8-bit microprocessors, including 6800, 8080, 8085, Z80.

The device operates from a +5 V to +15 V power supply, dis­sipating only 20 mW of power.

Both DACs offer excellent four quadrant multiplication charac­teristics with a separate reference input and feedback resistor for
each DAC.

PRODUCT HIGHLIGHTS

1. DAC-to-DAC matching: since both of the AD7528 DACs are
fabricated at the same time on the same chip, precise match­ing and tracking between DAC A and DAC B is inherent.

Model

AD7528JN –40°C to +85°C ±1 LSB ±4 LSB N-20
AD7528KN –40°C to +85°C ±1/2 LSB ±2 LSB N-20
AD7528LN –40°C to +85°C ±1/2 LSB ±1 LSB N-20
AD7528JP –40°C to +85°C ±1 LSB ±4 LSB P-20A
AD7528KP –40°C to +85°C ±1/2 LSB ±2 LSB P-20A
AD7528LP –40°C to +85°C ±1/2 LSB ±1 LSB P-20A
AD7528JR –40°C to +85°C ±1 LSB ±4 LSB R-20
AD7528KR –40°C to +85°C ±1/2 LSB ±2 LSB R-20
AD7528LR –40°C to +85°C ±1/2 LSB ±1 LSB R-20
AD7528AQ –40°C to +85°C ±1 LSB ±4 LSB Q-20
AD7528BQ –40°C to +85°C ±1/2 LSB ±2 LSB Q-20
AD7528CQ –40°C to +85°C ±1/2 LSB ±1 LSB Q-20
AD7528SQ –55°C to +125°C ±1 LSB ±4 LSB Q-20
AD7528TQ –55°C to +125°C ±1/2 LSB ±2 LSB Q-20
AD7528UQ –55°C to +125°C ±1/2 LSB ±1 LSB Q-20

NOTES

1

Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts
will be marked with cerdip designator “Q.”

2

Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to
part number. For further information, see Analog Devices’ 1990 Military Products
Databook.

3

N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

The AD7528’s matched CMOS DACs make a whole new
range of applications circuits possible, particularly in the
audio, graphics and process control areas.

2. Small package size: combining the inputs to the on-chip DAC
latches into a common data bus and adding a DAC A/DAC B
select line has allowed the AD7528 to be packaged in either a
small 20-lead DIP, SOIC or PLCC.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

FUNCTIONAL BLOCK DIAGRAM

ORDERING GUIDE

Temperature Relative Gain Package

2

Ranges Accuracy Error Options

1

3

AD7528–SPECIFICATIONS

REF

A = V

B = +10 V; OUT A = OUT B = O V unless otherwise noted)

REF

(V

VDD = +5 V VDD = +15 V

Parameter Version1T

STATIC PERFORMANCE

2

= +25°CT

A

MIN

, T

MAXTA

= +25°CT

MIN

, T

Units Test Conditions/Comments

MAX

Resolution All 8 8 8 8 Bits
Relative Accuracy J, A, S ±1 ±1 ±1 ±1 LSB max This is an Endpoint Linearity Specification

K, B, T ±1/2 ±1/2 ±1/2 ±1/2 LSB max
L, C, U ±1/2 ±1/2 ±1/2 ±1/2 LSB max

Differential Nonlinearity All ±1 ±1 ±1 ±1 LSB max All Grades Guaranteed Monotonic Over
Gain Error J, A, S ± 4 ±6 ±4 ±5 LSB max Measured Using Internal R

K, B, T ±2 ±4 ±2 ±3 LSB max Both DAC Latches Loaded with 11111111

Full Operating Temperature Range

A and RFB B

FB

L, C, U ±1 ±3 ±1 ±1 LSB max Gain Error is Adjustable Using Circuits

Gain Temperature Coefficient

∆Gain/∆Temperature All ± 0.007 ±0.007 ±0.0035 ±0.0035 %/°C max

3

of Figures 4 and 5

Output Leakage Current

OUT A (Pin 2) All ±50 ±400 ±50 ±200 nA max DAC Latches Loaded with 00000000
OUT B (Pin 20) All ±50 ±400 ±50 ±200 nA max

Input Resistance (V

A/V

V

REF

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Current

Input Capacitance

B Input Resistance

REF

Match All ±1 ±1 ±1 ±1% max

V

IH

V

IL

I

IN

DB0–DB7 All 10 10 10 10 pF max
WR, CS, DAC A/DAC B All 15 15 15 15 pF max

SWITCHING CHARACTERISTICS

Chip Select to Write Set Up Time

t

CS

Chip Select to Write Hold Time

t

CH

DAC Select to Write Set Up Time

t

AS

DAC Select to Write Hold Time

t

AH

Data Valid to Write Set Up Time

t

DS

Data Valid to Write Hold Time

t

DH

Write Pulsewidth

t

WR

A, V

REF

4

B) All 8 8 8 8 kΩ min Input Resistance TC = –300 ppm/°C, Typical

REF

15 15 15 15 kΩ max Input Resistance is 11 kΩ

All 2.4 2.4 13.5 13.5 V min

All 0.8 0.8 1.5 1.5 V max
All ±1 ±10 ±1 ±10 µA max V

3

= 0 or V

IN

DD

See Timing Diagram

All 90 100 60 80 ns min

All 0 0 10 15 ns min

All 90 100 60 80 ns min

All 0 0 10 15 ns min

All 80 90 30 40 ns min

All 0 0 0 0 ns min

All 90 100 60 80 ns min

POWER SUPPLY See Figure 3

I

DD

All 2 2 2 2 mA max All Digital Inputs VIL or V
All 100 500 100 500 µA max All Digital Inputs 0 V or V

IH

DD

(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as

AC PERFORMANCE CHARACTERISTICS

5

Output Amplifiers)

VDD = +5 V VDD = +15 V

Parameter Version1T

= +25°CT

A

MIN

, T

MAXTA

= +25°CT

MIN

, T

Units Test Conditions/Comments

MAX

DC SUPPLY REJECTION (∆GAIN/∆VDD) All 0.02 0.04 0.01 0.02 % per % max ∆VDD = ±5%

CURRENT SETTLING TIME

PROPAGATION DELAY (From Digital In- V

put to 90% of Final Analog Output Current) All 220 270 80 100 ns max OUT A, OUT B Load = 100 Ω C

2

All 350 400 180 200 ns max To 1/2 LSB. OUT A/OUT B Load = 100 Ω.

WR = CS = 0 V. DB0–DB7 = 0 V to V
VDD to 0 V

A = V

REF

B = +10 V

REF

WR = CS = 0 V DB0–DB7 = 0 V to VDD or

= 13 pF

EXT

DD

or

VDD to 0 V

DIGITAL-TO-ANALOG GLITCH IMPULSE All 160 440 nV sec typ For Code Transition 00000000 to 11111111

OUTPUT CAPACITANCE

A All 50 50 50 50 pF max DAC Latches Loaded with 00000000

C

OUT

B 50 505050pF max

C

OUT

A 120 120 120 120 pF max DAC Latches Loaded with 11111111

C

OUT

C

B 120 120 120 120 pF max

OUT

AC FEEDTHROUGH

V

A to OUT A All –70 –65 –70 –65 dB max V

REF

V

B to OUT B –70 –65 –70 –65 dB max @ 100 kHz

REF

6

A, V

REF

B = 20 V p-p Sine Wave

REF

REV. B–2–

3 2 1 20 19

9 10 11 12 13

18
17
16
15
14

4
5
6
7
8

TOP VIEW

(Not to Scale)

PIN 1
IDENTIFIER

V

REF

A

DGND

DAC A/DAC B

(MSB) DB7

DB6

V

REF

B

V

DD

WR

CS

DB0 (LSB)

AD7528

R

FB

A

OUT A

AGND

OUT B

R

FB

B

DB5

DB4

DB3

DB2

DB1

AD7528

VDD = +5 V VDD = +15 V

Parameter Version1T

CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111.

A to OUT B All –77 –77 dB typ V

V

REF

B to OUT A –77 –77 dB typ V

V

REF

DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to

HARMONIC DISTORTlON All –85 –85 dB typ VIN = 6 V rms @ 1 kHz

NOTES

1

Temperature Ranges are J, K, L Versions: –40°C to +85°C

2

Specifications applies to both DACs in AD7528.

3

Guaranteed by design but not production tested.

4

Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.

5

These characteristics are for design guidance only and are not subject to test.

6

Feedthrough can be further reduced by connecting the metal lid on the ceramic package
(suffix D) to DGND.

Specifications subject to change without notice.

A, B, C Versions: –40°C to +85°C
S, T, U Versions: –55°C to +125°C

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V

, V

V
V
V

PIN2

REF

RFB

A, V
A, V

to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

PIN20

B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V

REF

B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V

RFB

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C

Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C

Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C

CAUTION:

1. ESD sensitive device. The digital control inputs are diode

protected; however, permanent damage may occur on uncon­nected devices subjected to high energy electrostatic fields.
Unused devices must be stored in conductive foam or shunts.

2. Do not insert this device into powered sockets. Remove

power before insertion or removal.

= +25°CT

A

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

MIN

, T

= +25°CT

MAXTA

AD7528, ideal maximum output is V

MIN

, T

Units Test Conditions/Comments

MAX

A = 20 V p-p Sine Wave @ 100 kHz

REF

B = 0 V see Figure 6.

V

REF

A = 20 V p-p Sine Wave @ 100 kHz

REF

V

A = 0 V see Figure 6.

REF

11111111

REF

– 1 LSB. Gain error of

both DACs is adjustable to zero with external resistance.

Output Capacitance

Capacitance from OUT A or OUT B to AGND.

Digital to Analog Glitch lmpulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with V

B = AGND.

V

REF

REF

A,

Propagation Delay

This is a measure of the internal delays of the circuit and is
defined as the time from a digital input change to the analog
output current reaching 90% of its final value.

Channel-to-Channel Isolation

The proportion of input signal from one DAC’s reference input
which appears at the output of the other DAC, expressed as a
ratio in dB.

Digital Crosstalk

The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci­fied in nV secs.

PIN CONFIGURATIONS

PLCC

TERMINOLOGY
Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB max over

the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For the

REV. B

–3–

AGND

OUT A

R

FB

V

REF

DGND

DAC A/DAC B

(MSB) DB7

DB6
DB5
DB4

DIP, SOIC

1

2

3

A

4

A

5

AD7528

TOP VIEW

6

(Not to Scale)

7

8

9

10

20

OUT B

19

RFB B

18

V

17

V

16

WR

15

CS

14

DB0 (LSB)

13

DB1

12

DB2

11

DB3

REF

DD

B