Analog Devices AD7395ARU, AD7395AR, AD7395AN, AD7394AR Datasheet

+3 V, Dual, Serial Input

a

FEATURES
Micropower: 100 mA/DAC

0.1 mA Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-14 Package
AD7394/12-Bit Resolution
AD7395/10-Bit Resolution
Serial Interface with Schmitt Trigger Inputs

APPLICATIONS
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals

GENERAL DESCRIPTION

The AD7394/AD7395 family of dual, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, this monolithic
DAC offers the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V making this device ideal for battery
operated applications.

The full-scale output voltage is determined by the applied exter­nal reference input voltage, VREF. The rail-to-rail VREF input
to V
positive supply V

A doubled-buffered serial data interface offers high speed,
microcontroller compatible inputs using serial-data-in (SDI),
clock (CLK) and load strobe (LDA + LDB) pins. A chip-select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, an RS
input sets the output to zero scale or to 1/2 scale based on the
logic level applied to the MSB pin. The power shutdown pin,
SHDN, reduces power dissipation to nanoamp current levels.
All digital inputs contain Schmitt-triggered logic levels to mini­mize power dissipation and prevent false triggering on the clock
input.

Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application with­out circuit card redesign.

outputs allows for a full-scale voltage set equal to the

OUT

or any value in between.

DD

12-/10-Bit DACs

AD7394/AD7395

FUNCTIONAL BLOCK DIAGRAM

VDDV

REF

AGND

OP
AMP A

OP
AMP B

SHDN

V

V

OUTA

OUTB

R

CS

CLK

SDI

(DATA)

LDA

LDB

EN

R
E

S

G

H

I

I

S

F

T

T

E
R

DGND MSB

E

D

G

A

I

C

S
T

A

E
R

D

PR

12

DAC A

AD7394/AD7395

R

D

E

D

G

A

I

C

S
T

B

E
R

PR

DAC B

RS

The AD7394/AD7395 is specified over the extended industrial

(–40°C to +85°C) temperature range. Packages available in-

clude plastic DIP and low profile 1.75 mm height SO-14 surface
mount packages. The AD7395ARU is available for ultracompact
applications in a thin 1.1 mm TSSOP-14 package. For automotive
applications the AD7395AR is specified for operation over the

(–40°C to +125°C) temperature range.

1

VDD = 3V

0.8

V

= 2.5V

REF

0.6

0.4

0.2

0

DNL – LSB

–0.2

–0.4

–0.6

TA = –558C, +258C, +858C

–0.8

SUPERIMPOSED

–1

0 1000500

1500 25002000 3000 40003500

CODE – Decimal

Figure 1. Differential Nonlinearity Error vs. Code

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7394/AD7395–SPECIFICATIONS

AD7394 12-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
ELECTRICAL CHARACTERISTICS

(@ V

= 2.5 V, –408C < TA < +858C, unless otherwise noted)

REF IN

Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units

STATIC PERFORMANCE

Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Voltage Error V
Full-Scale Tempco

1

2

2

2

2

3

N 12 12 Bits
INL T
INL T
DNL T

= +25°C ±1.5 ±1.5 LSB max

A

= –40°C, +85°C ±2.0 ±2.0 LSB max

A

= +25°C, Monotonic ±0.9 ±0.9 LSB max

A

DNL Monotonic ±1 ±1 LSB max

ZSE

FSE

FSE

TCV

FS

Data = 000
T

= +25°C, +85°C, Data = FFFH±8 ±8 mV max

A

T

= –40°C, Data = FFF

A

H

H

4.0 4.0 mV max

±20 ±20 mV max
–30 –30 ppm/°C typ

REFERENCE INPUT

V

Range V

REF IN

Input Resistance R
Input Capacitance

3

REF

REF

C

REF

0/V

DD

0/V

DD

V min/max

2.5 2.5 MΩ typ

5 5 pF typ

ANALOG OUTPUT

Output Current (Source) I
Output Current (Sink) I
Capacitive Load

3

OUT

OUT

C

L

Data = 800
Data = 800

H

H

, ∆V
, ∆V

= 5 LSB 1 1 mA typ

OUT

= 5 LSB 3 3 mA typ

OUT

No Oscillation 100 100 pF typ

LOGIC INPUTS

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance

INTERFACE TIMING

3

3, 5

Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t

IL

IH

IL

C

IL

CH

CL

LDW

DS

DH

CLRW

LD1

LD2

0.5 0.8 V max
VDD–0.6 4.0 V min

10 10 µA max

10 10 pF max

50 30 ns min
50 30 ns min
30 20 ns min
10 10 ns min
30 15 ns min
15 15 ns min
30 15 ns min
40 20 ns min

AC CHARACTERISTICS

Output Slew Rate SR Data = 000H to FFFH to 000
Settling Time
DAC Glitch Q Code 7FF

6

t

S

To ± 0.1% of Full Scale 70 60 µs typ

to 800H to 7FF

H

H

H

0.05 0.05 V/µs typ

65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V

OUT/VREF

V

= 1.5 VDC +1 V p-p

REF

,

Data = 000H, f = 100 kHz –63 –63 dB typ

SUPPLY CHARACTERISTICS

Power Supply Range V
Shutdown Supply Current I
Positive Supply Current I
Power Dissipation P

DD RANGE

DD_SD

DD

DISS

DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
SHDN = 0, V

V

= 0 V, No Load 125/200 125/200 µA typ/max

IL

V

= 0 V, No Load 600 1000 µW max

IL

= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max

IL

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max

NOTES

1

One LSB = V

2

The first two codes (000H, 001H) are excluded from the linearity error measurement.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at +25° C.

5

All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.

6

The settling time specification does not apply for negative going transitions within the last three LSBs of ground.

Specifications subject to change without notice.

/4096 V for the 12-bit AD7394.

REF

4

–2–

REV. 0

AD7395 10-BIT RAIL-TO-RAIL VOLTAGE OUT DAC

AD7394/AD7395

ELECTRICAL CHARACTERISTICS

(@ V

= 2.5 V, –408C < TA < +858C/+1258C, unless otherwise noted)

REF IN

Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units

STATIC PERFORMANCE

Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V

Full-Scale Voltage Error V
Full-Scale Tempco

1

2

2

2

3

N 10 10 Bits
INL T
INL T

= +25°C ±1.5 ±1.5 LSB max

A

= –40°C, +85°C, +125°C ±2.0 ±2.0 LSB max

A

DNL Monotonic ±1 ±1 LSB max

ZSE

FSE

FSE

TCV

FS

Data = 000
T

= +25°C, +85°C, +125°C

A

Data = FFF
T

= –40°C, Data = FFF

A

H

H

H

9.0 9.0 mV max

±42 ±42 mV max
±48 ±48 mV max

–35 –35 ppm/°C typ

REFERENCE INPUT

V

Range V

REF IN

Input Resistance R
Input Capacitance

3

REF

REF

C

REF

0/V

DD

0/V

DD

V min/max

2.5 2.5 MΩ typ

5 5 pF typ

ANALOG OUTPUT

Output Current (Source) I
Output Current (Sink) I
Capacitive Load

3

OUT

OUT

C

L

Data = 200
Data = 200

H

H

, ∆V
, ∆V

= 5 LSB 1 1 mA typ

OUT

= 5 LSB 3 3 mA typ

OUT

No Oscillation 100 100 pF typ

LOGIC INPUTS

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance

INTERFACE TIMING

3

3, 5

Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t

IL

IH

IL

C

IL

CH

CL

LDW

DS

DH

CLRW

LD1

LD2

0.5 0.8 V max
VDD–0.6 4.0 V min

10 10 µA max

10 10 pF max

50 30 ns min
50 30 ns min
30 20 ns min
10 10 ns min
30 15 ns min
15 15 ns min
30 15 ns min
40 20 ns min

AC CHARACTERISTICS

Output Slew Rate SR Data = 000H to 3FFH to 000
Settling Time
DAC Glitch Q Code 7FF

6

t

S

To ± 0.1% of Full Scale 70 60 µs typ

to 800H to 7FF

H

H

H

0.05 0.05 V/µs typ

65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V

OUT/VREF

V

= 1.5 VDC +1 V p-p

REF

,

Data = 000H, f = 100 kHz –63 –63 dB typ

SUPPLY CHARACTERISTICS

Power Supply Range V
Shutdown Supply Current I
Positive Supply Current I
Power Dissipation P

DD RANGE

DD_SD

DD

DISS

DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
SHDN = 0, V

V

= 0 V, No Load 125/200 125/200 µA typ/max

IL

V

= 0 V, No Load 600 1000 µW max

IL

= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max

IL

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max

NOTES

1

One LSB = V

2

The first two codes (000H, 001H) are excluded from the linearity error measurement.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at +25°C.

5

All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.

6

The settling time specification does not apply for negative going transitions within the last three LSBs of ground.

Specifications subject to change without notice.

/4096 V for the 10-bit AD7395.

REF

4

–3–REV. 0

AD7394/AD7395

SDI

CLK

LDA,B

SDI

CLK

LDA,B

V

OUT

CS

RS

FS
ZS

SHDN

I

D0D1D2D3D4D5D6D7D8D9D10D11

t

61 LSB

CSH

t

LD2

t

CLRW

t

S

t

CSS

t

LD1

t

t

DH

DS

t

CL

t

CH

t

LDW

t

S

ERROR BAND

Figure 2. Timing Diagram

t

SDR

DD

Figure 3. Timing Diagram

Table I. Control Logic Truth Table

CS CLK RS MSB SHDN LDA/B Serial Shift Register Function DAC Register Function

H X H X H H No Effect Latched
L L H X H H No Effect Latched
L H H X H H No Effect Latched

L ↑+ H X H H Shift-Register-Data Advanced One Bit Latched
L ↑+ H X H L Shift-Register-Data Advanced One Bit Transparent

L H H X H L No Effect Transparent

↑+ L H X H H No Effect Latched
HX H X H ↓– No Effect Updated with Current Shift Register

Contents
H X H X H L No Effect Transparent
X X L H H X No Effect Loaded with 800

XX ↑+ H H H No Effect Latched with 800

H

H

X X L L H X No Effect Loaded with All Zeros

XX ↑+ L H H No Effect Latched All Zeros

X X X X L X No Effect No Affect

NOTES

1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care

2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.

–4–

REV. 0