+3 V, Parallel Input
12
12
12-BIT
DAC
DAC REGISTER
V
REF
SHDN
AGND
RS
DB0–DB11
CS
DGND
AD7392
V
DD
V
OUT
CODE – Decimal
1024128 256 384 512 640 768 8960
AD7393
VDD = +2.7V
V
REF
= +2.5V
TA = 258C
1
21
0.4
20.2
20.4
20.6
20.8
0.2
0
0.8
0.6
DNL – LSB
a
FEATURES
Micropower: 100 A
0.1 A Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-20 Package
AD7392/12-Bit Resolution
AD7393/10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7392/AD7393 family of 10- and 12-bit voltage-output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, these monolithic
DACs offer the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V, making this device ideal for battery
operated applications.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail REF
DAC
supply V
allows for a full-scale voltage set equal to the positive
OUT
or any value in between. The voltage outputs are
DD
capable of sourcing 5 mA.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to the fastest processors without wait states.
to
IN
Micropower 10- and 12-Bit DACs
AD7392/AD7393
FUNCTIONAL BLOCK DIAGRAM
Additionally, an asynchronous RS input sets the output to zero
scale at power on or upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their applications
without circuit card changes.
The AD7392/AD7393 are specified for operation over the ex-
tended industrial (–40°C to +85°C) temperature range. The
AD7393AR is specified for the –40°C to +125°C automotive
temperature range. AD7392/AD7393s are available in plastic
DIP, and 20-lead SOIC packages. The AD7393ARU is available for ultracompact applications in a thin 1.1 mm height
TSSOP-20 package.
For serial data input, 8-lead packaged versions, see the AD7390
and AD7391 products.
1
AD7392
0.8
0.6
0.4
0.2
0
DNL – LSB
20.2
20.4
20.6
20.8
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
21
0 4096512
Figure 1. AD7392 Differential Nonlinearity Error vs. Code
1024 1536 2048 2560 3072 3584
CODE – Decimal
VDD = +2.7V
= +2.5V
V
REF
= 258C
T
A
Figure 2. AD7393 Differential Nonlinearity Error vs. Code
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD7392/AD7393–SPECIFICATIONS
AD7392 ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, ⴚ40ⴗC < TA < ⴙ85ⴗC, unless otherwise noted)
REF IN
Parameter Symbol Conditions 3 V ⴞ 10% 5 V ⴞ 10% Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
1
2
2
N 12 12 Bits
INL T
DNL T
= ⫹25°C ⫾1.8 ⫾1.8 LSB max
A
= ⫺40°C, ⫹85°C ⫾3 ⫾3 LSB max
T
A
= ⫹25°C, Monotonic ⫾0.9 ⫾0.9 LSB max
A
Monotonic ⫾1 ⫾1 LSB max
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco
3
ZSE
FSE
TCV
FS
Data = 000H, T
Data = 000
T
= ⫹25°C, ⫹85°C, Data = FFF
A
= ⫺40°C, Data = FFF
T
A
= ⫹25°C, ⫹85°C 4.0 4.0 mV max
A
, T
= –40°C 8.0 8.0 mV max
H
A
H
⫾8 ⫾8mV max
H
⫾20 ⫾20 mV max
28 28 ppm/°C typ
REFERENCE INPUT
V
Range V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
L
Data = 800
Data = 800
H
H
, ∆V
, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Chip Select Write Width t
Data Setup t
Data Hold t
Reset Pulsewidth t
IL
IH
IL
C
IL
CS
DS
DH
RS
0.5 0.8 V max
VDD⫺0.6 VDD⫺0.6 V min
10 10 µA max
10 10 pF max
45 45 ns min
30 15 ns min
20 5 ns min
40 30 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000
Settling Time
Shutdown Recovery Time t
6
t
S
SDR
To ±0.1% of Full Scale 70 60 µs typ
DAC Glitch Q Code 7FF
to FFFH to 000
H
to 800H to 7FF
H
H
0.05 0.05 V/µs typ
80 µs typ
H
65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V
OUT/VREFVREF
= 1.5 V dc +1 V p-p
,
Data = 000H, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range V
Positive Supply Current I
Shutdown Supply Current I
Power Dissipation P
DD RANGE
DD
DD–SD
DISS
Power Supply Sensitivity PSS ∆V
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
/4096 V for the 12-bit AD7392.
REF
DNL < ⫾1 LSB 2.7/5.5 2.7/5.5 V min/max
V
= 0 V, No Load 55/100 55/100 µA typ/max
IL
SHDN = 0, V
V
= 0 V, No Load 300 500 µW max
IL
= ⫾5% 0.006 0.006 %/% max
DD
= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
IL
4
–2–
REV. A
AD7392/AD7393
AD7393 ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, ⴚ40ⴗC < TA < ⴙ85ⴗC, unless otherwise noted)
REF IN
Parameter Symbol Conditions 3 V ⴞ 10% 5 V ⴞ 10% Units
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco
1
2
2
3
N 10 10 Bits
INL T
= ⫹25°C ⫾1.75 ⫾1.75 LSB max
A
= ⫺40°C, ⫹85°C, ⫹125°C ⫾2.0 ⫾2.0 LSB max
T
A
DNL Monotonic ⫾0.8 ⫾0.8 LSB max
ZSE
FSE
TCV
FS
Data = 000
T
= ⫹25°C, ⫹85°C, ⫹125°C, ⫾32 ⫾32 mV max
A
Data = 3FF
T
= ⫺40°C, Data = 3FF
A
H
H
H
9.0 9.0 mV max
⫾42 ⫾42 mV max
28 28 ppm/°C typ
REFERENCE INPUT
V
Range V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
L
Data = 200
Data = 200
H
H
, ∆V
, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Chip Select Write Width t
Data Setup t
Data Hold t
Reset Pulsewidth t
IL
IH
IL
C
IL
CS
DS
DH
RS
0.5 0.8 V max
VDD⫺0.6 VDD⫺0.6 V min
10 10 µA max
10 10 pF max
45 45 ns
30 15 ns
20 5 ns
40 30 ns
AC CHARACTERISTICS
Output Slew Rate SR Data = 000
Settling Time
Shutdown Recovery Time t
6
t
S
SDR
To ⫾0.1% of Full Scale 70 60 µs typ
DAC Glitch Q Code 7FF
to 3FFH to 000
H
to 800H to 7FF
H
H
0.05 0.05 V/µs typ
80 µs typ
H
65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V
OUT/VREFVREF
= 1.5 V dc ⫹1 V p-p,
Data = 000H, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range V
Positive Supply Current I
Shutdown Supply Current I
Power Dissipation P
DD RANGE
DD
DD–SD
DISS
Power Supply Sensitivity PSS ∆V
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of ⫹3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
/1024 V for the 10-bit AD7393.
REF
DNL < ⫾1 LSB 2.7/5.5 2.7/5.5 V min/max
VIL = 0 V, No Load, T
= 0 V, No Load 100 100 µA max
V
IL
SHDN = 0, V
V
= 0 V, No Load 300 500 µW max
IL
= ⫾5% 0.006 0.006 %/% max
DD
= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
IL
= ⫹25°C55 55 µA typ
A
4
REV. A
–3–
AD7392/AD7393
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
V
REF
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
V
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
I
OUT
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +2 V
Package Power Dissipation . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
max – T
J
)/θ
A
JA
20-Lead Plastic DIP Package (N-20) . . . . . . . . . . . 57°C/W
20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . . 60°C/W
20-Lead Thin-Shrink Surface Mount (RU-20) . . . 155°C/W
Maximum Junction Temperature (T
max) . . . . . . . . . . 150°C
J
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
AD7393AR . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
N-20 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . .+300°C
R-20 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . .+215°C
RU-20 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CS
DB11–DB0
RS
V
OUT
1
0
1
0
1
0
FS
ZS
t
CS
t
DS
DATA VALID
t
t
DH
t
RS
60.1% FS
ERROR BAND
S
t
S
Figure 3. Timing Diagram
PIN CONFIGURATIONS
V
SHDN
CS
RS
DD
D0
D1
D2
D3
D4
D5
1
2
3
4
5
AD7392
TOP VIEW
6
(Not to Scale)
7
8
9
10
20
V
REF
19
V
OUT
18
AGND
17
DGND
16
D11
15
D10
14
D9
13
D8
12
D7
11
D6
1
V
DD
2
SHDN
CS
3
4
RS
5
NC
6
NC
7
D0
8
D1
9
D2
10
D3
NC = NO CONNECT
AD7393
TOP VIEW
(Not to Scale)
20
V
REF
19
V
OUT
18
AGND
17
DGND
16
D9
15
D8
14
D7
13
D6
12
D5
11
D4
PIN DESCRIPTION
# Name Function
1V
DD
Positive Power Supply Input. Specified range
of operation +2.7 V to +5.5 V.
2 SHDN Power Shutdown active low input. DAC regis-
ter contents are saved as long as power stays on
the V
pin. When SHDN = 0, CS strobes will
DD
write new data into the DAC register.
3 CS Chip Select latch enable, active low.
4 RS Resets DAC register to zero condition. Asyn-
chronous active low input.
5, 6 NC No connect Pins 5 and 6 on the AD7393.
17 DGND Digital Ground.
18 AGND Analog Ground.
19 V
20 V
OUT
REFIN
DAC Voltage Output.
DAC Reference Input Pin. Establishes DAC
full-scale voltage.
D0–D11 12 parallel input data bits. D11 = MSB Pin 16,
D0 = LSB Pin 5, AD7392.
D0–D9 10 parallel input data bits. D9 = MSB. Pin 16,
D0 = LSB Pin 7, AD7393.
ORDERING GUIDE
DB
CS
RS
1 OF 12 LATCHES
OF THE
DAC REGISTER
TO
X
INTERNAL
DAC
SWITCHES
Model (LSB) Temp Description Option
AD7392AN 12 XIND 20-Lead P-DIP N-20
AD7392AR 12 XIND 20-Lead SOIC R-20
AD7393AN 10 XIND 20-Lead P-DIP N-20
AD7393AR 10 AUTO 20-Lead SOIC R-20
AD7393ARU 10 XIND TSSOP-20 RU-20
NOTES
Figure 4. Digital Control Logic
XIND = –40°C to +85°C; AUTO = –40°C to +125°C.
The AD7392 contains 709 transistors. The die size measures 78 mil × 85 mil =
Res Package Package
6630 sq. mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7392/AD7393 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Typical Performance Characteristics–
TOTAL UNADJUSTED ERROR – LSB
FREQUENCY
25
0
5.0
10
5
20
15
5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0
AD7392
SS = 100 UNITS
T
A
= 258C
V
DD
= 2.7V
V
REF
= 2.5V
FREQUENCY – Hz
OUTPUT VOLTAGE NOISE – mV/ Hz
10
8
0
1 10 100k
100 1k 10k
6
4
2
12
14
16
AD7392
VDD = 5V
V
REF
= 2.5V
T
A
= 258C
TEMPERATURE – 8C
SUPPLY CURRENT – mA
100
20
255 235 125
215 5 25 65 85 10545
90
60
50
40
30
80
70
AD7392
SAMPLE SIZE = 300 UNITS
VDD = 5.0V, V
LOGIC
= 0V
VDD = 3.0V, V
LOGIC
= 0V
VDD = 3.6V, V
LOGIC
= 2.4V
AD7392/AD7393
1
AD7392
0.8
0.6
0.4
0.2
0
INL – LSB
–0.2
–0.4
–0.6
–0.8
–1
0 512 1024 40961536 2048 2560 3072 3584
CODE – Decimal
VDD = 2.7V
V
= 2.5V
REF
T
= 258C
A
Figure 5. AD7392 Integral Nonlinearity Error vs. Code
100
90
80
70
60
50
40
FREQUENCY
30
20
10
0
–3.3 3.3 10 16 23 30 36 43 50
–10
TOTAL UNADJUSTED ERROR – LSB
AD7393
SS = 300 UNITS
T
= 258C
A
V
= 2.7V
DD
= 2.5V
V
REF
Figure 8. AD7393 Total Unadjusted
Error Histogram
1
AD7393
0.8
0.6
0.4
0.2
0
INL – LSB
–0.2
–0.4
–0.6
–0.8
–1
0 128 256 1024384 512 640 768 896
VDD = 2.7V
V
REF
T
= 258C
A
CODE – Decimal
= 2.5V
Figure 6. AD7393 Integral Nonlinear ity Error vs. Code
AD7393
SS = 100 UNITS
= 2408 to 858C
T
A
24
V
= 2.7V
DD
V
= 2.5V
REF
18
12
FREQUENCY
6
0
–60 –52 –46 –40 –32 –26 –20 –12 –6300
–66
FULL SCALE TEMPCO – ppm/8C
Figure 9. AD7393 Full-Scale Output
Tempco Histogram
Figure 7. AD7392 Total Unadjusted
Error Histogram
Figure 10. Voltage Noise Density vs.
Frequency
100
AD7392
95
TA = 258C
= 3.0V
V
DD
90
85
80
75
V
FROM
LOGIC
3.0V TO 0V
70
65
SUPPLY CURRENT – mA
60
55
50
0.0 0.5 3.0
1.0 1.5 2.0 2.5
VIN – Volts
Figure 11. Supply Current vs. Logic
Input Voltage
REV. A
V
FROM
LOGIC
0V TO 3.0V
5.0
AD7392
4.5
CODE = FFF
V
REF
4.0
RS LOGIC VOLTAGE
3.5
VARIED
3.0
V
LOGIC
2.5
HIGH TO LOW
2.0
1.5
THRESHOLD VOLTAGE – V
1.0
0.5
0.0
12 7
H
= 2V
FROM
V
LOGIC
LOW TO HIGH
3456
SUPPLY VOLTAGE – V
FROM
Figure 12. Logic Threshold vs.
Supply Voltage
–5–
Figure 13. Supply Current vs.
Temperature
AD7392/AD7393
V
OUT
– V
I
OUT
– mA
40
30
0
01 5
234
20
10
VDD = +5V
V
REF
= +3V
CODE = ØØØ
H
TIME – 100ms/DIV
HOURS OF OPERATION AT 1508C
NOMINAL CHANGE IN VOLTAGE – mV
1.2
0.0
0 100 600
200 300 400 500
1.0
0.8
0.6
0.4
0.2
AD7392
SAMPLE SIZE = 50
CODE = FFF
H
CODE = 000
H
1000
AD7393
V
= 0V TO VDD TO 0V
LOGIC
= 2.5V
V
REF
800
= 258C
T
A
600
a. VDD = 5.5V, CODE = 155
b. VDD = 5.5V, CODE = 3FF
c. VDD = 2.7V, CODE = 155
400
d. V
= 2.7V, CODE = 355
DD
SUPPLY CURRENT – mA
200
0
1k 10k 10M
CLOCK FREQUENCY – Hz
100k 1M
a
H
b
H
H
c
H
d
Figure 14. Supply Current vs. Clock
Frequency
60
VDD = 5V 6 5% TA = 258C
50
40
VDD = 3V 6 5%
30
PSRR – dB
20
10
0
10 100 10k
FREQUENCY – Hz
1k
Figure 15. Power Supply Rejection
vs. Frequency
Figure 16. I
at Zero Scale vs. V
OUT
OUT
TIME – 2ms/DIV
Figure 17. Midscale Transition
Performance
5
0
25
VDD = +5V
210
215
GAIN – dB
220
225
230
= +100mV + 2V
V
REF
DATA = FFF
10 100 100k
FREQUENCY – Hz
H
1k 10k
DC
Figure 20. Reference Multiplying
Bandwidth
TIME – 5ms/DIV
Figure 18. Digital Feedthrough
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
INTEGRAL NONLINEARITY – LSB
0.2
0.0
05
1324
REFERENCE VOLTAGE – V
AD7392
V
= +5V
DD
CODE = 768
TA = 258C
H
Figure 21. INL Error vs. Reference
Voltage
–6–
Figure 19. Large Signal Settling Time
Figure 22. Long-Term Drift
Accelerated by Burn-in
REV. A
100
100
(V)
SHDN
90
50
0
2
0
10
1
0%
0
TIME – 100ms/DIV
IDD (mA)
V
OUT
Figure 23. Shutdown Recovery Time
CS RS DAC Register Function
H H Latched
L H Transparent
↑ H Latched with New Data
X L Loaded with All Zeros
H ↑ Latched all Zeros
NOTE
↑ Positive logic transition; X Don’t Care.
1000
100
SUPPLY CURRENT – nA
10
Figure 24. Shutdown Current vs. Temperature
Table I. Control Logic Truth Table
AD7392/AD7393
AD7392
VDD = 5.5V
= 2.5V
V
REF
SHDN = 0V
–55 –35 125–15 65 85 105
52545
TEMPERATURE – 8C
OPERATION
The AD7392 and AD7393 comprise a set of pin compatible,
12-bit/10-bit digital-to-analog converters. These single-supply
operation devices consume less than 100 microamps of current
while operating from power supplies in the +2.7 V to +5.5 V
range making them ideal for battery operated applications. They
contain a voltage-switched, 12-bit/10-bit, laser-trimmed digitalto-analog converter, rail-to-rail output op amps, and a parallelinput DAC register. The external reference input has constant
input resistance independent of the digital code setting of the
DAC. In addition, the reference input can be tied to the same
supply voltage as V
span of 0 to V
DD
, resulting in a maximum output voltage
DD
. The parallel data interface consists of 12 data
bits, DB0–DB11, for the AD7392; 10 data bits, DB0–DB9, for
the AD7393; and a CS write strobe. A RS pin is available to
reset the DAC register to zero scale. This function is useful for
power-on reset or system failure recovery to a known state.
Additional power savings are accomplished by activating the
SHDN pin, resulting in a 1.5 µA maximum consumption sleep
mode. As long as the supply voltage remains, data will be retained in the DAC register to reset the DAC output when the
part is taken out of shutdown (SHDN = 1).
D/A CONVERTER SECTION
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
REF pin according to the following equation:
V
OUT=VREF
D
×
N
2
Equation 1
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of
the 10-bit AD7393 using a 2.5 V reference, Equation 1 simplifies to:
V
=2.5 ×
OUT
Using Equation 2, the nominal midscale voltage at V
D
1024
Equation 2
is 1.25 V
OUT
for D = 512; full-scale voltage is 2.497 volts. The LSB step size is
= 2.5 × 1/1024 = 0.0024 volts.
For the 12-bit AD7392 operating from a 5.0 V reference Equation 1 becomes:
V
OUT=VREF
D
×
N
2
Equation 3
Using Equation 3, the AD7392 provides a nominal midscale
voltage of 2.50 V for D = 2048, and a full-scale output of 4.998
volts. The LSB step size is = 5.0 × 1/4096 = 0.0012 volts.
REV. A
–7–
AD7392/AD7393
100mF
ELECT.
10-22mF
TANT.
0.1mF
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
+5V
+5V
RETURN
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling-time to within the last 6 LSBs of
zero volts has an extended settling time. The rail-to-rail output
stage of this amplifier has been designed to provide precision
performance while operating near either power supply. Figure
25 shows an equivalent output schematic of the rail-to-railamplifier with its N-channel pull-down FETs that will pull an
output load directly to GND. The output sourcing current is
provided by a P-channel pull-up device that can source current
to GND terminated loads.
V
P-CH
N-CH
DD
V
OUT
AGND
Figure 25. Equivalent Analog Output Circuit
The rail-to-rail output stage provides ±1 mA of output current.
The N-channel output pull-down MOSFET, shown in Figure
25, has a 35 Ω ON resistance that sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier also has been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches
on the external reference voltage source. The high 2.5 MΩ
input-resistance minimizes power dissipation within the
AD7392/AD7393 D/A converters. The V
input accepts
REF
input voltages ranging from ground to the positive-supply voltage V
. One of the simplest applications that saves an external
DD
reference voltage source is connection of the REF terminal to
the positive V
supply. This connection results in a rail-to-rail
DD
voltage output span maximizing the programmed range. The
reference input will accept ac signals as long as they are kept
within the supply voltage range, 0 < V
< VDD. The refer-
REF IN
ence bandwidth and integral nonlinearity error performance are
plotted in the typical performance section (see Figures 20 and
21). The ratiometric reference feature makes the AD7392/
AD7393 an ideal companion to ratiometric analog-to-digital
converters such as the AD7896.
POWER SUPPLY BYPASSING AND GROUNDING
Precision analog products, such as the AD7392/AD7393, require a
well filtered power source. Since the AD7392/AD7393 operate from a single +3 V to +5 V supply, it seems convenient to
simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches of hundreds of millivolts in amplitude due
to wiring resistance and inductance. The power supply noise
generated as a result means that special care must be taken to
assure that the inherent precision of the DAC is maintained.
Good engineering judgment should be exercised when addressing the power supply grounding and bypassing of the AD7392.
The AD7392 should be powered directly from the system power
supply. This arrangement, shown in Figure 26, employs an LC
filter and separate power and ground connections to isolate the
analog section from the logic switching transients.
Figure 26. Use Separate Traces to Reduce Power Supply
Noise
Whether or not a separate power supply trace is available, generous supply bypassing will reduce supply line induced errors.
Local supply bypassing, consisting of a 10 µF tantalum electro-
lytic in parallel with a 0.1 µF ceramic capacitor, is recom-
mended in all applications (Figure 27).
+2.7V TO +5.5V
C
*
DB0–DB11
CS
RS
2
3
4
SHDN
* OPTIONAL EXTERNAL
REFERENCE BYPASS
20
REF
AD7392
AD7393
OR
GND
17, 18
1
V
DD
0.1mF
10mF
19
V
OUT
POWER SUPPLY
The very low power consumption of the AD7392/AD7393 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for
the logic and the low noise, tight-matching of the complementary bipolar transistors, excellent analog accuracy is achieved.
One advantage of the rail-to-rail output amplifiers used in the
AD7392/AD7393 is the wide range of usable supply voltage.
The part is fully specified and tested for operation from +2.7 V
to +5.5 V.
Figure 27. Recommended Supply Bypassing for the
AD7392/AD7393
–8–
REV. A
AD7392/AD7393
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection structure (Figure 28) that allows logic input voltages to
exceed the V
supply voltage. This feature can be useful if the
DD
user is driving one or more of the digital inputs with a 5 V
CMOS logic input-voltage level while operating the AD7392/
AD7393 on a +3 V power supply. If this mode of interface is
used, make sure that the V
of the 5 V CMOS meets the V
OL
IL
input requirement of the AD7392/AD7393 operating at 3 V.
See Figure 12 for a graph for digital logic input threshold versus
operating V
supply voltage.
DD
V
DD
LOGIC
IN
GND
1kV
Figure 28. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input-logic levels
that are near the V
and VIL logic input voltage specifications, a
IH
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. Figure 11 shows a plot of incremental input voltage
versus supply current, showing that negligible current consumption takes place when logic levels are in their quiescent state.
The normal cross over current still occurs during logic transitions. A secondary advantage of this Schmitt trigger is the prevention of false triggers that would occur with slow moving logic
transitions when a standard CMOS logic interface or optoisolators are used. The logic inputs DB11–DB0, CS, RS, SHDN
all contain the Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7392/AD7393 have a parallel data input. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the logic control inputs.
The chip select (CS) pin controls loading of data from the data
inputs on pins DB11–DB0. This active low input places the
input register into a transparent state allowing the data inputs to
directly change the DAC ladder values. When CS returns to
logic high within the data setup and hold time specifications, the
new value of data in the input-register will be latched. See Truth
Table for complete set of conditions.
RESET (RS) PIN
Forcing the asynchronous RS pin low will set the DAC register
to all zeros and the DAC output voltage will be zero volts. The
reset function is useful for setting the DAC outputs to zero at
power-up or after a power supply interruption. Test systems and
motor controllers are two of many applications that benefit from
powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor or by an external resistor
and capacitor. RESET has a Schmitt trigger input which results
in a clean reset function when using external resistor/capacitor
generated pulses. See the Control-Logic Truth Table I.
POWER SHUTDOWN (SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt trigger input that helps desensitize it to slowly changing
inputs. By placing a logic low on this pin, the internal consumption of the AD7392 or AD7393 is reduced to nanoamp levels,
guaranteed to 1.5 µA maximum over the operating temperature
range. If power is present at all times on the V
pin while in
DD
the shutdown mode, the internal DAC register will retain the
last programmed data value. The digital interface is still active
in shutdown, so that code changes can be made that will produce new DAC settings when the device is taken out of shutdown. This data will be used when the part is returned to the
normal active state by placing the DAC back to its programmed
voltage setting. Figure 23 shows a plot of shutdown recovery
time with both I
DD
and V
displayed. In the shutdown state
OUT
the DAC output amplifier exhibits an open-circuit high resistance state. Any load connected will stabilize at its termination
voltage. If the power shutdown feature is not needed, the user
should tie the SHDN pin to the V
voltage thereby disabling
DD
this function.
REV. A
–9–
AD7392/AD7393
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7392. As shown
in Figure 29, the AD7392 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this
operation is shown in Table II.
+2.7V TO +5.5V
R
0.01mF
EXT
REF
DIGITAL INTERFACE
CIRCUITRY OMITTED
FOR CLARITY
20
V
DD
AD7392
REF
AGND/DGND
1
V
17, 18
OUT
0.1mF10mF
19
R
L
$5kV
C
L
$100pF
Figure 29. AD7392 Unipolar Output Operation
Table II. Unipolar Code Table
Hexadecimal Decimal Output
Number Number Voltage (V)
in DAC Register in DAC Register V
REF
= 2.5 V
FFF 4095 2.4994
801 2049 1.2506
800 2048 1.2500
7FF 2047 1.2494
000 0 0
The circuit can be configured with an external reference plus
power supply or powered from a single dedicated regulator
or reference depending on the application performance requirements.
BIPOLAR OUTPUT OPERATION
Although the AD7393 has been designed for single-supply operation, the output can be easily configured for bipolar operation. A typical circuit is shown in Figure 30. This circuit uses a
clean regulated +5 V supply for power, which also provides the
circuit’s reference voltage. Since the AD7393 output span swings
from ground to very near +5 V, it is necessary to choose an external amplifier with a common-mode input voltage range that
extends to its positive supply rail. The micropower consumption OP196 has been designed just for this purpose and results
in only 50 microamps of maximum current consumption. Con-
nection of the equal valued 470 kΩ resistors results in a differen-
tial amplifier mode of operation with a voltage gain of two,
which produces a circuit output span of ten volts (that is, –5 V
to +5 V). As the DAC is programmed from zero-code 000
to
H
midscale 200H to full scale 3FFH, the circuit output voltage V
O
is set at –5 V, 0 V and +5 V (minus 1 LSB). The output voltage
is coded in offset binary according to Equation 4.
V
O
D
V
=
O
512
–1
×5
Equation 4
where D is the decimal code loaded in the AD7393 DAC register. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption including
the 470 kΩ gain setting resistors, which should have low tem-
perature coefficients to maintain accuracy and matching (preferably the same resistor material, such as metal film). If better
stability is required, the power supply could be substituted with
a precision reference voltage such as the low drop out REF195,
which can easily supply the circuit’s 162 µA of current, and still
provide additional power for the load connected to V
. The
O
micropower REF195 is guaranteed to source 10 mA output
drive current, but only consumes 50 µA internally. If higher
resolution is required, the AD7392 can be used with the addition of two more bits of data inserted into the software coding,
which would result in a 2.5 mV LSB step size. Table III shows
examples of nominal output voltages V
provided by the Bipolar
O
Operation circuit application.
ISY < 162mA
+5V
C
REF
AD7393
DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
GND
470kV
<100mA<2mA
V
DD
V
OUT
470kV
OP196
–5V
<50mA
+5V
BIPOLAR
V
OUTPUT
O
SWING
–5V
Figure 30. Bipolar Output Operation
Table III. Bipolar Code Table
Hexadecimal Decimal Analog
Number Number Output
In DAC Register in DAC Register Voltage (V)
3FF 1023 4.9902
201 513 0.0097
200 512 0.0000
1FF 511 –0.0097
000 0 –5.0000
–10–
REV. A
OUTLINE DIMENSIONS
20
110
11
1.060 (26.90)
0.925 (23.50)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
20 11
10
1
0.260 (6.60)
0.252 (6.40)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
Dimensions shown in inches and (mm).
20-Lead Plastic DIP Package
(N-20)
20-Lead SOIC Package
(R-20)
0.5118 (13.00)
0.4961 (12.60)
20 11
AD7392/AD7393
C2210a–2–3/99
REV. A
0.0118 (0.30)
0.0040 (0.10)
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
0.0125 (0.32)
0.0091 (0.23)
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
8°
0°
0.0157 (0.40)
PIN 1
0.0500
(1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.0192 (0.49)
0.0138 (0.35)
101
SEATING
PLANE
20-Lead Thin Surface Mount TSSOP Package
(RU-20)
–11–
x 45°
PRINTED IN U.S.A.
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