Analog Devices AD7390 1 a Datasheet
3 V Serial-Input
a
Micropower 10-Bit and 12-Bit DACs
FEATURES
Micropower—100 A
Single-Supply—2.7 V to 5.5 V Operation
Compact 1.75 mm Height SO-8 Package
and 1.1 mm Height TSSOP-8 Package
AD7390—12-Bit Resolution
AD7391—10-Bit Resolution
SPI and QSPI Serial Interface Compatible with Schmitt
Trigger Inputs
APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
GENERAL DESCRIPTION
The AD7390/AD7391 family of 10-bit and 12-bit voltageoutput digital-to-analog converters is designed to operate
from a single 3 V supply. Built using a CBCMOS process,
these monolithic DACs offer the user low cost, and ease-of-use
in single-supply 3 V systems. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V consuming less than 100 µA
making this device ideal for battery operated applications.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail REF
DAC
supply V
allows for a full-scale voltage set equal to the positive
OUT
or any value in between.
DD
IN
to
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller compatible inputs using data
AD7390/AD7391
FUNCTIONAL BLOCK DIAGRAM
V
AD7390
REF
CLR
LD
EN
CLK
SDI
12-BIT DAC
12
DAC REGISTER
12
SERIAL REGISTER
in (SDI), clock (CLK) and load strobe (LD) pins. Additionally, a CLR input sets the output to zero scale at power on or
upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.
The AD7390/AD7391 are specified over the extended industrial
(40°C to 85°C) temperature range. The AD7391AR is
specified for the 40°C to 125°C automotive temperature
range. The AD7390/AD7391s are available in plastic DIP, and
low profile 1.75 mm height SO-8 surface mount packages. The
AD7391ARU is available for ultracompact applications in a thin
1.1 mm TSSOP-8 package.
DD
V
OUT
GND
1.00
AD7390
0.75
0.50
0.25
0.00
DNL – LSB
0.25
0.50
VDD = 3.0V
T
0.75
1.00
= 55C, +25C, +85C
A
SUPERIMPOSED
0 4096512
1024 1536 2048 2560 3072 3584
CODE – Decimal
Figure 1. Differential Nonlinearity Error vs. Code
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
2.0
AD7390
1.5
1.0
0.5
0.0
INL – LSB
0.5
1.0
VDD = 3.0V
1.5
2.0
= 2.5V
V
REF
0 4096512 1024 1536 2048 2560 3072 2584
+25C, +85C
55C
CODE – Decimal
Figure 2. INL Error vs. Code and Temperature
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD7390/AD7391–SPECIFICATIONS
AD7390 ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, –40C < TA < +85C unless otherwise noted.)
REF IN
Parameter Symbol Conditions 3 V 10% 5 V 10% Unit
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
1
2
2
N 12 12 Bits
INL TA = 25°C ±1.6 ±1.6 LSB max
INL T
= 40°C, 85°C ±2.0 ±2 LSB max
A
DNL TA = 25°C, Monotonic ±0.9 ±0.9 LSB max
DNL Monotonic ±1 ±1 LSB max
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco
3
ZSE
FSE
V
FSE
TCV
FS
Data = 000
H
TA = 25°C, 85°C, Data = FFF
TA = 40°C, Data = FFF
H
4.0 4.0 mV max
±8 ±8mV max
H
±20 ±20 mV max
16 16 ppm/°C typ
REFERENCE INPUT
Range V
V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
L
Data = 800H, ∆V
Data = 800H, ∆V
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t
AC CHARACTERISTICS
6
IL
IH
IL
C
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
Output Slew Rate SR Data = 000H to FFFH to 000
Settling Time t
S
DAC Glitch Q Code 7FF
To 0.1% of Full Scale 70 60 µs typ
to 800H to 7FF
H
H
H
0.5 0.8 V max
V
0.6 V
DD
0.6 V min
DD
10 10 µA max
10 10 pF max
50 30 ns min
50 30 ns min
30 20 ns min
10 10 ns min
30 15 ns min
15 15 ns min
30 15 ns min
40 20 ns min
0.05 0.05 V/µs typ
65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V
OUT/VREFVREF
= 1.5 VDC 1 V p-p
,
63 63 dB typ
Data = 000H, f = 100 kHz
SUPPLY CHARACTERISTICS
Power Supply Range V
Positive Supply Current I
Power Dissipation P
DD RANGE
DD
I
DD
DISS
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
VIL = 0 V, No Load, TA = 25°C55 55 µA typ
VIL = 0 V, No Load 100 100 µA max
VIL = 0 V, No Load 300 500 µW max
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
/4096 V for the 12-bit AD7390.
REF
t
=
t
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.
R
F
4
–2–
REV. A
AD7390/AD7391
AD7391 ELECTRICAL CHARACTERISTICS
(@ V
= 2.5 V, 40C < TA < 85C unless otherwise noted.)
REF IN
Parameter Symbol Conditions 3 V 10% 5 V 10% Unit
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V
Full-Scale Error V
Full-Scale Tempco
1
2
2
3
N 10 10 Bits
INL TA = 25°C ±1.75 ±1.75 LSB max
INL T
INL T
= 40°C, 85°C, 125°C ±2.0 ±2.0 LSB max
A
= 55°C, S Grade ± 3 LSB max
A
DNL Monotonic ±0.9 ±0.9 LSB max
DNL T
ZSE
V
ZSE
FSE
V
FSE
TCV
FS
TCV
FS
= 55°C, S Grade ± 2 LSB max
A
Data = 000
H
9.0 9.0 mV max
TA = 55°C, S Grade 20 mV max
TA = 25°C, 85°C, 125°C, ±32 ±32 mV max
Data = 3FF
H
TA = 55°C, S Grade ± 55 mV max
16 16 ppm/°C typ
TA = 55°C, S Grade 32 ppm/°C typ
REFERENCE INPUT
Range V
V
REF IN
Input Resistance R
Input Capacitance
3
REF
REF
C
REF
0/V
DD
0/V
DD
V min/max
2.5 2.5 MΩ typ
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
Output Current (Sink) I
Capacitive Load
3
OUT
OUT
C
Data = 800H, ∆V
Data = 800H, ∆V
L
No Oscillation 100 100 pF typ
= 5 LSB 1 1 mA typ
OUT
= 5 LSB 3 3 mA typ
OUT
LOGIC INPUTS
Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance
INTERFACE TIMING
3
3, 5
Clock Width High t
Clock Width Low t
Load Pulsewidth t
Data Setup t
Data Hold t
Clear Pulsewidth t
Load Setup t
Load Hold t
AC CHARACTERISTICS
6
IL
IH
IL
C
IL
CH
CL
LDW
DS
DH
CLRW
LD1
LD2
Output Slew Rate SR Data = 000H to 3FFH to 000
Settling Time t
S
t
S
DAC Glitch Q Code 7FF
To 0.1% of Full Scale 70 60 µs typ
TA = –55°C, S Grade 100 µs typ
to 800H to 7FF
H
H
H
0.5 0.8 V max
V
0.6 V
DD
0.6 V min
DD
10 10 µA max
10 10 pF max
50 30 ns
50 30 ns
30 20 ns
10 10 ns
30 15 ns
15 15 ns
30 15 ns
40 20 ns
0.05 0.05 V/µs typ
65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V
OUT/VREFVREF
= 1.5 VDC 1 V p-p, 63 63 dB typ
Data = 000H, f = 100 kHz
SUPPLY CHARACTERISTICS
Power Supply Range V
Positive Supply Current I
Power Dissipation P
DD RANGE
DD
I
DD
DISS
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
VIL = 0 V, No Load, TA = 25°C55 55 µA typ
VIL = 0 V, No Load 100 100 µA max
VIL = 0 V, No Load 300 500 µW max
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
2
The first two codes (000H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. A
/1024 V for the 10-bit AD7391.
REF
–3–
4
AD7390/AD7391
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, 8 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V
REF
0.3 V
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .0.3 V, 8 V
to GND . . . . . . . . . . . . . . . . . . . . 0.3 V, V
V
OUT
I
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
OUT
Package Power Dissipation . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
J MAX
0.3 V
DD
TA)/θ
JA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (T
) . . . . . . . . . . 150°C
J MAX
Operating Temperature Range . . . . . . . . . . 40°C to 85°C
AD7391AR . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C
Storage Temperature Range . . . . . . . . . . . 65°C to 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
specification is not implied. Exposure to the above maximum rating conditions for
extended periods may affect device reliability.
CLR
LD
CLK
SDI
*AD7391 HAS A 10-BIT SHIFT REGISTER
RESET
REGISTER
LOAD
CLK
12-BIT AD7390*
SHIFT REGISTER
D
DAC
12
Figure 3. Digital Control Logic
PIN CONFIGURATIONS
TSSOP-8
1
2
TOP VIEW
(Not to
3
Scale)
4
8
7
6
5
SO-8
1
2
TOP VIEW
(Not to Scale)
3
4
8
7
6
5
P-DIP-8
LD
CLK
SDI
CLR
1
2
TOP VIEW
(Not to Scale)
3
4
8
V
REF
7
V
DD
6
V
OUT
5
GND
PIN DESCRIPTIONS
Pin No. Name Function
1 LD Load Strobe. Transfers shift register
data to DAC register while active low.
See truth table for operation.
2 CLK Clock Input. Positive edge clocks data
into shift register.
3 SDI Serial Data Input. Data loads directly
into the shift register.
4 CLR Resets DAC register to zero condition.
Active low input.
5 GND Analog and Digital Ground.
6V
OUT
DAC Voltage Output. Full-scale output
1 LSB less than reference input voltage REF.
7V
DD
Positive Power Supply Input. Specified
range of operation 2.7 V to 5.5 V.
8V
REF
DAC Reference Input Pin. Establishes
DAC full-scale voltage.
ORDERING GUIDE
Temperature Package Package Top Number of Devices
Model Resolution Range Description Option Mark
AD7390AN 12 40°C to 85°C 8-Lead P-DIP N-8 AD7390
AD7390AR 12 40°C to 85°C 8-Lead SOIC SO-8 AD7390
AD7390AR-REEL7 12 40°C to 85°C 8-Lead SOIC SO-8 AD7390
AD7391AN 10 40°C to 85°C 8-Lead P-DIP N-8 AD7391
AD7391AR 10 40°C to 125°C 8-Lead SOIC SO-8 AD7391
AD7391SR 10 55°C to 125°C 8-Lead SOIC SO-8 AD7391
1
2
Per Container
2
50
3
196
3
1000
2
50
3
196
3
39
AD7391ARU-REEL 10 40°C to 85°C TSSOP-8 RU-8 AD7391A42500
NOTES
1
The AD7390 contains 588 transistors. The die size measures 70 mm 68 mm.
2
Line 1 contains ADI logo symbol and part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number.
3
Line 1 contains part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number and the ADI logo symbol.
4
Line 1 contains the date code YWW. Line 2 contains the 4-digit part number plus grade.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7390/AD7391 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
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