Analog Devices AD7376AN50, AD7376AN1M, AD7376AN100, AD7376AN10, AD7376ARU50 Datasheet

615 V Operation

a

FEATURES
128 Position
Potentiometer Replacement
10 kV, 50 kV, 100 kV, 1 MV
Power Shutdown: Less than 1 mA
3-Wire SPI Compatible Serial Data Input
+5 V to +30 V Single Supply Operation
65 V to 615 V Dual Supply Operation
Midscale Preset

APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment

GENERAL DESCRIPTION

The AD7376 provides a single channel, 128-position digitally­controlled variable resistor (VR) device. This device performs the
same electronic adjustment function as a potentiometer or vari­able resistor. These products were optimized for instrument and
test equipment applications where a combination of high voltage
with a choice between bandwidth or power dissipation are avail­able as a result of the wide selection of end-to-end terminal resis­tance values. The AD7376 contains a fixed resistor with a wiper
contact that taps the fixed resistor value at a point determined by
a digital code loaded into the SPI-compatible serial-input regis­ter. The resistance between the wiper and either endpoint of the
fixed resistor varies linearly with respect to the digital code trans­ferred into the VR latch. The variable resistor offers a completely
programmable value of resistance between the A terminal and the
wiper or the B terminal and the wiper. The fixed A to B terminal
resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal tem­perature coefficient of –300 ppm/°C.

The VR has its own VR latch which holds its programmed resis­tance value. The VR latch is updated from an internal serial-to­parallel shift register which is loaded from a standard 3-wire
serial-input digital interface. Seven data bits make up the data
word clocked into the serial data input register (SDI). Only the
last seven bits of the data word loaded are transferred into the
7-bit VR latch when the CS strobe is returned to logic high. A
serial data output pin (SDO) at the opposite end of the serial
register allows simple daisy-chaining in multiple VR applications
without additional external decoding logic.

The reset (RS) pin forces the wiper to the midscale position by
loading 40

*Patent Number: 5495245

into the VR latch. The SHDN pin forces the resistor

H

Digital Potentiometer

AD7376*

FUNCTIONAL BLOCK DIAGRAM

AD7376

SDO

SDI

CLK

CS

Q

7-BIT

SERIAL

REGISTER
D

CK

GND

7

7-BIT

LATCH

RS

7

R

SHDN

SHDN

to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When shutdown is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown as long as power to V
moved. The digital interface is still active in shutdown so that
code changes can be made that will produce a new wiper posi­tion when the device is taken out of shutdown.

The AD7376 is available in both surface mount (SOL-16) and
the 14-lead plastic DIP package. For ultracompact solutions
selected models are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For operation at lower
supply voltages (+3 V to +5 V), see the AD8400/AD8402/
AD8403 products.

1

SDI

(DATA IN)

SDO

(DATA OUT)

CLK

CS

V

OUT

t

V

0

1

0

1

0

CSH0

1
0

DD

0V

D

X

t

D'

X

t

CH

t

CSS

D

X

DS

t

DH

D'

X

t

CL

t

CSH

61 LSB ERROR BAND

Figure 1. Detail Timing Diagram

The last seven data bits clocked into the serial input register will
be transferred to the VR 7-bit latch when CS returns to logic
high. Extra data bits are ignored.

is not re-

DD

t

PD_MAX

t

CS1

t

t

S

V

A
W
B

V

CSW

DD

SS

61 LSB

REV. 0

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Fax: [phone] © Analog Devices, Inc., 1997

AD7376–SPECIFICA TIONS

(VDD/VSS = 615 V 6 10% or 6 5 V 6 10%, VA = +VDD, VB = VSS/0 V, –408C < TA < +858C

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistor Tolerance ∆RT
Resistance Temperature Coefficient R
Wiper Resistance R
Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Resolution N 7 Bits
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Temperature Coefficient ∆V
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

4

5

A, B C

5

WC
Shutdown Supply Current
Shutdown Wiper Resistance R
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Output Logic High V
Output Logic Low
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Power Supply Range V
Supply Current I
Supply Current I
Supply Current I
Power Dissipation
Power Supply Sensitivity PSS ∆V

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K RAB = 10 kΩ, Code = 40
Bandwidth –3 dB BW_50K R
Bandwidth –3 dB BW_100K R
Total Harmonic Distortion THD
V

Settling Time t

W

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 5, 11])

Input Clock Pulsewidth t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay

CS Setup Time t
CS High Pulsewidth t

Reset Pulsewidth t
CLK Rise to CS Rise Hold Time t
CS Rise to Clock Rise Setup t

2

2

3

3

6

7

5

8

5, 9, 10

12

unless otherwise noted.)

R-DNL RWB, VA = NC –1 ±0.25 +1 LSB
R-INL RWB, VA = NC –1 ±0.5 +1 LSB

= +25°C –30 30 %

/∆TVAB = VDD, Wiper = No Connect –300 ppm/°C

AB
W
W

INL –1 ±0.5 +1 LSB
DNL –1 ±0.1 +1 LSB

/∆T Code = 40

W
WFSE
WZSE

V

A, B, W
A, B
W

I

A_SD

W_SD

CM

IH
IL
OH

V

OL

IL

C

IL

DD/VSS
DD

DD
DD
SS

P

DISS

PSS ∆VDD = +15 V ± 10% or ∆VSS = –15 V ± 10% 0.01 0.02 %/%

W

S

N_WB

, t

CH

CL
DS
DH

t

PD
CSS
CSW
RS
CSH
CS1

A

IW = ±15 V/R
IW = ±5 V/R

Code = 7F
Code = 00

f = 1 MHz, Measured to GND, Code = 40
f = 1 MHz, Measured to GND, Code = 40

NOMINAL

NOMINAL

H

H

H

H
H

120 200 Ω
200 Ω

5 ppm/°C
–2 –0.5 +0 LSB
0 +0.5 +1 LSB

V

SS

V

V

DD

45 pF

60 pF

VA = VDD, VB = 0 V, SHDN = 0 0.01 1 µA
VA = VDD, VB = 0 V, SHDN = 0, VDD = +15 V 170 400 Ω
VA = VB = V

W

1nA

VDD = +5 V or +15 V 2.4 V
VDD = +5 V or +15 V 0.8 V
RL = 2.2 kΩ to +5 V 4.9 V
IOL = 1.6 mA, V

= +5 V, VDD = +15 V 0.4 V

LOGIC

VIN = 0 V or +15 V ±1 µA

5pF

Dual Supply Range ±4.5 ±16.5 V
Single Supply Range, VSS = 0 4.5 28 V
VIH = +5 V or VIL = 0 V, VDD = +5 V 0.0001 0.01 mA
VIH = +5 V or VIL = 0 V, VDD = +15 V 0.75 2 mA
VIH = +5 V or VIL = 0 V, VSS = –5 V or –15 V 0.02 0.1 mA
VIH = +5 V or VIL = 0 V, VDD = +15 V, VSS = –15 V 11 30 mW

= +5 V ± 10%, or ∆VSS = –5 V ± 10% 0.05 0.15 %/%

DD

520 kHz

125 kHz

60 kHz

= 50 kΩ, Code = 40

AB

= 100 kΩ, Code = 40

AB

H
H

H

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.005 %
VA = 10 V, VB = 0 V, ±1 LSB Error Band 4 µs
RWB = 25 kΩ, f = 1 kHz, RS = 0 14 nV√Hz

Clock Level High or Low 120 ns

30 ns
20 ns

RL = 2.2 kΩ, CL < 20 pF 10 100 ns

120 ns
150 ns
120 ns
120 ns
120 ns

–2–

REV. 0

AD7376

WARNING!

ESD SENSITIVE DEVICE

NOTES

11

Typicals represent average readings at +25°C, VDD = +15 V, and VSS = –15 V.

12

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit.

13

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit.

14

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

15

Guaranteed by design and not subject to production test.

16

Measured at the A terminal. A terminal is open circuit in shutdown mode.

17

IOL = 200 µA for the 50 kΩ version operating at VDD = +5 V.

18

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

19

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band­width. The highest R value results in the minimum overall power consumption.

10

All dynamic characteristics use VDD = +15 V and VSS = –15 V.

11

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +5 V or +15 V.

12

Propagation delay depends on value of VDD, RL and CL see Applications section.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +30 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –16.5 V

SS

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +44 V

DD

V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, V

A

DD

AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . ±20 mA

Digital Input Voltages to GND . . . . . . . . . . 0 V, V

+ 0.3 V

DD

Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

MAX) . . . . . . .+150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Package Power Dissipation . . . . . . . . . . . . (T

Thermal Resistance θ

JA

MAX – TA)/θ

J

JA

P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W

SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C/W

ORDERING GUIDE

Temperature Package Package

Model kV Range Description Options

AD7376AN10 10 –40°C to +85°C PDIP-14 N-14
AD7376AR10 10 –40°C to +85°C SOL-16 R-16
AD7376ARU10 10 –40°C to +85°C TSSOP-14 RU-14
AD7376AN50 50 –40°C to +85°C PDIP-14 N-14
AD7376AR50 50 –40°C to +85°C SOL-16 R-16
AD7376ARU50 50 –40°C to +85°C TSSOP-14 RU-14
AD7376AN100 100 –40°C to +85°C PDIP-14 N-14
AD7376AR100 100 –40°C to +85°C SOL-16 R-16
AD7376ARU100 100 –40°C to +85°C TSSOP-14 RU-14
AD7376AN1M 1,000 –40°C to +85°C PDIP-14 N-14
AD7376AR1M 1,000 –40°C to +85°C SOL-16 R-16
AD7376ARU1M 1,000 –40°C to +85°C TSSOP-14 RU-14
Die Size: 101.6 mil × 127.6 mil, 2.58 mm × 3.24 mm
Number Transistors: 840

PIN CONFIGURATIONS

PDIP & TSSOP-14 SOL-16

1

A

1

B

2

V

3

SS

4

GND

CLK

TOP VIEW

(Not to Scale)

5

CS

6

RS

7

NC = NO CONNECT

AD7376

14

W

13

NC

12

V

DD

11

SDO

10

SHDN

SDI

9
8

NC

A

2

B

3

V

SS

4

GND

5

CS

(Not to Scale)

6

RS

CLK

7
8

NC

NC = NO CONNECT

AD7376

TOP VIEW

16
15
14
13
12
11
10

9

W
NC
V

DD

SDO

SHDN

SDI
NC
NC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7376 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0

AD7376

CODE – Decimal

R-DNL ERROR – LSB

0.25

–0.25

0 16 12832 48 64 80 96 112

0.20

0.05
0

–0.10

–0.20

0.15

0.10

–0.05

–0.15

TA = –558C

TA = +258C

VDD = +15V
V

SS

= –15V

R

AB

= 50kV

TA = +858C

100

AB

75

50

PERCENT OF NOMINAL

25

END-TO-END RESISTANCE – % R

–Typical Performance Characteristics

R

WB

0

0

32 128

64 96

CODE – Decimal

R

Figure 2. Wiper To End Terminal
Percent Resistance vs. Code

WA

0.5

0.4

0.3

0.2

0.1
0

–0.1
–0.2

R-INL ERROR – LSB

–0.3
–0.4
–0.5

0 16 128

TA = –558C

TA = +258C

TA = +858C

VDD = +15V

= –15V

V

SS

V

= 2.5V

A

= 0V

V

B

= 50kV

R

AB

32 48 64 80 96 112

CODE – Decimal

Figure 3. Resistance Step Position
Nonlinearity Error vs. Code

Figure 4. Relative Resistance Step
Change from Ideal vs. Code

50

49

48

47

46

NOMINAL END-TO-END RESISTANCE – kV

45

–55 –35 105

VDD = +15V
V
R

–15 5 25 45 65 85

TEMPERATURE – 8C

Figure 5. Nominal Resistance vs.
Temperature

1.0

0.8

0.6

INL – LSB

0.4

0.2

0

51015202530

SUPPLY VOLTAGE (VDD - VSS) – Volts

Figure 8. Potentiometer Divider
Nonlinearity Error vs. Supply
Voltage

= –15V

SS

= 50kV NOMINAL

AB

VA = 2.5V
V

= 0V

B

CODE = 40
RAB = 50kV

14

01

125

H

12

10

8

– V

WA

V

6

4

2

0

0 0.25 20.5 0.75 1 1.25 1.5 1.75

10

H

20

H

40

H

CODE = 70

IWA – mA

H

TA = +258C
V

= +15V

DD

V

= –15V

SS

R

= 50kV

AB

7F

H

Figure 6. Resistance Linearity vs.
Conduction Current

20
15

H

10

5
0

–5

–10

/DT POTENTIOMETER

–15

WB

MODE TEMPCO – ppm/8C

–20

DV

–25
–30

0 16 128

32 48 64 80 96 112

VDD = +15V
V

= –15V

SS

V

= +2.5V

A

V

= 0V

B

–558C < T
R

= 50kV

AB

CODE – Decimal

< +858C

A

Figure 9. ∆VWB/∆T Potentiometer
Mode Tempco

–4–

1.5

1.2

0.9

R_INL – LSB

0.6

0.3

0

51015202530

SUPPLY VOLTAGE (VDD - VSS) – Volts

Iw = 100mA, TA = +258C
DATA = 40

H

Figure 7. Resistance Nonlinearity
Error vs. Supply Voltage

1000

900

RAB = 50kV

800
700
600
500
400

VDD = +5V

300

V

200
100

WIPER CONTACT RESISTANCE – V

0
–55 –35 125

VDD = +5V
V

= 0V

SS

= –5V

SS

VDD = +15V
V

= –15V

–15 5 25 45 65 105

TEMPERATURE – 8C

SS

85

Figure 10. Wiper Contact
Resistance vs. Temperature

REV. 0