ANALOG DEVICES AD5750, AD5750-1, AD5750-2 Service Manual

Industrial Current/Voltage Output Driver

with Programmable Ranges

AD5750/AD5750-1/AD5750-2

Rev. E

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maximum supply, programmable ranges

AD5420

Single channel, 16-bit, serial input, 4 mA to

Data Sheet

FEATURES

Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA

to 24 mA, ±20 mA, and ±24 mA
±0.03% full-scale range (FSR) total unadjusted error (TUE)
±5 ppm/°C typical output drift

Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V

with 20% overrange
±0.02% FSR TUE

±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
Packet error checking (PEC)
Asynchronous CLEAR function
Flexible power-up condition to 0 V or tristate
Power supply range

AV

: +12 V (± 10%) to +24 V (± 10%)

DD

AV

: −12 V (± 10%) to −24 V (± 10%)

SS

Output loop compliance to AV
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package

APPLICATIONS

Process controls
Actuator controls
PLCs

GENERAL DESCRIPTION

The AD5750/AD5750-1/AD5750-2 are single-channel, low cost,
precision voltage/current output drivers with hardware- or
software-programmable output ranges. The software ranges are
configured via an SPI-/MICROWIRE™-compatible serial interface.
The AD5750/AD5750-1/AD5750-2 target applications in PLC
and industrial process control. The analog input to the AD5750/

AD5750-1/AD5750-2 is provided from a low voltage, single-supply

digital-to-analog converter (DAC) and is internally conditioned
to provide the desired output current/voltage range. Analog input
ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V
to 4.096 V (AD5750).

− 2.75 V

DD

The output current range is programmable across five current
ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA, ±20 mA,
and ±24 mA. An overrange of 2% is available on the unipolar
current ranges.

Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
output ranges. An overrange of 20% is available on the voltage
ranges.

Analog outputs are short-circuit and open-circuit protected and
can drive capacitive loads of 1 µF and inductive loads of 0.1 H.

The devices are specified to operate with a power supply range
from ±12 V to ±24 V. Output loop compliance is 0 V to AV

DD

−

2.75 V.

The flexible serial interface is SPI and MICROWIRE compatible
and can operate in 3-wire mode to minimize the digital isolation
required in isolated applications. The interface also features an
optional PEC feature using CRC-8 error checking, useful in
industrial environments where data communication corruption
can occur.

The devices also include a power-on-reset function, ensuring that
the devices power up in a known state (0 V or tristate), and an
asynchronous CLEAR pin that sets the outputs to a zero scale/mid­scale voltage output or the low end of the selected current range.

The HW SELECT pin is used to configure the parts for hardware
or software mode on power-up.

Table 1. Related Devices

Part Number Description

AD5422 Single channel, 16-bit, serial input current

source and voltage output DAC

AD5751 Industrial I/V output driver, single supply, 55 V

20 mA current source DAC

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license i s granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5750/AD5750-1/AD5750-2 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings .......................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Voltage Output ............................................................................ 13

Current Output ........................................................................... 17

Terminology .................................................................................... 22

Theory of Operation ...................................................................... 23

Software Mode ............................................................................ 23

Current Output Architecture .................................................... 25

Driving Inductive Loads ............................................................ 25

Power-On State of AD5750/AD5750-1/AD5750-2 ................... 25

Default Registers at Power-On ................................................. 26

Reset Function ............................................................................ 26

OUTEN ........................................................................................ 26

Software Control ........................................................................ 26

Hardware Control ...................................................................... 28

Transfer Function ....................................................................... 28

Detailed Description of Features .................................................. 29

Output Fault Alert—Software Mode ....................................... 29

Output Fault Alert—Hardware Mode ..................................... 29

Voltage Output Short-Circuit Protection ................................ 29

Asynchronous Clear (CLEAR) ................................................. 29

External Current Setting Resistor ............................................ 30

Programmable Overrange Modes ............................................ 30

Packet Error Checking ............................................................... 30

Applications Information .............................................................. 31

Transient Voltage Protection .................................................... 31

Thermal Considerations ............................................................ 31

Layout Guidelines....................................................................... 31

Galvanically Isolated Interface ................................................. 32

Microprocessor Interfacing ....................................................... 32

Outline Dimensions ....................................................................... 33

Ordering Guide .......................................................................... 33

REVISION HISTORY

6/12—Rev. D to Rev. E

Changes to Figure 3 .......................................................................... 9

Changes to Status Bit Read Operation Section ........................... 28

Updated Outline Dimensions ....................................................... 33

4/12—Rev. C to Rev. D

Added AD5750-2 ................................................................ Universal

Changes to Table 2 ............................................................................ 4

Updated Outline Dimensions ....................................................... 33

Changes to Ordering Guide .......................................................... 33

7/10—Rev. B to Rev. C

Added Leakage Current in Voltage Output Characteristics

Parameter (Table 2) .......................................................................... 5

Added Leakage Current in Current Output Characteristics

Parameter (Table 2) .......................................................................... 6

6/10—Rev. A to Rev. B

Changes to Table 1 ............................................................................ 1

Changes to Table 2, Power Requirements ..................................... 7

Rev. E | Page 2 of 36

8/09—Rev. 0 to Rev. A

Added AD5750-1................................................................ Universal

Changes to Features and General Description Sections .............. 1

Changes to Table 2 ............................................................................. 4

Changes to Theory of Operation Section and Figure 51 .......... 23

Change to Figure 52 and Table 6 Title ......................................... 24

Changes to Current Output Architecture Section and Power-On

State of AD5750/AD5750-1 .......................................................... 25

Changes to Transfer Function Section ........................................ 28

Changes to Programmable Overrange Modes Section ............. 30

Changes to Ordering Guide .......................................................... 33

7/09—Revision 0: Initial Version

Data Sheet AD5750/AD5750-1/AD5750-2

CLEAR

VSENSE+

VOUT

VSENSE–

REXT1

IOUT

DV

CC

GND

AVDDGND

COMP1 COMP2

AD2/R1* AD1/R2*

AD0/R3* AV

SS

CLRSEL

HW SELECT

VIN

VREF

SCLK/OUTEN*

SDIN/R0*

SYNC/RSET*

SDO/VFAULT*

INPUT SHIFT

REGISTER

AND

CONTROL

LOGIC

STATUS

REGISTER

VOUT RANGE

SCALING

IOUT RANG E

SCALING

VOUT

SHORT FAULT

POWER-

ON RESET

FAULT/TEMP*

NC/IFAULT*

OVERTEMP

VOUT SHO RT FAULT

IOUT OPENFAULT

RESET

R

SET

Vx**

V

SS

V

DD

R2 R3

REXT2

IOUT

OPEN FAULT

AD5750/AD5750-1/AD5750-2

*DENOTES S HARE D P IN. SOF TWARE MODE DE NOTED BY REGUL AR TEXT, HARDWARE MODE

DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/ TEMP PIN, IN SOFTWARE MODE, THIS
PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION.

**Vx IS AN I NTERNAL BIAS V OLTAG E ( CAN BE GROUND OR OT HE R V O LTAGE) T HAT IS USED

TO GENERATE THE INTERNAL SENSE CURRENT S NE E DE D FOR THE CURRENT OUTPUTS.

07268-001

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. E | Page 3 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet

INPUT VOLTAGE RANGE

Output unloaded

−5 +5 V

Bipolar Zero Error (Offset at Midscale)

−10 +10

mV

±10 V range

SPECIFICATIONS

AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: R
unless otherwise noted.

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

0 to 4.096 V AD5750

0 to 2.5 AD5750-1/AD5750-2
Input Leakage Current −1 +1 µA

REFERENCE INPUT

Reference Input Voltage 4.096 V AD5750; external reference must

2.5 V AD5750-2; external reference needs

1.25 V AD5750-1; external reference needs

Input Leakage Current −1 +1 µA

VOLTAGE OUTPUT

Output Voltage Ranges 0 5 V
0 10 V AVDD needs to have minimum

= 300 Ω. All specifications T

LOAD

to be exactly as stated; otherwise,
accuracy errors show up as error
in output

to be exactly as stated; otherwise,
accuracy errors show up as error
in output

to be exactly as stated; otherwise,
accuracy errors show up as error
in output

1.3 V headroom or >11.3 V

MIN

to T

MAX

,

−10 +10 V AVDD/AVSS needs to have minimum

1.3 V headroom or >±11.3 V

Output Voltage Overranges 0 6 V Programmable overranges; see the

Detailed Description of Features
section

0 12 V

−6 +6 V

−12 +12 V

−2.5 +2.5 V
Accuracy

Total Unadjusted Error (TUE)

B Version2 −0.1 +0.1 % FSR

−0.05 ±0.02 +0.05 % FSR TA = 25°C

A Version2 −0.3 +0.3 % FSR

−0.1 ±0.05 +0.1 % FSR TA = 25°C
Relative Accuracy (INL) −0.02 ±0.005 +0.02 % FSR

−8 ±0.5 +8 mV TA = 25°C, ±10 V range

−5 +5 mV ±5 V range

−4 ±0.3 +4 mV TA = 25°C, ± 5 V range
Bipolar Zero Error Temperature

Coefficient
Zero-Scale Error −10 +10 mV ±10 V range

−8 ±0.5 +8 mV TA = 25°C, ±10 V range

−5 +5 mV ± 5 V range

−4 ±0.3 +4 mV TA = 25°C, ±5 V range

3

±1.5 ppm FSR/°C All bipolar ranges

Rev. E | Page 4 of 36

Data Sheet AD5750/AD5750-1/AD5750-2

−0.04

±0.015

+0.04

% FSR

TA = 25°C, AD5750 and AD5750-1

Loads section

DC Output Impedance

0.12 Ω

Parameter1 Min Typ Max Unit Test Conditions/Comments

Zero-Scale Error Temperature

Coefficient

3

Zero-Scale/Offset Error −5 +5 mV 0 V to 10 V range

−4 ±0.5 +4 mV TA = 25°C, 0 V to 10 V range

−3 +3 mV 0 V to 5 V range

−2.2 ±0.3 +2.2 mV TA = 25°C, 0 V to 5 V range
Offset Error Temperature Coefficient3 ±2 ppm FSR/°C All unipolar ranges
Gain Error −0.05 +0.05 % FSR All bipolar/unipolar ranges,

−0.07 +0.07 % FSR AD5750-2

−0.04 ±0.015 +0.04 % FSR TA = 25°C, AD5750, AD5750-1, and

Gain Error Temperature Coefficient3 ±0.5 ppm FSR/°C
Full-Scale Error −0.05 +0.05 % FSR All bipolar/unipolar ranges,

−0.07 +0.07 % FSR AD5750-2
Full-Scale Error Temperature

Coefficient

3

VOLTAGE OUTPUT CHARACTERISTICS3

Headroom 1.3 V Output unloaded

Short-Circuit Current 15 mA

Load 1 kΩ

Capacitive Load Stability TA = 25°C

R

= ∞ 1 nF

LOAD

R

= 2 kΩ 1 nF

LOAD

R

= ∞ 2 µF External compensation capacitor

LOAD

±1 ppm FSR/°C All bipolar ranges

AD5750 and AD5750-1

AD5750-2

AD5750 and AD5750-1

±1.5 ppm FSR/°C

required; see the Driving Inductive

Leakage Current −110 +110 nA Output disabled; leakage to ground

0 V to 5 V Range, ¼ to ¾ Step 7 µs Specified with 2 kΩ || 220 pF, ±0.05%

0 V to 5 V Range, 40 mV Input Step 4.5 µs Specified with 2 kΩ || 220 pF, ±0.05%

Slew Rate 2 V/µs Specified with 2 kΩ || 220 pF

Output Noise 2.5 µV rms 0.1 Hz to 10 Hz bandwidth

45.5 µV rms 100 kHz bandwidth

Output Noise Spectral Density 165 nV/√Hz Measured at 10 kHz; specified with

2 kΩ || 220 pF

AC PSRR −65 dB 200 mV, 50 Hz/60 Hz sine wave super-

imposed on power supply voltage

DC PSRR 10 µV/V Outputs unloaded
CURRENT OUTPUT

Output Current Ranges 0 24 mA

0 20 mA

4 20 mA

−20 +20 mA

−24 +24 mA

Output Current Overranges 0 24.5 mA See the Detailed Description of

Features section

0 20.4 mA See the Detailed Description of

Features section

4 20.4 mA See the Detailed Description of

Features section

Rev. E | Page 5 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet

A Version2

−0.5 +0.5

% FSR

−10

+5

+10

µA

TA = 25°C

Gain Temperature Coefficient3

±8 ppm FSR/°C

All ranges

Full-Scale Error

−0.1 +0.1

% FSR

All ranges

Parameter1 Min Typ Max Unit Test Conditions/Comments

ACCURACY, INTERNAL R

Total Unadjusted Error (TUE)

B Version2 −0.2 +0.2 % FSR

−0.08 ±0.03 +0.08 % FSR TA = 25°C

−0.3 ±0.15 +0.3 % FSR TA = 25°C

Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR Unipolar ranges

−0.03 ±0.015 +0.03 % FSR Bipolar ranges
Offset Error −16 +16 µA 4 mA to 20 mA, 0 mA to 20 mA,

−50 +50 µA ±20 mA, ±24 mA ranges

−26 +8 +26 µA TA = 25°C

Offset Error Temperature Coefficient3 ±3 ppm FSR/°C All ranges
Bipolar Zero Error −35 +35 µA ±20 mA, ±24 mA ranges

−24 +15 +24 µA TA = 25°C
Bipolar Zero Temperature Coefficient3 ±0.5 ppm FSR/°C
Gain Error −0.2 +0.2 % FSR 4 mA to 20 mA, 0 mA to 20 mA,

−0.25 +0.25 % FSR ±20 mA, ±24 mA ranges

−0.03 ±0.006 +0.03 % FSR TA = 25°C

SET

0 mA to 24 mA ranges

0 mA to 24 mA ranges

Full-Scale Error −0.2 +0.2 % FSR All ranges

−0.125 ±0.02 +0.125 % FSR TA = 25°C
Full-Scale Temperature Coefficient3 ±4 ppm FSR/°C All ranges

ACCURACY, EXTERNAL R

SET

Total Unadjusted Error (TUE)

B Version2 −0.1 +0.1 % FSR

−0.08 ±0.03 +0.08 % FSR TA = 25°
A Version2 −0.3 +0.3 % FSR

−0.1 ±0.02 +0.1 % FSR TA = 25°C

Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 20 mA, 0 mA to 20 mA,

0 mA to 24 mA ranges

−0.03 ±0.015 +0.03 % FSR ±20 mA, ±24 mA ranges

Offset Error −14 +14 µA 4 mA to 20 mA, 0 mA to 20 mA,

0 mA to 24 mA ranges

−11 +5 +11 µA TA = 25°C

−20 +20 µA ±20 mA, ±24 mA ranges
+8 +15 µA TA = 25°C

Offset Error Temperature Coefficient3 ±2 ppm FSR/°C All ranges
Bipolar Zero Error −32 +32 µA All ranges

−22 +12 +22 µA TA = 25°C
Bipolar Zero Temperature Coefficient3 ±0.5 ppm FSR/°C
Gain Error −0.08 +0.08 % FSR All ranges

−0.07 ±0.02 +0.07 % FSR TA = 25°C
Gain Temperature Coefficient ±1 ppm FSR/°C All ranges

−0.07 ±0.02 +0.07 % FSR TA = 25°C
Full-Scale Temperature Coefficient3 ±2 ppm FSR/°C All ranges

Rev. E | Page 6 of 36

Data Sheet AD5750/AD5750-1/AD5750-2

DIGITAL INPUT

JEDEC compliant

Output High Voltage, VOH

3.6

V

10 kΩ pull-up resistor to DVCC

High Impedance Leakage Current

−1 +1

µA

Parameter1 Min Typ Max Unit Test Conditions/Comments

CURRENT OUTPUT CHARACTERISTICS3

Current Loop Compliance Voltage 0 AVDD − 2.75 V

Resistive Load See test conditions/comments column Chosen such that compliance is

not exceeded

Inductive Load See test conditions/comments column Needs appropriate capacitor at

higher inductance values; see the
Driving Inductive Loads section

Settling Time

4 mA to 20 mA, Full-Scale Step 8.5 µs 250 Ω load

4 mA to 20 mA, 120 µA Step 1.2 µs 250 Ω load
DC PSRR 1 µA/V
Output Impedance 130 MΩ
Leakage Current −12 +12 nA Output disabled; leakage to ground
VOUT/VSENSE− Error 0.9994 1.0006 Gain Error in VOUT voltage due to changes

Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current −1 +1 µA Per pin
Pin Capacitance 5 pF Per pin

DIGITAL OUTPUTS3

FAULT, IFAULT, TEMP, VFAULT

Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC

0.6 V At 2.5 mA

in VSENSE−; specified as gain, for
example, if VSENSE− moves by 1 V,
VOUT moves by 0.9994 V

SDO

Output Low Voltage, VOL 0.5 0.5 V Sinking 200 µA
Output High Voltage, VOH DVCC − 0.5 DVCC − 0.5 V Sourcing 200 µA
High Impedance Output Capacitance 3 pF

POWER REQUIREMENTS

AVDD 12 24 V ±10%
AVSS −12 −24 V ±10%
DVCC

Input Voltage 2.7 5.5 V

AIDD 4.4 5.6 mA Output unloaded, output disabled,

R3, R2, R1, R0 = 0, 1, 0, 1; RSET = 0

5.2 6.2 mA Current output enabled

5.2 6.2 mA Voltage output enabled
AISS 2.0 2.5 mA Output unloaded, output disabled,

R3, R2, R1, R0 = 0, 1, 0, 1; RSET = 0,

AD5750 and AD5750-1

2.0 3.5 mA AD5750-2

2.5 3 mA Current output enabled

2.5 3 mA Voltage output enabled
DICC 0.3 1 mA VIH = DVCC, VIL = GND
Power Dissipation 108 mW AVDD/AVSS = ±24 V, outputs unloaded

1

Temperature range: −40°C to +105°C; typical at +25°C.

2

Specification includes gain and offset errors over temperature and drift after 1000 hours, TA = 125°C.

3

Guaranteed by characterization, but not production tested.

Rev. E | Page 7 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet

t5

10

ns min

16th SCLK falling edge to

rising edge (on 24th SCLK falling edge if using PEC)

TIMING CHARACTERISTICS

AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: R
300 Ω. All specifications T

MIN

to T

, unless otherwise noted.

MAX

= 2 kΩ, CL = 200 pF, IOUT: R

LOAD

LOAD

=

Table 3.

Parameter

1, 2

Limit at T

MIN

, T

Unit Description

MAX

t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 5 ns min

falling edge to SCLK falling edge setup time

SYNC

SYNC

t6 5 ns min Minimum

high time (write mode)

SYNC
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9, t10 1.5 µs max CLEAR pulse low/high activation time
t11 5 ns min Minimum

high time (read mode)

SYNC
t12 40 ns max SCLK rising edge to SDO valid (SDO CL = 15 pF)
t13 10 ns min

1

Guaranteed by characterization, but not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

pulse low time

RESET

Rev. E | Page 8 of 36

Data Sheet AD5750/AD5750-1/AD5750-2

D15

1 2 16

D0

t

1

t

2

t

5

t

8

t

7

t

3

SCLK

SYNC

SDIN

CLEAR

VOUT

t

10

t

9

t

13

RESET

t

4

t

6

07268-003

t

11

t

12

A2

SDIN

SYNC

SCLK

A0 R = 1 0 R3 R2 R1 R0

CLRSEL OUTEN CLEAR RSET RESET

0 0A1

XSDO X X X R3 R2 R1 R0

CLRSEL OUTEN RSET

PEC

ERROR

OVER
TEMP

IOUT

FAULT

VOUT

FAULT

X

07268-004

Timing Diagrams

Figure 2. Write Mode Timing Diagram

Figure 3. Readback Mode Timing Diagram

Rev. E | Page 9 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD to GND −0.3 V to +30 V
AVSS to GND +0.3 V to −28 V
AVDD to AVSS −0.3 V to +58 V
DVCC to GND −0.3 V to +7 V
VSENSE+ to GND AVSS to AVDD
VSENSE− to GND ±5.0 V
Digital Inputs to GND

Digital Outputs to GND

VREF to GND −0.3 V to +7 V
VIN to GND −0.3 V to +7 V
VOUT, IOUT to GND AVSS to AVDD
Operating Temperature Range,

Industrial
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
32-Lead LFCSP Package

θJA Thermal Impedance 28°C/W
Lead Temperature JEDEC industry standard

Soldering J-STD-020

ESD (Human Body Model) 3 kV

−0.3 V to DV
+7 V (whichever is less)

−0.3 V to DV
+7 V (whichever is less)

−40°C to +105°C

+ 0.3 V or

CC

+ 0.3 V or

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. E | Page 10 of 36

Data Sheet AD5750/AD5750-1/AD5750-2

C

2

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

C

AULT/TEMP

NC/IFAULT

F

RESET

32

31

30

PIN 1
INDICATOR

1SDO/VFAULT
2CLRSEL

AD5750/

3CLEAR

AD5750-1/

4DV

CC

NOTES

1. NC = NO CONNE
. THE EXPOSED PADDLE IS TIED TO AVSS.

5GND
6SYNC/RSET
7SCLK/OUTEN
8SDIN/R0

AD5750-2

TOP VIEW

(Not to Scale)

9

11

10

AD1/R2

AD0/R3

AD2/R1

T.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 SDO/VFAULT

Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin
is a CMOS output.

Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to
a pull-up resistor.

2 CLRSEL

In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.

3 CLEAR

Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the
range selected (user selectable). CLEAR is a logic OR with the internal clear bit.

In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage

channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details.
4 DVCC Digital Power Supply.
5 GND Ground Connection.
6

/RSET Positive Edge Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data

SYNC

into the AD5750/AD5750-1/AD5750-2, also updating the output.

Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is

used. If RSET = 0, the external sense resistor is chosen, and if RSET = 1, the internal sense resistor is chosen.
7 SCLK/OUTEN

Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of

SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.

Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output

current/voltage range setting on the part.
9 AD2/R1

Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight

devices to be addressed on one bus.

Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output

current/voltage range setting on the part.
10 AD1/R2

Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0, allows up to eight

devices to be addressed on one bus.

Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output

current/voltage range setting on the part.

C

NC

N

NC

N

HW SELECT
29

28

27

26

25

24 VSENSE+
23 VOUT
22 VSENSE–
21 AV

SS

20 COMP1
19 COMP2
18 IOUT
17 AV

DD

12

15

13

16

14

VIN

GND

VREF

REXT2

REXT1

07268-005

Rev. E | Page 11 of 36