Analog Devices AD5744 64 prc Datasheet

Complete, Quad, 14/16-Bit, High Accuracy,

TM

i

CMOS

Preliminary Technical Data

FEATURES

Complete quad 14/16-bit D/A converter
Programmable output range: ±10 V, ±10.25 V, or ±10.5 V
±1 LSB max INL error, ±1 LSB max DNL error
Low noise : 60 nV/√

Settling time: 10µs max
Integrated reference buffers
Internal reference, 10 ppm/°C
On-chip temp sensor, ±5°C accuracy
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC

Asynchronous
Digital offset and gain adjust
Logic output control pins
DSP/microcontroller compatible serial interface
Temperature range:−40°C to +85°C
iCMOS™ Process Technology

Hz

CLR

to zero code

APPLICATIONS

Industrial automation
Open/Closed-loop servo control
Process control
Data acquisition systems
Automatic Test Equipment
Automotive test and measurement
High accuracy instrumentation

Serial Input, Bipolar Voltage Output DAC

AD5744/ AD5764

GENERAL DESCRIPTION

The AD5744/64 is a quad, 14/16-bit serial input, voltage output
digital-to analog converter that operates from supply voltages of
±12 V up to ±15 V. Nominal full-scale output range is ±10 V,
provided are integrated output amplifiers, reference buffers,
internal reference, and proprietary power-up/power-down
control circuitry. It also features a digital I/O port that may be
programmed via the serial interface, and an analog temperature
sensor. The part incorporates digital offset and gain adjust
registers per channel.

The AD5744/64 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise and 10 µs settling time and includes an on-chip 5 V
reference with a reference tempco of 10 ppm/°C max. During
power-up (when the supply voltages are changing), Vout is
clamped to 0V via a low impedance path.

The AD5744/64 uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or Offset binary formats. The asynchronous
clear function clears all DAC registers to either bipolar zero or
zero-scale depending on the coding used. The AD5744/64 is ideal
for both closed-loop servo control and open-loop control
applications. The AD5744/64 is available in a 32-lead TQFP
package, and offers guaranteed specifications over the −40°C to
+85°C industrial temperature range. See functional block
diagram, Figure 1.

iCMOS™ Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC performance.

Rev. PrC 8-Mar-05

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5744/AD5764 Preliminary Technical Data

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

Coarse gain register.................................................................... 20

Specifications..................................................................................... 4

AC Performance Characteristics................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Te r mi n ol o g y .................................................................................... 13

typical performance characteristics ............................................. 15

General Description....................................................................... 16

dac architecture........................................................................... 16

Reference Buffers........................................................................ 16

Serial interface ............................................................................16

Simultaneous Updating Via

transfer function......................................................................... 18

Asynchronous Clear (

LDAC

.......................................... 17

CLR

)....................................................... 18

Fine gain register ........................................................................ 21

offset register............................................................................... 21

AD5744/64 Features....................................................................... 22

Analog Output Control............................................................. 22

Digital Offset and Gain Control............................................... 22

Programmable Short-Circuit protection................................. 22

Digital I/O Port........................................................................... 22

Temperature Sensor ................................................................... 22

Local ground offset adjust......................................................... 22

applications information............................................................... 23

typical operating circuit............................................................. 23

layout guidelines......................................................................... 24

Isolated interface ........................................................................ 24

microprocessor interfacing....................................................... 24

Evaluation board ........................................................................ 26

Function Register ....................................................................... 19

DAta register ............................................................................... 20

REVISION HISTORY

Revision PrC 8-Mar-05: Preliminary Version

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

Rev. PrC 8-Mar-05| Page 2 of 27

Preliminary Technical Data AD5744/AD5764

FUNCTIONAL BLOCK DIAGRAM

PGND

AV

DD

AV

AV

AV

SS

DD

SS

REFOUT

REFGND

RSTINRSTOUTVREF AB

DV

CC

DGND

SDIN
SCLK
SYNC

SDO

D0

D1

BIN/2SCOMP

CLR

INPUT SHIFT

REGISTER

AND

CONTROL

LOGIC

14/16

REFERENCE

INPUT
REG A

GAIN REG A

OFFSET REG A

INPUT
REG B

GAIN REG B

OFFSET REG B

INPUT
REG C

GAIN REG C

OFFSET REG C

INPUT
REG D

GAIN REG D

OFFSET REG D

+5V

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

14/16

14/16

14/16

14/16

REFERENCE

BUFFERS

DAC A

DAC B

DAC C

DAC D

REFERENCE

BUFFERS

VOLTAGE
MONITOR

AND

CONTROL

ISCC

G1

VOUTA

G2

AGNDA

G1

VOUTB

G2

AGNDB

G1

VOUTC

G2

AGNDC

G1

VOUTD

G2

AGNDD

TEMP

SENSOR

Figure 1. Functional Block Diagram

LDAC VREF CD TEMP

Rev. PrC 8-Mar-05| Page 3 of 27

AD5744/AD5764 Preliminary Technical Data

SPECIFICATIONS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;

= 2.7 V to 5.5 V, R

DV

CC

Table 1.

Parameter A Grade

ACCURACY

Resolution 16

Relative Accuracy (INL) ±4 ±2 ±1 LSB max
Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic
Bipolar Zero Error ±1 ±1 ±1 mV max

Bipolar Zero TC ±2 ±2 ±2 ppm FSR/°C max
Zero Code Error ±1 ±1 ±1 mV max

Zero Code TC ±2 ±2 ±2 ppm FSR/°C max
Gain Error ±0.02 ±0.02 ±0.02 % FSR max

Gain TC 2 2 2 ppm FSR/°C max
DC Crosstalk

2

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 5 5 V nom ±1% for specified performance
DC Input Impedance 1 1 1 MΩ min Typically 100 MΩ
Input Current ±10 ±10 ±10 µA max Typically ±30 nA
Reference Range 1/5 1/5 1/5 V min/max

Reference Output

Output Voltage 4.999/5.001 4.999/5.001 4.999/5.001 V min/max At 25°C
Reference TC ±10 ±10 ±10 ppm/°C max
Output Noise(0.1 Hz to 10 Hz) TBD TBD TBD µV p-p typ
Noise Spectral Density TBD TBD TBD

OUTPUT CHARACTERISTICS2

Output Voltage Range
±13 ±13 ±13 V min/max AVDD/AVSS = ±16.5 V
Output Voltage TC ±2 ±2 ±2 ppm FSR/°C max
Output Voltage Drift VS Time ±TBD ±TBD ±TBD

Short Circuit Current 10 10 10 mA max
Load Current ±1 ±1 ±1 mA max For specified performance

Capacitive Load Stability

RL = ∞ 200 200 200 pF max
RL = 10 kΩ TBD TBD TBD pF max

DC Output Impedance 0.3 0.3 0.3 Ω max

DIGITAL INPUTS2

VIH, Input High Voltage 2 2 2 V min

1

Temperature range −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

2

Guaranteed by characterization. Not production tested.

3

Output amplifier headroom requirement is 1.4 V min.

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

1

B Grade

16

14

14

0.5 0.5 0.5 LSB max

3

±10 ±10 ±10 V min/max AVDD/AVSS = ±11.4 V

to T

MIN

1

C Grade1 Unit Test Conditions/Comments

16
14

, unless otherwise noted.

MAX

Bits AD5764

AD5744

At 25°C. Error at other
temperatures
obtained using bipolar zero TC.

At 25°C. Error at other
temperatures
obtained using zero code TC.

At 25°C. Error at other
temperatures
obtained using gain TC.

Hz

typ

nV/√

ppm FSR/1000 Hours
typ

= 6 KΩ , See Figure ???

RI

SCC

= 2.7 V to 5.5 V, JEDEC

DV

CC

compliant

Rev. PrC 8-Mar-05| Page 4 of 27

Preliminary Technical Data AD5744/AD5764

Parameter A Grade

1

B Grade

1

C Grade1 Unit Test Conditions/Comments

VIL, Input Low Voltage 0.8 0.8 0.8 V max
Input Current ±10 ±10 ±10 µA max Total for All Pins. TA = T

MIN

to T

Pin Capacitance 10 10 10 pF max

DIGITAL OUTPUTS (D0,D1, SDO)

2

Output Low Voltage 0.4 0.4 0.4 V max DVCC= 5 V ± 10%, sinking 200 µA
Output High Voltage DVCC – 1 DVCC – 1 DVCC – 1 V min

= 5 V ± 10%, Sourcing 200

DV

CC

µA

Output Low Voltage 0.4 0.4 0.4 V max

= 2.7 V to 3.6 V, Sinking 200

DV

CC

µA

Output High Voltage DVCC – 0.5 DVCC – 0.5 DVCC – 0.5 V min

= 2.7 V to 3.6 V, Sourcing

DV

CC

200 µA

High Impedance Leakage

±1 ±1 ±1 µA max SDO only

Current
High Impedance Output

5 5 5 pF typ SDO only

Capacitance

TEMP SENSOR

Accuracy ±1 ±1 ±1 °C typ At 25°C

±5 ±5 ±5 °C max −40°C < T <+85°C

Output Voltage @ 25°C 1.5 1.5 1.5 V typ
Output Voltage Scale Factor 5 5 5 mV/°C typ
Output Voltage Range 0/3.0 0/3.0 0/3.0 V min/max
Output Load Current 200 200 200 µA max Current source only.
Power On Time 10 10 10 ms typ To within ±5°C

POWER REQUIREMENTS

AVDD/AVSS 11.4/16.5 11.4/16.5 11.4/16.5 V min/max
DVCC 2.7/5.5 2.7/5.5 2.7/5.5 V min/max
Power Supply Sensitivity

∆V

/∆ΑVDD −85 −85 −85 dB typ

OUT

4

AIDD 3.75 3.75 3.75 mA/Channel max Outputs unloaded
AISS 2.75 2.75 2.75 mA/Channel max Outputs unloaded

DICC 1 1 1 mA max

= DVCC, VIL = DGND. TBD mA

V

IH

typ

Power Dissipation 244 244 244 mW typ

±12 V operation output
unloaded

MAX

.

4

Guaranteed by characterization. Not production tested.

Rev. PrC 8-Mar-05| Page 5 of 27

AD5744/AD5764 Preliminary Technical Data

AC PERFORMANCE CHARACTERISTICS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND=0 V; REFAB = REFCD= 5 V Ext;
DV

= 2.7 V to 5.5 V, R

CC

characterization, not production tested.

Table 2.

Parameter A Grade B Grade C Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 8 8 8 µs typ Full-scale step
10 10 10 µs max
1 1 1 µs max 512 LSB step settling @ 16 Bits

Slew Rate 5 5 5 V/µs typ

Digital-to-Analog Glitch Energy 5 5 5 nV-s typ

Glitch Impulse Peak Amplitude 5 5 5 mV max

Channel-to-Channel Isolation 100 100 100 dB typ

DAC-to-DAC Crosstalk 5 5 5 nV-s typ

Digital Crosstalk 5 5 nV-s typ

Digital Feedthrough 1 1 nV-s typ

Output Noise (0.1 Hz to 10 Hz) 0.1 0.1 LSB p-p typ

Output Noise (0.1 kHz to 100 kHz)

1/f Corner Frequency 1 1 kHz typ

Output Noise Spectral Density 60 60

Complete System Output Noise Spectral

6

Density

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

5

45 45 µV rms max

80 80

MIN

to T

, unless otherwise noted. Guaranteed by design and

MAX

Effect of input bus activity on DAC
output under test

nV/√
nV/√

Hz
Hz

typ
typ

Measured at 10 kHz
Measured at 10 kHz

5

Guaranteed by design and characterization. Not production tested.

6

Includes noise contributions from integrated reference buffers, 14/16-bit DAC and output amplifier.

Rev. PrC 8-Mar-05| Page 6 of 27

Preliminary Technical Data AD5744/AD5764

TIMING CHARACTERISTICS

AVDD = +11.4 V to +16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;

= 2.7 V to 5.5 V, R

DV

CC

Table 3.

Parameter

7, ,8 9

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min

10

t5
t6 40 ns min
t7 5 ns min Data setup time

t8 0 ns min Data hold time
t9 20 ns min

t10 20 ns min
t11 5 ns min
t12 10 µs max DAC output settling time

t13 20 ns min
t14 12 µs max

11,12

t

15

12

t

16

12

t

17

7

Guaranteed by design and characterization. Not production tested.

8

All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

9

See Figure 2, Figur , and . e 3 Figure 4

10

Stand-alone mode only.

11

Measured with the load circuit of . Figure 5

12

Daisy-chain mode only.

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

Limit at T

MIN

, T

MAX

Unit Description

13 ns min

to T

MIN

SYNC

th

24
Minimum

SYNC
LDAC
LDAC

CLR
CLR

, unless otherwise noted.

MAX

falling edge to SCLK falling edge setup time

SCLK falling edge to

SYNC

high time

rising edge to

pulse width low
falling edge to DAC output response time

pulse width low

pulse activation time
20 ns max SCLK rising edge to SDO valid
8 ns min

20 ns min

SYNC

rising edge to SCLK rising edge

SYNC

rising edge to

SYNC

LDAC

falling edge

LDAC

falling edge

rising edge

Rev. PrC 8-Mar-05| Page 7 of 27

AD5744/AD5764 Preliminary Technical Data

SCLK

SYNC

SDIN

LDAC

V

OUT

LDAC = 0

V

OUT

t

1

12 24

t

6

t

4

t

7

DB23

t

3

t

8

t

2

DB0

t

5

t

t

9

t

11

10

t

t

11

t

12

12

t

13

t

14

V

CLR

OUT

Figure 2. Serial Interface Timing Diagram

SCLK

t

6

t

4

SYNC

t

7

SDIN

SDO

DB23 DB0 DB23 DB0

04641-PrA-002

t

1

24 48

t

3

t

8

t

2

INPUT WORD FOR DAC N+1INPUT WORD FOR DAC N

t

15

DB23

DB0

t

5

t

16

LDAC

Figure 3. Daisy Chain Timing Diagram

Rev. PrC 8-Mar-05| Page 8 of 27

INPUT WORD FOR DAC NUNDEFINED

t

17

t

10

4641-PrA-003

Preliminary Technical Data AD5744/AD5764

T

SCLK

SYNC

SDIN

SDO

DB23 DB0 DB23 DB0

REGISTER TO BE READ

UNDEFINED

24 48

NOP CONDITIONINPUT WORD SPECIFIES

DB23

SELECTED REGISTER DATA

CLOCKED OUT

DB0

04641-PrA-005

Figure 4. Readback Timing Diagram

O OUTPUT

PIN

200µAI

C

L

50pF

200µAI

OL

VOH (MIN) OR
V

(MAX)

OL

OH

04641-PrA-004

Figure 5. Load Circuit for SDO Timing Diagram

Rev. PrC 8-Mar-05| Page 9 of 27