Analog Devices AD1853 a Datasheet

a

Stereo, 24-Bit, 192 kHz, Multibit  DAC

AD1853*

FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz

Multibit Sigma-Delta Modulator with “Perfect Differential

Linearity Restoration” for Reduced Idle Tones and

Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz

(A-Weighted Mono)

117 dB Signal to Noise (Not Muted) at 48 kHz

(A-Weighted Stereo)

119 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)

116 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,

Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz

Sample Rates
Clock Auto-Divide Circuit Supports Five Master-Clock

Frequencies
Flexible Serial Data Port with Right-Justified, Left-

Justified, I

2

S-Compatible and DSP Serial Port Modes

28-Lead SSOP Plastic Package

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive

Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors

PRODUCT OVERVIEW

The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per­formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at­tenuator and mute capability, programmed through an SPI­compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.

The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I

2

S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.

The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.

DATA INPUT

*Patents Pending.

DIGITAL

SERIAL

MODE

2

INT2 INT4

SERIAL

DATA

INTERFACE

AD1853

ATTEN/

MUTE

ATTEN/

MUTE

RESET

INTERPOLATOR

INTERPOLATOR

8  F

8  F

VOLUME

MUTE

S

S

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

2

AUTO-CLOCK

DIVIDE CIRCUIT

22

ZERO
FLAG

CLOCK

IN

ANALOG
OUTPUTS

CONTROL DATA

INPUT

3

SERIAL CONTROL

INTERFACE

MULTIBIT SIGMA-

DELTA MODULATOR

MULTIBIT SIGMA-

DELTA MODULATOR

DE-EMPHASISMUTE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

ANALOG

SUPPLY

DIGITAL
SUPPLY

VOLTAGE

REFERENCE

IDAC

IDAC

AD1853–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AVDD, DVDD) +5.0 V
Ambient Temperature +25°C
Input Clock 24.576 MHz (512 × FS Mode)
Input Signal 996.094 kHz

–0.5 dB Full Scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 Bits
Input Voltage HI 3.5 V
Input Voltage LO 0.8 V

ANALOG PERFORMANCE (See Figures)

Min Typ Max Units

Resolution 24 Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)

No Filter (Stereo) 114 dB
No Filter (Mono—See Figure 30) 117 dB
With A-Weighted Filter (Stereo) 117 dB
With A-Weighted Filter (Mono—See Figure 30) 120 dB

Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

No Filter (Stereo) 107.5 113 dB
No Filter (Mono—See Figure 30) 116 dB
With A-Weighted Filter (Stereo) 110 116 dB
With A-Weighted Filter (Mono—See Figure 30) 119 dB

Total Harmonic Distortion + Noise (Stereo) –94 –104 dB

0.00063 %

Total Harmonic Distortion + Noise (Mono—See Figure 30) –107 dB

0.00045 %

Analog Outputs

Differential Output Range (±Full Scale w/1 mA into I
Output Capacitance at Each Output Pin 30 pF
Out-of-Band Energy (0.5 × F

to 75 kHz) –90 dB

S

CMOUT 2.75 V
DC Accuracy

Gain Error ± 3.0 %
Interchannel Gain Mismatch –0.15 0.01 +0.15 dB

Gain Drift 25 ppm/°C
Interchannel Crosstalk (EIAJ Method) –125 dB
Interchannel Phase Deviation ± 0.1 Degrees
Mute Attenuation –100 dB
De-Emphasis Gain Error ± 0.1 dB

NOTES
Single-ended current output range: 1 mA ± 0.75 mA.

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.

) 3.0 mA p-p

REF

DIGITAL I/O (+25C–AVDD, DVDD = +5.0 V  10%)

Min Typ Max Units

Input Voltage HI (V
Input Voltage LO (V
Input Leakage (I
Input Leakage (I

) 2.4 V

IH

) 0.8 V

IL

@ VIH = 3.5 V) 10 µA

IH

@ V

IL

= 0.8 V) 10 µA

IL

Input Capacitance 20 pF
Output Voltage HI (V

)DV

OH

–0.5 DVDD–0.4 V

DD

Output Voltage LO (VOL) 0.2 0.5 V

Specifications subject to change without notice.

–2–

REV. A

AD1853

POWER

Min Typ Max Units

Supplies

Voltage, Analog and Digital 4.5 5 5.5 V
Analog Current 12 15 mA
Digital Current 28 33 mA

Dissipation

Operation—Both Supplies 200 mW
Operation—Analog Supply 60 mW
Operation—Digital Supply 140 mW

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins –77 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –72 dB

Specifications subject to change without notice.

TEMPERATURE RANGE

Min Typ Max Units

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 125 °C

Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB)

44.1 DC–20 24.1–328.7 110 ± 0.0002
48 DC–21.8 26.23–358.28 110 ± 0.0002
96 DC–39.95 56.9–327.65 115 ± 0.0005
192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz)

+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)

Specifications subject to change without notice.

GROUP DELAY

Chip Mode Group Delay Calculation F

INT8x Mode 5553/(128 × F
INT4x Mode 5601/(64 × F

) 48 kHz 903.8 µs

S

) 96 kHz 911.6 µs

S

S

Group Delay Units

INT2x Mode 5659/(32 × FS) 192 kHz 921 µs

Specifications subject to change without notice.

DIGITAL TIMING (Guaranteed Over 0C to +70C, AVDD = DVDD = +5.0 V  10%)

Min Units

t

DMP

t

DML

t

DMH

t

DBH

t

DBL

t

DBP

t

DLS

t

DLH

t

DDS

t

DDH

t

PDRP

*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature.

Specifications subject to change without notice.

MCLK Period (With F
MCLK LO Pulsewidth (All Modes) 0.4 × t
MCLK HI Pulsewidth (All Modes) 0.4 × t
BCLK HI Pulsewidth 20 ns
BCLK LO Pulsewidth 20 ns
BCLK Period 140 ns
LRCLK Setup 20 ns
LRCLK Hold (DSP Serial Port Mode Only) 5 ns
SDATA Setup 5 ns
SDATA Hold 10 ns
PD/RST LO Pulsewidth 5 ns

MCLK

= 256 × F

)* 54 ns

LRCLK

DMP

DMP

ns
ns

REV. A –3–

AD1853

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD1853

FILTR

OUTL–

OUTL+

AGND

IREF

DEEMP

ZEROR

DGND

MCLK

CLATCH

CCLK

INT2

INT4

CDATA

FCR

OUTR–

OUTR+

AVDD

FILTB

IDPM1

IDPM0

DVDD

SDATA

BCLK

L/RCLK

ZEROL

MUTE

RST

ABSOLUTE MAXIMUM RATINGS*

Min Max Units

to DGND –0.3 6 V

DV

DD

AV

to AGND –0.3 6 V

DD

Digital Inputs DGND – 0.3 DV
Analog Outputs AGND – 0.3 AV

+ 0.3 V

DD

+ 0.3 V

DD

AGND to DGND –0.3 0.3 V
Reference Voltage (AV

+ 0.3)/2

DD

Soldering +300 °C

10 sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min Typ Max Units

(Thermal Resistance

θ

JA

[Junction-to-Ambient]) 109 °C/W

(Thermal Resistance

θ

JC

[Junction-to-Case]) 39 °C/W

ORDERING GUIDE

PIN CONFIGURATION

Model Temperature Package Description Package Options

AD1853JRS 0°C to +70°C 28-Lead Shrink Small Outline RS-28
AD1853JRSRL 0°C to +70°C 28-Lead Shrink Small Outline RS-28 on 13" Reels

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

AD1853

PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source. See Table II for allowable

frequencies.
3 I CLATCH Latch input for control data. This input is rising-edge sensitive.
4 I CCLK Control clock input for control data. Control input data must be valid on the rising edge

of CCLK. CCLK may be continuous or gated.
5 I CDATA Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying

control information and channel-specific attenuation.
6 I INT4× Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or

96 kHz). Assert LO to select 8× interpolation ratio.
7 I INT2× Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).

Assert LO to select 8× interpolation ratio.
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal

input for more than 1024 LR Clock Cycles.
9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to

impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed

44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via

SPI control register.
10 I IREF Connection point for external bias resistor. Voltage held at V
11 I AGND Analog Ground.
12 O OUTL+ Left Channel Positive line level analog output.
13 O OUTL– Left Channel Negative line level analog output.
14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-

ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).
15 I FCR Filter cap return pin for cap connected to FILTB (Pin 19).
16 O OUTR– Right Channel Negative line level analog output.
17 O OUTR+ Right Channel Positive line level analog output.
18 I AVDD Analog Power Supply. Connect to analog +5 V supply.
19 O FILTB Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).
20 I IDPM1 Input serial data port mode control one. With IDPM0, defines one of four serial modes.
21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four serial modes.
22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input

for more than 1024 LR Clock Cycles.
23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
24 I RST Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is

reset on the rising edge of this signal. The serial control port registers are reset to the

default values. Connect HI for normal operation.
25 I L/RCLK Left/Right clock input for input data. Must run continuously.
26 I BCLK Bit clock input for input data.
27 I SDATA Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement

data.
28 I DVDD Digital Power Supply Connect to digital +5 V supply.

REF

.

REV. A

–5–