Analog Devices AD1852 Datasheet

Stereo, 24-Bit, 192 kHz

a

FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/18-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and
192 kHz

Multibit Sigma-Delta Modulator with “Perfect

Differential Linearity Restoration” for Reduced Idle
Tones and Noise Floor

Data-Directed Scrambling DAC—Least Sensitive to

Jitter
Differential Output for Optimum Performance
117 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)
114 dB Signal-to-Noise (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)
117 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)
114 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)
–105 dB THD+N (Mono Application Circuit)
–102 dB THD+N (Stereo)
115 dB Stopband Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,

Sample Rate, Volume, Mute, De-Emp
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,

48 kHz Sample Rates
Clock Autodivide Circuit Supports Five Master-Clock

Frequencies

Multibit Σ∆ DAC

AD1852*

Flexible Serial Data Port with Right-Justified, Left-

Justified, I

28-Lead SSOP Plastic Package

APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive

Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors

PRODUCT OVERVIEW

The AD1852 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma­delta modulator, digital interpolation filters, and analog output
drive circuitry. Other features include an on-chip stereo attenuator
and mute, programmed through an SPI-compatible serial control
port. The AD1852 is fully compatible with all known DVD
formats including 192 kHz as well as 96 kHz sample frequen­cies and 24 bits. It also is backwards compatible by supporting

50 µs/15 µs digital de-emphasis intended for “Redbook” compact

discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate.

The AD1852 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters. The
AD1852 can be configured in left-justified, I
or DSP serial port compatible modes. It can support 16, 18, 20,
and 24 bits in all modes. The AD1852 accepts serial audio data
in MSB first, twos-complement format. The AD1852 oper­ates from a single 5 V power supply. It is fabricated on a single
monolithic integrated circuit and is housed in a 28-lead SSOP

package for operation over the temperature range 0°C to 70°C.

2

S-Compatible and DSP Serial Port Modes

2

S, right-justified,

FUNCTIONAL BLOCK DIAGRAM

VOLUME

MUTE

AD1852

16-/18-/20-/24-BIT

DATA INPUT

*Patents Pending

DIGITAL

SERIAL

MODE

2

SERIAL

DATA

INTERFACE

ATTEN/

ATTEN/

RESET

MUTE

MUTE

8 3 F

S

INTERPOLATOR

8 3 F

INTERPOLATION

S

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

2

AUTO-CLOCK

DIVIDE CIRCUIT

22

ZERO
FLAG

CLOCK

IN

ANALOG
OUTPUTS

CONTROL DATA

INPUT

3

SERIAL CONTROL

INTERFACE

MULTIBIT SIGMA-

DELTA MODULATOR

MULTIBIT SIGMA-

DELTA MODULATOR

DE-EMPHASISMUTE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ANALOG

SUPPLY

DIGITAL
SUPPLY

VOLTAGE

REFERENCE

DAC

DAC

AD1852–SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AVDD, DVDD) 5.0 V

Ambient Temperature 25°C
Input Clock 24.576 MHz (512 × F

Input Signal 996.11 Hz

–0.5 dB Full Scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 Bits
Load Capacitance 100 pF

Load Impedance 47 kΩ

Input Voltage HI 2.4 V
Input Voltage LO 0.8 V

ANALOG PERFORMANCE (See Figures)

Resolution 24 Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)

No Filter (Stereo) 112 dB

No Filter (Mono—See Figure 29) 115 dB

With A-Weighted Filter (Stereo) 114 dB

With A-Weighted Filter (Mono—See Figure 29) 117 dB

Dynamic Range (20 Hz to 20 kHz, –60 dB Input)

No Filter (Stereo) 107 112 dB

No Filter (Mono—See Figure 29) 115 dB

With A-Weighted Filter (Stereo) 110 114 dB

With A-Weighted Filter (Mono—See Figure 29) 117 dB

Total Harmonic Distortion + Noise (Stereo) –94 –102 dB

Total Harmonic Distortion + Noise (Mono—See Figure 29) –105 dB

Total Harmonic Distortion + Noise (Stereo) V
Total Harmonic Distortion + Noise (Stereo) V

= –20 dB –92 dB

O

= –60 dB –52 dB

O

Analog Outputs

Differential Output Range (± Full Scale) 5.6 V p-p

Output Capacitance at Each Output Pin 2 pF

Out-of-Band Energy (0.5 × F

to 100 kHz) –90 dB

S

CMOUT 2.37 V
DC Accuracy

Gain Error –10 ±2.0 +10 %
Interchannel Gain Mismatch –0.15 ±0.015 +0.15 dB
Gain Drift 150 250 ppm/°C

DC Offset –50 mV

Interchannel Crosstalk (EIAJ Method) –120 dB

Interchannel Phase Deviation ±0.1 Degrees

Mute Attenuation –100 dB

De-Emphasis Gain Error ±0.1 dB

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.

Mode)

S

Min Typ Max Unit

0.00079 %

0.00056 %

DIGITAL I/O (0ⴗC TO 70ⴗC)

Min Typ Max Unit

Input Voltage HI (V
Input Voltage LO (V
Input Leakage (I
Input Leakage (I
High Level Output Voltage (V
Low Level Output Voltage (V

) 2.2 V

IH

) 0.8 V

IL

@ V

IH

IL

= 2.4 V) 10 µA

IH

@ V

= 0.8 V) 10 µA

IL

) IOH = 1 mA 2.0 V

OH

) IOL = 1 mA 0.4 V

OL

Input Capacitance 20 pF

Specifications subject to change without notice.

–2–

REV. 0

AD1852

TEMPERATURE RANGE

Min Typ Max Unit

Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 +150 °C

Specifications subject to change without notice.

POWER

Min Typ Max Unit

Supplies

Voltage, Analog and Digital 4.50 5 5.50 V
Analog Current 33 40 mA
Analog Current—RESET 32 46 mA
Digital Current 20 30 mA
Digital Current—RESET 27 37

Dissipation

Operation—Both Supplies 265 mW
Operation—Analog Supply 165 mW
Operation—Digital Supply 100 mW

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins –60 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –50 dB

Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB)

44.1 DC–20 24.1–328.7 110 ±0.0002
48 DC–21.8 26.23–358.28 110 ±0.0002
96 DC–39.95 56.9–327.65 115 ±0.0005

192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz)

+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)

Specifications subject to change without notice.

GROUP DELAY

Chip Mode Group Delay Calculation F

INT8x Mode 5553/(128 × F
INT4x Mode 5601/(64 × F

) 48 kHz 903.8 µs

S

) 96 kHz 911.6 µs

S

S

Group Delay Unit

INT2x Mode 5659/(32 × FS) 192 kHz 921 µs

Specifications subject to change without notice.

DIGITAL TIMING (Guaranteed Over 0ⴗC to 70ⴗC, AVDD = DVDD = +5.0 V ⴞ 10%)

Min Unit

t

DMP

t

DML

t

DMH

t

DBH

t

DBL

t

DBP

t

DLS

t

DLH

t

DDS

t

DDH

t

RSTL

*Higher MCLK frequencies are allowable when using the on-chip Master Clock Autodivide Feature.
Specifications subject to change without notice.

MCLK Period (FMCLK = 256 × FL/RCLK)* 54 ns
MCLK LO Pulsewidth (All Modes) 0.4 × t
MCLK HI Pulsewidth (All Modes) 0.4 × t

DMP

DMP

ns

ns
BCLK HI Pulsewidth 20 ns
BCLK LO Pulsewidth 20 ns
BCLK Period 60 ns
L/RCLK Setup 20 ns
L/RCLK Hold (DSP Serial Port Mode Only) 5 ns
SDATA Setup 5 ns
SDATA Hold 10 ns
RST LO Pulsewidth 15 ns

REV. 0

–3–

AD1852

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD1852

FILTR

OUTR–

OUTR+

AGND

96/48

DEEMP

ZEROR

DGND
MCLK

CLATCH

CCLK

192/48

NC

CDATA

AGND

OUTL–

OUTL+

AVDD

FILTB

IDPM1

IDPM0

DVDD
SDATA
BCLK
LRCLK

ZEROL

MUTE

RESET

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Min Max Unit

DV

to DGND –0.3 6 V

DD

to AGND –0.3 6 V

AV

DD

Digital Inputs DGND – 0.3 DV
Analog Outputs AGND – 0.3 AV

+ 0.3 V

DD

+ 0.3 V

DD

AGND to DGND –0.3 0.3 V
Reference Voltage (AV

+ 0.3)/2 V

DD

Soldering 300 °C

10 sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min Typ Max Unit

θ

(Thermal Resistance 109 °C/W

JA

[Junction-to-Ambient])

(Thermal Resistance 39 °C/W

θ

JC

[Junction-to-Case])

ORDERING GUIDE

Model Temperature Package Description Package Option

AD1852JRS 0°C to 70°C 28-Lead Shrink Small Outline Package (SSOP) RS-28
AD1852JRSRL 0°C to 70°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 on 13" Reels

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1852 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

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AD1852

PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source at either 256 F

, 768 FS, or 1024 FS.

512 F

S

3 I CLATCH Latch Input for Control Data. This input is rising-edge sensitive.
4 I CCLK Control Clock Input for Control Data. Control input data must be valid on the rising

edge of CCLK. CCLK may be continuous or gated.

5 I CDATA Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used

for specifying channel-specific attenuation and mute.

6 NC No Connect.
7 I 192/48 Selects 48 kHz (LO) or 192 kHz Sample Frequency.
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal

input for more than 1024 LR Clock Cycles.

9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used

to impose a 50 µs/15 µs response characteristic on the output audio spectrum at an

assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.

10 I 96/48 Selects 48 kHz (LO) or 96 kHz Sample Frequency.
11, 15 I AGND Analog Ground.
12 O OUTR+ Right Channel Positive Line Level Analog Output.
13 O OUTR– Right Channel Negative Line Level Analog Output.
14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-

ence with parallel 10 µF and 0.1 µF capacitors to the AGND.

16 O OUTL– Left Channel Negative Line Level Analog Output.
17 O OUTL+ Left Channel Positive Line Level Analog Output.
18 I AVDD Analog Power Supply. Connect to Analog 5 V Supply.

19 FILTB Filter Capacitor Connection. Connect 10 µF capacitor to AGND (Pin 15).

20 I IDPM1 Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
21 I IDPM0 Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
22 O ZEROL Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal

input for more than 1024 LR Clock Cycles.

23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
24 I RESET Reset. The AD1852 is reset on the rising edge of this signal. The serial control port

registers are reset to the default values. Connect HI for normal operation.

25 I L/RCLK Left/Right Clock Input for Input Data. Must run continuously.
26 I BCLK Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a

burst fashion.

27 I SDATA Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos

complement data per channel.

28 I DVDD Digital Power Supply Connect to digital 5 V supply.

, 384 FS,

S

Table I. Serial Data Input Mode

IDPM1 (Pin 20) IDPM0 (Pin 21) Serial Data Input Format

0 0 Right-Justified
01 I
1 0 Left-Justified
1 1 DSP

2

S-Compatible

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