Analog Devices AD1846JP Datasheet

Low Cost Parallel-Port 16-Bit

a

FEATURES
Low Cost, Pin- and Register-Compatible Alternative to

AD1848

Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input and Output
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters

Digital Interpolation and Decimation

Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
68-Lead PLCC Package
Operation from +5 V Supply
Byte-Wide Parallel Interface to ISA and EISA Buses
Supports One or Two DMA Channels and

Programmed I/O

PRODUCT OVERVIEW

The Parallel-Port AD1846 SoundPort® Stereo Codec integrates
key audio data conversion and control functions into a single in­tegrated circuit. The AD1846 is intended to provide a complete,
single-chip audio solution for business audio and multimedia
applications requiring operation from a single +5 V supply.

*Windows Sound System is a trademark of Microsoft Corp.

SoundPort is a registered trademark of Analog Devices, Inc.

FUNCTIONAL BLOCK DIAGRAM

SoundPort Stereo Codec

AD1846

It provides a direct, byte-wide interface to both ISA (“AT”) and
EISA computer buses for simplified implementation on a com­puter motherboard or add-in card. The AD1846 generates en­able and direction controls for IC buffers such as the 74_245.

The AD1846 SoundPort Stereo Codec supports a DMA re­quest/grant architecture for transferring data with the host com­puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control reg­ister accesses and for applications lacking DMA control. Two
input control lines support mixed direct and indirect addressing
of twenty-one internal control registers over this asynchronous
interface.

External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. DAC dynamic range exceeds
80 dB over the 20 kHz audio band. Sample rates from 5.5 kHz
to 48 kHz are supported from external crystals.

The Codec includes a stereo pair of ∑∆ analog-to-digital con­verters and a stereo pair of ∑∆ digital-to-analog converters. In­puts to the ADC can be selected from four stereo pairs of analog
signals: line, microphone (“mic”), auxiliary (“aux”) line #1, and
post-mixed DAC output. A software-controlled programmable
gain stage allows independent gain for each channel going into
the ADC. The ADCs’ output can be digitally mixed with the
DACs’ input.

(Continued on page 9)

ANALOG

ANALOG

L_LINE

R_LINE

L_MIC

R_MIC

L_AUX1

R_AUX1

L_OUT

R_OUT

L_AUX2

R_AUX2

SUPPLY

GAIN/ATTEN/

MUTE

L

∑

R

∑

GAIN/ATTEN/

MUTE

ATTEN/

MUTE

ATTEN/

MUTE

MUX

L

R

ANALOG

FILTER

ANALOG

FILTER

GAIN

GAIN

CONVERTER

CONVERTER

AD1846

∑∆ D/A

CONVERTER

∑∆ D/A

CONVERTER

REFERENCE

V

REF

∑∆ A/D

∑∆ A/D

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DIGITAL
SUPPLY

16

16

INTERPOL

INTERPOL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

CRYSTALS

OSCILLATORS

ATTENUATE

ATTENUATE

DIGITAL

MIX

∑

∑

CONTROL

POWER DOWN

µ/
A

L
A
W

µ/
A

L
A
W

REGS

DIGITAL

PLAYBACK REQ

P
A
R
A
L
L
E
L

P
O
R
T

PLAYBACK ACK

CAPTURE REQ
CAPTURE ACK

ADR1:0
DATA7:0

CS
WR

RD
BUS DRIVER

CONTROL
HOST DMA

INTERRUPT

EXTERNAL
CONTROL

AD1846–SPECIFICA TIONS

STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED

DAC Output Conditions

Post-Autocalibrated
Temperature 25 °C 0 dB Attenuation
Digital Supply (V
Analog Supply (V
Word Rate (F
Input Signal 1007 Hz Mute Off
Analog Output Passband 20 Hz to 20 kHz ADC Input Conditions
FFT Size 4096 Post-Autocalibrated
V

IH

V

IL

V

OH

V

OL

ANALOG INPUT

Full Scale Input Voltage (RMS Values Assume Sine Wave Input)

Line 1 V rms
Mic 1 V rms

MGE = 0 2.5 2.8 3.1 V p-p

MGE = 1 0.29 0.36 0.43 V p-p
Input Impedance 100 kΩ
Input Capacitance 15 pF

) 5.0 V Full Scale (0 dB)

DD

) 5.0 V 16-Bit Linear Mode

CC

) 48 kHz No Output Load

S

2.4 V 0 dB Gain

0.8 V –1.0 dB Relative to Full Scale

2.4 V Line Input

0.4 V 16-Bit Linear Mode
Inputs Driven with Low Impedance (≈ 50 Ω) Source

Min Typ Max Units

2.5 2.8 3.1 V p-p

PROGRAMMABLE GAIN AMPLIFIER—ADC

Min Typ Max Units

Step Size (0 dB to 22.5 dB) 1.0 1.5 2.0 dB

(All Steps Tested)

PGA Gain Range Span 21.0 22.5 24.0 dB

AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS

Min Typ Max Units

Step Size (+12 dB to –28.5 dB, Referenced to DAC Full Scale) 1.3 1.5 1.7 dB

(–30 dB to –34.5 dB, Referenced to DAC Full Scale) 1.0 1.5 2.0 dB
Auxiliary Gain/Attenuation Range Span 45.5 46.5 47.5 dB
Auxiliary Input Impedance* 10 kΩ

–2–

REV. A

DIGITAL DECIMATION AND INTERPOLATION FILTERS*

Min Max Units

AD1846

Passband 0 0.4 3 F

S

Hz
Passband Ripple ±0.1 dB
Transition Band 0.4 3 F
Stopband 0.6 3 F

S
S

0.6 3 F

S

Hz

∞ Hz
Stopband Rejection 74 dB
Group Delay 30/F

S

Group Delay Variation Over Passband 0.0 µs

ANALOG-TO-DIGITAL CONVERTERS

Min Typ Max Units

Resolution 16 Bits
Dynamic Range (–60 dB Input, 70 75 dB

THD+N Referenced to Full Scale, A-Weighted)

THD+N (Referenced to Full Scale) 0.02 %

–72 –70 dB
Signal-to-Intermodulation Distortion 83 dB
ADC Crosstalk*

Line Inputs (Input L, Ground R, Read R; –80 dB
Input R, Ground L, Read L)
Line to MIC (Input LINE, Ground and –80 dB
Select MIC, Read Both Channels)
Line to AUX1 –80 dB

Line to AUX2 –80 dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %
Interchannel Gain Mismatch ±0.5 dB

(Difference of Gain Errors)
ADC Offset Error 12 mV

DIGITAL-TO-ANALOG CONVERTERS

Min Typ Max Units

Resolution 16 Bits
Dynamic Range (–60 dB Input, 80 83 dB

THD+N Referenced to Full Scale, A-Weighted)
THD+N (Referenced to Full Scale) 0.02 %

–73 –70 dB
Signal-to-Intermodulation Distortion 86 dB
Gain Error (Full-Scale Span Relative to Nominal Output Voltage) ±10 %
Interchannel Gain Mismatch ±0.5 dB

(Difference of L and R Gain Errors)

DAC Crosstalk* (Input L, Zero R, Measure –80 dB

R_OUT; Input R, Zero L, Measure L_OUT)

Total Out-of-Band Energy* –50 dB

(Measured from 0.6 3 F

to 96 kHz)

S

Audible Out-of-Band Energy* –70 dB

(Measured from 0.6 3 FS to 20 kHz, Tested at 5.5 kHz)

*Guaranteed Not Tested.
Specifications subject to change without notice.

REV. A

–3–

AD1846

DAC ATTENUATOR

Min Typ Max Units

Step Size (0 dB to –60 dB) 1.3 1.5 1.7 dB

(Tested at Steps 0 dB, –19.5 dB and –60 dB)
Step Size (–60 dB to –94.5 dB)* 1.0 1.5 2.0 dB
Output Attenuation Range Span* 93.5 94.5 95.5 dB

ANALOG OUTPUT

Min Typ Max Units

Full-Scale Output Voltage 0.707 V rms

1.8 2.0 2.2 V p-p
Output Impedance* 600 Ω
External Load Impedance 10 kΩ
Output Capacitance* 15 pF
External Load Capacitance 100 pF
V

REF

V

Current Drive 100 µA

REF

V

Output Impedance 4 kΩ

REF

Mute Attenuation of 0 dB –80 dB

Fundamental* (OUT)

Mute Click 5mV

(|Muted Output Minus Unmuted
Midscale DAC Output|)

2.00 2.25 2.50 V

SYSTEM SPECIFICATIONS

Min Typ Max Units

Peak-to-Peak Frequency Response Ripple* 1.0 dB

(Line In to Line Out)
Differential Nonlinearity* ± 1 Bit
Phase Linearity Deviation* 5 Degrees

STATIC DIGITAL SPECIFICATIONS

Min Max Units

High Level Input Voltage (V

Digital Inputs 2.4 (V

XTAL1/2I 2.4 (V
Low Level Input Voltage (V
High Level Output Voltage (V
Low Level Output Voltage (V

)

IH

) –0.3 0.8 V

IL

) at IOH = –2 mA 2.4 V

OH

) at IOL = 2 mA 0.4 V

OL

) + 0.3 V

DD

) + 0.3 V

DD

Input Leakage Current –10 10 µA

(GO/NOGO Tested)
Output Leakage Current –10 10 µA

(GO/NOGO Tested)

DIGITAL MIX ATTENUATOR

Min Typ Max Units

Step Size (0 dB to –94 dB)

(Tested at Steps 0 dB, –19.5 dB) 1.0 1.5 2.0 dB
Output Attenuation Range Span* –93.5 95.5 dB

*Guaranteed, not tested.

–4–

REV. A

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)

Min Max Units

AD1846

WR/RD Strobe Width (t
WR/RD Rising to WR/RD Falling (t

Write Data Setup to

RD Falling to Valid Read Data (t
CS Setup to WR/RD Falling (t
CS Hold from WR/RD Rising (t

Adr Setup to
Adr Hold from

WR/RD Falling (t

WR/RD Rising (t
DAK Rising to WR/RD Falling (t
DAK Falling to WR/RD Rising (t
DAK Setup to WR/RD Falling (t

Data Hold from
Data Hold from
DRQ Hold from

RD Rising (t
WR Rising (t

WR/RD Falling (t
DAK Hold from WR Rising (t
DAK Hold from RD Rising (t
DBEN/DBDIR Delay from WR/RD Falling (t

POWER SUPPLY

) 130 ns

STW

WR Rising (t

RDDV

CSSU

CSHD

ADSU

ADHD

SUDK1
SUDK2

DKSU

DHD1

DHD2

DKHDa

DKHDb

) 140 ns

BWND

)10 ns

WDSU

)2040ns

)10 ns

)0 ns

)10 ns

)10 ns

)60 ns
)0 ns

)25 ns

)020ns

)15 ns

)030ns

DRHD

)10 ns
)10 ns

)0 20 ns

DBDL

Min Max Units

Power Supply Range – Analog 4.75 5.25 V
Power Supply Range – 5 V Digital 4.75 5.25 V
Power Supply Current – 5 V Operating 120 mA

(5 V Supplies)
Analog Supply Current – 5 V Operating 65 mA
Digital Supply Current – 5 V Operating 55 mA
Digital Power Supply Current – Power Down 0.5 mA
Analog Power Supply Current – Power Down 0.5 mA
Power Dissipation – 5 V Operating 600 mW

(Current

Nominal Supplies)

•

Power Dissipation – Power Down

(Current

Nominal Supplies) 5 mW

•

Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* 40 dB

(At Both Analog and Digital Supply Pins, Both ADCs

and DACs)

CLOCK SPECIFICATIONS*

Min Max Units

Input Clock Frequency 27 MHz
Recommended Clock Duty Cycle Tolerance ±10 %
Initialization Time

16.9344 MHz Crystal Selected 70 ms

24.576 MHz Crystal Selected 90 ms

*Guaranteed, not tested.
Specifications subject to change without notice.

REV. A

–5–

AD1846

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

Min Max Units

Power Supplies

Digital (V
Analog (V

DD

CC

Input Current

) –0.3 6.0 V
) –0.3 6.0 V

Model Range Description

AD1846JP 0°C to +70°C 68-Lead PLCC

Temperature Package

(Except Supply Pins) ± 10.0 mA
Analog Input Voltage (Signal Pins) –0.3 (V
Digital Input Voltage (Signal Pins) –0.3 (V

) + 0.3 V

CC

) + 0.3 V

DD

Ambient Temperature (Operating) 0 +70 °C
Storage Temperature –65 +150 °C

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1846 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

68-Lead Plastic Leaded Chip Carrier Pinout

ADR0

CDAK

CDRQ

PDAK
PDRQ

V

GNDD

XTAL1I

XTAL1O

V

GNDD

XTAL2I

XTAL2O

PWRDWN

V

GNDD

R_FILT

DD

DATA0

DATA2

V

L_MIC

31 3230292827

L_LINE

DATA1

L_FILT

(2.25V)

REF

V

NC = NO CONNECT

GNDD

ADR1

10

11
12

13
14
15

DD

16

17

18
19

DD

20

21
22
23
24

DD

25
26

R_MIC

R_LINE

DD

GNDD

DATA3

V

AD1846

TOP VIEW

CC

V

GNDA

_F (BYPASS)

REF

V

36

DATA4

67 66 6568123 63 62 6164546789

37 38 39353433

CC

V

DATA5

GNDA

DATA6

L_AUX2

DATA7

40

L_AUX1

GNDD

41 42

L_OUT

DBEN

R_OUT

DBDIR

43

R_AUX1

WR

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

R_AUX2

RD
CS
XCTL1
INT
XCTL0
NC
V

DD

GNDD
NC
NC
NC
NC
NC
NC
NC
V

DD

GNDD

–6–

REV. A

AD1846

PIN DESCRIPTION
Parallel Interface

Pin Name PLCC I/O Description

CDRQ 12 O Capture Data Request. The assertion of this signal indicates that the Codec has a captured

audio sample from the ADC ready for transfer. This signal will remain asserted until all the
bytes from the capture buffer have been transferred.

CDAK 11 I Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD

cycle occurring is a DMA read from the capture buffer.

PDRQ 14 O Playback Data Request. The assertion of this signal indicates that the Codec is ready for

more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.

PDAK 13 I Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR

cycle occurring is a DMA write to the playback buffer.

ADR1:0 9 & 10 I Codec Addresses. These address pins are asserted by the Codec interface logic during a con-

trol register/PIO access. The state of these address lines determine which register is accessed.

RD 60 I Read Command Strobe. This active LO signal defines a read cycle from the Codec. The

cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.

WR 61 I Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The

cycle may be a write to the control/PIO registers, or the cycle could be a write to the Codec’s
DMA sample registers.

CS 59 I AD1846 Chip Select. The Codec will not respond to any control/PIO cycle accesses unless

this active LO signal is LO. This signal is ignored during DMA transfers.

DATA7:0 3–6 & I/O Data Bus. These pins transfer data and control information between the Codec and the host.

65–68

DBEN 63 O Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.

For control register/PIO cycles,

DBEN = (WR OR RD) AND CS

For DMA cycles,

DBEN = (WR OR RD) AND (PDAK OR CDAK)

DBDIR 62 O Data Bus Direction. This pin controls the direction of the data bus transceiver. HI enables

writes from the host to the AD1846; LO enables reads from the AD1846 to the host bus.
This signal is normally HI.

For control register/PIO cycles,

DBDIR =

For DMA cycles,

DBDIR = RD AND (PDAK OR CDAK)

RD AND CS

REV. A

–7–

AD1846

Analog Signals

Pin Name PLCC I/O Description

L_LINE 30 I Left Line Input. Line level input for the left channel.
R_LINE 27 I Right Line Input. Line level input for the right channel.
L_MIC 29 I Left Microphone Input. Microphone input for the left channel. This signal can be ei-

ther line level or –20 dB from line level.

R_MIC 28 I Right Microphone Input. Microphone input for the right channel. This signal can be

either line level or –20 dB from line level.
L_AUX1 39 I Left Auxiliary #1 Line Input
R_AUX1 42 I Right Auxiliary #1 Line Input
L_AUX2 38 I Left Auxiliary #2 Line Input
R_AUX2 43 I Right Auxiliary #2 Line Input
L_OUT 40 O Left Line Level Output
R_OUT 41 O Right Line Level Output

Miscellaneous

Pin Name PLCC I/O Description

XTAL1I 17 I 24.576 MHz Crystal #1 Input
XTAL1O 18 O 24.576 MHz Crystal #1 Output
XTAL2I 21 I 16.9344 MHz Crystal #2 Input
XTAL2O 22 O 16.9344 MHz Crystal #2 Output
PWRDWN 23 I Power-Down Signal. Active LO control places AD1846 in its lowest power consump-

tion mode. All sections of the AD1846, including the digital interface, are shut down

and consume minimal power.
INT 57 O Host Interrupt Pin. This signal is used to notify the host that the DMA Current Count

Register has underflowed.
XCTL1:O 56 & 58 O External Control. These signals reflect the current status of register bits inside the

AD1846. They can be used for signaling or to control external logic. XLTL1 and

XLTL0 are open-drain outputs.
V

REF

_F 33 I Voltage Reference Filter. Voltage reference filter point for external bypassing only.

V

REF

L_FILT 31 I Left Channel Filter Input. This pin requires a 1.0 µF capacitor to analog ground for

R_FILT 26 I Right Channel Filter Input. This pin requires a 1.0 µF capacitor to analog ground for

NC 46–52, 55 No Connect. Do not connect.

32 O Voltage Reference. Nominal 2.25 volt reference available externally for dc-coupling and

level-shifting. V

should not be used where it will sink or source current.

REF

proper operation.

proper operation.

Power Supplies

Pin Name PLCC I/O Description

V

CC

35 & 36 I Analog Supply Voltage (+5 V)
GNDA 34 & 37 I Analog Ground
V

DD

1, 7, 15, 19, I Digital Supply Voltage (+5 V)

24, 45, 54
GNDD 2, 8, 16, 20, I Digital Ground

25, 44, 53, 64

–8–

REV. A

AD1846

(Continued from page 1)

AD1846

DATA7:0

WR

DBDIR

DBEN

PDRQ

CDRQ

PDAK

CDAK

INT

CS

RD

ADDRESS

DECODE

A1
A0

DIR
G

7
4

2
4
5

8

B

AEN

18

SA19:2
SA1
SA0
IOWC
IORC

8

DATA7:0

ISA BUS

A

DRQ<X>
DRQ<Y>
DAK<X>
DAK<Y>
IRQ<Z>

Figure 1. Interface to ISA Bus

The pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
input to the DACs and control information. The AD1846 can
accept and generate 16-bit twos-complement PCM linear digital
data, 8-bit unsigned magnitude PCM linear data, and 8-bit
µ-law or A-law companded digital data.

The ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs’ analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two stereo pairs
of auxiliary line-level inputs can also be mixed in the analog do­main with the DAC output.

AUDIO FUNCTIONAL DESCRIPTION

This section overviews the functionality of the AD1846 and is
intended as a general introduction to the capabilities of the de­vice. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.

Analog Inputs

The AD1846 SoundPort Stereo Codec accepts stereo line-level
and mic-level inputs. LINE, MIC, and AUX1 inputs and post­mixed DAC output analog stereo signals are multiplexed to the
internal programmable gain amplifier (PGA) stage.

The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left channel inputs appearing at
both channel outputs.

Analog Mixing

AUX1 and AUX2 analog stereo signals can be mixed in the ana­log domain with the DAC output. Each channel of each auxil­iary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post mixed DAC output is available on OUT externally and as
an input to the ADCs.

Even if the AD1846 is not playing back data from its DACs, the
analog mix function can still be active.

Analog-to-Digital Datapath

The AD1846 ∑∆ ADCs incorporate a fourth order modulator.
A single pole of passive filtering is all that is required for anti­aliasing the analog input because of the ADC’s high 64 times
oversampling ratio. The ADCs include linear phase digital deci­mation filters that low-pass filter the input to 0.4 3 F

. (“FS’’ is

S

the word rate or “sampling frequency”). ADC input overrange
conditions will cause bits to be set that can be read.

Each channel of the mic inputs can be amplified digitally by
+18 dB to compensate for the voltage swing differences between
line levels and typical condenser microphone levels. This +18
dB digital gain is enabled with the same control bits (LMGE
and RMGE) as the +20 dB analog gain in the AD1848.

Digital-to-Analog Datapath

The ∑∆ DACs contain a programmable attenuator and a low­pass digital interpolation filter. The anti-imaging interpolation
filter oversamples by 64 and digitally filters the higher frequency
images. The attenuator allows independent control of each
DAC channel from 0 dB to –94.5 dB in 1.5 dB steps plus full
mute. The DACs’ ∑∆ noise shapers also oversample by 64 and
convert the signal to a single bit stream. The DAC outputs are
then filtered in the analog domain by a combination of switched­capacitor and continuous-time filters. They remove the very
high frequency components of the DAC bitstream output. No
external components are required. Phase linearity at the analog
output is achieved by internally compensating for the group
delay variation of the analog output filters.

Changes in DAC output attenuation take effect only on zero
crossings, thereby eliminating “zipper” noise. Each channel has
its own independent zero-crossing detector and attenuator
change control circuitry. A timer guarantees that requested vol­ume changes will occur even in the absence of an input signal
that changes sign. The time-out period is 8 milliseconds at a
48 kHz sampling rate and 48 milliseconds at an 8 kHz sampling
rate. (Time out [ms] ≈ 384/F

[kHz].)

S

Digital Mixing

Stereo digital output from the ADCs can be mixed digitally with
the input to the DACs. Digital output from the ADCs going out
of the data port is unaffected by the digital mix. Along the digi­tal mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both chan­nels of the monitor data are attenuated by the same amount.
(Note that internally the AD1846 always works with 16-bit
PCM linear data, digital mixing included; format conversions
take place at the input and output.)

REV. A

–9–