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AD1839A b
Datasheet
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Analog Devices AD1839A b Datasheet

2 ADC, 6 DAC,

FEATURES

5 V stereo audio system with 3.3 V tolerant digital interface Supports up to 96 kHz sample rates 192 kHz sample rate available on 1 DAC Supports 16-/20-/24-bit word lengths Multibit Σ-∆ modulators with perfect differential linearity
restoration for reduced idle tones and noise floor Data-directed scrambling DACs—least sensitive to jitter Single-ended output ADCs: −95 dB THD + N, 105 dB SNR and dynamic range DACs: −92 dB THD + N, 108 dB SNR and dynamic range On-chip volume controls per channel with 1024-step linear
scale DAC and ADC software controllable clickless mutes Digital de-emphasis processing Supports 256 × f Power-down mode and soft power-down mode Flexible serial data port with right-justified, left-justified,
2
S compatible, and DSP serial modes
I TDM interface mode supports 8-in/8-out operation using a
single SHARC® SPORT 52-lead MQFP plastic package

APPLICATIONS

DVD video and audio players Home theater systems Automotive audio systems Audio/visual receivers Digital audio effects process
, 512 × fS, and 768 × fS master mode clocks
S

FUNCTIONAL BLOCK DIAGRAM

ODVDDDVDD AVDDAVDDDVDD
ASDATAABCLKALRCLK
96 kHz, 24-Bit Sigma-Delta Codec
AD1839A

GENERAL DESCRIPTION

The AD1839A is a high performance single-chip codec that features three stereo DACs and one stereo ADC. Each DAC comprises a high performance digital interpolation filter, a multibit Σ-∆ modulator featuring Analog Devices’ patented technology, and a continuous-time voltage-out analog section. Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit Σ-∆ modulators and decimation filters.
The AD1839A also contains an on-chip reference with a nominal value of 2.25 V.
The AD1839A contains a flexible serial interface that allows glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1839A can be configured in left-justified, right-justified, I ble serial modes. Control of the AD1839A is achieved by means of an SPI® compatible serial port. While the AD1839A can be operated from a single 5 V supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 V power supplies. The AD1839A is available in a 52-lead MQFP package and is specified for the −40°C to +85°C industrial temperature range.
M/S
CINCLATCHCCLK COUT
MCLK
PD/RST
2
S, or DSP compati-
AAUXDATA3
DLRCLK
DBCLK DSDATA1 DSDATA2 DSDATA3
DAUXDATA
ADCLP
ADCLN
ADCRP
ADCRN
Σ-∆
ADC
Σ-∆
ADC
SERIAL DATA
I/O PORT
DIGITAL
FILTER
DIGITAL
FILTER
AGNDDGND
Rev. B
CONTROL PORT CLOCK
VOLUME VOLUME VOLUME VOLUME VOLUME VOLUME
AD1839A
AGND AGND AGNDDGND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
www.analog.com
DAC
DAC
DAC
V
Σ-∆
Σ-∆
Σ-∆
REF
OUTL1 OUTR1 OUTL2 OUTR2 OUTL3 OUTR3
FILTD FILTR
03627-B-001
AD1839A
TABLE OF CONTENTS
Specifications..................................................................................... 3
DAC and ADC Coding.............................................................. 12
Test Conditions............................................................................. 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
Temperature Range ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 11
Functional Overview...................................................................... 12
ADCs............................................................................................ 12
DACs............................................................................................ 12
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format Universal Changes to Data Sheet Title1
AD1839A Clocking Scheme ..................................................... 12
RESET and Power-Down .......................................................... 13
Power Supply and Voltage Reference....................................... 13
Serial Control Port ..................................................................... 13
Serial Data Ports—Data Format............................................... 14
Packed Modes............................................................................. 14
Auxiliary Time Division Multiplexing (TDM) Mode........... 14
Control/Status Registers............................................................ 19
Cascade Mode............................................................................. 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
2/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Ordering Guide............................................................. 6
Deleted Clock Signals Section ....................................................... 11
Added AD1835A Clocking Scheme Section................................ 11
Added Table II and Table III and renumbered following tables 11
Changes to Auxiliary (TDM Mode) Section................................ 13
Changes to Figure 5......................................................................... 14
Changes to Figure 6......................................................................... 14
Added Figures 7a and 8a................................................................. 15
Renamed Figure 7 and Figure 8 to Figure 7b and Figure 8b ..... 15
Changes to Figure 9......................................................................... 15
Changes to Table VIII ..................................................................... 21
Updated Outline Dimensions........................................................ 24
Rev. B | Page 2 of 24
AD1839A

SPECIFICATIONS

TEST CONDITIONS

Supply Voltages 5.0 V (AVDD, DVDD) Ambient Temperature 25°C Input Clock 12.288 MHz (256 × f DAC Input Signal 1.0078125 kHz, 0 dBFS ADC Input Signal 1.0078125 kHz, −1 dBFS Input Sample Rate (f
) 48 kHz
S
Measurement Bandwidth 0 Hz to 20 kHz Word Width 24 bits Load Capacitance 100 pF Load Impedance 47 kΩ
Performance of all channels is identical (except for the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Table 1.
Parameter Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution 24 Bits Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter 103 dB A-Weighted (48 kHz and 96 kHz) 100 105 dB
Total Harmonic Distortion + Noise (THD + N)
48 kHz –95 –88.5 dB
96 kHz –95 –87.5 dB Interchannel Isolation 100 dB Interchannel Gain Mismatch 0.025 dB Analog Inputs
Differential Input Range (±Full Scale) –2.828 +2.828 V
Common-Mode Input Voltage 2.25 V
Input Impedance 4 kΩ
Input Capacitance 15 pF V
REF
DC Accuracy
Gain Error ±5 %
Gain Drift 35 ppm/°C
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution 24 Bits Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
No Filter 103 105 dB
A-Weighted Filter (48 kHz and 96 kHz) 105 108 dB Total Harmonic Distortion + Noise (48 kHz and 96 kHz) –92 –90 dB Interchannel Isolation 110 dB DC Accuracy
Gain Error ±4 %
Interchannel Gain Mismatch 0.025 dB
Gain Drift 200 ppm/°C Interchannel Phase Deviation ±0.1 Degrees Volume Control Step Size (1023 Linear Steps) 0.098 % Volume Control Range (Maximum Attenuation) 60 dB Mute Attenuation –100 dB De-emphasis Gain Error ±0.1 dB Full-Scale Output Voltage at Each Pin (Single-Ended) 1.0 (2.8) V rms (V p-p) Output Resistance at Each Pin 180 Ω Common-Mode Output Voltage 2.25 V
mode)
S
2.25 V
Rev. B | Page 3 of 24
AD1839A
Parameter Min Typ Max Unit
ADC DECIMATION FILTER, 48 kHz
Pass Band 21.77 kHz Pass-Band Ripple ±0.01 dB Stop Band 26.23 kHz Stop-Band Attenuation 120 dB Group Delay 910 µs
ADC DECIMATION FILTER, 96 kHz1
Pass Band 43.54 kHz Pass-Band Ripple ±0.01 dB Stop Band 52.46 kHz Stop-Band Attenuation 120 dB Group Delay 460 µs
DAC INTERPOLATION FILTER, 48 kHz1
Pass Band 21.77 kHz Pass-Band Ripple ±0.01 dB Stop Band 28 kHz Stop-Band Attenuation 55 dB Group Delay 340 µs
DAC INTERPOLATION FILTER, 96 kHz1
Pass Band 43.54 kHz Pass-Band Ripple ±0.01 dB Stop Band 52 kHz Stop-Band Attenuation 55 dB Group Delay 160 µs
DAC INTERPOLATION FILTER, 192 kHz1
Pass Band 81.2 kHz Pass-Band Ripple ±0.06 dB Stop Band 97 kHz Stop-Band Attenuation 80 dB Group Delay 110 µs
DIGITAL I/O
Input Voltage High 2.4 V Input Voltage Low 0.8 V Output Voltage High ODVDD – 0.4 V Output Voltage Low 0.4 V Leakage Current ±10 µA
POWER SUPPLIES
Supply Voltage (AVDD and DVDD) 4.5 5.0 5.5 V Supply Voltage (ODVDD) 3.0 DVDD V Supply Current I Supply Current I Supply Current I Supply Current I
ANALOG
, Power-Down 55 67 mA
ANALOG
DIGITAL
, Power-Down 1 4.5 mA
DIGITAL
Dissipation
Operation, Both Supplies 740 mW Operation, Analog Supply 420 mW
Operation, Digital Supply 320 mW Power-Down, Both Supplies 280 mW Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins –70 dB
20 kHz, 300 mV p-p Signal at Analog Supply Pins –75 dB
1
Guaranteed by design.
1
84 95 mA
64 74 mA
Rev. B | Page 4 of 24
AD1839A

TIMING SPECIFICATIONS

Table 2.
Parameter Min Max Unit Comments
MASTER CLOCK AND RESET
tMH MCLK High 15 ns tML MCLK Low 15 ns t
PDR
PD/RST Low
SPI PORT
t
CCLK High 40 ns
CCH
t
CCLK Low 40 ns
CCL
t
CCLK Period 80 ns
CCP
t
CDATA Setup 10 ns To CCLK rising edge
CDS
t
CDATA Hold 10 ns From CCLK rising edge
CDH
t
CLATCH Setup 10 ns To CCLK rising edge
CLS
t
CLATCH Hold 10 ns From CCLK rising edge
CLH
t
COUT Enable 15 ns From CLATCH falling edge
COE
t
COUT Delay 20 ns From CCLK falling edge
COD
t
COUT Three-State 25 ns From CLATCH rising edge
COTS
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
t
DBCLK High 60 ns
DBH
t
DBCLK Low 60 ns
DBL
fDB DBCLK Frequency 64 × fS t
DLRCLK Setup 10 ns To DBCLK rising edge
DLS
t
DLRCLK Hold 10 ns From DBCLK rising edge
DLH
t
DSDATA Setup 10 ns To DBCLK rising edge
DDS
t
DSDATA Hold 10 ns From DBCLK rising edge
DDH
Packed 128/256 Modes (Slave)
t
DBCLK High 15 ns
DBH
t
DBCLK Low 15 ns
DBL
fDB DBCLK Frequency 256 × fS t
DLRCLK Setup 10 ns To DBCLK rising edge
DLS
t
DLRCLK Hold 10 ns From DBCLK rising edge
DLH
t
DSDATA Setup 10 ns To DBCLK rising edge
DDS
t
DSDATA Hold 10 ns From DBCLK rising edge
DDH
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
t
ABCLK Delay 25 ns From MCLK rising edge
ABD
t
ALRCLK Delay 5 ns From ABCLK falling edge
ALD
t
ASDATA Delay 10 ns From ABCLK falling edge
ABDD
Normal Mode (Slave)
t
ABCLK High 60 ns
ABH
t
ABCLK Low 60 ns
ABL
fAB ABCLK Frequency 64 × fS t
ALRCLK Setup 5 ns To ABCLK rising edge
ALS
t
ALRCLK Hold 15 ns From ABCLK rising edge
ALH
t
ASDATA Delay 15 ns From ABCLK falling edge
ABDD
Packed 128/256 Mode (Master)
t
ABCLK Delay 40 ns From MCLK rising edge
PABD
t
LRCLK Delay 5 ns From ABCLK falling edge
PALD
t
ASDATA Delay 10 ns From ABCLK falling edge
PABDD
20 ns
Rev. B | Page 5 of 24
AD1839A
Parameter Min Max Unit Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
t
BCLK Delay 40 ns From MCLK rising edge
TBD
t
FSTDM Delay 5 ns From BCLK rising edge
FSD
t
ASDATA Delay 10 ns From BCLK rising edge
TABDD
t
DSDATA1 Setup 15 ns To BCLK falling edge
TDDS
t
DSDATA1 Hold 15 ns From BCLK falling edge
TDDH
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB BCLK Frequency 256 × fS
t
BCLK High 17 ns
TBCH
t
BCLK Low 17 ns
TBCL
t
FSTDM Setup 10 ns To BCLK falling edge
TFS
t
FSTDM Hold 10 ns From BCLK falling edge
TFH
t
ASDATA Delay 15 ns From BCLK rising edge
TBDD
t
DSDATA1 Setup 15 ns To BCLK falling edge
TDDS
t
DSDATA1 Hold 15 ns From BCLK falling edge
TDDH
TDM512 MODE (Master, 48 kHz)
t
BCLK Delay 40 ns From MCLK rising edge
TBD
t
FSTDM Delay 5 ns From BCLK rising edge
FSD
t
ASDATA Delay 10 ns From BCLK rising edge
TABDD
t
DSDATA1 Setup 15 ns To BCLK falling edge
TDDS
t
DSDATA1 Hold 15 ns From BCLK falling edge
TDDH
TDM512 MODE (Slave, 48 kHz)
fAB BCLK Frequency 512 × fS
t
BCLK High 17 ns
TBCH
t
BCLK Low 17 ns
TBCL
t
FSTDM Setup 10 ns To BCLK falling edge
TFS
t
FSTDM Hold 10 ns From BCLK falling edge
TFH
t
ASDATA Delay 15 ns From BCLK rising edge
TBDD
t
DSDATA1 Setup 15 ns To BCLK falling edge
TDDS
t
DSDATA1 Hold 15 From BCLK falling edge
TDDH
AUXILIARY INTERFACE (48 kHz and 96 kHz)
t
AAUXDATA Setup 10 ns To AUXBCLK rising edge
AXDS
t
AAUXDATA Hold 10 ns From AUXBCLK rising edge
AXDH
t
DAUXDATA Delay 10 ns From AUXBCLK falling edge
DXD
f
AUXBCLK Frequency 64 × fS ns
ABP
Slave Mode
t
AUXBCLK High 15 ns
AXBH
t
AUXBCLK Low 15 ns
AXBL
t
AUXLRCLK Setup 10 ns To AUXBCLK rising edge
AXLS
t
AUXLRCLK Hold 10 ns From AUXBCLK rising edge
AXLH
Master Mode
t
AUXBCLK Delay 20 ns From MCLK rising edge
AUXBCLK
t
AUXLRCLK Delay 15 ns From AUXBCLK falling edge
AUXLRCLK
t
MCLK
t
MCLK
MH
t
ML
PD/RST
t
PDR
Figure 2. MCLK and
Rev. B | Page 6 of 24
PD/RST
Timing
03627-B-002
AD1839A

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD, DVDD, ODVDD to AGND,
DGND −0.3 V to +6.0 V
AGND to DGND −0.3 V to +0.3 V
Digital I/O Voltage to DGND −0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) −40°C to +85°C

TEMPERATURE RANGE

Table 4.
Parameter Min Typ Max Unit
Specifications Guaranteed +25 °C
Functionality Guaranteed −40 +85 °C
Storage −65 +150 °C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 24
AD1839A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND51CCLK50COUT49ASDATA48ODVDD47MCLK46ALRCLK45ABCLK44AAUXDATA343DSDATA342DSDATA241DSDATA140DGND
52
25NC26
39 38 37 36 35 34 33 32 31 30 29 28 27
OUTL3
DVDD DBCLK DLRCLK DAUXDATA M/S AGND NC NC NC AGND AVDD OUTR3 NC
03627-B-003
1
DVDD
CIN
PD/RST
AGND
NC
OUTL1
NC
OUTR1
AGND AVDD
NC
OUTL2
2
3
4 5 6 7
8 9 10 11 12 13
CLATCH
NC = NO CONNECT
14NC15
16
AGND
OUTR2
AD1839A
TOP VIEW
(Not to Scale)
17
FILTD18FILTR19AVDD
20
ADCLN
21
ADCLP
22
ADCRN
23
ADCRP
24
AGND
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Input/Output Description
1, 39 DVDD Digital Power Supply. Connect to digital 5 V supply. 2 CLATCH I Latch Input for Control Data. 3 CIN I Serial Control Input. 4
PD/RST
I Power-Down/Reset. 5, 10, 16, 24, 30, 34 AGND Analog Ground. 6, 8, 12, 14, 25, 27, 31–33 NC Not connected. 7, 13, 26 OUTLx O DACx Right Channel Negative Output. 9, 15, 28 OUTRx O DACx Right Channel Positive Output. 11, 19, 29 AVDD Analog Power Supply. Connect to analog 5 V supply. 17 FILTD Filter Capacitor Connection. Recommended 10 µF/100 nF. 18 FILTR Reference Filter Capacitor Connection. Recommended 10 µF/100 nF. 20 ADCLN I ADC Left Channel Negative Input. 21 ADCLP I ADC Left Channel Positive Input. 22 ADCRN I ADC Right Channel Negative Input. 23 ADCRP I ADC Right Channel Positive Input. 35
M/S
I ADC Master/Slave Select. 36 DAUXDATA O Auxiliary DAC Output Data.
37 DLRCLK I/O DAC LR Clock. 38 DBCLK I/O DAC Bit Clock. 40, 52 DGND Digital Ground. 41–43 DSDATAx I DACx Input Data (left and right channels). 44 AAUXDATA3 I Auxiliary ADC3 Digital Input. 45 ABCLK I/O ADC Bit Clock. 46 ALRCLK I/O ADC LR Clock. 47 MCLK I Master Clock Input. 48 ODVDD Digital Output Driver Power Supply. 49 ASDATA O ADC Serial Data Output. 50 COUT O Output for Control Data. 51 CCLK I Control Clock Input for Control Data.
Rev. B | Page 8 of 24
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