AMIC A29800UV-90, A29800UV-70, A29800UV, A29800UM-90, A29800UM-70 Datasheet

A29800 Series

1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,

Preliminary	Boot Sector Flash Memory

Features

n5.0V ± 10% for read and write operations

nAccess times:

-55/70/90 (max.)

nCurrent:

-28mA read current (word mode)

-20 mA typical active read current (byte mode)

-30 mA typical program/erase current

-1 μA typical CMOS standby

nFlexible sector architecture

-16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors

-8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors

-Any combination of sectors can be erased

-Supports full chip erase

-Sector protection:

A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector

nTop or bottom boot block configurations available

nEmbedded Erase Algorithms

-Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors

-Embedded Program algorithm automatically writes and verifies bytes at specified addresses

nTypical 100,000 program/erase cycles per sector

n20-year data retention at 125°C

-Reliable operation for the life of the system

nCompatible with JEDEC-standards

-Pinout and software compatible with single-power- supply Flash memory standard

-Superior inadvertent write protection

nData Polling and toggle bits

-Provides a software method of detecting completion of program or erase operations

nErase Suspend/Erase Resume

-Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation

nHardware reset pin (RESET )

-Hardware method to reset the device to reading array data

nPackage options

-44-pin SOP or 48-pin TSOP (I)

General Description

The A29800 is a 5.0 volt only Flash memory organized as 1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The

A29800 offers the RESET function. The 1024 Kbytes of data are further divided into nineteen sectors for flexible sector erase capability. The 8 bits of data appear on I/O0 - I/O7 while the addresses are input on A1 to A18; the 16 bits of data appear on I/O0~I/O15. The A29800 is offered in 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29800 can also be programmed in standard EPROM programmers.

The A29800 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29800 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29800 also offers the ability to program in the Erase Suspend mode. The standard A29800 offers access times of 55, 70 and 90 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus

contention the device has separate chip enable ( CE ), write

enable ( WE ) and output enable ( OE ) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The A29800 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation.

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During erase, the device automatically times the erase pulse widths and verifies proper erase margin.

The host system can detect whether a program or erase

operation is complete by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29800 is fully erased when shipped from the factory.

The hardware sector protection feature disables operations for both program and erase in any combination of the

Pin Configurations

sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.

Power consumption is greatly reduced when the device is placed in the standby mode.

The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data.

n SOP

n TSOP (I)

RY/BY	1		44
A18	2		43
A17	3		42
A7	4		41
A6	5		40
A5	6		39
A4	7		38
A3	8		37
A2	9	A29800	36
A1	10		35
A0	11		34
CE	12		33
VSS	13		32
OE	14		31
I/O0	15		30
I/O8	16		29
I/O1	17		28
I/O9	18		27
I/O2	19		26
I/O10	20		25
I/O3	21		24
I/O11	22		23

RESET
WE
A8			A15					1		48		A16
			A14					2		47
A9												BYTE
			A13					3		46		VSS
A10			A12					4		45		I/O15 (A-1)
A11			A11					5		44		I/O7
			A10					6		43		I/O14
A12				A9				7		42		I/O6
A13				A8				8		41		I/O13
				NC				9		40		I/O5
A14				NC				10		39		I/O12
								11		38		I/O4
A15				WE
								12	A29800V	37		VCC
			RESET
A16				NC				13		36		I/O11
				NC				14		35		I/O3
BYTE
								15		34		I/O10
			RY/BY
VSS			A18					16		33		I/O2
I/O15 (A-1)			A17					17		32		I/O9
				A7				18		31		I/O1
I/O7				A6				19		30		I/O8
I/O14				A5				20		29		I/O0
				A4				21		28		OE
I/O6				A3				22		27		VSS
I/O13				A2				23		26		CE
				A1				24		25		A0
I/O5
I/O12
I/O4
VCC

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Block Diagram

RY/BY

VCC

I/O0 - I/O 15 (A-1)

VSS

Sector Switches

Input/Output

Erase Voltage

Buffers

RESET

Generator

WE	State
	Control
BYTE		PGM Voltage
	Command
	Register	Generator		Chip Enable
CE				Output Enable		STB	Data Latch
					Logic
OE
			STB		Y-Decoder		Y-Gating
				Latch
	VCC Detector	Timer
				Address
A0-A18					X-decoder		Cell Matrix

Pin Descriptions

Pin No.

Description

A0 - A18

Address Inputs

I/O0 - I/O14

Data Inputs/Outputs

I/O15

Data Input/Output, Word Mode

I/O15 (A-1)

A-1

LSB Address Input, Byte Mode

Chip Enable

CE

Write Enable

WE

Output Enable

OE

Hardware Reset (N/A A298001)

RESET

Selects Byte Mode or Word Mode

BYTE

RY/BY

Ready/ BUSY - Output

VSS

Ground

VCC

Power Supply

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Absolute Maximum Ratings*

Ambient Operating Temperature . . . . . -55°C to + 125°C Storage Temperature . . . . . . . . . . . . . . -65°C to + 125°C Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V

A9, OE & RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA

Notes:

1.Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC +0.5V. During voltage transitions, outputs may overshoot to VCC +2.0V for periods up to 20ns.

2.Minimum DC input voltage on A9 pins is -0.5V. During

voltage transitions, A9, OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC

input voltage on A9 and OE is +12.5V which may overshoot to 13.5V for periods up to 20ns.

3.No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to

*Comments

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . 0°C to +70°C

VCC Supply Voltages

VCC for ± 10% devices . . . . . . . . . . . . . . +4.5V to +5.5V Operating ranges define those limits between which the functionally of the device is guaranteed.

execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. A29800 Device Bus Operations

Operation

A0 - A18

I/O0 - I/O7

I/O8 - I/O15

CE

OE

WE

RESET

=VIH

=VIL

BYTE

BYTE

Read

L

L

H

H

AIN

DOUT

DOUT

High-Z

Write

L

H

L

H

AIN

DIN

DIN

High-Z

CMOS Standby

VCC ± 0.5 V

X

X

VCC ± 0.5 V

X

High-Z

High-Z

High-Z

TTL Standby

H

X

X

H

X

High-Z

High-Z

High-Z

Output Disable

L

H

H

H

X

High-Z

High-Z

High-Z

Hardware Reset

X

X

X

L

X

High-Z

High-Z

High-Z

Temporary Sector

X

X

X

VID

AIN

DIN

DIN

X

Unprotect (See Note)

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note:

See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

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Word/Byte Configuration

The BYTE pin determines whether the I/O pins I/O15-I/O0

operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O15-

I/O0 are active and controlled by CE and OE .

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O0-I/O7 are active and controlled

by CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CE and OE pins to VIL. CE is the power control and

selects the device. OE is the output control and gates

array data to the output pins. WE should remain at VIH all the time during read operation. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, lCC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing

sectors of memory), the system must drive WE and CE to

VIL, and OE to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 - I/O0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the OE input.

The device enters the CMOS standby mode when the CE

& RESET pins are both held at VCC ± 0.5V. (Note that this is a more restricted voltage range than VIH.) The device

enters the TTL standby mode when CE is held at VIH, while

RESET is held at VCC±0.5V. The device requires the standard access time (tCE) before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

ICC3 in the DC Characteristics tables represents the standby current specification.

Output Disable Mode

When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

RESET : Hardware Reset Pin

The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives

the RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for

the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

Refer to the AC Characteristics tables for RESET parameters and diagram.

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Table 2. A29800 Top Boot Block Sector Address Table

Sector

A18

A17

A16

A15

A14

A13

A12

Sector Size

Address Range (in hexadecimal)

(Kbytes/

(x16)

(x8)

Kwords)

Address Range

Address Range

SA0

0

0

0

0

X

X

X

64/32

00000h

- 07FFFh

00000h

- 0FFFFh

SA1

0

0

0

1

X

X

X

64/32

08000h

- 0FFFFh

10000h

- 1FFFFh

SA2

0

0

1

0

X

X

X

64/32

10000h

- 17FFFh

20000h

- 2FFFFh

SA3

0

0

1

1

X

X

X

64/32

18000h

- 1FFFFh

30000h

- 3FFFFh

SA4

0

1

0

0

X

X

X

64/32

20000h

- 27FFFh

40000h

- 4FFFFh

SA5

0

1

0

1

X

X

X

64/32

28000h

- 2FFFFh

50000h

- 5FFFFh

SA6

0

1

1

0

X

X

X

64/32

30000h

- 37FFFh

60000h

- 6FFFFh

SA7

0

1

1

1

X

X

X

64/32

38000h -3FFFFh

70000h -7FFFFh

SA8

1

0

0

0

X

X

X

64/32

40000h -47FFFh

80000h -8FFFFh

SA9

1

0

0

1

X

X

X

64/32

48000h -4FFFFh

90000h -9FFFFh

SA10

1

0

1

0

X

X

X

64/32

50000h

- 57FFFh

A0000h - AFFFFh

SA11

1

0

1

1

X

X

X

64/32

58000h

- 5FFFFh

B0000h - BFFFFh

SA12

1

1

0

0

X

X

X

64/32

60000h

- 67FFFh

C0000h - CFFFFh

SA13

1

1

0

1

X

X

X

64/32

68000h

- 6FFFFh

D0000h - DFFFFh

SA14

1

1

1

0

X

X

X

64/32

70000h

- 77FFFh

E0000h - EFFFFh

SA15

1

1

1

1

0

X

X

32/16

78000h - 7BFFFh

F0000h - F7FFFh

SA16

1

1

1

1

1

0

0

8/4

7C000h - 7CFFFh

F8000h - F9FFFh

SA17

1

1

1

1

1

0

1

8/4

7D000h - 7DFFFh

FA000h - FBFFFh

SA18

1

1

1

1

1

1

X

16/8

7E000h - 7FFFFh

FC000h - FFFFFh

Note:

Address range is A18: A-1 in byte mod and A18: A0 in word mode. See the “Word/Byte Configuration” section for more information.

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Table 3. A29800 Bottom Boot Block Sector Address Table

Sector

A18

A17

A16

A15

A14

A13

A12

Sector Size

Address Range

(Kbytes /

(x 16)

(x 8)

Kwords)

Address Range

Address Range

SA0

0

0

0

0

0

0

X

16/8

00000h - 01FFFh

00000h

- 03FFFh

SA1

0

0

0

0

0

1

0

8/4

02000h - 02FFFh

04000h

- 05FFFh

SA2

0

0

0

0

0

1

1

8/4

03000h - 03FFFh

06000h

- 07FFFh

SA3

0

0

0

0

1

X

X

32/16

04000h - 07FFFh

08000h

- 0FFFFh

SA4

0

0

0

1

X

X

X

64/32

08000h - 0FFFFh

10000h

- 1FFFFh

SA5

0

0

1

0

X

X

X

64/32

10000h - 17FFFh

20000h

- 2FFFFh

SA6

0

0

1

1

X

X

X

64/32

18000h - 1FFFFh

30000h

- 3FFFFh

SA7

0

1

0

0

X

X

X

64/32

20000h - 27FFFh

40000h

- 4FFFFh

SA8

0

1

0

1

X

X

X

64/32

28000h - 2FFFFh

50000h

- 5FFFFh

SA9

0

1

1

0

X

X

X

64/32

30000h - 37FFFh

60000h

- 6FFFFh

SA10

0

1

1

1

X

X

X

64/32

38000h - 3FFFFh

70000h

- 7FFFFh

SA11

1

0

0

0

X

X

X

64/32

40000h - 47FFFh

80000h

- 8FFFFh

SA12

1

0

0

1

X

X

X

64/32

48000h - 4FFFFh

90000h

- 9FFFFh

SA13

1

0

1

0

X

X

X

64/32

50000h - 57FFFh

A0000h

- AFFFFh

SA14

1

0

1

1

X

X

X

64/32

58000h - 5FFFFh

B0000h

- BFFFFh

SA15

1

1

0

0

X

X

X

64/32

60000h - 67FFFh

C0000h

- CFFFFh

SA16

1

1

0

1

X

X

X

64/32

68000h - 6FFFFh

D0000h

- DFFFFh

SA17

1

1

1

0

X

X

X

64/32

70000h - 77FFFh

E0000h

- EFFFFh

SA18

1

1

1

1

X

X

X

64/32

78000h - 7FFFFh

F0000h

- FFFFFh

Note:

Address range is A18: A-1 in byte mode and A18: A0 in word mode. See the “Word/Byte Configuration” section for more information

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect

Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O7 - I/O0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.

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Table 4. A29800 Autoselect Codes (High Voltage Method)

A18

A11

A9

A8

A6

A5

A1

A0

I/O8

I/O7

Description

Mode

to

to

to

to

to

to

CE

OE

WE

A12

A10

A7

A2

I/O15

I/O0

Manufacturer ID: AMIC

L

L

H

X

X

VID

X

L

X

L

L

X

37h

Device ID: A29800

Word

L

L

H

X

X

VID

X

L

X

L

H

B3h

0Eh

(Top Boot Block)

Byte

X

0Eh

Device ID: A29800

Word

L

L

H

X

X

VID

X

L

X

L

H

B3h

8Fh

(Bottom Boot Block)

Byte

X

8Fh

Continuation ID

L

L

H

X

X

VID

X

L

X

H

H

X

7Fh

X

01h

(protected)

Sector Protection Verification

L

L

H

SA

X

VID

X

L

X

H

L

X

00h

(unprotected)

L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.

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Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins.

The device is shipped with all sectors unprotected.

It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE , CE or WE do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE =VIL,

CE = VIH or WE = VIH. To initiate a write cycle, CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

If WE = CE = VIL and OE = VIH during power up, the device does not accept commands on the rising edge of

WE . The internal state machine is automatically reset to reading array data on the initial power-up.

Temporary Sector Unprotect

This feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the RESET pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.

Once VID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram shows the timing waveforms, for this feature.

START

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotect

Completed (Note 2)

Notes:

1.All protected sectors unprotected.

2.All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

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Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising

edge of WE or CE , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode.

The system must issue the reset command to re-enable the device for reading array data if I/O5 goes high, or while in the autoselect mode. See the "Reset Command" section, next.

See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).

If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX03h retrieves the continuation code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determine the status of the

program operation by using I/O7, I/O6, or RY/ BY . See “White Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Not that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5

to “1”, or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

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	START
	Write Program
	Command
	Sequence
	Data Poll
Embedded	from System
Program
algorithm in
progress
	Verify Data ?
	No
	Yes

Increment Address			Last Address ?

Yes

Programming

Completed

Note : See the appropriate Command Definitions table for program command sequence.

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase timeout of 50μs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50μs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50μs, the system need not monitor I/O3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands.

The system can monitor I/O3 to determine if the sector erase timer has timed out. (See the " I/O3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final

WE pulse in the command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation Status" for information on these status bits.

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