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31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
xList of Tables
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Revision History
DateRevDescription
August 2004A-1 ■Initial release of the AMD Sempron™ Processor Model 10 Data Sheet
Revision Historyxi
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
xiiRevision History
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
1Overview
The AMD Sempron™ processor model 10 with 256K of L2
cache, the new value brand for every-day computing, performs
at the top of its class. Using QuantiSpeed™ architecture, this
processor is designed to power over 60,000 home and business
applications, and it is compatible with various operating
systems including Linux and all existing Windows® operating
systems.
The AMD Sempron™ processor model 10 with 256K of L2
cache, based on proven 0.13 micron technology, integrates the
innovative design with the manufacturing expertise of AMD.
The processor delivers excellent performance and low power,
while maximizing system value and maintaining the stable and
compatible Socket A infrastructure of the AMD Sempron
processor. The 4-digit model(+) numbering system helps
identify overall software performance—the higher the number
the better the performance. Detailed technical documentation
and performance benchmarks are available at www.amd.com.
Visit the AMD Sempron processor product comparison site for
more production information.
Delivered in an OPGA package, the AMD Sempron processor
model 10 with 256K of L2 cache has full-featured capabilities
that deliver the integer, floating-point, and 3D multimedia
performance for highly demanding applications running on x86
system platforms. The AMD Sempron processor model 10 with
256K of L2 cache delivers compelling performance for over
60,000 cutting-edge software applications that include:
■high-speed, smooth stream Internet capability
■digital content creation
■digital photo editing and digital video
■image compression
■video encoding for streaming over the Internet
■soft DVD
■commercial 3D modeling
■workstation-class computer-aided design (CAD)
■commercial desktop publishing
■speech recognition
Chapter 1Overview1
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
The AMD Sempron processor model 10 with 256K of L2 cache is
binary-compatible with existing x86 software and backwards
compatible with applications optimized for MMX™, SSE, and
3DNow!™ technology. Using a data format and
single-instruction multiple-data (SIMD) operation based on the
MMX instruction model, the AMD
can produce as many as four, 32-bit, single-precision
floating-point results per clock cycle. The 3DNow! Professional
technology implemented in the AMD Sempron processor model
10 with 256K of L2 cache includes integer multimedia
instructions and software-directed data movement instructions
for optimizing such applications as digital content creation and
streaming video for the internet, as well as instructions for
digital signal processing (DSP) and communications
applications.
Sempron processor model 10
The AMD Sempron processor model 10 with 256K of L2 cache
features a seventh-generation microarchitecture with an
integrated, exclusive L2 cache, which supports the growing
processor and system bandwidth requirements of emerging
software, graphics, I/O, and memory technologies. The
high-speed execution core of the AMD Sempron processor
model 10 includes multiple x86 instruction decoders, a
dual-ported 128-Kbyte split level-one (L1) cache, an exclusive
256-Kbyte L2 cache, three independent integer pipelines, three
address calculation pipelines, and a superscalar, pipelined,
out-of-order, three-way floating-point engine. The floating-point
engine is capable of delivering top-of-the-class performance on
numerically complex applications.
The AMD Sempron processor model 10 with 256K of L2 cache
also includes QuantiSpeed™ architecture, a 333-MHz,
2.7-Gigabyte per second AMD Athlon™ system bus, and
3DNow! Professional technology. The AMD Athlon system bus
combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling to provide an extremely
powerful, scalable bus for an x86 processor.
2OverviewChapter 1
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
1.1QuantiSpeed™ Architecture Summary
The following design features summarize the QuantiSpeed
architecture of the AMD Sempron processor model 10 with
256K of L2 cache:
■
A nine-issue, superpipelined, superscalar x86 processor
microarchitecture designed for increased instructions per
cycle (IPC) and high clock frequencies
■
Pipelined floating-point unit that executes all x87
(floating-point), MMX, SSE and 3DNow! instructions
■
Hardware data pre-fetch that increases and optimizes
performance on high-end software applications utilizing
high-bandwidth system capabilitie
structures for both enhanced data and instruction address
translation. The AMD Sempron processor model 10 with
QuantiSpeed architecture incorporates three TLB
optimizations: the L1 DTLB increases from 32 to 40 entries,
the L2 ITLB and L2 DTLB both use exclusive architecture,
and the TLB entries can be speculatively loaded.
s
The AMD Sempron processor model 10 delivers excellent
system performance in a cost-effective, industry-standard form
factor. The AMD Sempron processor model 10 is compatible
with motherboards based on Socket A.
Figure 1 on page 4 shows a typical AMD Sempron processor
model 10 with 256K L2 cache system block diagram.
Chapter 1Overview3
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Thermal Monitor
AMD Sempron™ Proces-
sor Model 10
AMD Athlon™ System Bus
AGP Bus
AGP
System Controller
(Northbridge)
Peripheral Bus Con-
troller
(Southbridge)
Dual EIDE
USB
Memory Bus
PCI Bus
LPC Bus
LAN
Modem / Audio
SDRAM or DDR
SCSI
BIOS
Figure 1. Typical AMD Sempron™ Processor Model 10 System Block Diagram
4OverviewChapter 1
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
2Interface Signals
This section describes the interface signals utilized by the
AMD Sempron™ processor model 10.
2.1Overview
The AMD Athlon system bus architecture is designed to deliver
excellent data movement bandwidth for next-generation x86
platforms as well as the high-performance required by
enterprise-class application software. The system bus
architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 64-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Athlon™ System Bus Signals”
on page 6,Chapter 10, “Pin Descriptions” on page 49, and the
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
2.2Signaling Technology
The AMD Athlon system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (V
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
“Pin Descriptions” on page 49.
REF
). The reference signal is used by the receivers to
Chapter 2Interface Signals5
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
2.3Push-Pull (PP) Drivers
The AMD Sempron processor model 10 supports push-pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
See “ZN and ZP Pins” on page 75 for more information.
2.4AMD Athlon™ System Bus Signals
The AMD Athlon system bus is a clock-forwarded, point-topoint interface with the following three point-to-point channels:
For more information, see Chapter 6, “333 FSB
AMD Sempron™ Processor Model 10 with 256K L2 Cache
Specifications” on page 21, Chapter 7, “Electrical Data” on
page 25, and the AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902.
6Interface SignalsChapter 2
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
3Logic Symbol Diagram
Figure 2 is the logic symbol diagram of the processor. This
diagram shows the logical grouping of the input and output
signals.
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
8Logic Symbol DiagramChapter 3
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
4Power Management
This chapter describes the power management control system
of the AMD Sempron™ Processor Model 10. The power
management features of the processor are compliant with the
ACPI 1.0b and ACPI 2.0 specifications.
4.1Power Management States
The AMD Sempron processor model 10 supports low-power
Halt and Stop Grant states. These states are used by advanced
configuration and power interface (ACPI) enabled operating
systems for processor power management.
Figure 3 shows the power management states of the processor.
The figure includes the ACPI “Cx” naming convention for these
states.
C1
Halt
Incoming Probe
Probe
State
SMI#, INTR, NMI, INIT#, RESET#
P
r
o
b
e
S
e
r
v
i
c
e
d
1
Execute HLT
S
T
P
C
L
S
T
P
C
L
K
#
Incoming Probe
Probe Serviced
C0
4
Working
(Read PLVL2 register
or throttling)
K
#
d
e
a
s
s
e
r
t
a
e
3
s
d
s
e
r
t
e
2
d
Stop Grant
Cache Snoopable
STPCLK# deasserted
STPCLK# asserted
C2
Note:The AMD AthlonTMSystem Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
S
T
P
C
L
K
S
T
P
C
L
K
#
a
s
#
d
e
a
s
s
e
r
t
e
d
s
e
r
t
e
d
Stop Grant
Cache Not Snoopable
Sleep
Legend
Hardware transitions
Software transitions
S1
Figure 3. AMD Sempron™ Processor Model 10 Power Management States
Chapter 4Power Management9
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
The following sections provide an overview of the power
management states. For more details, refer to the
AMD
order# 21902.
Note: In all power management states that the processor is
Working StateThe Working state is the state in which the processor is
executing instructions.
Halt StateWhen the processor executes the HLT instruction, the processor
enters the Halt state and issues a Halt special cycle to the
AMD Athlon system bus. The processor only enters the low
power state dictated by the CLK_Ctl MSR if the system
controller (Northbridge) disconnects the AMD Athlon system
bus in response to the Halt special cycle.
Athlon™ and AMD Duron™ System Bus Specification,
powered, the system must not stop the system clock
(SYSCLK/SYSCLK#) to the processor.
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
system bus connect, if it is disconnected, then issue a Stop
Grant special cycle. When STPCLK# is deasserted, the
processor will exit the Stop Grant state and re-enter the Halt
state. The processor will issue a Halt special cycle when
re-entering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR
or NMI pins, or via a local APIC interrupt message. When the
Halt state is exited, the processor will initiate an AMD Athlon
system bus connect if it is disconnected.
Stop Grant StatesThe processor enters the Stop Grant state upon recognition of
assertion of STPCLK# input. After entering the Stop Grant
state, the processor issues a Stop Grant special bus cycle on the
AMD Athlon system bus. The processor is not in a low-power
state at this time, because the AMD Athlon system bus is still
connected. After the Northbridge disconnects the AMD Athlon
system bus in response to the Stop Grant special bus cycle, the
processor enters a low-power state dictated by the CLK_Ctl
MSR. If the Northbridge needs to probe the processor during
the Stop Grant state while the system bus is disconnected, it
10Power ManagementChapter 4
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
must first connect the system bus. Connecting the system bus
places the processor into the higher power probe state. After
the Northbridge has completed all probes of the processor, the
Northbridge must disconnect the AMD Athlon system bus
again so that the processor can return to the low-power state.
During the Stop Grant states, the processor latches INIT#,
INTR, NMI, SMI#, or a local APIC interrupt message, if they are
asserted.
The Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. When STPCLK# is
deasserted, the processor initiates a connect of the
AMD Athlon system bus if it is disconnected. After the
processor enters the Working state, any pending interrupts are
recognized and serviced and the processor resumes execution
at the instruction boundary where STPCLK# was initially
recognized. If RESET# is sampled asserted during the Stop
Grant state, the processor exits the Stop Grant state and the
reset process begins.
There are two mechanisms for asserting STPCLK#—hardware
and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This is accomplished by asserting the THERM#
input to the Southbridge. Throttling asserts STPCLK# for a
percentage of a predefined throttling period: STPCLK# is
repetitively asserted and deasserted until THERM# is
deasserted.
Software can force the processor into the Stop Grant state by
accessing ACPI-defined registers typically located in the
Southbridge.
The operating system places the processor into the C2 Stop
Grant state by reading the P_LVL2 register in the Southbridge.
If an ACPI Thermal Zone is defined for the processor, the
operating system can initiate throttling with STPCLK# using
the ACPI defined P_CNT register in the Southbridge. The
Northbridge connects the AMD Athlon system bus, and the
processor enters the Probe state to service cache snoops during
Stop Grant for C2 or throttling.
Chapter 4Power Management11
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
In C2, probes are allowed, as shown in Figure 3 on page 9
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 Sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe StateThe Probe state is entered when the Northbridge connects the
Athlon system bus to probe the processor (for example, to
AMD
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Athlon system bus again.
4.2Connect and Disconnect Protocol
Significant power savings of the processor only occur if the
processor is disconnected from the system bus by the
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
Connect ProtocolIn addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an
12Power ManagementChapter 4
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
interrupt for Halt or STPCLK# deassertion. Reconnect is
initiated by the Northbridge to probe the processor.
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
Northbridge asserts CLKFWDRST in anticipation of
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this
are possible.
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge
immediately.
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Grant special cycle to the Northbridge but before the
disconnect actually occurs. In this case, the processor sends the
Connect special cycle to the Northbridge, rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
For more information, see the AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.
Chapter 4Power Management13
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Figure 4 shows STPCLK# assertion resulting in the processor in
the Stop Grant state and the AMD Athlon system bus
disconnected.
STPCLK#
AMD Athlon™
System Bus
CONNECT
PROCRDY
CLKFWDRST
Stop Grant
PCI Bus
Stop Grant
Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Athlon system bus disconnect
sequence is as follows:
1. The peripheral controller (Southbridge) asserts STPCLK#
to place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters
the Stop Grant state and then issues a Stop Grant special
cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending,
initiating a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the
processor enters a low-power state. The Northbridge passes
the Stop Grant special cycle along to the Southbridge.
14Power ManagementChapter 4
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Figure 5 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to
the AMD Athlon system bus, and puts the processor into the
Working state.
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from
the Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the
processor of a wake event.
2. When the processor recognizes STPCLK# deassertion, it
exits the low-power state and asserts PROCRDY, notifying
the Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks between the processor and the
Northbridge.
5. The processor issues a Connect special cycle on the system
bus and resumes operating system and application code
execution.
Chapter 4Power Management15
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Connect State
Diagram
.
Figure 6 below and Figure 7 on page 17 show the Northbridge
and processor connect state diagrams, respectively.
Condition
1 A disconnect is requested and probes are still pending.
2 A disconnect is requested and no probes are pending.
3 A Connect special cycle from the processor.
4 No probes are pending.
5 PROCRDY is deasserted.
6 A probe needs service.
7 PROCRDY is asserted.
Three SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
8
Northbridge must not issue any non-NOP SysDC
commands for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
Deassert CONNECT eight SYSCLK periods
A
after last SysDC sent.
BAssert CLKFWDRST.
C Assert CONNECT.
D Deassert CLKFWDRST.
Action
Figure 6. Northbridge Connect State Diagram
16Power ManagementChapter 4
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Connect
6/B
1
2/B
Connect
Pending 2
Disconnect
Pending
5
Connect
Pending 1
3/A
Disconnect
Condition
CONNECT is deasserted by the Northbridge (for a
1
previously sent Halt or Stop Grant special cycle).
Processor receives a wake-up event and must cancel
2
the disconnect request.
3 Deassert PROCRDY and slow down internal clocks.
Processor wake-up event or CONNECT asserted by
4
Northbridge.
5 CLKFWDRST is deasserted by the Northbridge.
Forward clocks start three SYSCLK periods after
6
CLKFWDRST is deasserted.
4/C
Action
A CLKFWDRST is asserted by the Northbridge.
B Issue a Connect special cycle.*
Return internal clocks to full speed and assert
C
PROCRDY.
Note:
*
The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Athlon™ system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Figure 7. Processor Connect State Diagram
Chapter 4Power Management17
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
4.3Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
18Power ManagementChapter 4
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
5CPUID Support
AMD Sempron™ processor model 10 version and feature set
recognition can be performed through the use of the CPUID
instruction, that provides complete information about the
processor—vendor, type, name, etc., and its capabilities.
Software can make use of this information to accurately tune
the system for maximum performance and benefit to users.
For information on the use of the CPUID instruction see the
following document:
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
20CPUID SupportChapter 5
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
6333 FSB AMD Sempron™ Processor Model 10 with
256K L2 Cache Specifications
This chapter describes the electrical specifications that are
unique to the advanced 333 front-side bus (FSB)
AMD Sempron™ Processor Model 10 with 256K L2 cache.
6.1Electrical and Thermal Specifications for the AMD Sempron™
Processor Model 10 with 256K L2 Cache
Table 1 shows the electrical and thermal specifications in the
C0 working state and the S1 Stop Grant state for this processor.
Table 1.Electrical and Thermal Specifications for the AMD Sempron™ Processor Model 10 with 256K
L2 Cache
V
Frequency in MHz
(Model Number)
1500 (2200+)
2000 (2800+)
Notes:
1. See Figure 3, "AMD Sempron™ Processor Model 10 Power Management States" on page 9.
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of
2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD
AMD
Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.
4. The Stop Grant current consumption is characterized at 50°C and not tested.
CC_CORE
(Core
Voltage)
1.60 V38.75 A30.9 A8.10 A4.94 A62.0 W49.4 W90°C
Working State C0
Maximum TypicalMaximumTypicalMaximumTypical
ICC (Processor Current)
Stop Grant S1
1, 2, 3, 4
Thermal Power
5
Maximum Die
Temperature
Athlon™ and
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or
instruction sequences under normal system operation at nominal V
the processor to prevent the processor from exceeding its maximum die temperature.
CC_CORE
. Thermal solutions must monitor the temperature of
Chapter 6333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications21
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
6.2333 FSB AMD Sempron™ Processor Model 10 SYSCLK and
SYSCLK# AC Characteristics
Table 2 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of this processor.
Table 2.333 FSB SYSCLK and SYSCLK# AC Characteristics
1. The AMD Athlon™ system bus operates at twice this clock frequency.
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL
to track the jitter. The –20dB attenuation point, as measured into a 20
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD
AMD
Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
Athlon system bus period violate the minimum specification above.
- or 30-pF load must be less than 500 kHz.
Figure 8 shows a sample waveform of the SYSCLK signal.
t
2
V
CROSS
t
5
V
Threshold-AC
t
3
t
4
t
1
Figure 8. SYSCLK Waveform
22333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache SpecificationsChapter 6
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
6.3333 FSB AMD Athlon™ System Bus AC Characteristics
The AC characteristics of the AMD Athlon system bus of this
processor are shown in Tab le 3. The parameters are grouped
based on the source or destination of the signals involved.
Table 3.333 FSB AMD Athlon™ System Bus AC Characteristics
GroupSymbolParameterMinMaxUnitsNotes
T
All Signals
Forward
Clocks
Sync
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
RISE
T
FALL
T
SKEW-DIFFEDGE
T
SU
T
HD
C
IN
C
OUT
T
VAL
T
SU
T
HD
Output Rise Slew Rate13V/ns1
Output Fall Slew Rate13V/ns1
Output skew with respect to a
different clock edge
–770ps2
Input Data Setup Time300ps3
Input Data Hold Time300ps3
Capacitance on input clocks425pF
Capacitance on output clocks412pF
RSTCLK to Output Valid8002000ps4, 5
Setup to RSTCLK500ps4, 6
Hold from RSTCLK500ps4, 6
2. T
SKEW-DIFFEDGE
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.
5. T
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
VAL
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
Chapter 6333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications23
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
6.4333 FSB AMD Athlon™ System Bus DC Characteristics
Table 4 shows the DC characteristics of the AMD Athlon
system bus for this processor.
Table 4.333 FSB AMD Athlon™ System Bus DC Characteristics
SymbolParameterConditionMinMaxUnits Notes
(0.5 x V
V
REF
I
VREF_LEAK_PVREF
I
VREF_LEAK_NVREF
V
IH
V
IL
I
LEAK_P
I
LEAK_N
C
IN
R
ON
R
setP
R
setN
Notes:
1. V
DC Input Reference Voltage
Tristate Leakage PullupVIN = V
Tristate Leakage PulldownVIN = V
REF
REF
Nominal
Nominal
Input High Voltage
Input Low Voltage–500
Tristate Leakage Pullup
Tristate Leakage Pulldown
VIN = VSS
(Ground)
VIN = V
Nominal
CC_CORE
Input Pin Capacitance47pF
Output Resistance
Impedance Set Point, P Channel4070Ω2
Impedance Set Point, N Channel4070Ω2
is nominally set to 50% of V
REF
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the ± 50 mV specification listed
above.
with actual values that are specific to motherboard design implementation. V
CC_CORE
CC_CORE
–50
–100µA
V
+200V
REF
–1mA
0.90 x R
setN,P
)
(0.5 x V
CC_CORE
+50
100µA
CC_CORE
V
–200
REF
1mA
1.1 x R
+500
setN,P
)
mV1
mV
mV
Ω2
must be
REF
2. Measured at V
CC_CORE
/ 2.
24333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache SpecificationsChapter 6
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7Electrical Data
This chapter describes the electrical characteristics that apply
to all desktop AMD Sempron™ processors model 10 with 256K
L2 cache.
7.1Conventions
The conventions used in this chapter are as follows:
■Current specified as being sourced by the processor is
negative.
■Current specified as being sunk by the processor is positive.
7.2Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 5 defines each group and the signals contained in each
group.
Table 5. Interface Signal Groupings
Signal GroupSignalsNotes
See “Voltage Identification (VID[4:0])” on page 26,
Power
FrequencyFID[3:0]
System Clocks
AMD Athlon™
System Bus
VID[4:0], VCCA, V
COREFB#
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN#
and RSTCLK/RSTCLK#), PLLBYPASSCLK#,
PLLBYPASSCLK
“VID[4:0] Pins” on page 74, “VCCA AC and DC
Characteristics” on page 27, “V
on page 28, “VCCA Pin” on page 73, and “COREFB and
COREFB# Pins” on page 69.
See “Frequency Identification (FID[3:0])” on page 27 and
“FID[3:0] Pins” on page 70.
See Table 11, “SYSCLK and SYSCLK# DC Characteristics,”
on page 31 , Tab le 3, “333 FSB AMD Athlon™ System Bus
AC Characteristics,” on page 23, “SYSCLK and SYSCLK#”
on page 73, and “PLL Bypass and Test Pins” on page 72.
See “333 FSB AMD Sempron™ Processor Model 10 with
256K L2 Cache Specifications” on page 21, Tab le 3, “333
FSB AMD Athlon™ System Bus AC Characteristics,” on
page 23, Tab le 4, “333 FSB AMD Athlon™ System Bus DC
Characteristics,” on page 24, and “CLKFWDRST Pin” on
page 68.
CC_CORE
Characteristics”
Chapter 7Electrical Data25
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 5. Interface Signal Groupings (continued)
Signal GroupSignalsNotes
See “General AC and DC Characteristics” on page 32,
“INTR Pin” on page 72, “NMI Pin” on page 72, “SMI#
Southbridge
JTAGTMS, TCK, TRST#, TDI, TDOSee “General AC and DC Characteristics” on page 32.
Pin” on page 73, “INIT# Pin” on page 71, “A20M# Pin”
on page 68, “FERR Pin” on page 69,“IGNNE# Pin” on
page 71, “STPCLK# Pin” on page 73, and “FLUSH# Pin”
on page 71.
PLLBYPASS#, PLLTEST#, PLLMON1,
Test
Miscellaneous DBREQ#, DBRDY, PWROK
APICPICD[1:0]#, PICCLK
ThermalTHERMDA, THERMDC
PLLMON2, SCANCLK1, SCANCLK2,
SCANSHIFTEN, SCANINTEVAL, ANALOG
See “General AC and DC Characteristics” on page 32,
“PLL Bypass and Test Pins” on page 72, “Scan Pins” on
page 73, “Analog Pin” on page 68.
See “General AC and DC Characteristics” on page 32,
“DBRDY and DBREQ# Pins” on page 69, “PWROK Pin”
on page 73.
See “APIC Pins AC and DC Characteristics” on page 37,
and “APIC Pins, PICCLK, PICD[1:0]#” on page 68.
See Table 13, “Thermal Diode Electrical Characteristics,”
on page 35, and “THERMDA and THERMDC Pins” on
page 73.
7.3Voltage Identification (VID[4:0])
Table 6 shows the VID[4:0] DC Characteristics. For more
information on VID[4:0] DC Characteristics, see “VID[4:0]
Pins” on page 74.
Table 6.VID[4:0] DC Characteristics
ParameterDescriptionMinMax
I
OL
V
OH
Note:
* The VID pins are either open circuit or pulled to ground. It is recommended that these pins
Output Current Low6 mA
Output High Voltage–5.25 V *
are not pulled above 5.25 V, which is 5.0 V + 5%.
26Electrical DataChapter 7
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.4Frequency Identification (FID[3:0])
Table 7 shows the FID[3:0] DC characteristics. For more
information, see “FID[3:0] Pins” on page 70.
Table 7.FID[3:0] DC Characteristics
ParameterDescriptionMinMax
I
OL
V
OH
Note:
1. The FID pins must not be pulled above 2.625 V, which is equal to 2.5 V plus a maximum of five percent.
2. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
Output Current Low6 mA
Output High Voltage–
| V
OH
– V
2.625 V
CC_CORE
1
| ≤ 1.60 V 2
7.5VCCA AC and DC Characteristics
Table 8 shows the AC and DC characteristics for VCCA. For
more information, see “VCCA Pin” on page 73.
Table 8.VCCA AC and DC Characteristics
SymbolParameterMinNominalMaxUnitsNotes
V
VCCA
I
VCCA
Notes:
1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.
2. For more information, refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
3. Measured at 2.5 V.
VCCA Pin Voltage2.252.5
| V
VCCA
VCCA Pin Current050mA/GHz3
2.75V1
– V
CC_CORE
| ≤ 1.60 V
–2
7.6Decoupling
See the AMD Athlon™ Processor-Based Motherboard Design
Guide, order# 24363, or contact your local AMD office for
information about the decoupling required on the motherboard
for use with the AMD Sempron processor model 10.
Chapter 7Electrical Data27
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
7.7V
CC_CORE
Characteristics
Table 9 shows the AC and DC characteristics for V
Figure 9 on page 29 for a graphical representation of the
V
CC_CORE
Table 9.V
CC_CORE
AC and DC Characteristics
SymbolParameterLimit in Working StateUnits
V
CC_CORE_DC_MAX
V
CC_CORE_DC_MIN
V
CC_CORE_AC_MAX
V
CC_CORE_AC_MIN
t
MAX_AC
t
MIN_AC
Note:
*
All voltage measurements are taken differentially at the COREFB/COREFB# pins.
Maximum static voltage above V
Maximum static voltage below V
Maximum excursion above V
Maximum excursion below V
Maximum excursion time for AC transients10µs
Negative excursion time for AC transients5µs
waveform.
CC_CORE_NOM
CC_CORE_NOM
CC_CORE_NOM
CC_CORE_NOM
*
*
*
*
50mV
–50mV
150mV
–100mV
CC_CORE
. See
28Electrical DataChapter 7
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
V
CC_CORE_AC_MAX
V
CC_CORE_DC_MAX
V
CC_CORE_NOM
V
CC_CORE_DC_MIN
Figure 9 shows the processor core voltage (V
waveform response to perturbation. The t
transient excursion time) and t
MAX_AC
(positive AC transient
MIN_AC
(negative AC
CC_CORE
)
excursion time) represent the maximum allowable time below
or above the DC tolerance thresholds.
t
max_AC
V
CC_CORE_AC_MIN
Figure 9. V
I
CORE_MAX
I
CORE_MIN
CC_CORE
Voltage Waveform
t
min_AC
dI /dt
Chapter 7Electrical Data29
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
7.8Absolute Ratings
The AMD Sempron processor model 10 should not be subjected
to conditions exceeding the absolute ratings, as such conditions
can adversely affect long-term reliability or result in functional
damage.
Table 10 lists the maximum absolute ratings of operation for the
AMD Sempron processor model 10.
Table 10. Absolute Ratings
ParameterDescriptionMinMax
V
CC_CORE
VCCAProcessor PLL voltage supply–0.5 VVCCA Max + 0.5 V
Processor core voltage supply–0.5 V
V
CC_CORE
Max + 0.5 V
V
PIN
T
STORAGE
Voltage on any signal pin–0.5 V
Storage temperature of processor–40ºC100ºC
V
CC_CORE
Max + 0.5 V
30Electrical DataChapter 7
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.9SYSCLK and SYSCLK# DC Characteristics
Table 11 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together. For more
information about SYSCLK and SYSCLK#, see “SYSCLK and
SYSCLK#” on page 73 and Tab le 19, “Pin Name
Abbreviations,” on page 52.
Table 11. SYSCLK and SYSCLK# DC Characteristics
SymbolDescriptionMinMaxUnits
V
Threshold-DC
V
Threshold-AC
I
LEAK_P
I
LEAK_N
V
CROSS
C
PIN
Note:
* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
Crossing before transition is detected (DC)400mV
Crossing before transition is detected (AC)450mV
Leakage current through P-channel pullup to V
CC_CORE
–1mA
Leakage current through N-channel pulldown to VSS (Ground)1mA
V
Differential signal crossovermV
CC_CORE
------------------------1 0 0±
2
Capacitance *425 *pF
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
Figure 10 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
V
CROSS
V
Threshold-DC
= 400 mVV
Threshold-AC
= 450 mV
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals
Chapter 7Electrical Data31
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
7.10General AC and DC Characteristics
Table 12 shows the AMD Sempron processor model 10 AC and
DC characteristics of the Southbridge, JTAG, test, and
miscellaneous pins.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
Sync Input Setup Time2.0ns4, 5
Sync Input Hold Time0.0ps4, 5
Output Delay with respect to RSTCLK0.06.1ns5
Input Time to Acquire20.0ns7, 8
Input Time to Reacquire40.0ns9–13
Signal Rise Time1.03.0V/ns6
Signal Fall Time1. 03.0V/ns6
Pin Capacitance412pF
Time to data valid100ns14
CC_CORE
and IOH are measured at VOL maximum and VOH minimum, respectively.
OL
configurations.
information.
. Scale parameters between V
CC_CORE.
minimum and V
CC_CORE.
maximum.
Chapter 7Electrical Data33
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
7.11Open Drain Test Circuit
Figure 11 is a test circuit that may be used on automated test
equipment (ATE) to test for validity on open-drain pins.
Refer to Table 12, “General AC and DC Characteristics,” on
page 32 for timing requirements.
V
Termination
Open-Drain Pin
IOL = Output Current
Notes:
1. V
Termination
V
Termination
= 1.2 V for VID and FID pins
= 1.0 V for APIC pins
2. IOL = –6 mA for VID and FID pins
IOL = –9 mA for APIC pins
Figure 11. General ATE Open-Drain Test Circuit
1
50 Ω ±3%
2
34Electrical DataChapter 7
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.12Thermal Diode Characteristics
The AMD Sempron processor model 10 provides a diode that
can be used in conjunction with an external temperature sensor
to determine the die temperature of the processor. The diode
anode (THERMDA) and cathode (THERMDC) are available as
pins on the processor, as described in
THERMDC Pins” on page 73.
For information about thermal design for the AMD Sempron
processor model 10, including layout and airflow
considerations, see the AMD Processor Thermal, Mechanical, and Chassis Cooling Design Guide, order# 23794, and the cooling
guidelines on http://www.amd.com.
“THERMDA and
Thermal Diode
Electrical
Characteristics
Table 13 shows the AMD Sempron processor model 10
characteristics of the on-die thermal diode. For information
about calculations for the ideal diode equation and
temperature offset correction, see Appendix A, "Thermal
Diode Calculations," on page 77.
1. The sourcing current should always be used in forward bias only.
2. Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA. AMD
recommends using a minimum of two sourcing currents to accurately measure the
temperature of the thermal diode.
3. Not 100% tested. Specified by design and limited characterization.
4. The lumped ideality factor adds the effect of the series resistance term to the actual ideality
factor. The series resistance term indicates the resistance from the pins of the processor to the
on-die thermal diode. The value of the lumped ideality factor depends on the sourcing current
pair used.
Parameter
Description
Sourcing current5300µA1
Lumped ideality
factor
Actual ideality factor1.002613, 4
Series Resistance0.93Ω3, 4
MinNomMaxUnitsNotes
1.000001.003741.009002, 3, 4
Chapter 7Electrical Data35
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Thermal Protection
Characterization
The following section describes parameters relating to thermal
protection. The implementation of thermal control circuitry to
control processor temperature is left to the manufacturer to
determine how to implement.
Thermal limits in motherboard design are necessary to protect
the processor from thermal damage. T
SHUTDOWN
is the
temperature for thermal protection circuitry to initiate
shutdown of the processor. T
SD_DELAY
is the maximum time
allowed from the detection of the over-temperature condition to
processor shutdown to prevent thermal damage to the
processor.
Systems that do not implement thermal protection circuitry or
that do not react within the time specified by T
SD_DELAY
can
cause thermal damage to the processor during the unlikely
events of fan failure or powering up the processor without a
heat-sink. The processor relies on thermal circuitry on the
motherboard to turn off the regulated core voltage to the
processor in response to a thermal shutdown event.
Thermal protection circuitry reference designs and thermal
solution guidelines are found in the following documents:
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
See http://www.amd.com for more information about thermal
solutions.
36Electrical DataChapter 7
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 14 shows the T
SHUTDOWN
and T
SD_DELAY
specifications
for circuitry in motherboard design necessary for thermal
protection of the processor.
Table 14. Guidelines for Platform Thermal Protection of the Processor
SymbolParameter DescriptionMaxUnitsNotes
TSHUTDOWN
T
SD_DELAY
Notes:
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.
3. The AMD Sempron™ processor model 10 provides a thermal diode for measuring die temperature of the processor. The
processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a
thermal shutdown event. Refer to AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for thermal
protection circuitry designs.
Thermal diode shutdown temperature for processor protection125°C1, 2, 3
Maximum allowed time from T
SHUTDOWN
detection to processor shutdown
500ms1, 3
7.13APIC Pins AC and DC Characteristics
Table 15 shows the AMD Sempron processor model 10 AC and
DC characteristics of the APIC pins.
Table 15. APIC Pin AC and DC Characteristics
Symbol Parameter DescriptionConditionMinMaxUnitsNotes
V
IH
V
IL
V
OH
V
OL
I
LEAK_P
I
LEAK_N
I
OL
Notes:
Input High Voltage
V
CC_CORE
< V
CC_CORE_MAX
Input Low Voltage–300700mV1
Output High Voltage
V
CC_CORE
< V
CC_CORE_MAX
Output Low Voltage–300400mV
Tristate Leakage Pullup
Tristate Leakage
Pulldown
Output Low Current
1. Characterized across DC supply voltage range.
2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent.
3. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
4. Edge rates indicate the range for characterizing the inputs.
VIN = VSS (Ground)
VIN = 2.5 V
VOL Max
1.72.625V1, 2
| VIH – V
CC_CORE
| ≤ 1.60 V
V3
2.625V2
| VOH – V
CC_CORE
| ≤ 1.60 V
V3
–1mA
1mA
9mA
Chapter 7Electrical Data37
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 15. APIC Pin AC and DC Characteristics (continued)
Symbol Parameter DescriptionConditionMinMaxUnitsNotes
T
RISE
T
FALL
T
SU
T
HD
C
PIN
Notes:
Signal Rise Time1.03.0V/ns3
Signal Fall Time1.03.0V/ns3
Setup Time1ns
Hold Time1ns
Pin Capacitance412pF
1. Characterized across DC supply voltage range.
2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent.
3. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
4. Edge rates indicate the range for characterizing the inputs.
38Electrical DataChapter 7
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
8Signal and Power-Up Requirements
The AMD Sempron™ processor model 10 is designed to provide
functional operation if the voltage and temperature parameters
are within the limits of normal operating ranges.
8.1Power-Up Requirements
Signal Sequence and
Timing Description
3.3 V Supply
VCCA (2.5 V)
(for PLL)
VCC_CORE
(Processor Core)
RESET#
NB_RESET#
PWROK
Figure 12 shows the relationship between key signals in the
system during a power-up sequence. This figure details the
requirements of the processor.
2
1
5
6
4
7
8
Warm reset
condition
FID[3:0]
3
System Clock
Figure 12. Signal Relationship Requirements During Power-Up Sequence
Notes: 1. Figure 12 represents several signals generically by using names not necessarily consistent
with any pin lists or schematics.
2.
Requirements 1–8 in Figure 12 are described in “Power-Up Timing Requirements” on page 40.
Chapter 8Signal and Power-Up Requirements39
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Power-Up Timing Requirements.
The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The AMD Sempron processor model 10 does not set the
correct clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET# be
asserted at least 10 nanoseconds prior to the assertion of
PWROK.
In practice, a Southbridge asserts RESET# milliseconds
before PWROK is asserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that V
CC_CORE
and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of three milliseconds from the 3.3 V supply
being within specification. This delay ensures that the
system clock (SYSCLK/SYSCLK#) is operating within
specification when PWROK is asserted.
The processor core voltage, V
CC_CORE
, must be within
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Sempron processor is clocked by a ring
oscillator.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least five
microseconds before PWROK is asserted.
In practice VCCA, V
CC_CORE
, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
40Signal and Power-Up RequirementsChapter 8
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
requirements as defined in Tab le 12, “General AC and DC
Characteristics,” on page 32. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
Chapter 8Signal and Power-Up Requirements41
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Clock Multiplier
Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct serial initialization packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information about FID[3:0], see “FID[3:0] Pins” on
page 70.
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for details
of the SIP protocol.
Athlon system bus for the clock
8.2Processor Warm Reset Requirements
Northbridge Reset
Pins
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
42Signal and Power-Up RequirementsChapter 8
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
9Mechanical Data
The AMD Sempron™ processor model 10 connects to
themotherboard through a Pin Grid Array (PGA) socket named
Socket A. This processor utilizes the Organic Pin Grid Array
(OPGA) package type described in this chapter. For more
information, see the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
9.1Die Loading
The processor die on the OPGA package is exposed at the top of
the package. This feature facilitates heat transfer from the die
to an approved heat sink. Any heat sink design should avoid
loads on corners and edges of die. The OPGA package has
compliant pads that serve to bring surfaces in planar contact.
Tool-assisted zero insertion force sockets should be designed so
that no load is placed on the ceramic substrate of the package.
Table 16 shows the mechanical loading specifications for the
processor die. It is critical that the mechanical loading of the
heat sink does not exceed the limits shown in Tabl e 1 6.
Table 16. Mechanical Loading
LocationDynamic (MAX)Static (MAX)UnitsNote
Die Surface10030lbf1
Die Edge1010lbf2
Notes:
1. Load specified for coplanar contact to die surface.
2. Load defined for a surface at no more than a two-degree angle of inclination to die surface.
Chapter 9Mechanical Data43
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
9.2AMD Sempron™ Processor Model 10 Part Number 27488 OPGA
Package Dimensions
Table 17 shows the part number 27488 OPGA package
dimensions in millimeters assigned to the letters and symbols
used in the 27488 package diagram,
Table 17.Dimensions for the AMD Sempron™ Processor Model 10 Part
Number 27488 OPGA Package
Figure 13 on page 45.
Letter or
Symbol
D/E49.2749.78E91. 661. 96
D1/E145.72 BSCG/H–4.50
D27.42 REFA1.942 REF
D33.303.60A11.001.20
D410.7811.3 3A20.800.88
D510.7811.3 3A30 .116–
D68.138.68A4–1.9 0
D712 .3312 .8 8φP–6.60
D83.053.35φb0.430.50
D912. 7113.26φb11.40 REF
E213.61 REFS1.4352.375
E32.352.65L3.053.31
E47. 8 78.42M37
E57. 8 78.42N453
E611.4111.9 6e1.27 BS C
E711.4111.9 6e12.54 BSC
E813.2813 .8 3
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts and
pins.
Minimum
Dimension
Maximum
1
Dimension
1
Letter or
Symbol
2
Mass
Minimum
Dimension
11.0 g R EF
Maximum
1
Dimension
1
44Mechanical DataChapter 9
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Figure 13. AMD Sempron™ Processor Model 10 Part Number 27488 OPGA Package Diagram
Chapter 9Mechanical Data45
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
9.3AMD Sempron™ Processor Model 10 Part Number 27493 OPGA
Package Dimensions
Table 18 shows the part number 27493 OPGA package
dimensions in millimeters assigned to the letters and symbols
shown in the 27493 package diagram,
Table 18. Dimensions for the AMD Sempron™ Processor Model 10 Part
Number 27493 OPGA Package
Figure 14 on page 47.
Letter or
Symbol
D/E49.2749.78G/H–4.50
D1/E145.72 BSCA1.917 REF
D27.42 REFA10.9771.177
D33.303.60A20.800.88
D410.7811.3 3A30 .116–
D510.7811.3 3A4–1.9 0
D68.138.68φP–6.60
D712 .3312 .8 8φb0.430.50
D83.053.35φb11.40 REF
D912. 7113.26S1.4352.375
E213.61 REFL3.053.31
E32.352.65M37
E47. 8 78.42N453
E57. 8 78.42e1. 27 BSC
E611.4111.9 6e12.54 BSC
E813.2813 .8 3
Minimum
Dimension
Maximum
1
Dimension
1
Letter or
Symbol
2
Mass
Minimum
Dimension
11.0 g R EF
1
Dimension
Maximum
1
E91.661. 96
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts and
pins.
46Mechanical DataChapter 9
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Figure 14. AMD Sempron™ Processor Model 10 Part Number 27493 OPGA Package Diagram
Chapter 9Mechanical Data47
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
48Mechanical DataChapter 9
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
10Pin Descriptions
This chapter includes pin diagrams of the organic pin grid array
(OPGA) for the AMD Sempron™ processor model 10, a listing
of pin name abbreviations, and a cross-referenced listing of pin
locations to signal names.
10.1Pin Diagram and Pin Name Abbreviations
Figure 15 on page 50 shows the staggered Pin Grid Array (PGA)
for the AMD Sempron™ processor model 10. Because some of
the pin names are too long to fit in the grid, they are
abbreviated. Figure 16 on page 51 shows the bottomside view of
the array. Tabl e 19 on page 52 lists all the pins in alphabetical
order by pin name, along with the abbreviation where
necessary.
Chapter 10Pin Descriptions49
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 19. Pin Name Abbreviations
AbbreviationFull NamePin
A20M#AE1
AMDAH6
ANLOGANALOGAJ13
CLKFRCLKFWDRSTAJ21
CLKINAN17
CLKIN#AL17
CNNCTCONNECTAL23
COREFBAG11
COREFB#AG13
CPR#CPU_PRESENCE#AK6
DBRDYAA1
DBREQ#AA3
FERRAG1
FID[0]W1
FID[1]W3
Table 19.Pin Name Abbreviations (continued)
AbbreviationFull NamePin
KEYAA7
KEYAG7
KEYAG9
KEYAG15
KEYAG17
KEYAG27
KEYAG29
NCA19
NCA31
NCC13
NCE25
NCE33
NCF8
NCF30
NCG11
FID[2]Y1
FID[3]Y3
FLUSH#AL3
FSB0FSB_Sense[0]AG31
FSB1FSB_Sense[1]AH30
IGNNE#AJ1
INIT#AJ3
INTRAL1
K7COK7CLKOUTAL21
K7CO#K7CLKOUT#AN21
KEYG7
KEYG9
KEYG15
KEYG17
KEYG23
KEYG25
KEYN7
KEYQ7
KEYY7
NCG13
NCG19
NCG21
NCG27
NCG29
NCG31
NCH6
NCH8
NCH10
NCH28
NCH30
NCH32
NCJ5
NCJ31
NCK8
NCK30
NCL31
NCL35
NCN31
52Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
NCQ31
NCS31
NCU31
NCU37
NCW7
NCW31
NCY5
NCY31
NCY33
NCAA5
NCAA31
NCAC7
NCAC31
NCAD8
NCAD30
Table 19.Pin Name Abbreviations (continued)
AbbreviationFull NamePin
NCAJ19
NCAJ27
NCAK8
NCAL7
NCAL9
NCAL11
NCAL25
NCAL27
NCAM8
NCAN7
NCAN9
NCAN11
NCAN25
NCAN27
NMIAN3
NCAE7
NCAE31
NCAF6
NCAF8
NCAF10
NCAF28
NCAF30
NCAF32
NCAG5
NCAG19
NCAG21
NCAG23
NCAG25
NCAH8
NCAJ7
NCAJ9
NCAJ11
NCAJ15
NCAJ17
PICCLKN1
PICD#0PICD[0]#N3
PICD#1PICD[1]#N5
PLBYP#PLLBYPASS#AJ25
PLBYCPLLBYPASSCLKAN15
PLBYC#PLLBYPASSCLK#AL15
PLMN1PLLMON1AN13
PLMN2PLLMON2AL13
PLTST#PLLTEST#AC3
PRCRDYPROCREADYAN23
PWROKAE3
RESET#AG3
RCLKRSTCLKAN19
RCLK#RSTCLK#AL19
SAI#0SADDIN[0]#AJ29
SAI#1SADDIN[1]#AL29
SAI#2SADDIN[2]#AG33
SAI#3SADDIN[3]#AJ37
SAI#4SADDIN[4]#AL35
Chapter 10Pin Descriptions53
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
SAI#5SADDIN[5]#AE33
SAI#6SADDIN[6]#AJ35
SAI#7SADDIN[7]#AG37
SAI#8SADDIN[8]#AL33
SAI#9SADDIN[9]#AN37
SAI#10SADDIN[10]#AL37
SAI#11SADDIN[11]#AG35
SAI#12SADDIN[12]#AN29
SAI#13SADDIN[13]#AN35
SAI#14SADDIN[14]#AN31
SAIC#SADDINCLK#AJ33
SAO#0SADDOUT[0]#J1
SAO#1SADDOUT[1]#J3
SAO#2SADDOUT[2]#C7
SAO#3SADDOUT[3]#A7
Table 19.Pin Name Abbreviations (continued)
AbbreviationFull NamePin
SD#3SDATA[3]#Y35
SD#4SDATA[4]#U35
SD#5SDATA[5]#U33
SD#6SDATA[6]#S37
SD#7SDATA[7]#S33
SD#8SDATA[8]#AA33
SD#9SDATA[9]#AE37
SD#10SDATA[10]#AC33
SD#11SDATA[11]#AC37
SD#12SDATA[12]#Y37
SD#13SDATA[13]#AA37
SD#14SDATA[14]#AC35
SD#15SDATA[15]#S35
SD#16SDATA[16]#Q37
SD#17SDATA[17]#Q35
SAO#4SADDOUT[4]#E5
SAO#5SADDOUT[5]#A5
SAO#6SADDOUT[6]#E7
SAO#7SADDOUT[7]#C1
SAO#8SADDOUT[8]#C5
SAO#9SADDOUT[9]#C3
SAO#10SADDOUT[10]#G1
SAO#11SADDOUT[11]#E1
SAO#12SADDOUT[12]#A3
SAO#13SADDOUT[13]#G5
SAO#14SADDOUT[14]#G3
SAOC#SADDOUTCLK#E3
SCNCK1SCANCLK1S1
SCNCK2SCANCLK2S5
SCNINVSCANINTEVALS3
SCNSNSCANSHIFTENQ5
SD#0SDATA[0]#AA35
SD#1SDATA[1]#W37
SD#2SDATA[2]#W35
SD#18SDATA[18]#N37
SD#19SDATA[19]#J33
SD#20SDATA[20]#G33
SD#21SDATA[21]#G37
SD#22SDATA[22]#E37
SD#23SDATA[23]#G35
SD#24SDATA[24]#Q33
SD#25SDATA[25]#N33
SD#26SDATA[26]#L33
SD#27SDATA[27]#N35
SD#28SDATA[28]#L37
SD#29SDATA[29]#J37
SD#30SDATA[30]#A37
SD#31SDATA[31]#E35
SD#32SDATA[32]#E31
SD#33SDATA[33]#E29
SD#34SDATA[34]#A27
SD#35SDATA[35]#A25
SD#36SDATA[36]#E21
54Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
SD#37SDATA[37]#C23
SD#38SDATA[38]#C27
SD#39SDATA[39]#A23
SD#40SDATA[40]#A35
SD#41SDATA[41]#C35
SD#42SDATA[42]#C33
SD#43SDATA[43]#C31
SD#44SDATA[44]#A29
SD#45SDATA[45]#C29
SD#46SDATA[46]#E23
SD#47SDATA[47]#C25
SD#48SDATA[48]#E17
SD#49SDATA[49]#E13
SD#50SDATA[50]#E11
SD#51SDATA[51]#C15
SD#52SDATA[52]#E9
SD#53SDATA[53]#A13
SD#54SDATA[54]#C9
SD#55SDATA[55]#A9
SD#56SDATA[56]#C21
SD#57SDATA[57]#A21
SD#58SDATA[58]#E19
SD#59SDATA[59]#C19
SD#60SDATA[60]#C17
SD#61SDATA[61]#A11
SD#62SDATA[62]#A17
SD#63SDATA[63]#A15
SDIC#0SDATAINCLK[0]#W33
SDIC#1SDATAINCLK[1]#J35
SDIC#2SDATAINCLK[2]#E27
SDIC#3SDATAINCLK[3]#E15
SDINV#SDATAINVALID#AN33
SDOC#0SDATAOUTCLK[0]#AE35
SDOC#1SDATAOUTCLK[1]#C37
Table 19.Pin Name Abbreviations (continued)
AbbreviationFull NamePin
SDOC#2SDATAOUTCLK[2]#A33
SDOC#3SDATAOUTCLK[3]#C11
SDOV#SDATAOUTVALID#AL31
SFILLV#SFILLVALID#AJ31
SMI#AN5
STPC#STPCLK#AC1
TCKQ1
TDIU1
TDOU5
THDATHERMDAS7
THDCTHERMDCU7
TMSQ3
TRST#U3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
B4
B8
B12
B16
B20
B24
B28
B32
B36
D2
D4
D8
D12
D16
D20
D24
D28
D32
F12
F16
F20
Chapter 10Pin Descriptions55
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
F24
F28
F32
F34
F36
H2
H4
H12
H16
H20
H24
K32
K34
K36
M2
M4
M6
M8
P30
P32
P34
P36
R2
R4
R6
R8
T30
T32
T34
T36
V2
V4
V6
V8
Table 19.Pin Name Abbreviations (continued)
AbbreviationFull NamePin
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
X30
X32
X34
X36
Z2
Z4
Z6
Z8
AB30
AB32
AB34
AB36
AD2
AD4
AD6
AF14
AF18
AF22
AF26
AF34
AF36
AH2
AH4
AH10
AH14
AH18
AH22
AH26
AK10
AK14
AK18
AK22
AK26
AK30
56Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VREF_SVREF_SYSW5
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
AK34
AK36
AJ5
AL5
AM2
AM10
AM14
AM18
AM22
AM26
AM22
AM26
AM30
AM34
VCCAAJ23
VID[0]L1
VID[1]L3
VID[2]L5
VID[3]L7
VID[4]J7
VSSB2
VSSB6
VSSB10
VSSB14
VSSB18
VSSB22
VSSB26
VSSB30
VSSB34
VSSD6
VSSD10
VSSD14
VSSD18
Table 19.Pin Name Abbreviations (continued)
AbbreviationFull NamePin
VSSD22
VSSD26
VSSD30
VSSD34
VSSD36
VSSF2
VSSF4
VSSF6
VSSF10
VSSF14
VSSF18
VSSF22
VSSF26
VSSH14
VSSH18
VSSH22
VSSH26
VSSH34
VSSH36
VSSK2
VSSK4
VSSK6
VSSM30
VSSM32
VSSM34
VSSM36
VSSP2
VSSP4
VSSP6
VSSP8
VSSR30
VSSR32
VSSR34
VSSR36
Chapter 10Pin Descriptions57
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
VSST2
VSST4
VSST6
VSST8
VSSV30
VSSV32
VSSV34
VSSV36
VSSX2
VSSX4
VSSX6
VSSX8
VSSZ30
VSSZ32
VSSZ34
Table 19. Pin Name Abbreviations (continued)
AbbreviationFull NamePin
VSSAH12
VSSAH16
VSSAH20
VSSAH24
VSSAH28
VSSAH32
VSSAH34
VSSAH36
VSSAK2
VSSAK4
VSSAK12
VSSAK16
VSSAK20
VSSAK24
VSSAK28
VSSZ36
VSSAB2
VSSAB8
VSSAB4
VSSAB6
VSSAD32
VSSAD34
VSSAD36
VSSAF2
VSSAF4
VSSAF12
VSSAF16
VSSAK32
VSSAM4
VSSAM6
VSSAM12
VSSAM16
VSSAM20
VSSAM24
VSSAM28
VSSAM32
VSSAM36
ZNAC5
ZPAE5
58Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
10.2Pin Li st
Tabl e 20 on page 60 cross-references Socket A pin location to
signal name.
The “L” (Level) column shows the electrical specification for
this pin. “P” indicates a push-pull mode driven by a single
source. “O” indicates open-drain mode that allows devices to
share the pin.
Note: The AMD Sempron processor supports push-pull drivers. For
more information, see
The “P” (Port) column indicates if this signal is an input (I),
output (O), or bidirectional (B) signal. The “R” (Reference)
column indicates if this signal should be referenced to VSS (G)
or VCC_CORE (P) planes for the purpose of signal routing with
respect to the current return paths.
“Push-Pull (PP) Drivers” on page 6.
Chapter 10Pin Descriptions59
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 20. Cross-Reference by Pin Location
PinNameDescriptionLPR
A1No Pinpage 72---
A3SADDOUT[12]#POG
A5SADDOUT[5]#POG
A7SADDOUT[3]#POG
A9SDATA[55]#PBP
A11SDATA[61]#PBP
A13SDATA[53]#PBG
A15SDATA[63]#PBG
A17SDATA[62]#PBG
A19NC Pin page 72---
A21SDATA[57]#PBG
A23SDATA[39]#PBG
A25SDATA[35]#PBP
A27SDATA[34]#PBP
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
B24
B26 VSS---
B28
B30 VSS---
B32
B34 VSS---
B36
C1SADDOUT[7]#POG
C3SADDOUT[9]#POG
C5SADDOUT[8]#POG
C7SADDOUT[2]#POG
C9SDATA[54]#PBP
C11SDATAOUTCLK[3]#POG
C13NC Pin page 72---
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
A29SDATA[44]#PBG
A31NC Pin page 72---
A33SDATAOUTCLK[2]#POP
A35SDATA[40]#PBG
A37SDATA[30]#PBP
B2 VSS---
B4
V
CC_CORE
---
B6 VSS---
B8
V
CC_CORE
---
B10 VSS---
B12
V
CC_CORE
---
B14 VSS---
B16
V
CC_CORE
---
B18 VSS---
B20
V
CC_CORE
---
B22 VSS---
C15SDATA[51]#PBP
C17SDATA[60]#PBG
C19SDATA[59]#PBG
C21SDATA[56]#PBG
C23SDATA[37]#PBP
C25SDATA[47]#PBG
C27SDATA[38]#PBG
C29SDATA[45]#PBG
C31SDATA[43]#PBG
C33SDATA[42]#PBG
C35SDATA[41]#PBG
C37SDATAOUTCLK[1]#POG
D2
D4
V
CC_CORE
V
CC_CORE
---
---
D6 VSS---
D8
V
CC_CORE
---
60Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
D10VSS---
D12
V
CC_CORE
---
D14VSS---
D16
V
CC_CORE
---
D18VSS---
D20
V
CC_CORE
---
D22VSS---
D24
V
CC_CORE
---
D26VSS---
D28
V
CC_CORE
---
D30VSS---
D32
V
CC_CORE
---
D34VSS---
D36VSS---
E1SADDOUT[11]#POP
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
E33NC Pin page 72---
E35SDATA[31]#PBP
E37SDATA[22]#PBG
F2 VSS---
F4 VSS---
F6 VSS---
F8NC Pin page 72---
F10 VSS---
F12
F14 VSS---
F16
F18 VSS---
F20
F22 VSS---
F24
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
E3SADDOUTCLK#POG
E5SADDOUT[4]#POP
E7SADDOUT[6]#POG
E9SDATA[52]#PBP
E11SDATA[50]#PBP
E13SDATA[49]#PBG
E15SDATAINCLK[3]#PIG
E17SDATA[48]#PBP
E19SDATA[58]#PBG
E21SDATA[36]#PBP
E23SDATA[46]#PBP
E25NC Pin page 72---
E27SDATAINCLK[2]#PIG
E29SDATA[33]#PBP
E31SDATA[32]#PBP
F26 VSS---
F28
V
CC_CORE
---
F30NC Pin page 72---
F32
F34
F36
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
G1SADDOUT[10]#POP
G3SADDOUT[14]#POG
G5SADDOUT[13]#POG
G7Key Pinpage 72---
G9Key Pinpage 72---
G11NC Pinpage 72---
G13NC Pin page 72---
G15Key Pinpage 72---
G17Key Pin page 72---
Chapter 10Pin Descriptions61
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
G19NC Pin page 72---
G21NC Pin page 72---
G23Key Pinpage 72---
G25Key Pin page 72---
G27NC Pin page 72---
G29NC Pin page 72---
G31NC Pin page 72---
G33SDATA[20]#PBG
G35SDATA[23]#
PBG
G37SDATA[21]#PBG
H2
H4
V
CC_CORE
V
CC_CORE
---
---
H6NC Pinpage 72---
H8NC Pinpage 72---
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
J5NC Pin page 72---
J7VID[4]page 74OO-
J31NC Pinpage 72---
J33SDATA[19]#PBG
J35SDATAINCLK[1]#PIP
J37SDATA[29]#PBP
K2 VSS---
K4 VSS---
K6 VSS---
K8NC Pin page 72---
K30NC Pinpage 72---
K32
K34
K36
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
H10NC Pinpage 72---
H12
V
CC_CORE
---
H14VSS---
H16
V
CC_CORE
---
H18VSS---
H20
V
CC_CORE
---
H22VSS---
H24
V
CC_CORE
---
H26VSS---
H28NC Pin page 72---
H30NC Pin page 72---
H32NC Pin page 72---
H34VSS---
H36VSS---
J1SADDOUT[0]#page 73PO-
J3SADDOUT[1]#page 73PO-
L1VID[0]page 74OO-
L3VID[1] page 74OO-
L5VID[2] page 74OO-
L7VID[3]page 74OO-
L31NC Pin page 72---
L33SDATA[26]#PBP
L35NC Pin page 72---
L37SDATA[28]#PBP
M2
M4
M6
M8
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
M30VSS---
M32VSS---
M34VSS---
M36VSS---
62Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
N1PICCLKpage 68OI-
N3PICD#[0]page 68OB-
N5PICD#[1]page 68OB-
N7Key Pin page 72---
N31NC Pinpage 72---
N33SDATA[25]#PBP
N35SDATA[27]#PBP
N37SDATA[18]#PBG
P2 VSS---
P4 VSS---
P6 VSS---
P8 VSS---
P30
P32
P34
P36
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Q1TCK page 72PI-
Q3TMSpage 72PI-
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
R34 VSS---
R36 VSS---
S1SCANCLK1 page 73PI-
S3SCANINTEVAL page 73PI-
S5SCANCLK2page 73PI-
S7THERMDApage 73---
S31NC Pinpage 72---
S33SDATA[7]#PBG
S35SDATA[15]#PBP
S37SDATA[6]#PBG
T2 VSS---
T4 VSS---
T6 VSS---
T8 VSS---
T30
T32
T34
T36
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Q5SCANSHIFTEN page 73PI-
Q7Key Pin page 72---
Q31NC Pin page 72---
Q33SDATA[24]#PBP
Q35SDATA[17]#PBG
Q37SDATA[16]#PBG
R2
R4
R6
R8
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
R30 VSS---
R32 VSS---
U1TDI page 72PI-
U3TRST# page 72PI-
U5TDO page 72PO-
U7THERMDCpage 73---
U31NC Pinpage 72---
U33SDATA[5]#PBG
U35SDATA[4]#PBG
U37NC Pin page 72---
V2
V4
V6
V8
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Chapter 10Pin Descriptions63
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
V30 VSS---
V32 VSS---
V34 VSS---
V36 VSS---
W1FID[0] page 70OO-
W3FID[1]page 70OO-
W5VREFSYSpage 74P--
W7NC Pinpage 72---
W31NC Pinpage 72---
W33SDATAINCLK[0]#PIG
W35SDATA[2]#PBG
W37SDATA[1]#PBP
X2 VSS---
X4 VSS---
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
Z6
Z8
Z30 VSS---
Z32 VSS---
Z34 VSS---
Z36 VSS---
AA1DBRDY page 69PO-
AA3DBREQ# page 69PI-
AA5NC---
AA7Key Pinpage 72---
AA31NC Pinpage 72---
AA33SDATA[8]#PBP
AA35SDATA[0]#PBG
AA37SDATA[13]#PBG
V
CC_CORE
V
CC_CORE
---
---
X6 VSS---
X8 VSS---
X30
X32
X34
X36
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
Y1FID[2]page 70OO-
Y3FID[3] page 70OO-
Y5NC Pinpage 72---
Y7Key Pin page 72---
Y31NC Pinpage 72---
Y33NC Pin page 72---
Y35SDATA[3]#PBG
Y37SDATA[12]#PBP
Z2
Z4
V
CC_CORE
V
CC_CORE
---
---
AB2VSS---
AB4VSS---
AB6VSS---
AB8VSS---
AB30
AB32
AB34
AB36
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
AC1STPCLK#page 73PI-
AC3PLLTEST# page 72PI-
AC5ZN page 75P--
AC7NC---
AC31NC Pinpage 72---
AC33SDATA[10]#PBP
AC35SDATA[14]#PBG
AC37SDATA[11]#PBG
64Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
AD2
AD4
AD6
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
AD8NC Pinpage 72---
AD30NC Pinpage 72---
AD32VSS---
AD34VSS---
AD36VSS---
AE1A20M#PI-
AE3PWROKPI-
AE5ZP page 75P--
AE7 NC---
AE31NC Pinpage 72---
AE33SADDIN[5]#PIG
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
AF30NC Pinpage 72---
AF32NC Pinpage 72---
AF34
AF36
AG1FERRpage 69PO-
AG3RESET#-I-
AG5NC Pinpage 72---
AG7Key Pin page 72---
AG9Key Pinpage 72---
AG11COREFBpage 69---
AG13COREFB#page 69---
AG15Key Pin page 72---
AG17Key Pinpage 72---
AG19NC Pinpage 72---
V
CC_CORE
V
CC_CORE
---
---
AE35SDATAOUTCLK[0]#POP
AE37SDATA[9]#PBG
AF2 VSS---
AF4 VSS---
AF6NC Pinpage 72---
AF8NC Pinpage 72---
AF10NC Pinpage 72---
AF12VSS---
AF14
V
CC_CORE
---
AF16VSS---
AF18
V
CC_CORE
---
AF20VSS---
AF22
V
CC_CORE
---
AF24VSS---
AF26
V
CC_CORE
---
AF28NC Pinpage 72---
AG21NC Pinpage 72---
AG23NC Pinpage 72---
AG25NC Pinpage 72---
AG27Key Pinpage 72---
AG29Key Pinpage 72---
AG31FSB_Sense[0]page 71-OG
AG33SADDIN[2]#PIG
AG35SADDIN[11]#PIG
AG37SADDIN[7]#PIP
AH2
AH4
V
CC_CORE
V
CC_CORE
---
---
AH6AMD Pin page 68---
AH8NC Pinpage 72---
AH10
V
CC_CORE
---
AH12VSS---
AH14
V
CC_CORE
---
Chapter 10Pin Descriptions65
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
AH16VSS---
AH18
V
CC_CORE
---
AH20VSS---
AH22
V
CC_CORE
---
AH24VSS---
AH26
V
CC_CORE
---
AH28VSS---
AH30FSB_Sense[1]page 71-OG
AH32VSS---
AH34VSS---
AH36VSS---
AJ1IGNNE#page 71PI-
AJ3INIT#page 71PI-
AJ5
V
CC_CORE
---
AJ7NC Pinpage 72---
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
AK2VSS---
AK4VSS---
AK6CPU_PRESENCE#page 69---
AK8NC Pinpage 72---
AK10
AK12VSS---
AK14
AK16VSS---
AK18
AK20VSS---
AK22
AK24VSS---
AK26
AK28VSS---
AK30
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
---
---
---
---
---
---
AJ9NC Pinpage 72---
AJ11NC Pinpage 72---
AJ13Analog page 68---
AJ15NC Pinpage 72---
AJ17NC Pinpage 72---
AJ19NC Pinpage 72---
AJ21CLKFWDRSTpage 68PIP
AJ23VCCA page 73---
AJ25PLLBYPASS# page 72PI-
AJ27NC Pinpage 72---
AJ29SADDIN[0]#page 73PI-
AJ31SFILLVALID#PIG
AJ33SADDINCLK#PIG
AJ35SADDIN[6]#PIP
AJ37SADDIN[3]#PIG
AK32VSS---
AK34
AK36
V
CC_CORE
V
CC_CORE
---
---
AL1INTRpage 72PI-
AL3FLUSH#page 71PI-
AL5
V
CC_CORE
---
AL7NC Pinpage 72---
AL9NC Pinpage 72---
AL11NC Pinpage 72---
AL13PLLMON2page 72OO-
AL15PLLBYPASSCLK#page 72PI-
AL17CLKIN#page 69PIP
AL19RSTCLK#page 69PIP
AL21K7CLKOUTpage 72PO-
AL23CONNECTpage 69PIP
66Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location
(continued)
PinNameDescriptionLPR
AL25NC Pinpage 72---
AL27NC Pinpage 72---
AL29SADDIN[1]#page 73PI-
AL31SDATAOUTVALID#POP
AL33SADDIN[8]#PIP
AL35SADDIN[4]#PIG
AL37SADDIN[10]#PIG
AM2
V
CC_CORE
---
AM4VSS---
AM6VSS---
AM8NC Pinpage 72---
AM10
V
CC_CORE
---
AM12VSS---
AM14
V
CC_CORE
---
Table 20.Cross-Reference by Pin Location
PinNameDescriptionLPR
AM32VSS---
AM34
AM36VSS---
AN1No Pin page 72---
AN3NMIPI-
AN5SMI#PI-
AN7NC Pinpage 72---
AN9NC Pinpage 72---
AN11NC Pinpage 72---
AN13PLLMON1 page 72OB-
AN15PLLBYPASSCLK page 72PI-
AN17CLKIN page 69PIP
AN19RSTCLK page 69PIP
AN21K7CLKOUT# page 72PO-
V
CC_CORE
---
AM16VSS---
AM18
V
CC_CORE
---
AM20VSS---
AM22
V
CC_CORE
---
AM24VSS---
AM26
V
CC_CORE
---
AM28VSS---
AM30
V
CC_CORE
---
AN23PROCRDYPOP
AN25NC Pinpage 72---
AN27NC Pinpage 72---
AN29SADDIN[12]#PIG
AN31SADDIN[14]#PIG
AN33SDATAINVALID#PIP
AN35SADDIN[13]#PIG
AN37SADDIN[9]#PIG
Chapter 10Pin Descriptions67
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
10.3Detailed Pin Descriptions
The information in this section pertains to Table 20 on page 60.
A20M# PinA20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD PinAMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
blocks this pin location. When the cover plate blocks this
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Athlon™
System Bus Pins
Analog PinTreat this pin as a NC.
APIC Pins, PICCLK,
PICD[1:0]#
See the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902 for information about the system
The Advanced Programmable Interrupt Controller (APIC) is a
feature that provides a flexible and expandable means of
delivering interrupts in a system using an AMD processor. The
pins, PICD[1:0], are the bidirectional message-passing signals
used for the APIC and are driven to the Southbridge or a
dedicated I/O APIC. The pin, PICCLK, must be driven with a
valid clock input.
Refer to “VCC_2.5V Generation Circuit” found in the section,
“Motherboard Required Circuits,” of the AMD Athlon™ Processor Motherboard Design Guide, order# 24363 for the
required supporting circuitry.
For more information, see Table 15, “APIC Pin AC and DC
Characteristics,” on page 37.
CLKFWDRST PinCLKFWDRST resets clock-forward circuitry for both the system
and processor.
Chapter 10Pin Descriptions68
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
CLKIN, RSTCLK
(SYSCLK) Pins
Connect CLKIN with RSTCLK and name it SYSCLK. Connect
CLKIN# with RSTCLK# and name it SYSCLK#. Length match
the clocks from the clock generator to the Northbridge and
processor.
See “SYSCLK and SYSCLK#” on page 73 for more information.
CONNECT PinCONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB and
COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# PinCPU_PRESENCE# is connected to VSS on the processor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor in
the Socket A-style socket.
DBRDY and DBREQ#
Pins
DBRDY and DBREQ# are routed to the debug connector.
DBREQ# is tied to V
CC_CORE
with a pullup resistor.
FERR PinFERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0. FERR is a push-pull active High signal that must be
inverted and level shifted to an active Low signal. For more
information about FERR and FERR#, see the “Required
Circuits” chapter of the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
Chapter 10Pin Descriptions69
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
FID[3:0] PinsFID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 21 describes the encodings of the clock multipliers on
FID[3:0].
Table 21. FID[3:0] Clock Multiplier Encodings
FID[3:0]
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.
For more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.
The FID[3:0] signals are open-drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (serial initialization packet) that is sent to
the processor. The FID[3:0] signals are valid after PWROK is
asserted. The FID[3:0]signals must not be sampled until they
become valid. See the AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902 for more information about
Serialization Initialization Packets and SIP protocol.
The processor FID[3:0] outputs are open-drain and 2.5-V
tolerant. To prevent damage to the processor, do not pull these
70Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
signals High above 2.5 V. Do not expose these pins to a
differential voltage greater than 1.60 V, relative to the
processor core voltage.
Refer to “VCC_2.5V Generation Circuit” found in the section,
“Motherboard Required Circuits,” of the AMD Athlon™ Processor Motherboard Design Guide, order# 24363 for the
required supporting circuitry.
See “Frequency Identification (FID[3:0])” on page 27 for the
DC characteristics for FID[3:0].
FSB_Sense[1:0] PinsFSB_Sense[1:0] pins are either open circuit (logic level of 1) or
are pulled to ground (logic level of 0) on the processor package
with a 1 kΩ resistor. In conjunction with a circuit on the
motherboard, these pins may be used to automatically detect
the front-side bus (FSB) setting of this processor. Proper
detection of the FSB setting requires the implementation of a
pull-up resistor on the motherboard. Refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363 and the
technical note FSB_Sense Auto Detection Circuitry for Desktop Processors, order# TN26673 for more information.
Table 22 is the truth table to determine the FSB of desktop
processors.
Table 22. Front-Side Bus Sense Truth Table
FSB_Sense[1] FSB_Sense[0] Bus Frequency
10 RESERVED
11133 MHz
01166 MHz
00200 MHz
The FSB_Sense[1:0] pins are 3.3-V tolerant.
FLUSH# PinFLUSH# must be tied to V
CC_CORE
with a pullup resistor. If a
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# PinIGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# PinINIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0_FFFF_FFF0h.
Chapter 10Pin Descriptions71
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
INTR PinINTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
JTAG Pins
TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.
Connect these pins directly to the motherboard debug
connector. Pull TDI, TCK, TMS, and TRST# up to V
CC_CORE
with
pullup resistors.
K7CLKOUT and
K7CLKOUT# Pins
Key Pins
K7CLKOUT and K7CLKOUT# are each run for two to three
inches and then terminated with a resistor pair: 100 ohms to
V
CC_CORE
resistance and voltage are 50 ohms and V
and 100 ohms to VSS. The effective termination
CC_CORE
/2.
These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
Motherboard designers should treat key pins like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
See “NC Pins“ for more information.
NC PinsThe motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin
NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2,
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
and test interface. This interface is tied disabled on the
motherboard. All six pin signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to V
CC_CORE
with pullup
resistors.
72Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
For more information, Chapter 8, “Signal and Power-Up
Requirements” on page 39.
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
The AMD Sempron processor model 10 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models can support SADDIN[1]#).
SADDOUT[1:0]# are tied to VCC with pullup resistors if these
pins are supported by the Northbridge. For more information,
see the AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902.
Scan PinsSCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2
are the scan interface. This interface is AMD internal and is
tied disabled with pulldown resistors to ground on the
motherboard.
SMI# PinSMI# is an input that causes the processor to enter the system
management mode.
STPCLK# PinSTPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK and SYSCLK# SYSCLK and SYSCLK# are differential input clock signals
provided to the PLL of the processor from a system-clock
generator.
See “CLKIN, RSTCLK (SYSCLK) Pins” on page 69 for more
information.
THERMDA and
THERMDC Pins
Thermal Diode anode and cathode pins are used to monitor the
actual temperature of the processor die, providing more
accurate temperature control to the system.
See Table 13, “Thermal Diode Electrical Characteristics,” on
page 35 for more information.
VCCA PinVCCA is the processor PLL supply. For information about the
VCCA pin, see Table 5, “VCCA AC and DC Characteristics,” on
page 35 and the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
To prevent damage to the processor, do not pull this signal High
above 2.5 V. Do not expose this pin to a differential voltage
greater than 1.60 V, relative to the processor core voltage.
Chapter 10Pin Descriptions73
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
VID[4:0] PinsThe VID[4:0] (Voltage Identification) outputs are used to
dictate the V
CC_CORE
voltage level. The VID[4:0] pins are
strapped to ground or left unconnected on the processor
package. The VID[4:0] pins are pulled up on the motherboard
and used by the V
CC_CORE
DC/DC converter.
The VID codes and corresponding voltage levels are shown in
Table 23.
Table 23. VID[4:0] Code to Voltage Definition
VID[4:0]
000001. 850100001. 45 0
000011.825100011.4 25
000101.800100101.400
000111.77510 0111. 375
001001.7501010 01.350
001011.725101011.325
001111. 675101111.2 75
010001.6 50110001.250
010011.625110 011.225
010101.600110101.200
010111.575110111.175
011001.5501110 01.150
011011.525111011.125
011101.500111101.10 0
011111.47511111No CPU
V
CC_CORE
(V)
VID[4:0]
V
CC_CORE
(V)
For more information, see the “Required Circuits” chapter of
the AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363.
VREFSYS PinVREFSYS (W5) drives the threshold voltage for the system bus
input receivers. The value of VREFSYS is system specific. In
addition, to minimize V
CC_CORE
noise rejection from VREFSYS,
include decoupling capacitors. For more information, see the
AMD Athlon™ Processor-Based Motherboard Design Guide, order#
24363.
74Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
ZN and ZP PinsZN (AC5) and ZP (AE5) are the push-pull compensation circuit
pins. In Push-Pull mode (selected by the SIP parameter
SysPushPull asserted), ZN is tied to V
CC_CORE
that has a resistance matching the impedance Z
with a resistor
of the
0
transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z
of the transmission line.
0
Chapter 10Pin Descriptions75
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
76Pin DescriptionsChapter 10
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
11Ordering Information
Standard AMD Sempron™ Processor Model 10 Products
AMD standard products are available in several operating ranges. The ordering part
numbers (OPN) are formed by a combination of the elements, as shown in Figure 17.
1
OPN
SDCD2800
Note:
1. Spaces are added to the number shown above for viewing clarity only.
2. This processor is available only with an advanced 333 FSB.
D U T 3
Advanced Front-Side Bus: D = 333
Size of L2 Cache: 3 = 256 Kbytes
Die Temperature: T = 90°C
Operating Voltage: U = 1.60 V
Package Type: D = OPGA
Model Number: 2800 operates at 2000 MHz
Maximum Power: C = Desktop Processor
Architecture Segment: SD = AMD Sempron™ Processor Model 10 with
QuantiSpeed™ Architecture for Desktop Products
2
, 2200 operates at 1500 MHz
Figure 17. OPN Example for the AMD Sempron™ Processor Model 10 with 256K L2 Cache
2
Chapter 11Ordering Information77
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
78Ordering InformationChapter 11
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Appendix A
Thermal Diode Calculations
This section contains information about the calculations for the
on-die thermal diode of the AMD Sempron™ processor model
10. For electrical information about this thermal diode, see
Tabl e 13, “Thermal Diode Electrical Characteristics,” on
page 35.
Ideal Diode Equation
The ideal diode equation uses the variables and constants
defined in Tabl e 2 4.
Table 24. Constants and Variables for the Ideal Diode Equation
Equation SymbolVariable, Constant Description
n
f, lumped
kBoltzmann constant
qElectron charge constant
TDiode temperature (Kelvin)
V
BE
I
C
I
S
Lumped ideality factor
Voltage from base to emitter
Collector current
Saturation current
Appendix A - Thermal Diode Calculations79
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Equation (1) shows the ideal diode calculation.
V
BE
n
f lumped,
Sourcing two currents and using Equation (1) derives the
difference in the base-to-emitter voltage that leads to finding
the diode temperature as shown in Equation (2). The use of
dual sourcing currents allows the measurement of the thermal
diode temperature to be more accurate and less susceptible to
die and process revisions. Temperature sensors that utilize
series resistance cancellation can use more than two sourcing
currents and are suitable to be used with the AMD thermal
diode. Equation (2) is the formula for calculating the
temperature of a thermal diode.
A temperature offset may be required to correct the value
measured by a temperature sensor. An offset is necessary if a
difference exists between the lumped ideality factor of the
processor and the ideality factor assumed by the temperature
sensor. The lumped ideality factor can be calculated using the
equations in this section to find the temperature offset that
should be used with the temperature sensor.
k
-- - T
q
–
k
-- -
q
ln⋅⋅⋅=
V
BE low,
I
high
⎛⎞
------- -
ln⋅⋅
⎝⎠
I
I
⎛⎞
--- -
⎝⎠
I
low
C
S
(1)
(2)
Table 25 shows the constants and variables used to calculate the
temperature offset correction.
Table 25. Constants and Variables Used in Temperature Offset Equations
Equation SymbolVariable, Constant Description
n
f, actual
n
f, lumped
n
f, TS
I
high
I
low
T
die, spec
T
offset
Actual ideality factor
Lumped ideality factor
Ideality factor assumed by temperature sensor
High sourcing current
Low sourcing current
Die temperature specification
Temperature offset
80Appendix A - Thermal Diode Calculations
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
The formulas in Equation (3) and Equation (4) can be used to
calculate the temperature offset for temperature sensors that
do not employ series resistance cancellation. The result is
added to the value measured by the temperature sensor.
Contact the vendor of the temperature sensor being used for
the value of n
. Refer to the document, On-Die Thermal Diode
f,TS
Characterization, order# 25443, for further details.
Equation (3) shows the equation for calculating the lumped
ideality factor (n
Equation (4) shows the equation for calculating temperature
offset (T
) in sensors that do not employ series resistance
offset
cancellation.
n
T
offset
T
die spec,
273.15+()=1
⎛⎞
⋅
⎝⎠
–
-------------- -
f lumped,
n
fTS,
(4)
Equation (5) is the temperature offset for temperature sensors
that utilize series resistance cancellation. Add the result to the
value measured by the temperature sensor. Note that the value
of n
in Equation (5) may not equal the value used in
f,TS
Equation (4).
n
T
offset
T
die spec,
273.15+()=1
⎛⎞
⋅
⎝⎠
–
-------------- -
f actual,
n
fTS,
(5)
Appendix A - Thermal Diode Calculations81
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
82Appendix A - Thermal Diode Calculations
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Appendix B
Conventions and
Abbreviations
Signals and Bits
This section contains information about the conventions and
abbreviations used in this document.
■Active-Low Signals — Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and Low
are written with an initial upper case letter.
■Signal Ranges — In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by a
colon (for example, D[63:0]).
■Reserved Bits and Signals — Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
■Three-State — In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
■Invalid and Don’t-Care — In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen pattern.
Appendix B - Conventions and Abbreviations83
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Data Terminology
The following list defines data terminology:
■Quantities
•A word is two bytes (16 bits)
•A doubleword is four bytes (32 bits)
•A quadword is eight bytes (64 bits)
■Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
■Abbreviations — The following notation is used for bits and
bytes:
•Kilo (K, as in 4-Kbyte page)
•Mega (M, as in 4 Mbits/sec)
•Giga (G, as in 4 Gbytes of memory space)
See Table 26 on page 85 for more abbreviations.
■Little-Endian Convention — The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left — the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
■Bit Ranges — In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
■Bit Values — Bits can either be set to 1 or cleared to 0.
■Hexadecimal and Binary Numbers — Unless the context
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
84Appendix B - Conventions and Abbreviations
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Abbreviations and Acronyms
Table 26 contains the definitions of abbreviations used in this
document.
Table 26. Abbreviations
AbbreviationMeaning
AAmpere
FFarad
GGiga–
GbitGigabit
GbyteGigabyte
HHenry
hHexadecimal
KKilo–
KbyteKilobyte
MMega–
MbitMegabit
MbyteMegabyte
MHzMegahertz
mMilli–
msMillisecond
mWMilliwatt
µMicro–
µAMicroampere
µFMicrofarad
µHMicrohenry
µsMicrosecond
µVMicrovolt
nnano–
nAnanoampere
nFnanofarad
nHnanohenry
nsnanosecond
ohmOhm
ppico–
pApicoampere
Appendix B - Conventions and Abbreviations85
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 26. Abbreviations (continued)
AbbreviationMeaning
pFpicofarad
pHpicohenry
pspicosecond
sSecond
VVolt
WWatt
Table 27 contains the definitions of acronyms used in this
document.
Table 27. Acronyms
AbbreviationMeaning
ACPIAdvanced Configuration and Power Interface
AGPAccelerated Graphics Port
APCIAGP Peripheral Component Interconnect
APIApplication Programming Interface
APICAdvanced Programmable Interrupt Controller
BIOSBasic Input/Output System
BISTBuilt-In Self-Test
BIUBus Interface Unit
CPGACeramic Pin Grid Array
DDRDouble-Data Rate
DIMMDual Inline Memory Module
DMADirect Memory Access
DRAMDirect Random Access Memory
EIDEEnhanced Integrated Device Electronics
EISAExtended Industry Standard Architecture
EPROMEnhanced Programmable Read Only Memory
FIFOFirst In, First Out
GARTGraphics Address Remapping Table
HSTLHigh-Speed Transistor Logic
IDEIntegrated Device Electronics
ISAIndustry Standard Architecture
JEDECJoint Electron Device Engineering Council
JTAGJoint Test Action Group
86Appendix B - Conventions and Abbreviations
31994A —1 August 2004AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 27. Acronyms (continued)
AbbreviationMeaning
LANLarge Area Network
LRULeast-Recently Used
LV TT LLow Voltage Transistor Transistor Logic
MSBMost Significant Bit
MTRRMemory Type and Range Registers
MUXMultiplexer
NMINon-Maskable Interrupt
ODOpen-Drain
OPGAOrganic Pin Grid Array
PBGAPlastic Ball Grid Array
PAPhysical Address
PCIPeripheral Component Interconnect
PDEPage Directory Entry
PDTPage Directory Table
PGAPin Grid Array
PLLPhase Locked Loop
PMSMPower Management State Machine
POSPower-On Suspend
POSTPower-On Self-Test
RAMRandom Access Memory
ROMRead Only Memory
RXARead Acknowledge Queue
SCSISmall Computer System Interface
SDISystem DRAM Interface
SDRAMSynchronous Direct Random Access Memory
SIMDSingle Instruction Multiple Data
SIP
SMbusSystem Management Bus
Serial Initialization Packet
SPDSerial Presence Detect
SRAMSynchronous Random Access Memory
SROMSerial Read Only Memory
TLBTranslation Lookaside Buffer
TOMTop of Memory
TTLTransistor Transistor Logic
Appendix B - Conventions and Abbreviations87
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet31994A —1 August 2004
Table 27. Acronyms (continued)
AbbreviationMeaning
VASVirtual Address Space
VPAVirtual Page Address
VGAVideo Graphics Adapter
USBUniversal Serial Bus
ZDBZero Delay Buffer
88Appendix B - Conventions and Abbreviations
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