AMD SC520 Service Manual

Élan™SC520 Microcontroller

User’s Manual

Order #22004B

© 2001 Advanced Micro Devices, Inc. All rights reserved.

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, order #21058, describe these

Élan™SC520 Microcontroller User’s Manual iii

iv Élan™SC520 Microcontroller User’s Manual

TABLE OF CONTENTS

PREFACE INTRODUCTION XXIII

Élan™SC520 Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Overview of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

AMD Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxv

Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxv

CHAPTER 1 ARCHITECTURAL OVERVIEW 1-1

1.1 Élan™SC520 Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.1 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.1 Industry-Standard x86 Architecture. . . . . . . . . . . . . . . . . . . . . . . .1-4

1.3.2 AMDebug™ Technology for Advanced Debugging . . . . . . . . . . . .1-4

1.3.3 Industry-Standard PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . .1-5

1.3.4 High-Performance SDRAM Controller. . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.5 ROM/Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.6 Flexible Address-Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.7 General-Purpose (GP) Bus Interface . . . . . . . . . . . . . . . . . . . . . .1-6

1.3.8 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.9 Integrated Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.10 JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.11 System Testing and Debugging Features . . . . . . . . . . . . . . . . . . .1-8

1.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.4.1 Smart Residential Gateway. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

1.4.2 Thin Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

1.4.3 Digital Set Top Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

1.4.4 Telephone Line Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

CHAPTER 2 PIN INFORMATION 2-1

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.3 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

CHAPTER 3 SYSTEM INITIALIZATION 3-1

3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Native Embedded Initialization Sequence . . . . . . . . . . . . . . . . . .3-1

3.1.2 BIOS Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

3.1.3 Memory-Mapped Configuration Region (MMCR) . . . . . . . . . . . . . 3-3

3.1.4 Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.5 Reset V ector and Reset Segment . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2 Configuring the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.3 Identifying the CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4 Setting the CPU Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.5 Configuring External GP Bus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.6 Configuring the Pin Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.7 Configuring the Programmable Address Region (PAR) Registers . . . . . . .3-8

3.7.1 Specifying Pages and Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

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Table of Contents

3.7.2 Address Region Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

3.7.2.1 Write-Protect Attribute . . . . . . . . . . . . . . . . . . . . . . . . .3-12

3.7.2.2 Cacheability Control Attribute . . . . . . . . . . . . . . . . . . .3-12

3.7.2.3 Code Execution Attribute . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.7.2.4 Performance Considerations . . . . . . . . . . . . . . . . . . . .3-12

3.7.3 PAR Register Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

3.7.4 External GP Bus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

3.7.4.1 Single Device (an A/D Converter) Using

One Chip Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

3.7.4.2 Single Device That Performs Its Own Decode. . . . . . .3-14

3.7.4.3 Multiple Devices On One Chip Select . . . . . . . . . . . . .3-14

3.7.5 PCI Bus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.7.5.1 VGA Controller on the PCI Bus . . . . . . . . . . . . . . . . . .3-15

3.7.5.2 Network Adapter for Remote Program Loading. . . . . .3-16

3.7.6 External ROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.7.6.1 Boot ROM Device Mapping for BIOS Shadowing . . . .3-17

3.7.6.2 Two Banks of Flash for an Execute-In-Place (XIP)

Operating System . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.7.7 SDRAM Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.7.7.1 Setting Up DMA Buffers. . . . . . . . . . . . . . . . . . . . . . . .3-18

3.7.7.2 Write-Protected Code Segments. . . . . . . . . . . . . . . . . 3-18

3.8 Configuring the Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19

3.8.1 Edge-Sensitive or Level-Triggered Interrupts . . . . . . . . . . . . . . . 3-19

3.8.2 Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.8.3 Interrupt Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20

3.9 Configuring the Programmable I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . .3-20

3.10 Configuring the PCI Host Bridge and Arbitration . . . . . . . . . . . . . . . . . . .3-20

3.11 Disabling Internal Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21

CHAPTER 4 SYSTEM ADDRESS MAPPING 4-1

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

4.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3.1 Programming External Memory, Buses, and Chip Selects . . . . . .4-4

4.3.2 Programmable Address Region (PAR) Registers . . . . . . . . . . . . .4-5

4.3.3 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

4.3.3.1 SDRAM Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

4.3.3.2 ROM/Flash Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

4.3.3.3 GP Bus Memory Space . . . . . . . . . . . . . . . . . . . . . . . . .4-9

4.3.3.4 PCI Bus Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.3.3.5 Memory-Ma pped Config uration Regi on (M MCR)

Registers Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

4.3.4 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.3.4.1 Configuration Base Address (CBAR) Register . . . . . .4-11

4.3.4.2 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.3.4.3 PCI I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12

4.3.4.4 PC/AT-Compatible I/O Peripherals Region. . . . . . . . . . 4-13

4.3.4.5 GP Bus I/O Region . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.3.5 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-15

4.3.5.1 Configuring ROM/Flash Space . . . . . . . . . . . . . . . . . .4-15

4.3.5.2 Configuring SDRAM Address Space . . . . . . . . . . . . . .4-15

4.3.5.3 Configuring GP Bus Peripheral Space. . . . . . . . . . . . .4-16

4.3.5.4 Configuring the Élan™SC520 Microcontroller

for Windows® Compatibility. . . . . . . . . . . . . . . . . . . . .4-17

4.3.5.5 Configuring PCI Bus Devices. . . . . . . . . . . . . . . . . . . .4-18

4.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

4.3.7 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

4.4 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

vi Élan™SC520 Microcontroller User’s Manual

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CHAPTER 5 CLOCK GENERATION AND CONTROL 5-1

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

5.3.1 Clock Pin Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.2 Selecting a Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.2.1 Running the Élan™SC520 Microcontroller

at 33.333 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.3.3 Bypassing Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

5.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.5.1 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.5.1.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.5.1.2 PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

5.5.1.3 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.5.1.4 ROM/Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

5.5.1.5 GP Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.5.1.6 GP-DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.5.1.7 Programmable Interval Timer. . . . . . . . . . . . . . . . . . . . . 5-8

5.5.1.8 General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.5.1.9 Software Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.5.1.10 Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.5.1.11 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.5.1.12 UART Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.5.1.13 Synchronous Serial Interface. . . . . . . . . . . . . . . . . . . . .5-8

5.5.2 Using the CLKTIMER[CLKTEST] Pin . . . . . . . . . . . . . . . . . . . . . .5-9

5.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

CHAPTER 6 RESET GENERATION 6-1

6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

6.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3

6.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.5.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4

6.5.2 System Reset with SDRAM Retention . . . . . . . . . . . . . . . . . . . . . 6-6

6.5.3 Soft CPU Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

6.5.4 GP Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5.5 PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

6.5.6 RTC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

6.5.7 Determining Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.5.8 CPU A20 Gate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.5.9 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.5.10 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.5.11 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

6.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

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CHAPTER 7 Am5X86® CPU 7-1

7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

7.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.4.1 Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.4.2 Cache Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4

7.4.3 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

7.4.5 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

7.5 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.5.1 Hard CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

7.5.2 Soft CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

CHAPTER 8 SYSTEM ARBITRATION 8-1

8.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

8.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.4.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.4.1.1 Nonconcurrent Arbitration Mode . . . . . . . . . . . . . . . . . . 8-3

8.4.1.2 Concurrent Arbitration Mode . . . . . . . . . . . . . . . . . . . . .8-4

8.4.2 CPU Bus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.4.2.1 CPU Arbitration Protocol . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.4.2.2 CPU Cache Snooping . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

8.4.2.3 Accessing the PCI Host Bridge Target. . . . . . . . . . . . . . 8-6

8.4.2.4 GP Bus DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . .8-7

8.4.2.5 Arbitration During Clock Speed Changes . . . . . . . . . . .8-7

8.4.3 PCI Bus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.4.3.1 PCI Bus Arbitration Protocol . . . . . . . . . . . . . . . . . . . . .8-8

8.4.3.2 Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10

8.4.3.3 Rearbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.4.4 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.4.4.1 CPU Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.4.4.2 CPU Bus Cache Write-Back . . . . . . . . . . . . . . . . . . . . 8-12

8.4.4.3 CPU-to-PCI Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14

8.4.4.4 PCI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

8.4.4.5 PCI Bus Arbitration Parking . . . . . . . . . . . . . . . . . . . . . 8-16

8.4.4.6 Nonconcurrent Mode Arbitration . . . . . . . . . . . . . . . . .8-18

8.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.4.6 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.4.7 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20

8.4.7.1 Simple Rotating Priority Latency . . . . . . . . . . . . . . . . .8-20

8.4.7.2 High-Priority Queue Latency . . . . . . . . . . . . . . . . . . . .8-21

8.4.7.3 Low-Priority Queue Latency. . . . . . . . . . . . . . . . . . . . .8-21

8.4.7.4 CPU Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21

8.4.7.5 Nonconcurrent Arbitration Mode Latency . . . . . . . . . . 8-21

8.4.7.6 Concurrent Arbitration Mode Latency . . . . . . . . . . . . . 8-22

8.4.7.7 Concurrent Arbitration Mode Bus Parking Latency . . .8-22

8.5 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

CHAPTER 9 PCI BUS HOST BRIDGE 9-1

9.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2

9.3.1 PCI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.3.1.1 Running the Élan™SC520 Microcontroller

at 33.333 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

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9.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

9.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.5.1 Unsupported PCI Bus Functions . . . . . . . . . . . . . . . . . . . . . . . . .9-8

9.5.1.1 Unsupported PCI Bus Configuration Registers . . . . . . . 9-9

9.5.2 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9

9.5.2.1 Generating PCI Bus Configuration Cycles. . . . . . . . . .9-10

9.5.3 Élan™SC520 Mic roco nt ro lle r ’s Host Bridge as PCI Bus Master . 9-11

9.5.3.1 Write Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11

9.5.3.2 Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12

9.5.3.3 Delayed Transaction Support. . . . . . . . . . . . . . . . . . . . 9-12

9.5.3.4 Host Bridge Master Bus Cycles. . . . . . . . . . . . . . . . . .9-12

9.5.4 Élan™SC520 Microcontroller’s Host Bridge as PCI Bus Target . .9-18

9.5.4.1 PCI Host Bridge Target Address Space. . . . . . . . . . . . 9-18

9.5.4.2 PCI Bus Command Support . . . . . . . . . . . . . . . . . . . . 9-19

9.5.4.3 DEVSEL

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19

9.5.4.4 Delayed Transaction Support. . . . . . . . . . . . . . . . . . . . 9-19

9.5.4.5 Address FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-20

9.5.4.6 PCI Host Bridge FIFOs and Prefetching . . . . . . . . . . .9-20

9.5.4.7 Burst Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21

9.5.4.8 Maintaining Data Coherency . . . . . . . . . . . . . . . . . . . .9-21

9.5.4.9 PCI Host Bridge Target Bus Cycles. . . . . . . . . . . . . . . 9-22

9.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-27

9.5.6 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-28

9.5.6.1 Master Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

9.5.6.2 Target Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

9.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29

CHAPTER 10 SDRAM CONTROLLER 10-1

10.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

10.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

10.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.3.1 SDRAM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.3.2 SDRAM Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6

10.3.3 SDRAM Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8

10.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

10.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11

10.5.1 SDRAM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11

10.5.2 SDRAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.5.2.1 Supported SDRAM Devices. . . . . . . . . . . . . . . . . . . .10-13

10.5.2.2 Page Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-16

10.5.3 Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . .10-16

10.5.4 Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-17

10.5.5 SDRAM Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

10.5.5.1 Refresh Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

10.5.5.2 Drive-Strength Selection . . . . . . . . . . . . . . . . . . . . . . 10-19

10.5.5.3 Write Buffer Test Mode . . . . . . . . . . . . . . . . . . . . . . .10-19

10.5.5.4 Operation Mode Select . . . . . . . . . . . . . . . . . . . . . . . 10-20

10.5.6 SDRAM Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 10-20

10.5.6.1 CAS

10.5.6.2 RAS

10.5.6.3 RAS

10.5.6.4 RAS

10.5.6.5 Minimum RAS

Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20

Precharge (TRP) . . . . . . . . . . . . . . . . . . . . . . . .10-21

-to-CAS Delay (T

). . . . . . . . . . . . . . . . . . . . . 10-21

RCD

-to-RAS or Auto-Refresh-to-RAS (TRC) . . . . . . .10-21

(T

). . . . . . . . . . . . . . . . . . . . . . . . .10-22

RAS

10.5.7 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-22

10.5.7.1 SDRAM Burst Read Cycle. . . . . . . . . . . . . . . . . . . . .10-22

10.5.7.2 SDRAM Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . .10-23

10.5.7.3 ECC SDRAM Cycles . . . . . . . . . . . . . . . . . . . . . . . . .10-24

10.5.7.4 SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . .10-26

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10.5.7.5 SDRAM Mode Register Access Cycles . . . . . . . . . . .10-27

10.5.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

10.5.9 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

10.5.9.1 ECC Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28

10.5.9.2 Buffer Disabling During SDRAM Configuration . . . . .10-28

10.5.9.3 Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28

10.5.10 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

10.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29

10.6.1 Programmable Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29

10.6.2 SDRAM Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

10.6.2.1 Operation Mode Select . . . . . . . . . . . . . . . . . . . . . . . 10-30

10.6.2.2 NOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31

10.6.2.3 Precharge Command. . . . . . . . . . . . . . . . . . . . . . . . . 10-31

10.6.2.4 Auto Refresh Command . . . . . . . . . . . . . . . . . . . . . .10-31

10.6.2.5 Mode Register Programming. . . . . . . . . . . . . . . . . . .10-31

10.6.3 Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-32

10.6.4 SDRAM Sizing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32

10.6.4.1 Determining the Number of Columns

for an External Bank . . . . . . . . . . . . . . . . . . . . . . . . .10-33

10.6.4.2 Determining the Number of Internal Banks . . . . . . . . 10-34

10.6.4.3 Determining the True External Bank Ending Address 10-35

CHAPTER 11 WRITE BUFFER AND READ BUFFER 11-1

11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

11.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2

11.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4

11.5.1 Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.5.1.1 Write Buffer Disabled. . . . . . . . . . . . . . . . . . . . . . . . . .11-5

11.5.1.2 Write Buffer Enabled . . . . . . . . . . . . . . . . . . . . . . . . . .11-5

11.5.1.3 Write Buffer Watermark . . . . . . . . . . . . . . . . . . . . . . . .11-9

11.5.2 Read Buffer and the Read-Ahead Feature . . . . . . . . . . . . . . . .11-10

11.5.2.1 Read-Ahead Feature Disabled. . . . . . . . . . . . . . . . . .11-10

11.5.2.2 Read-Ahead Feature Enabled . . . . . . . . . . . . . . . . . . 11-10

11.5.3 DMA Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

11.5.4 PCI Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

11.5.4.1 Write Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

11.5.4.2 Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

11.5.5 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

11.5.6 SDRAM Bandwidth Improvements . . . . . . . . . . . . . . . . . . . . . .11-13

11.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15

CHAPTER 12 ROM/FLASH CONTROLLER 12-1

12.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

12.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2

12.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.3.1 Voltage Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

12.5.1 ROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

12.5.1.1 Supported Device Types . . . . . . . . . . . . . . . . . . . . . . .12-6

12.5.2 ROM Control and Timing Configuration . . . . . . . . . . . . . . . . . . . 12-7

12.5.2.1 ROM Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.2.2 ROM Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.2.3 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.2.4 Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8

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12.5.3 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-9

12.5.3.1 Single CPU Read Access . . . . . . . . . . . . . . . . . . . . . . 12-9

12.5.3.2 Page-Mode Read Access . . . . . . . . . . . . . . . . . . . . . 12-10

12.5.3.3 Cache-Line Fill. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11

12.5.3.4 Writing to Flash Devices . . . . . . . . . . . . . . . . . . . . . . 12-11

12.5.4 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.5.4.1 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12

12.5.4.2 Programming Flash Memory . . . . . . . . . . . . . . . . . . .12-12

12.5.5 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-13

12.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14

CHAPTER 13 GENERAL-PURPOSE BUS CONTROLLER 13-1

13.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

13.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.3.1 GP Bus Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.3.2 Voltage Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4

13.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6

13.5.1 Programmable Bus Interface Timing . . . . . . . . . . . . . . . . . . . . .13-7

13.5.1.1 Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . .13-7

13.5.1.2 Using GPRDY with Programmable Timing. . . . . . . . . . 13-8

13.5.1.3 Using GP Bus Echo Mode with Program ma ble Timing 13-8

13.5.2 I/O-Mapped and Memory-Mapped Device Support . . . . . . . . . .13-9

13.5.3 Chip Select Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

13.5.4 Data Sizing and Unaligned Accesses . . . . . . . . . . . . . . . . . . . . .13-9

13.5.5 Sharing the Address and Data Bus

13.5.6 GP Bus Echo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-10

13.5.7 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11

13.5.8 Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11

13.5.9 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-16

13.5.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

13.5.11 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

13.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-22

with the ROM/Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

13.5.8.1 Compatibility with Common ISA Devices. . . . . . . . . .13-11

13.5.8.2 Interfacing with a Super I/O Controller. . . . . . . . . . . .13-13

13.5.8.3 Interfacing with an AMD Enhanced

Serial Communications Controller (8 MHz) . . . . . . . . 13-14

13.5.9.1 8-Bit Data Access of an 8-Bit I/O Device . . . . . . . . . .13-16

13.5.9.2 16-Bit Data Access of a 16-Bit I/O Device . . . . . . . . . 13-17

13.5.9.3 16-Bit Data Access of an 8-Bit I/O Device . . . . . . . . .13-17

13.5.9.4 32-Bit Data Access of an 8-Bit I/O Device . . . . . . . . .13-18

13.5.9.5 32-Bit Data Access of a 16-Bit I/O Device . . . . . . . . . 13-18

13.5.9.6 8-Bit Data Access of a 16-Bit I/O Device . . . . . . . . . .13-19

13.5.9.7 GPIOCS16

13.5.9.8 Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-20

13.5.11.18/16-Bit GP Bus Width. . . . . . . . . . . . . . . . . . . . . . . .13-21

13.5.11.2Slow GP Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . .13-21

13.5.11.3Noncacheable GP Bus. . . . . . . . . . . . . . . . . . . . . . . .13-21

and GPMEMCS16 Timing. . . . . . . . . . . . 13-19

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CHAPTER 14 GP BUS DMA CONTROLLER 14-1

14.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.4.1 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4

14.4.2 Direct-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-6

14.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8

14.5.1 GP-DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8

14.5.1.1 GP-DMA Initiators . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-9

14.5.1.2 GP-DMA Channel Mapping . . . . . . . . . . . . . . . . . . . .14-10

14.5.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-10

14.5.2.1 Normal GP-DMA Mode . . . . . . . . . . . . . . . . . . . . . . .14-10

14.5.2.2 Enhanced GP-DMA Mode . . . . . . . . . . . . . . . . . . . . .14-11

14.5.3 Addressing GP-DMA Channels . . . . . . . . . . . . . . . . . . . . . . . .14-11

14.5.3.1 Addressing In Normal GP-DMA Mode. . . . . . . . . . . .14-11

14.5.3.2 Addressing In Enhanced GP-DMA Mode . . . . . . . . . 14-12

14.5.4 GP-DMA Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-12

14.5.4.1 Single Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

14.5.4.2 Demand Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . 14-12

14.5.4.3 Block Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . .14-13

14.5.4.4 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

14.5.4.5 Automatic Initialization Control. . . . . . . . . . . . . . . . . . 14-14

14.5.4.6 Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-15

14.5.4.7 Buffer Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15

14.5.5 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-16

14.5.5.1 GP Bus I/O to SDRAM. . . . . . . . . . . . . . . . . . . . . . . .14-16

14.5.5.2 GP-DMA Read with Cache Hit. . . . . . . . . . . . . . . . . .14-17

14.5.6 GP Bus Echo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-17

14.5.7 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-18

14.5.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18

14.5.9 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18

14.5.10 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18

14.5.10.1Nonpreemptive Latency. . . . . . . . . . . . . . . . . . . . . . .14-18

14.5.10.2Preemptive Latency . . . . . . . . . . . . . . . . . . . . . . . . . .14-19

14.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-19

14.6.1 Example Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19

14.6.1.1 Configuring an 8-Bit Channel

in Normal GP-DMA Mode . . . . . . . . . . . . . . . . . . . . .14-19

14.6.1.2 Configuring a 16-Bit Channel

in Normal GP-DMA Mode . . . . . . . . . . . . . . . . . . . . .14-20

14.6.1.3 Configuring an 8-Bit Channel

in Enhanced GP-DMA Mode . . . . . . . . . . . . . . . . . . . 14-20

14.6.1.4 Configuring a 16-Bit Channel

in Enhanced GP-DMA Mode . . . . . . . . . . . . . . . . . . . 14-21

CHAPTER 15 PROGRAMMABLE INTERRUPT CONTROLLER 15-1

15.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1

15.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-2

15.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

15.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7

15.5.1 Interrupt Flow Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7

15.5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-8

15.5.2.1 Hardware-Generated Interrupts. . . . . . . . . . . . . . . . . . 15-8

15.5.3 Interrupt Source Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-10

15.5.3.1 Polarity Inversion of Interrupt Requests. . . . . . . . . . .15-10

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15.5.3.2 PC/AT Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

15.5.3.3 Floating Point Errors . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

15.5.3.4 Disabling the Slave Controllers . . . . . . . . . . . . . . . . .15-13

15.5.4 Edge-Triggered or Level-Sensitive Interrupts . . . . . . . . . . . . . .15-13

15.5.5 Interrupt Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-13

15.5.6 Non-Maskable Interrupts and Routing . . . . . . . . . . . . . . . . . . .15-14

15.5.6.1 Sharing NMIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14

15.5.7 Priority Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

15.5.8 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-16

15.5.8.1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-16

15.5.8.2 PC/AT Configuration . . . . . . . . . . . . . . . . . . . . . . . . .15-18

15.5.9 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18

15.5.9.1 Interrupt Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-18

15.5.9.2 Disabling the Slave Controllers . . . . . . . . . . . . . . . . .15-19

15.5.9.3 Detecting Invalid Interrupt Requests . . . . . . . . . . . . .15-19

15.5.9.4 Floating Point Unit Error Handling . . . . . . . . . . . . . . . 15-19

15.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-20

CHAPTER 16 PROGRAMMABLE INTERVAL TIMER 16-1

16.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1

16.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1

16.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

16.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3

16.5.1 PIT Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3

16.5.2 PIT Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3

16.5.3 PIT Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-4

16.5.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-4

16.5.4.1 Mode 0: Interrupt on Te rminal Count . . . . . . . . . . . . . .16-4

16.5.4.2 Mode 1: Hardware-Retriggerable One-Shot . . . . . . . .16-4

16.5.4.3 Mode 2: Rate Generator . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.5.4.4 Mode 3: Square Wave Mode . . . . . . . . . . . . . . . . . . . . 16-5

16.5.4.5 Mode 4: Software-Triggered Strobe. . . . . . . . . . . . . . . 16-5

16.5.4.6 Mode 5: Hardware-Triggered Strobe . . . . . . . . . . . . . . 16-5

16.5.5 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6

16.5.5.1 Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6

16.5.5.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6

16.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

16.5.7 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

16.5.7.1 Using the PIT Clock Source in PC/AT-Compatible

Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6

16.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-7

CHAPTER 17 GENERAL-PURPOSE TIMERS 17-1

17.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1

17.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1

17.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3

17.5.1 GP Timer 0 and GP Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.5.2 GP Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4

17.5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4

17.5.3.1 Interrupt on Terminal Count Mode . . . . . . . . . . . . . . . .17-4

17.5.3.2 Hardware Retrigger Mode . . . . . . . . . . . . . . . . . . . . . .17-4

17.5.3.3 Alternate Compare Mode. . . . . . . . . . . . . . . . . . . . . . . 17-4

17.5.3.4 Square Wave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.5.3.5 Continuous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4

17.5.3.6 Prescaler Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

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17.5.4 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5

17.5.5 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5

17.5.5.1 Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5

17.5.5.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-6

17.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.5.7 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.5.7.1 Combining GP Timer Count Elements. . . . . . . . . . . . . 17-6

17.5.7.2 Reading the Cascaded 32-Bit Timer . . . . . . . . . . . . . . 17-6

17.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8

CHAPTER 18 SOFTWARE TIMER 18-1

18.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1

18.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1

18.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2

18.4.1 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3

18.5 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3

CHAPTER 19 WATCHDOG TIMER 19-1

19.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1

19.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1

19.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3

19.4.1 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3

19.4.1.1 Keyed Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3

19.4.1.2 Interrupt Request Generation . . . . . . . . . . . . . . . . . . . 19-4

19.4.1.3 System Reset Generation . . . . . . . . . . . . . . . . . . . . . . 19-4

19.4.1.4 Time-Out Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-4

19.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.4.3 AMDebug™ Technology Interface . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.4.4 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.5 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-6

CHAPTER 20 REAL-TIME CLOCK 20-1

20.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1

20.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1

20.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.3.1 Backup Battery Considerations . . . . . . . . . . . . . . . . . . . . . . . . .20-3

20.3.1.1 System with an External Backup Battery. . . . . . . . . . .20-3

20.3.1.2 System without an External Backup Battery . . . . . . . .20-4

20.3.2 Selecting and Interfacing a 32.768-kHz Crystal . . . . . . . . . . . . .20-5

20.3.3 Using an External RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-5

20.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

20.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-7

20.5.1 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-7

20.5.1.1 Configuring the Hour Format . . . . . . . . . . . . . . . . . . . . 20-7

20.5.1.2 Programming the Date and Time. . . . . . . . . . . . . . . . .20-8

20.5.1.3 Generating Periodic Interrupts. . . . . . . . . . . . . . . . . . .20-8

20.5.1.4 Using the Alarm Function . . . . . . . . . . . . . . . . . . . . . .20-9

20.5.1.5 Handling Year 2000 Issues . . . . . . . . . . . . . . . . . . . . . 20-9

20.5.2 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-9

20.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9

20.5.4 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10

20.5.4.1 Initializing the RTC Divider Chain . . . . . . . . . . . . . . . 20-10

20.5.4.2 Accessing the CMOS Memory. . . . . . . . . . . . . . . . . . 20-10

20.5.4.3 Legacy NMI Enable Bit Moved. . . . . . . . . . . . . . . . . .20-10

20.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-10

20.6.1 RTC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11

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CHAPTER 21 UART SERIAL PORTS 21-1

21.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1

21.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1

21.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

21.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5

21.5.1 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-6

21.5.1.1 16450-Compatible UART Mode. . . . . . . . . . . . . . . . . .21-6

21.5.1.2 16550-Compatible UART Mode. . . . . . . . . . . . . . . . . .21-7

21.5.2 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7

21.5.2.1 16450-Compatible UART Mode. . . . . . . . . . . . . . . . . .21-7

21.5.2.2 16550-Compatible UART Mode. . . . . . . . . . . . . . . . . .21-7

21.5.3 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8

21.5.3.1 Parity Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-8

21.5.3.2 Framing Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-8

21.5.3.3 Break Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-8

21.5.3.4 Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-8

21.5.4 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9

21.5.4.1 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9

21.5.4.2 Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.5.4.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9

21.5.5 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10

21.5.5.1 Transmit DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10

21.5.5.2 Receive DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10

21.5.6 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10

21.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

21.5.7.1 Serial Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .21-12

21.5.7.2 DMA Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12

21.5.7.3 Interrupt Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-13

21.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-13

CHAPTER 22 SYNCHRONOUS SERIAL INTERFACE 22-1

22.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

22.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

22.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

22.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

22.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3

22.5.1 Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3

22.5.1.1 Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3

22.5.1.2 Three-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

22.5.2 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

22.5.2.1 Bit Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

22.5.2.2 Clock Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

22.5.2.3 Clock Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

22.5.3 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

22.5.3.1 4-Bit Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-6

22.5.3.2 Burst, 16-Bit, and 32-Bit Cycles. . . . . . . . . . . . . . . . . .22-7

22.5.4 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-7

22.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

22.5.6 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-8

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CHAPTER 23 PROGRAMMABLE INPUT/OUTPUT 23-1

23.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1

23.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1

23.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-4

23.5.1 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-5

23.5.1.1 PIO Pins and Simple Input. . . . . . . . . . . . . . . . . . . . . .23-5

23.5.1.2 PIO Pins and Simple Output . . . . . . . . . . . . . . . . . . . .23-5

23.5.2 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-6

CHAPTER 24 SYSTEM TEST AND DEBUGGING 24-1

24.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1

24.2 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

24.2.1 Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-2

24.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

24.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-3

24.4.1 System Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.4.1.1 Pin Functions in System Test Mode. . . . . . . . . . . . . . .24-3

24.4.1.2 Using the System Test Mode Interface . . . . . . . . . . . .24-4

24.4.1.3 SDRAM Write Cycle in System Test Mode . . . . . . . . .24-4

24.4.1.4 SDRAM Read Cycle in System Test Mode . . . . . . . . .24-5

24.4.1.5 Tracing Transactions on the ROM Interface. . . . . . . . . 24-5

24.4.1.6 Tracing Transactions on the GP Bus Interface. . . . . . .24-6

24.4.2 Write Buffer Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-7

24.4.2.1 Using the Write Buffer Test Mode Interface . . . . . . . . .24-7

24.4.2.2 SDRAM Write Cycle in Write Buffer Test Mode . . . . . .24-8

24.4.2.3 SDRAM Read Cycle in Write Buffer Test Mode. . . . . .24-8

24.4.3 Other Debugging Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-10

24.4.3.1 Nonconcurrent Arbitration Mode . . . . . . . . . . . . . . . . 24-10

24.4.3.2 Echoing Integrated Peripheral Accesses

on the GP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-10

24.4.3.3 Summary of Additional System Debugg in g Features. 24-10

24.4.4 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11

24.4.5 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-11

24.5 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-12

CHAPTER 25 BOUNDARY SCAN TEST INTERFACE 25-1

25.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1

25.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1

25.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.3.1 JTAG Pin Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-2

25.5.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-3

25.5.1.1 Implemented Instructions. . . . . . . . . . . . . . . . . . . . . . .25-3

25.5.2 Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-5

25.5.2.1 Instruction Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-5

25.5.2.2 Bypass Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.5.2.3 Main Data Scan Path. . . . . . . . . . . . . . . . . . . . . . . . . .25-5

25.5.2.4 Serial Debug Port Data Register . . . . . . . . . . . . . . . .25-14

25.5.2.5 Device Identification Register . . . . . . . . . . . . . . . . . . 25-14

25.5.3 Test Access Port (TAP) Controller . . . . . . . . . . . . . . . . . . . . . .25-15

25.5.3.1 TAP Controller States. . . . . . . . . . . . . . . . . . . . . . . . . 25-15

25.5.4 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19

25.5.5 Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20

25.6 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20

xvi Élan™SC520 Microcontroller User’s Manual

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CHAPTER 26 AMDebug™ TECHNOLOGY 26-1

26.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-1

26.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2

26.3 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.3.1 Connecting the AMDebug™ Port . . . . . . . . . . . . . . . . . . . . . . . . 26-3

26.3.2 Mechanical Specifications for the Target Connector . . . . . . . . . .26-5

26.3.3 Locating the Connector on the Target System . . . . . . . . . . . . . .26-5

26.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-6

26.4.1 On-Chip Trace Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-7

26.4.2 Software Performance Profiling . . . . . . . . . . . . . . . . . . . . . . . . . 26-7

INDEX Index-1

Élan™SC520 Microcontroller User’s Manual xvii

Table of Contents

LIST OF FIGURES

Figure 1-1 Élan™SC520 Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-2 Élan™SC520 Microcontroller-Based Smart Residential Gateway

Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

Figure 1-3 Élan™SC520 Microcontroller-Based Thin Client Reference Design. . . . . . . . . . . . .1-11

Figure 1-4 Élan™SC520 Microcontroller-Based Digital Set Top Box Reference Design . . . . . .1-12

Figure 1-5 Élan™SC520 Microcontroller-Based Telephone Line Concentrator

Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13

Figure 2-1 Logic Diagram by Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2 Logic Diagram by Default Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 3-1 Initial Near Jump Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-2 Programmable Address Region (PAR) Register Format . . . . . . . . . . . . . . . . . . . . . . 3-10

Figure 3-3 Programmable Address Region (PAR) Register Worksheet . . . . . . . . . . . . . . . . . . . 3-11

Figure 4-1 Programmable Address Region (PAR) Register Format . . . . . . . . . . . . . . . . . . . . . . .4-6

Figure 4-2 System Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Figure 4-3 System I/O Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11

Figure 5-1 Clock Source Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Figure 5-2 System Clock Distribution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Figure 5-3 Bypassing the 32.768-kHz Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5

Figure 5-4 Bypassing the 33-MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Figure 5-5 Clock Routing for the CLKTEST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Figure 6-1 Reset Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

Figure 6-2 PRGRESET Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Figure 6-3 Power-On Reset Sequence of Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

Figure 7-1 Am5

86® CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2

x

Figure 8-1 System Arbitration Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Figure 8-2 Skipped Master Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5

Figure 8-3 CPU Bus Rotating Priority Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 8-4 External PCI Master Arbitration Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

Figure 8-5 Host Bridge Master Arbitration Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9

Figure 8-6 CPU Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11

Figure 8-7 CPU Bus Cache Write-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

Figure 8-8 CPU-to-PCI Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14

Figure 8-9 PCI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15

Figure 8-10 PCI Bus Concurrent Mode Arbitration Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16

Figure 8-11 Nonconcurrent Mode Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18

Figure 8-12 Simple Rotating Priority Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20

Figure 9-1 PCI Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Figure 9-2 Élan™SC520 Microcontroller Connection to an External PCI Bus Target. . . . . . . . . . 9-3

Figure 9-3 Élan™SC520 Microcontroller Connection to an External PCI Bus Master . . . . . . . . .9-4

Figure 9-4 Élan™SC520 Microcontroller SERR

and PERR Connection . . . . . . . . . . . . . . . . . . . 9-5

Figure 9-5 PCI Bus Clocking Example 1: Lightly Loaded System . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Figure 9-6 PCI Bus Clocking Example 2: Heavily Loaded System. . . . . . . . . . . . . . . . . . . . . . . . 9-6

Figure 9-7 PCI Configuration Address (PCICFGADR) Register . . . . . . . . . . . . . . . . . . . . . . . .9-10

Figure 9-8 CPU Read Cycle to the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

Figure 9-9 CPU Read Cycle to the PCI Bus with External Target Retry. . . . . . . . . . . . . . . . . . . 9-14

Figure 9-10 CPU Posted Write Cycle to the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

Figure 9-11 Am5

86 CPU Non-Posted Write Cycle to the PCI Bus . . . . . . . . . . . . . . . . . . . . . . .9-16

x

Figure 9-12 CPU Write Cycles to Internal PCI Bus Configuration Registers . . . . . . . . . . . . . . . .9-17

Figure 9-13 CPU Read Cycles from Internal PCI Bus Configuration Registers . . . . . . . . . . . . . .9-18

Figure 9-14 External PCI Bus Master Posted Write to SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . .9-23

Figure 9-15 External PCI Master SDRAM Read (Delayed Transaction). . . . . . . . . . . . . . . . . . . . 9-24

Figure 9-16 PCI Host Bridge Target Disconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26

Figure 10-1 SDRAM Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2

Figure 10-2 Detailed Block Diagram of SDRAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Figure 10-3 SDRAM Bank Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4

Figure 10-4 Example Configuration of a 168-Pin SDRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

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Figure 10-5 SDRAM Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7

Figure 10-6 Alternate SDRAM Clock Generation with External Clock Driver. . . . . . . . . . . . . . . .10-7

Figure 10-7 SDRAM Burst Read Cyc l e (R ea d- Ahe ad Feature Disabled) (Pa ge Mis s / Page Hit). . 10-22

Figure 10-8 SDRAM Write Cycle (Write Buffer and ECC Disabled) (Page Miss/page Hit) . . . . . .10-23

Figure 10-9 SDRAM CPU Burst Write (Write Buf fer and ECC Disabled) (Page Miss/P ag e H it ). .10-24

Figure 10-10 SDRAM Burst Read Cycle with ECC Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25

Figure 10-11 SDRAM Read-Modify-Write Cycl e (for Data Write) with ECC Enabled (Page Hit). . . 10-26

Figure 10-12 SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

Figure 10-13 SDRAM Mode Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

Figure 11-1 Write Buffer and Read Buffer Block Diagram (SDRAM Subsystem) . . . . . . . . . . . . .11-2

Figure 11-2 Write Buffer and Read Buffer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3

Figure 11-3 Write Buffer Merging Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7

Figure 11-4 Write Buffer Collapsing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Figure 11-5 Write Buffer Read-Merging Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

Figure 11-6 Bus Thrashing with Write Buffer Disabled and Enabled . . . . . . . . . . . . . . . . . . . . .11-14

Figure 12-1 ROM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

Figure 12-2 Voltage Isolation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

Figure 12-3 Page-Mode ROM: Fetching Four Words from a 16-Bit ROM. . . . . . . . . . . . . . . . . . . 12-6

Figure 12-4 Non-Page-Mode ROM: Fetching Four Words from a 16-Bit ROM. . . . . . . . . . . . . . .12-8

Figure 12-5 Page-Mode ROM: Fetching Four Doublewords (Aligned) from a 32-Bit ROM. . . . . . 12-8

Figure 12-6 Page-Mode ROM: Fetching Four Doublewords (Unaligned) from an 8-Bit ROM. . . . 12-8

Figure 12-7 Multiple Accesses: Data Amounts Smaller than One Doubleword (2 Bytes)
Figure 12-8 Page Access for Fetching Four Doublewords from a 32-Bit ROM

Figure 12-9 Page Access for Fetching Two Doublewords from a 16-Bit ROM . . . . . . . . . . . . . . 12-11

Figure 12-10 Cache-Line Fill (Fetching Four Doublewords from a 32-Bit ROM). . . . . . . . . . . . . .12-11

Figure 12-11 Word Write Cycle to Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12

Figure 13-1 GP Bus Controller System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2

Figure 13-2 Example: Using an External Data Buffer to Address Excess Loading . . . . . . . . . . .13-4

Figure 13-3 Example: Using a Voltage Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-5

Figure 13-4 GP Bus Timing Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8

Figure 13-5 Élan™SC520 Microcontroller Interfacing with a Super I/O Controller . . . . . . . . . . .13-13

Figure 13-6 Timing Diagram of a Super I/O Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-14

Figure 13-7 Élan™SC520 Microcontroller Interfacing with an Am85C30. . . . . . . . . . . . . . . . . .13-15

Figure 13-8 Timing Diagram of an Am85C30 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

Figure 13-9 8-Bit Data Access of an 8-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-16

Figure 13-10 16-Bit Data Access of a 16-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

Figure 13-11 16-Bit Data Access of an 8-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

Figure 13-12 32-Bit Data Access of an 8-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

Figure 13-13 32-Bit Data Access of a 16-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

Figure 13-14 8-Bit Data Access of a 16-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19

Figure 13-15 16-Bit Access of a 16-Bit I/O Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-20

Figure 13-16 GPRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

Figure 14-1 GP-DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Figure 14-2 Master and Slave Core Cascading Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

Figure 14-3 GP-DMA Read Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

Figure 14-4 GP-DMA Write Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14

Figure 14-5 GP-DMA Verify Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14

Figure 14-6 GP-DMA Read in Demand Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-16

Figure 14-7 GP-DMA Read Transfer with Cache Hit (Write-Back Cache) . . . . . . . . . . . . . . . . . 14-17

Figure 15-1 Programmable Interrupt Controller (PIC) Block Diagram . . . . . . . . . . . . . . . . . . . . .15-3

Figure 15-2 Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-9

Figure 15-3 Interrupt Source Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-11

Figure 15-4 NMI Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15

Figure 16-1 Programmable Interval Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-2

Figure 17-1 General-Purpose Timers Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

Figure 18-1 Software Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1

from an 8-Bit ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

(Burst Sequence: 2-1-1-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10

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Figure 19-1 Watchdog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2

Figure 20-1 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

Figure 20-2 RTC Voltage Monitor Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

Figure 20-3 Circuit with Backup Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

Figure 20-4 Circuit without Backup Battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-5

Figure 21-1 UART Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

Figure 21-2 UART Frame Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5

Figure 21-3 UART Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5

Figure 22-1 SSI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

Figure 22-2 SSI Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4

Figure 22-3 SSI Simultaneous Transmit and Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4

Figure 22-4 SSI Three-Pin Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4

Figure 22-5 SSI Typical Half-Duplex Communication, Non-Inverted Phase and Clock Modes. . . 22-4

Figure 22-6 SSI Clock Phase and Clock Idle State: Effects on Data . . . . . . . . . . . . . . . . . . . . . . 22-6

Figure 22-7 SSI 4-Bit Read Cycle: Full-Duplex, Non-Inverted Phase, Non-Inverted Clock . . . . .22-6

Figure 22-8 SSI Back-to-Back Transactions for Full-duplex,

Microwire-Compatible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

Figure 22-9 SSI Timing: TC_INT and BSY_STA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

Figure 23-1 PIO Signal Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2

Figure 24-1 System Test Mode Timing During a SDRAM Write Cycle (Page Hit) . . . . . . . . . . . . 24-5

Figure 24-2 System Test Mode Timing During an SDRAM Read Cycle (Page Miss). . . . . . . . . .24-5

Figure 24-3 Write Buffer Test Mode Timing During an SDRAM Write Cycle (Page Hit). . . . . . . . 24-8

Figure 24-4 Write Buffer Test Mode Timing During a SDRAM Read Cycle (Page Miss) . . . . . . .24-9

Figure 25-1 Logical Structure of Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1

Figure 25-2 Serial Debug Port Data Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14

Figure 25-3 Device Identification Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-14

Figure 25-4 Test Access Port Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-15

Figure 25-5 Test Logic Operation: Data Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-19

Figure 25-6 Test Logic Operation: Instruction Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-20

Figure 26-1 AMDebug™ Technology Software Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2

Figure 26-2 12-Pin Connector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4

Figure 26-3 20-Pin Serial Connector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-4

Figure 26-4 Mechanical Specifications for AMDebug™ Technology Target Connector . . . . . . . .26-5

Figure 26-5 Locating the Target Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-6

xx Élan™SC520 Microcontroller User’ s Manual

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LIST OF TABLES

Table 0-1 Documentation Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxv

Table 2-1 Signal Descriptions Table Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

Table 2-2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

Table 3-1 CPUID Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Table 3-2 Example PAR Programming: Single Device Using One Chip Select. . . . . . . . . . . . .3-14

Table 3-3 Example PAR Programming: Single Device That Performs Its Own Decode . . . . . .3-14

Table 3-4 Example PAR Programming: Multiple Devices on One Chip Select . . . . . . . . . . . . .3-14

Table 3-5 Example PAR Programming: VGA Controller on the PCI Bus. . . . . . . . . . . . . . . . . . 3-15

Table 3-6 Example PAR Programming: COM3 with VGA Present on the PCI Bus . . . . . . . . . . 3-16

Table 3-7 Example PAR Programming: Network Adapter for Remote Program Loading . . . . .3-16

Table 3-8 Example PAR Programming: Boot ROM Device Mapping for BIOS Shadowing . . . .3-17

Table 3-9 Example PAR Programming: First Bank of Flash for XIP Operating System. . . . . . . 3-17

Table 3-10 Example PAR Programming: Second Bank of Flash for XIP Operating System . . . .3-18

Table 3-11 Example PAR Programming: Setting Up DMA Buffers . . . . . . . . . . . . . . . . . . . . . . .3-18

Table 3-12 Example PAR Programming: Write-Protected Code Segments . . . . . . . . . . . . . . . . 3-19

Table 4-1 Address Decoding Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-2 Address Decoding Registers—Direct-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

Table 4-3 Bus Master Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

Table 4-4 Memory and I/O Space Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-5 PC/AT Peripherals I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Table 5-1 Clock Start-up and Lock Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

Table 5-2 Clock Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Table 5-3 Timing Error as It Translates to Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Table 5-4 Clock Control Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Table 6-1 Reset Generation Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-2 Reset Generation Registers—Direct-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-3 Élan™SC520 Microcontroller Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 6-4 States of Cores after System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5

Table 7-1 Am5
Table 7-2 Am5

86® CPU Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

x

86® CPU Registers—Direct-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

x

Table 7-3 Cache Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4

Table 8-1 System Arbitration Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

Table 9-1 PCI Host Bridge Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Table 9-2 PCI Host Bridge Registers—Direct-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8

Table 9-3 PCI Host Bridge Registers—PCI Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8

Table 10-1 SDRAM Clock Loading Estimates Based on Device Width. . . . . . . . . . . . . . . . . . . . 10-6

Table 10-2 Estimated Capacitance (4-Bit SDRAM Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

Table 10-3 Estimated Capacitance (8-Bit SDRAM Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

Table 10-4 Estimated Capacitance (16-Bit SDRAM Devices). . . . . . . . . . . . . . . . . . . . . . . . . . .10-9

Table 10-5 Estimated Capacitance (32-Bit SDRAM Devices). . . . . . . . . . . . . . . . . . . . . . . . . . .10-9

Table 10-6 SDRAM Controller Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . .10-10

Table 10-7 Address Mapping to MAx Signals for SDRAM Devices. . . . . . . . . . . . . . . . . . . . . . 10-12

Table 10-8 SDRAM Devices Supported with Column Boundary Specification . . . . . . . . . . . . . 10-13

Table 10-9 Column Address Configuration Settings for SDRAM. . . . . . . . . . . . . . . . . . . . . . . . 10-15

Table 10-10 SDRAM Page Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

Table 10-11 SDRAM Refresh Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-18

Table 10-12 Load Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31

Table 11-1 SDRAM Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Table 11-2 SDRAM Buffer Control Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Table 12-1 ROM/Flash Data Bus Connection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

Table 12-2 ROM Signals Shared with Other Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

Table 12-3 ROM Controller Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

Table 12-4 Example: ROM Access Timing and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

Table 12-5 Accesses and ROM Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-9

Table 12-6 CFGx Pinstrap Configuration Options for BOOTCS

. . . . . . . . . . . . . . . . . . . . . . . .12-14

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Table 13-1 GP Bus Signals Shared with Other Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

Table 13-2 GP Bus Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-5

Table 13-3 GP Bus Echo Mode Minimum Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9

Table 13-4 Cross-Reference Table of ISA Signals and GP Bus Signals. . . . . . . . . . . . . . . . . .13-12

Table 13-5 Example Super I/O Controller Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13

Table 13-6 Example AMD Enhanced Serial Communications Controller Interface Timing . . . . 13-15

Table 13-7 Differentiating Upper/Lower Byte Access of 16-Bit Devices . . . . . . . . . . . . . . . . . . 13-19

Table 13-8 Dynamic Bus Sizing Override of Programmed Data Width . . . . . . . . . . . . . . . . . . .13-20

Table 14-1 GP-DMA Signals Shared with Other Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4

Table 14-2 GP-DMA Controller Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . .14-4

Table 14-3 GP-DMA Controller Registers—Direct-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-7

Table 14-4 Supported GP-DMA Initiator/Target Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

Table 14-5 GP-DMA Channel Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

Table 14-6 8-Bit GP-DMA Channel Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

Table 14-7 16-Bit GP-DMA Channel Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

Table 14-8 GP-DMA Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-16

Table 15-1 Programmable Interrupt Controller Signals Shared with Other Interfaces. . . . . . . . .15-2

Table 15-2 Programmable Interrupt Controller Registers—Memory-Mapped. . . . . . . . . . . . . . . 15-4

Table 15-3 Programmable Interrupt Controller Registers—Direct-Mapped. . . . . . . . . . . . . . . . . 15-6

Table 15-4 PC/AT Interrupt Channel Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-12

Table 16-1 Programmable Interval Timer Signals Shared with Other Interfaces. . . . . . . . . . . . . 16-1

Table 16-2 Programmable Interval Timer Configuration Registers—Memory-Mapped. . . . . . . .16-2

Table 16-3 Programmable Interval Timer Configuration Registers—Direct-Mapped . . . . . . . . .16-3

Table 16-4 PIT Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

Table 16-5 PIT External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

Table 17-1 General-Purpose Timer Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . 17-1

Table 17-2 General-Purpose Timer Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . .17-2

Table 17-3 GP Timers Internal Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5

Table 17-4 GP Timers External Clock Sources (Using a 33.333 MHz Crystal). . . . . . . . . . . . . .17-6

Table 18-1 Software Timer Configuration Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . 18-2

Table 19-1 Watchdog Timer Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2

Table 19-2 Watchdog Timer Time-Out Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

Table 20-1 Real-Time Clock Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-6

Table 20-2 Real-Time Clock Registers—Direct-Mapped. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-6

Table 20-3 Real-Time Clock Registers—RTC Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-6

Table 20-4 Using RATE_SEL to Specify a Periodic Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . .20-8

Table 21-1 UART Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

Table 21-2 Connection of DTE to DTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

Table 21-3 UART Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

Table 21-4 UART Registers—Direct-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4

Table 21-5 Baud Rates, Divisors, and Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9

Table 21-6 UART Interrupt Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

Table 21-7 Serial Port Interrupt and Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-12

Table 22-1 Synchronous Serial Interface Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . 22-2

Table 23-1 PIO Signals Shared with Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-3

Table 23-2 PIO Registers—Memory-Mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

Table 23-3 PIO Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

Table 24-1 System Test and Debugging Signals Shared with Other Interfaces . . . . . . . . . . . . .24-2

Table 24-2 System Test and Debugging Registers—Memory-Mapped. . . . . . . . . . . . . . . . . . . .24-2

Table 24-3 WBMSTR2–WBMSTR0 Pin Definition During Write Buffer Write Cycles . . . . . . . . . 24-8

Table 24-4 WBMSTR2–WBMSTR0 Pin Definition During SDRAM Read Cycles . . . . . . . . . . . . 24-9

Table 25-1 Chip Test and Debugging Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-2

Table 25-2 Test Access Port Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

Table 25-3 Main Data Scan Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

Table 26-1 AMDebug™ Technology Connector Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

xxii Élan™SC520 Microcontroller User’s Manual

PREFACE

INTRODUCTION

Élan™SC520 MICROCONTROLLER

The Élan™SC520 microcontroller is a full-featured microcontroller developed for the
general embedded market. The ÉlanSC520 microcontr oller combines a 32-bit, low-v oltage

86® CPU with a complete set of integrat ed peripherals suitable f or both real-time and

Am5

x

PC/AT-compatible embedded applications.

PURPOSE OF THIS MANUAL

This manual describes the tech nical features and programming interf ace of the ÉlanSC520
microcontroller.

Intended Audience

The

Élan™SC520 Microcontroller User’s Manual

software and hardwar e eng ineers and system architects who are designing or are

considering designing systems based on the ÉlanSC520 microcontroll er.

, order #22004, is intend ed for computer

Overview of this Manual

The manual is organized into the following chapters:

■ Chapter 1 includes an architectural o verview of the ÉlanSC520 microcontroller, al ong

with applications diagrams.

■ Chapter 2 describes the signals and pins of the ÉlanSC520 microcontroller. Logic

diagrams showing def ault s and pins with shared si gnals are also f ound in this chapter.

Detailed pin state information is available in the

.

Sheet

■ Chapter 3 provides an overview of system initialization and shows example

configurations.

■ Chapter 4 describes the system address mapping on the ÉlanSC520 microcontroller.

■ Chapter 5 provides information on cloc k generati on and control.

■ Chapter 6 describes the reset sources and states of the ÉlanSC520 microcontroller.

■ Chapter 7 includes an overview of the integrated Am5

information about the CPU, consult the references provided in this chapter.

■ Chapter 8 describes the system arbiter on the ÉlanSC520 microcontroller, which

includes a CPU bus arbiter and a PCI bus arbiter.

■ Chapter 9 describes the PCI bus host bridge implemented on the ÉlanSC520

microcontroller.

Élan™SC520 Microcontroller Data

86 CPU. For additional

x

■ Chapter 10 describes the synchronous DRAM (SDRAM) controller.

■ Chapter 11 describes the SDRAM write buffer and read buffer with read-ahead

feature .

■ Chapter 12 describes the ROM/Flash controller.

Élan™SC520 Microcontroller User’s Manual xxiii

Introduction

■ Chapter 13 describes the programmable general-purpose (GP) b us interface included

on the ÉlanSC520 microcontroller.

■ Chapter 14 describes the GP bus DMA controller.

■ Chapter 15 describes the programmable interrupt controller (PIC), which includes

three interrupt controllers.

■ Chapter 16 describes the programmable interval timer (PIT) , which includes three

timers.

■ Chapter 17 describes the three general-purpose (GP) timers included on the

ÉlanSC520 microcontroller.

■ Chapter 18 describes the software timer that eases the task of keeping system time.

■ Chapter 19 describes the watchdog timer used to guard against runaway software.

■ Chapter 20 describes the real-time clock (RTC) and RTC voltage monitor included

on the ÉlanSC520 microcontroller.

■ Chapter 21 describes the two UART serial ports.

■ Chapter 22 describes the synchronous serial interface (SSI).

■ Chapter 23 describes the 32 programmable input/output (PIO) pins on the

ÉlanSC520 microcontroller.

■ Chapter 24 is a summary of the system test features found on the ÉlanSC520

microcontroller.

■ Chapter 25 describes the Joint Test Action Group (JTAG) (IEEE Std. 1149.1-1990)

boundary scan test interface features of the ÉlanSC520 microcontroller.

■ Chapter 26 provides an overview of AMDebug™ technology and the board

specifications necessary to utilize this capability, which is supported by third-party
FusionE86 vendors.

RELATED DOCUMENTS

The follo wing do cuments conta in addit ional i nformation that will be useful in designing an

embedded application based on the ÉlanSC520 microcontroller.

AMD Documentation

In addition to this manual, the documentation set for the ÉlanSC520 microcontroller includes
the following documents:

■

Élan™SC520 Microcontroller Register Set Manual

configuration registers requir ed to program the microcontroller.

■

Élan™SC520 Microcontroller Data Sheet

, order #22003, includes complete pin lists , pin

state tables, timing and thermal characteristics, and package dimensions for the

ÉlanSC520 microcontroller.

, order #22005, fully describes all the

Other information of interest:

■ The

■

■

xxiv Élan™SC520 Microcontroller User’s Manual

Am486® Microprocessor Software User’s Manual

complete instruction set for the integrated Am5

Am5x86® Microprocessor Family Data Sheet

86 CPU.

x

, order #19751

Am486® DX/DX2 Microprocessor Hardware Reference Manual

, order #18497, includes the

, order #17965

Introduction

■

E86 Family Products and Development Tools CD

, order #21058, provides a single­source multimedia tool f or customer e valuat ion of AMD products, as well as Fusion E86
partner tools and technologies that support the E86 family. Technical documentation is
included on the CD in PDF format.

To order literature, c ontact the nearest AMD sales of fice or c all the liter ature center at o ne
of the numbers listed on the back cover of this manual. In addition, t hese documents are
avail able in PDF form on the AMD web site. To access the web site, go to www.amd.com
and follow the Embedded Processor link for information about the E86 family.

Additional Information

The followi ng non-AMD d ocuments and sources provide additional information that may

be of interest to ÉlanSC520 microcontroller users:

■

PCI Local Bus Specification,

Group, 800-433-5177 (US), 503-693-6360 (International), www .pcisig.com.

■

IEEE Std 1149.1-1990 Standard Test Access P ort and Boundary-Scan Architecture,

(order #SH16626-NYF), Institute of Elect rical and Electronic Engineers, Inc., 800-678­4333, www.ieee.org.

■

PCI System Architecture

0-201-40993-3.

Revision 2.2, December 18, 1998, PCI Special Interest

, Mindshare, Inc., Reading, MA: Addison- Wesley, 1995, ISBN

■

ISA System Architecture

0-201-40996-8.

■

80486 System Architecture

0-201-40994-1.

■

The Indispensable PC Hardw a re Book

Addison-Wesley, 1995, ISBN 0-201-87697-3.

DOCUMENTATION CONVENTIONS

Table 0-1 lists the documentation conventions used throughout this manual.

Table 0-1 Documentation Notation

Notation Meaning
Reset Default Va lues

Default Value after a system reset
0Low
1 Active or High
x No value is guaranteed

, Mindshare, Inc., Reading, MA: Addison-Wesley , 1995, ISBN

, Mindshare, Inc., Reading, MA: Addison-Wesley , 1995, ISBN

, Hans-Peter Messmer, Wokingham, England:

?

Read/Write Attributes

R

Élan™SC520 Microcontroller User’s Manual xxv

Determined by sources external to the ÉlanSC520
microcontroller

The bit field is read-only. A write to the register at this bit field
has no effect. The contents may or may not be changed by
hardware.

Introduction

Table 0-1 Documentation Notation (Continued)

Notation Meaning

W

R/W

R/W!

RSV

RSV!

Reference Notation

MMCR offset 00h

The bit field is write-only. Reading this register at this bit field
does not return a meaningful value and has no side effects.

The bit field is read/write. Reading the register at this bit field
always returns the last value written. Reads have no side effects.

The bit field is read/write with conditions. The “!” indicates that
there are side effects to using this bit. For example, reading a
bit or register might not always return the last value written. Note
that both reads and writes can have side effects. If you see a “!”,
be sure to read the bit description and programming notes.

The bit field is reserved for internal test/debug or future
expansion. This bit field should be written to 0 for normal system
operation. This bit field always returns 0 when read.

The bit field is reserved for compatibility purposes. For example,
the bit field might be ignored during writes to maintain software
compatibility. If you see a “!”, be sure to read the bit description
and programming notes.

ÉlanSC520 microcontroller Memory-Mapped Configuration

Region (MMCR) offset register 00h
PCI index 00h PCI indexed register 00h
Port 00h Direct-mapped I/O register 00h
RTC index 00h RTC and configuration RAM indexed register 00h

Pin Naming

{ } Pin function during hardware reset
[ ] Alternative pin function selected by software configuration

ROMCS1

GPRESET

, hold A signal name in all lowercase indicates an internal signal.

ads
ROMCS2
ROMCSx

Numbers

b Binary number

–ROMCS1 Two ROM chip select signals

An overbar indicates that the signal assumes the logic Low state

when asserted.

The absence of an overbar indicates that the signal assumes

the logic High state when asserted.

Any of the two ROM chip select signals

d

xxvi Élan™SC520 Microcontroller User’s Manual

Decimal number

Decimal is the default radix

Introduction

Table 0-1 Documentation Notation (Continued)

Notation Meaning

h Hexadecimal number

Any of several legal values; e.g., using 0xF8h for the UART
x in register address

Transmit Holding register is either 02F8h or 03F8h, depending

on the UART

[X–Y]

33 MHz

General

field Bit field in a register (one or more consecutive and related bits)
can It is possible to perform an action if properly configured
will A certain action is going to occur

Set the ENB bit.

The bit field that consists of bits X through Y.

Example: The SB_ADDR[23–16] bit field.

Refers to the system clock frequency being used. This can be

either 33.000 MHz or 33.333 MHz. See the

Microcontroller User’s Manual

generation.

Write the ENB bit to 1.

for more information about clock

Élan™SC520

Note: The bit referred to is either in the register being described,

or the register is referred to explicitly in the surrounding text.

Clear the ENB bit.

Reset the ENB bit.

Change the ENB bit to 0. Usually a bit is cleared by writing a 0

to it; however, some bits are cleared by writing a 1.

Context-sensitive. Can refer either to resetting the bit to its

default value or to clearing the bit.

Élan™SC520 Microcontroller User’s Manual xxvii

Introduction

xxviii Élan™SC520 Microcontroller User’s Manual

CHAPTER

ARCHITECTURAL OVERVIEW

1

1.1 Élan™SC520 MICROCONTROLLER

The Élan™SC520 microcontroller is a full-featured microcontroller developed for the
general embedded market. The ÉlanSC520 microcontr oller combines a 32-bit, low-v oltage

86 CPU with a complete set of integ r at ed peripher als suitab l e for both real-time and

Am5

x

PC/AT-compatible embedded applications.
An integrated PCI host bridge, SDRAM controller , enhanced PC/A T -compatib le peripherals,

and advanced debuggi ng features provide the system designer with a wide range of on­chip resources, all owing support for legacy devi ces as well as ne w devices av ailable in t he
current PC marketplace.

Designed for medium- to high-performance applications in the telecommunicati ons, data
communications, and information appliance markets, the ÉlanSC520 microcontr oller is
particularly well suited for applicati ons requiring high throughput combined with low latency .

1.1.1 Distinctive Characteristics

■ Industry-standard Am5

cache

86® CPU with floating point unit (FPU) and 16- Kbyte write-back

x

– 100-MHz and 133-MHz operating frequencies
– Low-voltage operation (core V

– 5-V tolerant I/O (3.3-V output levels)

■ E86™ family of x86 embedded processors

– Part of a software-compatible family of microprocessors and microcontrollers well

supported by a wide variety of development tools

■ Integrated PCI host bridge controller leverages standard peripherals and software

– 33 MHz, 32-bit PCI bus Revision 2.2-compliant
– High-throughput 132-Mbyte/s peak transfer
– Supports up to five external PCI masters
– Integrated write-posting and read-buffering for high-throughput applications

■ Synchronous DRAM (SDRAM) controller

– Supports 16-, 64-, 128-, and 256-Mbit SDRAM.
– Supports 4 banks for a total of 256 Mbytes .
– Error Correction Code provides system reliability.
– Buffers improve read and write performance.

= 2.5 V)

CC

■ AMDebugÉ technology offers a lo w-cost solution for the advanced debugging

capabilities required by embedded designers.
– Allows instruction tracing during execution from the Am5

– Uses an enhanced JTAG port for low-cost debugging

Élan™SC520 Microcontroller User’s Manual 1-1

86 CPU’s internal cache

x

Architectural Overview

– Parallel debug port for high-speed data exchange during in-circuit emulation

■ General-purpose (GP) bus with progr ammable timing f or 8- and 16-bit de vices pro vides

good performance at very low cost.

■ ROM/Flash controller for 8-, 16-, and 32-bit devices

■ Enhanced PC/AT-compatible peripherals provide improved performance.

– Enhanced progr a mmable interrupt controller (PIC) prioritizes 22 interrupt levels (up

to 15 external sources) with flexible routing.

– Enhanced DMA controller includes double buffer chaining, extended address and

transfer counts, and flexible channel routing.

– Two 16550-compatible UARTs operate at baud rates up to 1.15 Mbit/s with optional

DMA interface.

■ Standard PC/AT-compatible peripherals

– Programmable inter val timer (P I T )
– Real-time clock (RTC) with battery backup capability and 114 bytes of RAM

■ Additional integrated peripherals

– Three general-purpose 16-bit timers provi de flexible cascading for 32-bit operation.
– Watchdog timer guards against runaway software.
– Software timer
– Synchronous serial interface (SSI) offers full-dupl ex or half-duplex operation.
– Flexible address decoding for programmable memory and I/O mapping and system

addressing configuration

■ 32 programmable input/output (PIO) pi ns

■ Native support for pSOS, QNX, R TXC , VxW orks, and Windows

■ Industry-standard BIOS support

1.2 BLOCK DIAGRAM

Figure 1-1 on page 1-3 illustrates the integr ated Am5x86 CPU, bus structure, and on- chip

peripherals of the ÉlanSC520 microcontroller. Three primary interfaces are provided:

■ A high-performance, 66-MHz 32-bit synchr onous DRAM (SDRAM) interface of up to 256

Mbytes is used for Am5
PCI bus masters and GP bus DMA initia tors. A high-perf ormance ROM/Flash interf ace
can also be connected to the SDRAM interface.

■ An industry-standard, 32-bit PCI bus is provided f or high bandwidth I/O peripherals such

as local area network controllers, synchronous communications controllers, and disk
storage controllers.

®

CE operating systems

86 CPU code executi on, as well as buffer st orage of external

x

■ A simple 8/16-bit, 33-MHz gener al-purpose bus (GP bus) provides a gl ueless connection

to lower bandwidth peripherals , and NVRAM, SRAM, ROM, or custom ASICs; supports
dynamic bus sizing and compatibility with many common ISA devices.

These three buses listed above are provided in all operating modes of the ÉlanSC520
microcontroller.

1-2 Élan™SC520 Microcontroller User’s Manual

Architectural Overview

In addition to these three primary interfaces , the ÉlanSC520 microco ntroller also contains
internal oscillator circuitry and phase lock ed loop (PLL) circuitry, requiring only two simple
crystals for virtually all system clock generation.

Diagrams showing how the ÉlanSC520 microcontroller can be used in various system
designs are included in “Applications” on page 1-8.

Figure 1-1 Élan™SC520 Microcontroller Block Diagram

Ç

Am5x86

AMDebug™

Technology and

JTAG

GP-DMA

Request and

Grant

CPU

Request

CPU Bus

Arbiter

PCI Bus

Arbiter

CPU

Bus Interface Unit



PCI

Master

Address

CPU Address Bus

CPU Data Bus

Data

CPU Bus Interface

FIFOs and FIFO

CPU Control/Status Bus

Control/Status

Control

Generation

PCI

Target

Clock

CPU Bus Interface

Address
Decode

Unit

GP-DMA
Controller

SDRAM

Controller

Read/Write Buffers

ROM/Flash

Controller

GP Bus

Controller

GP Bus

External GP Bus

Programmable

Interrupt Controlle r

Programmable

Interval Timer

Watchdog Timer

Real-Time Clock

CMOS RAM

General-Purpose

Timers

PCI Requests and Grants

Élan™SC520 Microcontroller

Software

Timer

16550 UART

16550 UART

PCI Bus

Synchronous Serial

Interface

Programmable I/O



Controls

PC/AT Compatibility

Logic

Élan™SC520 Microcontroller User’s Manual 1-3

Architectural Overview

1.3 ARCHITECTURAL OVERVIEW

The ÉlanSC520 microcontroller was designed to provide:

■ A balanced mix of high performance and low-cost interface mechanisms

■ A high-performance, industry-standard 32-bit PCI bus

■ Glueless interfaci ng to many 8- and 16-bit I/O peripherals and an 8- and 16-bit bus with

programmable timing

■ A cost-effective system architecture that meets a wide range of performance criteria

while retaining the lower cost of a 32-bit system

■ A high degree of leverage from present day hardware and software technologies

1.3.1 Industry-Standard x86 Architecture (Chapter 7)

The Am5x86 CPU in the ÉlanSC520 microcontroller utilizes the industry-standard x86
microprocessor instruction set that enables compatibility across a variety of performance
levels from the 16-bit Am186™ processors to the hig h-end AMD Athlon™ processor. Softwar e
written for the x86 architecture famil y is compatib le with the ÉlanSC520 microcontroll er.

Other benefits of the Am5

■ Improved time-to-market and easy software migrati on

■ Existing availability of multiple operating systems that directly support the x86

86 CPU include:

x

architecture. Whether the application requires a real-time operating system ( RTOS) or

®

one of the popular Microsoft

operating systems, the ÉlanSC520 microcontroller

provides consistent compatibility with many off-the-shelf operating systems.

■ Multiple sources of field-proven development tools

■ Integrated floating point unit (FPU) (compliant with ANSI/IEEE 754 standard)

■ 16-KByte unified cache configurable for either write-back or write-through cache mode

The Am5

86 CPU is described in Chapter 7.

x

1.3.2 AMDebug™ Technology for Advanced Debugging (Chapter 26)

The ÉlanSC520 microcontroller provi des support f or low-cost, full-featured, in-circuit
emulation capability. This in-circuit emulation support was developed at AMD specifically
to enable users to test and debug their software earlier in the design cycle . Utilizing this
capability, the software can be more ex tensiv ely e xer cised, and at ful l ex ecut ion speeds. I t
also allows tracing during execution from the Am5

AMDebug support provides the product des ign team with two different comm unication paths
on the ÉlanSC520 microcontroller, each of which is supported by pow erful debug tools from
third-party vendors in AMD’s FusionE86 program.

86 CPU’s internal cache.

x

■ Serial AMDebug technology uses a serial connection based on an enhanced JTAG

protocol and an ine xpensive 12-pin connector that can be placed on each board design.
This low-cost solution sat isfies the requirement of a large number of software de velopers.

■ Parallel AMDebug technology uses a parallel debug port to exchange commands and

data between the ÉlanSC520 microcontroller and the hos t. The higher pin count requires
that the extra si gnal pins be pro vided on a special bond-out pac kage of the ÉlanSC520
microcontroller, which is only made available to tool developers, such as in-circuit
emulator manufacturers. The parallel AMDebug port greatly simplifies the task of
supporting high speed data exchange.

1-4 Élan™SC520 Microcontroller User’s Manual

Architectural Overview

1.3.3 Industry-Standard PCI Bus Interface (Chapter 9)

The ÉlanSC520 microcontroller provi des a 33-MHz, 32-bit PCI bus Re vision 2.2-compliant
host bridge interface, including integrated write-posting and read-buffering capabilities
suitable for high-throughput applications. The PCI host bridge leverag es standard
peripherals and software. It also provides:

■ High throughput (132 Mbytes/s peak transfer rate)

■ Deep buffering and support for burst transactions from PCI bus masters to SDRAM

■ Flexib le arbitration mechanism

■ Support for up to five external PCI masters

1.3.4 High-Performance SDRAM Controller (Chapter 10)

The ÉlanSC520 microcontroller provi des an integrated SDRAM controller that supports
popular industry-standard synchronous DRAMs (SDRAM).

■ The SDRAM controller interfac es wit h SDRAM chips as well as wit h most standard

DIMMs to enable use of standard off-the-shelf memory components.

■ The SDRAM controller supports programmable ti ming options and provides the required

external cloc k.

■ Up to four 32-bit banks of SDRAM are supported with a maximum capacity of 256 Mbytes.

■ An important reliability-enhancing Error Correcti on Code (ECC) feature is built into the

SDRAM controller . The resultant inc rease in the memory content reliability enab les the
ÉlanSC520 microcontroller to be effectively utilized in applications that require more
reliable operat ion, such as communications environments.

■ The SDRAM controller contains a write buffer and read ahead buffer subsystem that

improves both write and read performance.

■ SDRAM refresh options allow the SDRAM contents to be maintained during reset.

1.3.5 ROM/Flash Controller (Chapter 12)

The ÉlanSC520 microcontroller provi des an integrated ROM controller for glueless
interfacin g to ROM and Flash de vices. The Éla nSC520 microcontrol ler supports two types
of interf aces to such devices—a simple interface via the GP b us for 8- and 16-bit devices ,
and an interface to the SDRAM memory data bus fo r higher performance 8-, 16-, and 32­bit devices.

The ROM/Flash controller:

■ Reduces system cost by gluelessly interfacing static memory with up to three ROM/

Flash chip selects

■ Supports execute-in-place (XIP) operating systems for applications that require

ex ecuting out of ROM or Flash memory instead of DRAM

■ Supports high-performance page-mode devices

1.3.6 Flexible Address-Mapping (Chapter 4)

In addition to the memory management unit (MMU) within the Am5x86 CPU core, the
ÉlanSC520 microcontroller provi des 16 Programmable Address Region (PAR) registers
that enable flexible placement of memory (SDRAM, ROM, Flash, SRAM, etc.) and
peripherals into the tw o address spac es of the Am5
I/O address space). The PAR hardware all ows designers to fle xibly c onfigure both address

Élan™SC520 Microcontroller User’s Manual 1-5

86 CPU (memory address space and

x

Architectural Overview

spaces and place memory and/or e xternal peripherals, as required b y the application. The
internal memory-mapped configuration registers space can also be remapped to
accommodate system requirements. PAR registers also allow control of important
attributes, suc h as cacheability , write protect ion, and code ex ecution protection fo r memory
resources.

1.3.7 General-Purpose (GP) Bus Interface (Chapter 13)

The ÉlanSC520 microcontroller includes a simple general-purpose (GP) bus that pro vides
programmable bus timing and allows the connection of 8/16-bit peripheral devices and
memory to the ÉlanSC520 microcontroller. The GP b us op erat es at 33 MHz, which of fers
good performance at a very low interface cost.

The ÉlanSC520 microcontroller p rovides up to eight chip selects f or external GP bus de vices
such as off-the-shelf I/O peripherals, custom ASICs, and SRAM or NVRAM. The GP bus
interface supports programmable timing and dynamic bus width and cycle stretching to
accommodate a wide variety of standard peripherals, such as UARTs, 10-Mbit LAN
controller chips and serial communi cati ons co ntroll er s. Up to four external DMA channels
provide fly-by DMA transfers between peripheral devices on the GP bus and system
SDRAM.

Internally, the GP bus is used to provide a full complement of int egr ated peripherals , such
as a DMA controller, programmable interrupt controller, timers, and UARTs, as described
in “Integrated P eripherals” on page 1-7. These internal peripherals are designed to operate
at the full clock rate of the GP bus. The internal peripherals can also be configured to
operate in PC/AT-compatible configuration, but are generally not restricted to this
configuration.

The ÉlanSC520 microcontroller provi des a way to view accesses to the int ernal peripherals
on the external GP bus for debugging purposes.

1.3.8 Clock Generation (Chapter 5)

The ÉlanSC520 microcontroller offers user-configurab le CPU cor e clock speed operation
at 100 or 133 MHz for different power/performance points depending on the application.

Not all ÉlanSC520 microcontroller devices support all CPU clock rates. The maximum
supported clock rate for a device is indicated by the part number printed on the package.
The clocking circui try can be programmed to run the devi ce at higher than the rated speeds .
However, if an ÉlanSC520 microcontroller is programmed to run at a higher clock speed
than that for which it is rated, then erroneous operation can result, and physical damage
to the device may occur.

The ÉlanSC520 microcontroller includes on-chip oscillators and PLLs, as well as most of
the required PLL loop filter components. The ÉlanSC520 microcontroller requires two
standard crystals, one for 32.768 kHz and one for 33 MHz. All the clocks required insi de
the ÉlanSC520 microcontroller are generated from these crystals. The ÉlanSC520
microcontroller also supplies the clocks for the SDRAM and PCI bus; however, external
clock buffering may be required in some systems.

Note: The ÉlanSC520 microcontroller supports either a 33.000-MHz or 33.333-MHz
crystal. In this document, the generic term “33 MHz” refers to the system clock derived fr om
whichever 33-MHz crystal frequency is being used in the system.

1-6 Élan™SC520 Microcontroller User’s Manual

Architectural Overview

1.3.9 Integrated Peripherals

The ÉlanSC520 microcontroller is a highly integr ated single- chip CPU with a complete set
of integrated peripherals th at are a superset of common PC/AT peripherals, plus a set of
memory-mapped peripherals that enhance its usability in various applications.

■ A programmable interrupt control ler (PIC) (see Chapter 15) that provides the capabi lity

to prioritize 22 interrupt levels, up to 15 of these being external sources. The PIC can
be programmed to operate in PC/AT-compatibl e mode, but also contains extended
features , including support for more sources and fle xible routing that allo ws any interrupt
request to be steered to any PIC input. Interrupt req uests can be programmed to
generate either non-maskable interrupt (NMI) or maskable interrupt requests.

■ An integrated DMA controller (see Chapter 14) is included fo r transferring data bet ween

SDRAM and GP bus peripherals. The GP-DMA controller operates in single-cycle (fly­by) mode for more efficient transfers. The GP-DMA controller can be programmed for
PC/AT compatibility, but also contains enhanced features:

– A double buffer-chaining mode provides a more efficient software interface.
– Extended address and transfer counts
– Flexi ble routing of DMA channels

■ Three general-purpose 16-bit timers (see Chapter 17) that provide flexible cascading

for extension to 32-bit operation. These timers provide the ability to configure down to
the resolution of four cl ock periods where the clock period is the 33-MHz clock. Ti mer
input and output pins prov ide the ability to interface with off-chip hardware.

■ A standard PC/AT-compatible programmable interval ti mer (PIT) (see Chapte r 16) that

consists of three 16-bit timers.

■ A software timer (see Chapter 18) that eases the task of keeping system time . It provides

1-ms resolution and can also be used for performance monitoring.

■ A watchdog timer (see Chapter 19) to guard against runaway software.

■ A real-time clock (R TC) with battery backup capabil ity (see Chapter 20). The RTC also

provides 114 bytes of batt e ry-bac ked RAM for storage of configuration parameters.

■ T wo integrated 16550-compat ible UARTs (see Chapt er 21) that provide full handshaking

capability with eight pins each. Enhancements enable the UARTs to operate at baud
rates up to 1.152 Mbit s/s. The UARTs can be configured to use the inte grated GP bus
DMA controller to transfer data between the serial ports and SDRAM.

■ A synchronous serial interface (SSI) that is compatible with SCP, SPI, and Microwire

slav e devices (see Chapt er 22). The SSI interf ace can be configured for either full-duple x
or half-duplex operation using a 4-wire or 3-wire interface.

■ 32 programmable I/O pins are provided (see Chapter 23). These pins are multiplexed

with other peripherals and interface functions.

■ The ÉlanSC520 microcontroller al so provides PC/AT-compatible functions f or control of

the a20 gate and the soft CPU reset (Ports 0060h, 0064h, 0092h).

1.3.10 JTAG Boundary Scan Test Interface (Chapter 25)

The ÉlanSC520 microcontroller provi des a full JTAG test port that is compliant with IEEE
Std 1149.1-1990 for use during board testing.

Élan™SC520 Microcontroller User’s Manual 1-7

Architectural Overview

1.3.11 System Testing and Debugging Features (Chapter 24)

To facilitate debugging, the ÉlanSC520 microcontroller provides observability of many
portions of its internal operation, including:

■ A three-pin interface that can be used in either system test mode or write buffer tes t

mode, to aid in determining internal bus initiators of SDRAM cycles, and determining
when SDRAM data is valid on the interface. An additional mode provides observability
of integrated peripheral accesses.

■ A nonconcurrent arbitration mode to reduce debug complexity when PCI bus masters

and GP bus DMA initiators are also accessing SDRAM.

■ CPU cache control and dynamic core clock speed control under program control.

■ Ability to disable write posting and read pref etching in the SDRAM controller to si mplify

tracing of SDRAM cycles.

■ Notification of memory write protection and non-executable memory region violations.

1.4 APPLICATIONS

The figures on the f ollowing pages show t he ÉlanSC520 microcontroller as it might be used
in several reference design applications in the data communications, information
appliances, and telecommunication markets.

1.4.1 Smart Residential Gateway

Figure 1-2 on page 1-10 shows an ÉlanSC520 microcontroller-based Smart Resident
Gateway (SRG), which is a router for a home network between the wide area network
(WAN) (t he internet) and a local area network (LAN) (an intranet of computers and
information appliances in the h ome). The SRG provides fire wall protection of the LAN from
unauthorized access through the internet. A common internet access medium is shared
by all users on the LAN.

A variety of connections ar e possible for both the WAN and the LAN. For e xample, the W AN
connection can be a V.90 modem, cable modem, ISDN, ADSL, or Ethernet.

The LAN connection can be:

■ HomePNA—Home Phoneline Networking Alliance, an alliance with a widel y endorsed

home networking specification

■ Bluetooth—a computing and telecommunications indus try specification that describes

how computing devices can easily interconnect with each other and with home and
business phones and computers using a short-range wireless connection)

■ Home RF—a standard competing with Bluetooth for the interconnection of computing

devices in a LAN using radio frequency

■ Ethernet—local area network technology

■ Power line—a LAN using the AC power distribution network in a home or business to

interconnect de vices. Digital information is transmitted on a hi gh-frequency carrier signal
on top of the AC power.

1.4.2 Thin Client

Figure 1-3 on page 1-11 shows an ÉlanSC520 microcontroller -based “thin client,” whic h is
the modern replacement for the traditional terminal in a remote computing paradigm.
Application programs run remotely on a server, and data is warehoused on centrally
managed disks at the “server farm.” An efficient communications protocol transmits

1-8 Élan™SC520 Microcontroller User’s Manual

Architectural Overview

keyboard and mouse commands upstream and transmits video BIOS calls downstream.
The thin client renders and displays the graphics for the user.

The thin client is typically connected to an Ethernet LAN, although a remote location can
connect to a server via a W AN connection such as a modem. A minimum speed of 24 kbaud
is required for the communication protocol, unless the application is gr aphics-intensive, i n
which case a faster connection is required.

1.4.3 Digital Set Top Box

Figure 1-4 on page 1-12 shows an ÉlanSC520 microcontroller-based digital set top box
(DSTB), which is a consumer client device that uses a t elevision set as the displ ay . Common
applications for the DSTB are internet access, e-mail, and streaming audio and video
content.

The minimal system includes a connection to the WAN via a modem, ADSL, or cable
modem; an output to a TV ; and an InfraRed (IR) link to a remote control or wireless k eyboard.
Expanded systems include DVD drives and MPEG2 decoders to deliver digital video
content. A hard drive may be employed to store video data for future replay. Keyboard,
mouse, printer, or a video camera are options that can be included.

1.4.4 Telephone Line Concentrator

Figure 1-5 on page 1-13 shows an ÉlanSC520 microcontroller-based telephone line
concentrator located in the neighborhood that converts multiple analog subscriber loops
into a high-speed digitally multiplexed line for connection to the central office switching
network.

Élan™SC520 Microcontroller User’s Manual 1-9

Architectural Overview

Figure 1-2 Élan™SC520 Microcontroller-Based Smart Residential Gateway

Reference Design

RJ-11
or

Am79C978

LAN Interface

RJ-45

RJ-11

PCnet™-Home

or

RJ-45

MA12–MA0

MD31–MD0

SDRAM

Control

or V.90

WAN Interface

ADSL, Cable Modem

Control

AD31–AD0

PCI Bus

GPA25–GPA0

Élan™SC520 Microcontroller

SDRAM Bus

GPD15–GPD0

GP Bus

Control

Flash or ROM

33-MHz Crystal

32-kHz Crystal

1-10 Élan™SC520 Microcontroller User’s Manual

Architectural Overview

Figure 1-3 Élan™SC520 Microcontroller-Based Thin Client Reference Design

Controller

CRT/LCD

VGA/LCD

PS/2 Keyboard

PS/2 Mouse

Parallel

Serial

MA12–MA0

MD31–MD0

SDRAM

RJ-45

Control

LAN Interface

PCnet™-Fast III

Am79C973/Am79C975

Control

AD31–AD0

PCI Bus

Élan™SC520 Microcontroller

SDRAM Bus

33-MHz Crystal

32-kHz Crystal

Control

GPD15–GPD0

GPA25–GPA0

GP Bus

Control

Super I/O

Flash

Memory

Élan™SC520 Microcontroller User’s Manual 1-11

Architectural Overview

Figure 1-4 Élan™SC520 Microcontroller-Based Digital Set Top Box Reference Design

VGA

NTSC/PAL

PS/2 Keyboard

PS/2 Mouse

Parallel

IR

MA12–MA0

MD31–MD0

SDRAM

RJ-11

Control

or V.90

WAN Interface

ADSL, Cable Modem

Control

AD31–AD0

Control

PCI Bus

GPD15–GPD0

Élan™SC520 Microcontroller

SDRAM Bus

33-MHz Crystal

32-kHz Crystal

GPA25–GPA0

GP Bus

Control

Super I/O

Control

GPA1–GPA0

Flash

Memory

GPD15–GPD0

EIDE

DVD or HDD

1-12 Élan™SC520 Microcontroller User’s Manual

Architectural Overview

Figure 1-5 Élan™SC520 Microcontroller-Based Telephone Line Concentrator

Reference Design

Analog

Phone

Lines

ISLIC

ISLIC

Am79R241

Am79R241

Quad ISLAC

Am79Q2241

ISLIC

ISLIC

Am79R241

Am79R241

(6x to 10X)

PCM Highway

SSI

ISLIC

ISLIC

Am79R241

Am79R241

Quad ISLAC

ISLIC

Am79Q2241

ISLIC

Am79R241

Am79R241

T1 or E1

T1/E1

Interface

HDLC

Control

MD31–MD0

MA12–MA0

SDRAM

Control

GPD15–GPD0

Élan™SC520 Microcontroller

SDRAM Bus

33-MHz Crystal

32-kHz Crystal

GPA25–GPA0

GP Bus

Control

Flash

Memory

Élan™SC520 Microcontroller User’s Manual 1-13

Architectural Overview

1-14 Élan™SC520 Microcontroller User’s Manual

CHAPTER

PIN INFORMATION

2

2.1 OVERVIEW

The ÉlanSC520 microcontroller contains 258 signal pins plus power and ground signals.
A minimal number of signals are shared with others .

The signals are organized alphabet ically within the follow ing functional groups:

■ Synchronous DRAM controller (page 2-5)

■ ROM/Flash controller (page 2-6)

■ PCI bus (page 2-6)

■ General-purpose (GP) bus (page 2-7)

■ Serial ports (page 2-9)

■ Timers (page 2-10)

■ Clocks and reset (page 2-10)

■ Chip selects (page 2-11)

■ Programmable I/O (PIO) (page 2-11)

■ JTAG boundary scan test interface (page 2-12)

■ AMDebug interface (page 2-12)

■ System test (page 2-12)

■ Configuration (page 2-13)

■ Power (page 2-14)

2.2 LOGIC SYMBOLS

Figure 2-1 shows a logical symbol of the de vice, wi th pins grouped by function or interf ace.
Figure 2-2 shows a logical symbol with pins grouped by default function. Figure 2-2 also
shows pin multiplexing on the ÉlanSC520 microcontroller.

Élan™SC520 Microcontroller User’s Manual 2-1

Pin Information

Figure 2-1 Logic Diagram by Interface

PCI Bus

SDRAM

Serial Ports:
UART 1
UART 2
SSI

Programmable
Input/Output

Clocks and Reset

AD31–AD0

–CBE0

CBE3
PAR

SERR
PERR

FRAME
TRDY
IRDY
STOP

DEVSEL

CLKPCIOUT
CLKPCIIN
RST

INTA–INTD
REQ4–REQ0
GNT4–GNT0

MA12–MA0
BA1–BA0
MD31–MD0

–SCS0

SCS3
CLKMEMOUT
CLKMEMIN

–SRASB

SRASA

SCASA–SCASB
SWEA–SWEB

SDQM3–SDQM0

MECC6–MECC0

SOUT2–SOUT1
SIN2–SIN1

–RTS1

RTS2

CTS2–CTS1
DSR2–DSR1
DTR2–DTR1

DCD2–DCD1

RIN2–RIN1
SSI_CLK

SSI_DO

SSI_DI

PIO31–PIO0

32KXTAL2–32KXTAL1
33MXTAL2–33MXTAL1

LF_PLL1

CLKTIMER
CLKTEST
PWRGOOD

PRGRESET

BBATSEN

1

GPA25–GPA0

GPD15–GPD0

GPRESET

GPIORD

GPIOWR

GPMEMRD

GPMEMWR

GPALE
GPBHE
GPRDY

GPAEN

GPTC

GPDRQ3–GPDRQ0

GPDACK3

TMROUT1–TMROUT0

WBMSTR2–WBMSTR0

–GPDACK0

GPIRQ10–GPIRQ0

GPDBUFOE

GPIOCS16

GPMEMCS16

GPCS7–GPCS0

GPA25–GPA0*

GPD15–GPD0*

MD31–MD0*

BOOTCS

ROMCS2–ROMCS1

ROMRD

FLASHWR

ROMBUFOE

TMRIN1–TMRIN0

PITGATE2

PITOUT2

JTAG_TRST

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

CMDACK

BR/TC

STOP/TX

TRIG/TRACE

CF_DRAM

DAT ASTRB

CF_ROM_GPCS

DEBUG_ENTER

INST_TRCE

AMDEBUG_DIS

CFG3–CFG0

RSTLD7–RSTLD0

GP Bus

ROM/Flash

Timers

JTAG

AMDebug

System Test

Configuration

Notes:

1. Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface.

2-2 Élan™SC520 Microcontroller User’s Manual

Pin Information

Figure 2-2 Logic Diagram by Default Pin Function

PCI Bus

SDRAM

Serial Ports:
UART 1
UART 2
SSI

Clocks and Reset

AD31–AD0

–CBE0

CBE3
PAR

SERR

PERR
FRAME

TRDY

IRDY
STOP

DEVSEL
CLKPCIOUT
CLKPCIIN
RST

INTA–INTD
REQ4–REQ0
GNT4–GNT0

MA12–MA0

BA1–BA0

MD31–MD0

–SCS0

SCS3

CLKMEMOUT

CLKMEMIN

–SRASB

SRASA

SCASA–SCASB

SWEA–SWEB
SDQM3–SDQM0

MECC6–MECC0

SOUT2–SOUT1
SIN2–SIN1

–RTS1

RTS2

CTS1
DSR1
DTR2–DTR1

DCD1

RIN1
PIO28 [CTS2]

PIO29 [DSR2
PIO30 [DCD2

PIO31 [RIN2

SSI_CLK

SSI_DO
SSI_DI

32KXTAL2–32KXT AL1

32MXTAL2–32MXTAL1

LF_PLL1
CLKTIMER [CLKTEST]

PWRGOOD
PRGRESET

BBATSEN

]

]

]

GPA22–GPA15 {RSTLD7–RSTLD0}

PIO9–PIO12 [GPDACK3

ROMCS2–ROMCS1 [GPCS2–GPCS1]

TMRIN1–TMRIN0 [GPCS4–GPCS5]

TMROUT1–TMROUT0 [GPCS6–GPCS7]

CF_ROM_GPCS

1

GPA25 {DEBUG_ENTER}

GPA24 {INST_TRCE}

GP A23 {AMDEBUG_DIS}

GPA13–GPA0
GPD15–GPD0

GPRESET

GPIORD

GPIOWR

GPMEMRD

GPMEMWR

PIO0 [GPALE]
PIO1 [GPBHE]
PIO2 [GPRDY]

PIO3 [GPAEN]

PIO4 [GPTC]

PIO5–PIO8 [GPDRQ3–GPDRQ0]

–GPDACK0]

PIO13–PIO23 [GPIRQ10– GP IRQ0 ]

PIO24 [GPDBUFOE]

PIO25 [GPIOCS16]

PIO26 [GPMEMCS16

PIO27 [GPCS0]

GPA25–GPA0*
GPD15–GPD0*

MD31–MD0*

BOOTCS

ROMRD

FLASHWR

ROMBUFOE

PITGATE2 [GPCS3]

PITOUT2 {CFG3}

JTAG_TRST

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

CMDACK

BR/TC

STOP/TX

TRIG/TRACE

CF_DRAM [WBMSTR2] {CFG2}

DAT ASTRB [WBMSTR1] {CFG1}

[WBMSTR0] {CFG0}

GP Bus

]

ROM/Flash

Timers

JTAG

AMDebug

System Test

Notes:

1. Pin names in bold indica te the d efa ult pin function. Br ac kets , [ ] , indica te alternate , mul tiple x ed functi ons. Braces , { }, indicate
pinstrap pins. Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface.

Élan™SC520 Microcontroller User’s Manual 2-3

Pin Information

2.3 SIGNAL DESCRIPTIONS

Table 2-1 describes the terms used in the signal description table . In general, the br acket s,
[ ], indicate alternate, multiplex ed functions, and braces, { }, i ndicate reset configuration
pins (pinstraps). The line over a pin name indicates an active Low signal. The word pin
refers to the physical wire; the word signal ref ers to the electrical signal t hat flows through it.

Table 2-2, “Signal Descriptions” on page 5 contains a description of the ÉlanSC520
microcontroller signals. The descriptions in Table 2-2 are organized by functional g roup.
Table 2-2 describes the signals that are av ailab le for each interface and which signals are
shared with others. Signal sharing is also shown in Figure 2-2.

Detailed information on pin state , incl uding maxim um load values, power-on res et default
function, reset stat e, po wer-on reset def ault operation, hold state , and v oltage , is a v ailab le
in the

diagrams, as well as pin number assignments, are also included in that document.

Table 2-1 Signal Descriptions Table Definitions

Élan™SC520 Microcontroller Data Sheet

Term Definition
General Terms

[ ] Indicates the pin alternate function; a pin defaults to the signal named without the

brackets.

{ } Indicates the reset configuration pin (pinstrap).

pin Refers to the physical wire.

signal Refers to the electrical signal that flows across a pin.

SIGNAL

Signal Types

Analog Analog voltage

B Bidir ectional
HHigh

I Input

LS Programmable to hold last state of pin

O Totem pole output

O/TS Totem pole output/three-state output

OD Open-drain output

OD-O Open-drain output or totem pole output

Osc Oscillator

PD Internal pulldown resistor (~100–150 kW)

Power Power pins

PU Internal pullup resistor (~100–150 kW)

STI Schmitt trigger input

STI-OD Schmitt trigger input or open-drain output

TS Three-state output

A line over a signal name indicates that the signal is active Low; a signal name
without a line is active High.

, order #22003. Connection and package

2-4 Élan™SC520 Microcontroller User’s Manual

Pin Information

Table 2-2 Signal Descriptions

Multiplexed

Signal

Signal Type Description

Synchronous DRAM Controller

BA1–BA0 — O Bank Address is the SDRAM bank address bus.
CLKMEMIN — I SDRAM Clock Input is the SDRAM clock return signal used to

minimize skew between the internal SDRAM clock and the
CLKMEMOUT signal provided to the SDRAM devices. This signal
compensates for buff er and load dela ys introduced by the board design.

CLKMEMOUT — O SDRAM Clock Output is the 66-MHz clock that provides clock

signalling f or the sy nchro nous DR AM de v ices . Th is clo c k ma y requ ire
an external Lo w skew buffer for system im pl em ent ations that result in

heavy loading on the SDRAM clock signal.
MA12–MA0 — O SDRAM Address is the SDRAM multiplexed address bus.
MD31–MD0 — B SDRAM Data Bus inputs data during SDRA M read cycles an d outputs

data during SDRAM write cycles.
MECC6–MECC0 — B Memory Error Correction Code contains the ECC checksum

(syndrome) bits used to validate and correct data errors.
SCASA

SCS3

SDQM3–SDQM0 — O Data Input/Output Masks make SDRAM data out put high-impedance

SRASA

SWEA

–SCASB —OColumn Address Strobes are us ed in c ombinati on wi th the SR ASA–

SRASB

SCASA

to reduce the total load connected to CAS

Suggested system connection:

SCASA

SCASB

–SCS0 —OSDRAM Chip Selects are the SDRAM chip-select outputs. These

signals are asserted to select a bank of SDRAM devices. The chip-

select signals enable the SDRAM devices to decode the commands

asserted via SRASA

and blocks data input on SDRAM while active. Each of the four

SDQM3–SDQM0 signals is associated with one byte of four

throughout the array. Each SDQMx signal provides an input mask

signal for write accesses and an output enable signal for read

accesses.

–SRASB —ORow Address Strobes are used in combination with the SCASA–

SCASB

SRASA

to reduce the total load connected to RAS

Suggested system connection:

SRASA for SDRAM banks 0 and 1

SRASB

–SWEB —OSDRAM Memory Write Enables are used in combination with the

SRASA

command type.

SWEA

to reduce the total load connected to WE.

Suggested system connection:

SWEA

SWEB

and SWEA–SWEB to encode the SDRAM command type.
and SCASB are the same signal prov ided on two diff erent pins

.

for SDRAM banks 0 and 1
for SDRAM banks 2 and 3

–SRASB, SCASA–SCASB, and SWEA–SWEB.

and SWEA–SWEB to encode the SDRAM command type.
and SRASB are the same signal prov ided on two diff erent pins

.

for SDRAM banks 2 and 3

–SRASB and SCASA–SCASB to encode the SDRAM

and SWEB are the same signal provided on two diffe r ent pi ns

for SDRAM banks 0 and 1
for SDRAM banks 2 and 3

Élan™SC520 Microcontroller User’s Manual 2-5

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

Signal Type Description

ROM/Flash Controller

BOOTCS —OROM/Flash Boot Chip Select is an active Low output that provides

the chip select for the startup R OM and/or the R OM/Flash arra y (BIOS,

HAL, O/S, etc. ). The BOOTCS signal asserts for access es made to the

64-Kbyte segment that contains the Am5

addresses 3FF0000h–3FFFFFFh. In addition to this linear decode

region, BOOTCS asserts in response to accesses to user-

programmable address regions.
FLASHWR

GPA25–GPA0 — O General-Purpose Address Bus provides the address to the sy stem’ s

GPD15–GPD0 — B General-Purpose Data Bus inputs data during memory and I/O read

MD31–MD0 — B Memory Data Bus inputs data during SDRAM read cycles and

ROMBUFOE —OROM Buffer Output Enable is an optional signal used to enable a

ROMCS2
ROMCS1
ROMRD

[GPCS2]OROM/Flash Chip Selects are signals that can be programmed to be
[GPCS1]O

—OFlash Write indicates that the current cycle is a write of the selected

Flash devic e . When this signal is asse rted, the sele cted Flash device

can latch data from the data bus.

ROM/Flash de vi ces. I t is also the addres s bus fo r the GP b us devices.

T w enty-six address li nes provide a m aximum address able space of 64

Mbytes for each ROM chip select.

cycles and outputs data during memory and I/O write cycles.

A reset configurat ion pi n (CFG2 ) allo ws th e GP b u s to b e used for the

boot chip-select ROM interface. Configuration registers are used to

select whether ROMCS2

the MD data bus. The GP data bus supports 16-bit or 8-bit ROM

interfaces . Two data buses are se lec t able to facili tate the use of ROM

in a mixed voltage system.

outputs data during SDRAM write cycles. Configuration registers are

used to select whether R OMC S2

bus or the MD data bus. A reset configuration pin (CFG2) allows the

GP data b u s to be used f or BOOT

an 8-, 16-, or 32-bit ROM interface.

buffer to the ROM/Flash devices if they need to be isolated from the

ÉlanSC520 microcontrolle r, other GP bus de vices , or SDRAM syst em

for voltage or loading considerations. This signal asserts for all

accesses through the R OM controller . The buffer dir ection is controlled

by the ROMRD

asserted for accesses to user-programmable address regions.

—OROM/Flash Read indicates that the current cycle is a read of the

selected ROM/Flash device. When this signal is asserted, the selected

ROM device can drive data onto the data bus.

or FLASHWR signal.

and ROMCS1 use the GP bus data bus or

and ROMCS1 use the GP bus data

CS. The memory data bus su pports

86 CPU boot vector:

x

Peripheral Component Interconnect (PCI) Bus

AD31–AD0 — B PCI Address Data Bus is the PCI time-m ultiple xed a ddress/data b us.

–CBE0 —BCommand or Byte-Enable Bus functions 1) as a time-multiplexed

CBE3

bus command that defines the type of transaction on the AD bus,

or 2) as byte enables:

for AD7–AD0

CBE0

for AD15–AD8

CBE1

for AD23–AD16

CBE2

CBE3

for AD31–AD24

CLKPCIIN — I PCI Bus Clock Input is the 33-MHz PCI bus clock. This pin can be

connected to the CLKPCIOUT pin for systems where the ÉlanSC520

microcontroller is the source of the PCI bus clock.

2-6 Élan™SC520 Microcontroller User’s Manual

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

CLKPCIOUT —OPCI Bus Clock Output is a 33-MHz clock output for the PCI bus

DEVSEL

FRAME

–GNT0 —OBus Grants are asserted by the ÉlanSC520 microcontroller to grant

GNT4

–INTD —IInterrupt Requests are asserted to request an interrupt. These four

INTA

IRDY

PAR — B PCI Parity is driven by the initiator or target to indicate parity on the

PERR

–REQ0 —IBus Requests are asserted by the master to request access to the

REQ4

RST —OReset is asserted to reset the PCI devices.
SERR

STOP

TRDY

Signal Type Description

devices. This signal is derived from the 33MXTAL2–33MXTAL1

interface.

—BDevice Select is asserted by the target when it has decoded its

address as the target of the current transaction.

—BFrame is driven by the transaction initiator to indicate the start and

duration of the transaction.

access to the bus.

interrupts are the same type of interrupt as the GPIRQ10–GPIRQ0

signals, and th ey go to the same interrupt c ont roller. The y a re named

x to match the common PCI interrupt naming convention.

INT

Configuration registers allow inversion of these interrupt requests to

recognize active low interrupt requests. These interrupt requests can

be routed to generate NMI.

—BInitiator Ready is asserted by the current bus master to indic ate t hat

data is ready on the bus (write) or that the master is ready to accept

data (read).

AD31–AD0 and CBE3

—BParity Error is asserted to indicate a PCI bus data parity error in the

previous clock cycle.

bus.

—ISystem Error is use d for reporting address parity errors or any o ther

system error where the result is catastrophic.

—BStop is asserted by the target to request that the current bus

transaction be stopped.

—BT arget Ready is as serted by the curre ntly addressed target to indi cate

its ability to complete the current data phase of a transaction.

–CBE0 buses.

General-Purpose (GP) Bus

GPA14–GPA0 — O General-Purpose Address Bus outputs the physical memory or I/O
GPA15 {RSTLD0} O{I}
GPA16 {RSTLD1} O{I}
GPA17 {RSTLD2} O{I}
GPA18 {RSTLD3} O{I}
GPA19 {RSTLD4} O{I}
GPA20 {RSTLD5} O{I}
GPA21 {RSTLD6} O{I}
GPA22 {RSTLD7} O{I}
GPA23 {AMDEBUG_DIS} O{I}
GPA24 {INST_TRCE} O{I}
GPA25 {DEBUG_ENTER} O{I}

port address. Twenty-six address lines provide a maximum

addressable space of 64 Mbytes. This bus also provides the address

to the system’s ROM/Flash devices.

Élan™SC520 Microcontroller User’s Manual 2-7

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

[GPAEN] PIO3 O GP Bus Address Enable indicates that the current address on the

[GPALE] PIO0 O GP Bus Add ress Latch Enable is driven at th e beginning of a GP bus

[GPBHE

GPD15–GPD0 — B General-Purpose Data Bus inputs data during memory and I/O read

[GPDACK0
[GPDACK1
[GPDACK2
[GPDACK3
[GPDBUFOE

[GPDRQ0] PIO8 I GP Bus DMA Request can each be mapped to one of the seven
[GPDRQ1] PIO7 I
[GPDRQ2] PIO6 I
[GPDRQ3] PIO5 I
[GPIOCS16

GPIORD

GPIOWR

]PIO1 OGP Bus Byte High Enable is driven active when data is to be

]PIO12 OGP Bus DMA Acknowledge can each be mapped to one of the se ve n
]PIO11 O
]PIO10 O
]PIO9 O

]PIO24 OGP Bus Data Bus Buffer Output Enable is used to control t he output

] PIO25 STI GP Bus I/O Chip-Select 16 is driven active early in the cycle by the

Signal Type Description

GPA25–GP A0 address b us is a mem ory address, a nd that the cu rrent

cycle is a DMA cycle. All I/O de vices should use this signal in decoding

their I/O addresses and should not respond when this signal is

asserted. When GPAEN is asserted, the GPDACKx signals are used

to select the appropriate I/O device for the DMA transfer. GPAEN also

asserts when a DMA cycle is occurring internally.

cycle with valid address. This signal can be used by external devices

to latch the GP address for the current cycle.

transferred on the upper 8 bits of the GP data bus.

cycles, and outputs data during memory and I/O write cycles.

available DMA channels. They are asserted active Low to

acknowledge the corresponding DMA requests.

enable on an external transceiver that may be on the GP data bus.

Using this transceiver is optional in the system design and is

necessary only to alleviate loading or voltage issues. This pin is

asserted for all external GP bus accesses. It is not asserted during

accesses to the internal peripherals even if GP bus echo mode is

enabled.

Note that if the ROM is configured to use the GP data bus, then its

bytes are not control led by this buf fer enable ; they are controlled by the

ROMBUFOE

available DMA channels. They are asserted active High to request

DMA service.

targeted I/O device on the GP bus to request a 16-bit I/O transfer.

—OGP Bus I/O Read indicates that the current cycle is a read of the

currently addressed I/O device on the GP bus. When this signal is

asserted, the selected I/O device can drive data onto the data bus.

—OGP Bus I/O Write indicates that the current cycle is a write of the

currently addressed I/O device on the GP bus. When this signal is

asserted, the selected I/O device can latch data from the data bus.

signal.

2-8 Élan™SC520 Microcontroller User’s Manual

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

[GPIRQ0] PIO23 I GP Bus Interrupt Request can each be mapped to one of the
[GPIRQ1] PIO22 I
[GPIRQ2] PIO21 I
[GPIRQ3] PIO20 I
[GPIRQ4] PIO19 I
[GPIRQ5] PIO18 I
[GPIRQ6] PIO17 I
[GPIRQ7] PIO16 I
[GPIRQ8] PIO15 I
[GPIRQ9] PIO14 I
[GPIRQ10] PIO13 I
[GPMEMCS16

[GPMEMRD

[GPMEMWR

[GPRDY] PIO2 STI GP Bus Ready can be driv en by open -drain dev ices. When p ulled Low

GPRESET — O GP B us Rese t, wh en as serted, re-initializes to rese t s tate all devices

[GPTC] PIO4 O GP Bus Terminal Count is driv en fro m the in ternal DMA c ontroll er to

] PIO26 STI GP Bus Memo ry Chip-Select 16 is driv en activ e early in the cycl e b y

] —OGP Bus Memory Read indicates that the current GP bus cycle is a

]—OGP Bus Memory Write indicates that the current GP bus cycle is a

Signal Type Description

available interrupt channels or NMI. They are asserted when a

peripheral requires interrupt service.

Configuration registers allow inversion of these interrupt requests to

recognize active low interrupt requests. These interrupt requests can

be routed to generate NMI.

the targeted memory device on the GP bus to request a 16-bit

memory transfer.

read of the selected memory de vice. When this s ignal is asserted, the

selected memory device can drive data onto the data bus.

write of the selected mem ory device . When this s ignal is asserted, the

selected memory device can latch data from the data bus.

during a GP bus access, wait states are in se rted in t he current cycle.

This pin has an internal weak pullup that should be supplemented by

a stronger external pullup for faster rise time.

connected to the GP bus.

indicate that the transfer count for the currently active DMA channel

has reached zero, and that the current DMA cycle is the last transfer.

Serial Ports

CTS1
CTS2

DCD1

]PIO30 I

[DCD2
DSR1 —IData Set Ready is used to indicate that the external DCE is ready to

]PIO29 I

[DSR2

–DTR1 —OData Terminal Ready indicates to the external DCE that the internal

DTR2

RIN1
[RIN2

]PIO31 I

–RTS1 —ORequest To Send indica tes to the e xternal DCE tha t the internal se rial

RTS2

SIN2–SIN1 — I Serial Data In is used to receiv e the serial data from the external serial

SOUT2–SOUT1 — O Serial Data Out is used to transmit the serial data from the internal

PIO28

—

—IData Carrier Detect is driven back to the serial port from a piece of

—IRing Indicate is used b y an external modem to inform the serial port

I

Clear To Send is driven back to the serial port to indicate that the

I

external data carrier equipment (DCE) is ready to accept data.

DCE when it has detected a carrier signal from a communications

target.

establish a communication link with th e internal serial port controller.

serial port controller is ready to communicate.

that a ring signal was detected.

port controller is ready to send data.

device or DCE into the internal serial port controller.

serial port controller to the external serial device or DCE.

Élan™SC520 Microcontroller User’s Manual 2-9

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

SSI_CLK —OSSI Clock is driven b y the Élan SC520 micro controller SSI port during

SSI_DI — STI SSI Data Input receives incoming data from a peripheral device SSI

SSI_DO — OD SSI Data Output drives data to a peripheral device SSI port. Data is

Signal Type Description

active SSI trans mi t or re cei ve transactions . Th e id le s tat e of the c lo ck

and the assertion/sample edge are configurable.

port. Data is shifted in on t he o pp osite SSI_CLK signal edge in w hic h

SSI_DO drives data. SSI_DO and SSI_DI can be tied together to

interface to a three-pin SSI peripheral.

driven on the opposite SSI_C LK s ign al ed ge in whic h SSI_DI la tc hes

data. The DO signal is normally at high-impedance when no transmit

transaction is active on the SSI port.

Timers

PITGATE2 [GPCS3]IProgrammable Interval Timer 2 Gate provides control for the PIT

Channel 2.
PITOUT2 {CFG3} O{I}

TMRIN0 [GPCS5
TMRIN1 [GPCS4
TMROUT0 [GPCS7
TMROUT1 [GPCS6

]ITimer Inputs 0 and 1 can be programmed to be the control or clock
]I
]OTimer Outputs 0 and 1 are outputs from two o f the GP ti mers. Thes e
]O

Programmable Interval Timer 2 Output is output from the PIT

Channel 2. This signal is typically used as the PC speaker signal.

for the general-purpose (GP) timers 0 and 1.

outputs can be used as pulse-width modulation signals.

Clocks and Reset

32KXTAL2–
32KXTAL1

33MXTAL2–
33MXTAL1

[CLKTEST] CLKTIMER O Test Clock Output is a shared pin that allows many of the internal

CLKTIMER [CLKTEST] I Timer Clock Input is a shared clock pin that can be used to input a

LF_PLL1 — I Loop Filter Interface is used fo r connecting external loop filter

PRGRESET —STIProgrammable Reset can be programmed to reset the ÉlanSC520

PWRGOOD — STI Power Go od is a reset signal that indicates to the ÉlanSC520

—osc32.768-kHz Crystal Interface is used for connecting an external

crystal or oscillator to the ÉlanSC520 microcontroller. This clock

source is used to cloc k th e rea l-ti me cl ock (RTC). In addit ion , in ternal

PLLs generate clocks for the timers and UARTs based on this clock

source. When an external oscillator is used, 32KXTAL1 should be

grounded and the clock source driven on 32KXTAL2.

—osc33-MHz Crystal Interface is the main system clock for the chip. This

clock source is used to derive the SDRAM, CPU, and PCI clocks.

When an external oscillator is used, 33MXTAL1 should be

unconnected and the clock source driven on 33MXTAL2.

clocks to be driven externally. CLKTEST can drive the internal clocks

of the UARTs, PLL1, PLL2, the programmable interval timer (PIT), or

the real-time clock (RTC) for testing or for driving an external device.

frequency to the programmable interval timer (PIT).

components. Component values and c ircuit descriptions are contained

Élan™SC520 Microcontroller Data Sheet

in the

microcontroller, b ut allow SDRAM refresh to continue du ring the reset.

This allows the system to be reset witho ut losing the information stored

in SDRAM. On power-up, PRGRESET is disabled and must be

programmed to be operational. When disabled, this pin has no effect

on the ÉlanSC520 microcontroller.

microcontroller that the V

range. It is used to reset the e ntire ch ip and m ust be held Lo w f o r one

second after all V

This signal must be returned Low before the V

put the RTC into the correct state for operation in RTC-only mode.

CC

levels are within the normal operation

CC

signals (exc ept VCC_R T C) on the chip are High .

, order #22003.

signals degrade to

CC

2-10 Élan™SC520 Microcontroller User’s Manual

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

Signal Type Description

Chip Selects

[GPCS0]PIO27 OGeneral-Purpose Chip Select signals are for the GP bus. They can
[GPCS1
[GPCS2
[GPCS3
[GPCS4
[GPCS5
[GPCS6
[GPCS7

]ROMCS1 O
]ROMCS2 O
]PITGATE2 O
]TMRIN1 O
]TMRIN0 O
]TMROUT1 O
]TMROUT0 O

be used for either memory or I/O accesses. These chip selects are

asserted for Am5x86 CPU access es t o the corresponding regi ons set

up in the Programmable Address Region (PAR) registers.

Programmable I/O (PIO)

PIO0 [GPALE] B Programmable Input/Output signals can be programmed as inputs
PIO1 [GPBHE
PIO2 [GPRDY] B
PIO3 [GPAEN] B
PIO4 [GPTC] B
PIO5 [GPDRQ3] B
PIO6 [GPDRQ2] B
PIO7 [GPDRQ1] B
PIO8 [GPDRQ0] B
PIO9 [GPDACK3
PIO10 [GPDACK2
PIO11 [GPDACK1
PIO12 [GPDACK0
PIO13 [GPIRQ10] B
PIO14 [GPIRQ9] B
PIO15 [GPIRQ8] B
PIO16 [GPIRQ7] B
PIO17 [GPIRQ6] B
PIO18 [GPIRQ5] B
PIO19 [GPIRQ4] B
PIO20 [GPIRQ3] B
PIO21 [GPIRQ2] B
PIO22 [GPIRQ1] B
PIO23 [GPIRQ0] B
PIO24 [GPDBUFOE
PIO25 [GPIOCS16
PIO26 [GPMEMCS16
PIO27 [GPCS0
PIO28 [CTS2
PIO29 [DSR2
PIO30 [DCD2
PIO31 [RIN2

]B

]B
]B
]B
]B

]B

]B

]B

]B

]B

]B

]B

]B

or outputs. When the y ar e out puts, the y ca n be driv en High or Lo w b y

programming bits in registers.

Élan™SC520 Microcontroller User’s Manual 2-11

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

Signal Type Description

JTAG Boundary Scan Test Interface

JTAG_TCK —ITest Clock is the input clock for test access port.
JTAG_TDI — I Test Data Input is the serial input stream for input data. This pin has

a weak internal pullup resistor. It is sampled on the rising edge of

JTAG_TCK. If not driven, this input is sampled High internally.
JTAG_TDO — O/TS Test Data Output is the serial output stream f or res ult data. It is in the

high-impedance state except when scanning is in progress.
JTAG_TMS — I Test Mode Select is an input for controlling the test access port. This

pin has a weak internal pullup resistor. If it is not driven, it is sampled

High internally.
JTAG_TRST

—IJTAG Reset is the test access port (TAP) reset. This pin has a weak

inter nal pulldown resistor. If not driven, this input is sampled Low

internally and causes the TAP controller logic to remain in the reset

state.

AMDebug Interface

BR/TC — I Break Request/Trace Capture requests entry to AMDebug

technology mode. The AMDebug technology serial/parallel interface

can reconfigure this pin to turn instruction trace capture on or off.
CMDACK — O Command Acknowledge indicates com mand com pletion st atus . It is

asserted High when the in-circuit emulator logic is ready to receive

new commands from the host. It is driven Low when the in-circuit

emulator core is e xecutin g a command from the host and remains Lo w

until the command is completed.
STOP/TX — O Stop/Transmit is asserted High on entry to AMDebug mode. During

normal mode, this is set High when there is data to be transmitted to

the host (during operating system/application communication).
TRIG/TRACE — O Trigger/Trace triggers event to lo gic an alyz er (op tional , from Am5

CPU debug registers).The AMDebug technology serial/parallel

interface can reconfigure this pin to indicate the trace on or off status.

x

System Test

CF_DRAM [WBMSTR2]

{CFG2}

CF_ROM_GPCS

DATASTRB [WBMSTR1]

[WBMSTR0]
{CFG0}

{CFG1}

O{I} Code Fetch SDRAM, during SDRAM reads, provides code fetch

status. When Low, this indicates that the current SDRAM read is a

CPU code fe tch demanded b y the CPU , or a read pre fetch initia ted due

to a demand code fetch by the CPU. When High during reads, this

indicates that the SDRAM read is not a code fetch, and it could have

been initiated by the CPU, PCI master, or the GP bus GP-DMA

controller , eithe r dema nd or pref e tch. During SDRAM write cycles this

pin provides an indication of the source of the data, either GP-DMA

controller/PCI bus master or CPU. When High, this indicates that

either a GP bus DMA initiator or an external PCI bus master

contributed to the current SDRAM write cycl e (the CPU ma y al so ha ve

contributed). A Low indicates that the CPU is the only master that

contributed to this write cycle.

O{I} Code Fetch ROM/GPCS provides an indication that the CPU is

performing a code fe tch from ROM (on either the GP bus or SDRAM

data bus), or from an y GPC Sx pin. When Low during a re ad cycle (as

indicated by either GPMEMRD

code fetch from ROM or a GP bus chip select. At all other times

(including writes), this signal is High.

O{I} Data Strobe is a debug signal that is asserted to allow the external

system to latch SDRAM data. This can be used to trace data on the

SDRAM interface with an in-circuit emulator probe or logic analyzer.

or ROMRD), the CPU is performing a

86

2-12 Élan™SC520 Microcontroller User’s Manual

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

[WBMSTR0] CF_ROM_GPCS

[WBMSTR1] DATASTRB

[WBMSTR2] CF_DRAM

Signal Type Description

O{I} Write Buffer Master indicates which block(s) wrote to a rank in the

{CFG0}

O{I} WBMSTR1, when a logical 1, indicates that the PCI master has

{CFG1}

O{I} WBMSTR2, when a logical 1, it indi cates that the CPU has cont ributed

{CFG2}

write buffer (during SDRAM write cycles) and which block is reading

from SDRAM (during SDRAM read cycles).

WBMSTR0, when a logical 1, indicates that the internal GP bus DMA

controller has contributed to the write buffer rank (write cycles) or is

reading from SDRAM (read cycles).

contributed to the write buffer rank (write cycles) or is reading from

SDRAM (read cycles).

to the write buffer r ank (w rite cycles) or is read ing from SDRAM (read

cycles).

Configuration

{AMDEBUG_DIS} GP A23 I AMDebug Disable is an ac tive High co nfiguration si gnal latched at th e

assertion of Power Good (PWRGOOD). This pin has a built-in

pulldown resistor.

At Power Good assertion:

Low = Normal operation, mode can be enabled by software.
High = AMDebug mode is disabled and cannot be enabled by software.

{CFG0} CF_ROM_GPCS

[WBMSTR0]

{CFG1} DATASTRB

[WBMSTR1]

I Configuration Inputs 3–0 are latched into the chip when PWRGOOD

is asserted. These signals are all shared with other features. These

signals have built-in pulldown resistors.

CFG0: Choose 8-, 16-, or 32-bit ROM/Flash interface for BOOTCS.

I CFG1: Choose 8-, 16-, or 32-bit ROM/Flash interface for BOOTCS

.

CFG1 CFG0 BOOTCS Data Width

00 8-bit
0 1 16-bit
1 x (don’t care) 32-bit

{CFG2} CF_DRAM

[WBMSTR2]

{CFG3} PITOUT2 I CFG3 (Internal AMD test mode enable):

I CFG2: When Low when PWRGOOD is asserted, the ÉlanSC520

microcontroller uses the GP data bus for BOOTCS. When seen as

High during PWRGOOD a ssertion, the BOO TCS

SDRAM data bus. Default is Low (by a built- in pulldown resistor).

access is acros s the

For normal ÉlanSC520

microcontroller operation, do not pull High during reset.

{DEBUG_ENTER} GPA25 I Enter A MDebug Mode is an active High configuration signal latched

at the assertion of Power Good (PWRGOOD). This pin enables the

AMDebug mode, w hich causes the processor to fe tch and exec ute one

instruction from the BOOTCS

where the CPU waits for debug commands to be delivered by the JTA G

port. This pin has a built-in pulldown resistor.

At PWRGOOD assert ion:

High = AMDebug mode enabled

Low = Normal operation
{INST_TRCE} GPA24 I Instruction Trace is an active High co nfigur ation si gnal latc hed at th e

assertion of Power Good (PWRGOOD). Enables trace record

generation from Power Good assertion. This pin has a built-in

pulldown resistor.

At PWRGOOD assert ion:

High = Trace controller enabled to output trace records

Low = Normal operation

device , and th en ente r AM Deb ug mode

Élan™SC520 Microcontroller User’s Manual 2-13

Pin Information

Table 2-2 Signal Descriptions (Continued)

Multiplexed

Signal

{RSTLD0} GPA15 I Reset Latched Inputs are shared signals that are latched into a
{RSTLD1} GPA16 I
{RSTLD2} GPA17 I
{RSTLD3} GPA18 I
{RSTLD4} GPA19 I
{RSTLD5} GPA20 I
{RSTLD6} GPA21 I
{RSTLD7} GPA22 I

Signal Type Description

register when PWRGOOD is asserted. They are used to input static

information to software (i.e., board re v is ion ). Th es e sign als have built-

in pulldown resistor s.

Power

BBATSEN — Analog Backup Battery Sense is a pin on which real-time clock (RTC) backup

battery voltage is sampled each time PWRGOOD is asserted. If this

pin samples below 2.0 V, the Valid RAM and Time (VRT) bit in RTC

index 0Dh is cleared until read. After the read, the VRT bit is set until

BBATSEN is sensed via a subsequent PWRGOOD assertion.

BBA TSEN also prov ides a pow er-on-reset signal f or the R TC when an

RTC backup battery is applied for the first time.
VCC_ANLG — Power Analog Power Supply for the analog circuits (PLLs).
VCC_CORE — Power Power Supply for the ÉlanSC520 microcontroller core logic.
VCC_I/O — Power Power Supply to the I/O pad ring.
VCC_RTC — Powe r Power Supply for the real-time clock and 32-kHz oscillator.
GND — Power Digital Ground for the remaining ÉlanSC520 mic rocontroller core logic.
GND_ANLG — Power Analog Ground for the analog circuits.

2-14 Élan™SC520 Microcontroller User’s Manual

CHAPTER

SYSTEM INITIALIZATION

3

3.1 OVERVIEW

This chapter provides information and guidelines for initializing the ÉlanSC520
microcontroller. Se veral source code e xamples of inf ormation described in this chapter are
avail able on the AMD web site. This CodeKit software is tested source code for e xample
applications. To obtain this software, as we ll as other product inf ormation and tools, access
the AMD home page at www.amd.com and follow the Embedded Processors link.

From a software perspective, the types of systems that can be developed with the
ÉlanSC520 microcontroller fall into two broad categories, native embedded systems and
systems that use a BIOS

Of course, these are not the only types of syst ems that can be built with the ÉlanSC520
microcontroller. It is quit e possible to dev el op hybrid systems that have a BIOS but do not
run a “desktop” operating system like Windows
many possible w ays to in itialize the ÉlanSC520 microc ontroller, any ini tialization sequence
can be derived from the following two techniques.

1

.

®

, DOS, Unix, or Linux. While ther e are

■ System initialization with a BIOS

■ System initialization fo r a native embedded system without a BIOS

For systems with a BIOS , most, or all, of the system initial ization is done by the BIOS while
the system is running in real mode. After init ialization, the BIOS loads an oper ating system
or application from nonvolatile media, which is generally a disk drive, but could be Flash
memory or other media. The operating system or applic ation begins operating in real mode
and then may mak e its own trans ition into protected mode . Windows

are examples of such oper ating systems. Real-time oper ating systems can also operate in
this manner.

BIOS initialization can be comple x. Some BIOS products ma y make a temporary transition
into protected mode to perf orm certain operations and then rev ert back to real mode, bef ore
passing execution to an operating system or application. Such behavior is dependent on
how the BIOS is written and the features provided and are beyond the scope of this
discussion.

For embedded syst ems, the i niti ali zation sequenc e is us ually muc h simpl er and gen eral ly
occurs primarily in protected mode. In this scenario , the processor comes up from a re set
and transitions into protected mode as soon as possible. The only real-mode code in the
system is the code required to jump from the reset vector and the ex ecute code that causes

the ÉlanSC520 microcontroller to transition into protected mode.

3.1.1 Native Embedded Initialization Sequence

Many systems designed wit h the ÉlanSC520 microcontroller are native embedded systems
that do not have a BI OS. The softwar e architecture f or such systems can tak e many forms.

95 and Windows NT®

1. A BIOS is a PC software component. It is a set of real-mode code that is responsible for
initializing the system and providing a standard set of I/O and system services used by an
operating system and application level software. These services are provided via a standard
interface.

Élan™SC520 Microcontroller User’s Manual 3-1

System Initialization

Some use a commercial real-time operat ing system ( R T OS), a custom R TOS, or a simple

‘main loop’ or non-preemptive executive. In general, the executiv e or RTOS generally
interfaces to the hardware using a hardware dependent layer called a

1

package (BSP)

.

board support

In general, the system initialization flow for a native embedded system follows this
sequence:

1 < Reset event >
2 Near Jump to reset handler from the reset vector
3 Switch to simple protected mode
4 Determine the cause of the reset
5 Initialize the DRAM controller and DRAM. Size the DRAM
6 Setup a Stack and begin execution from “C” code

7 if (NOT Execute-In-Place) then
8 Copy the Operating System to DRAM
9 Jump to the operating system’s entry point
10 Set up the Global Descriptor Table (GDT), Local Descriptor Table (LDT),

Interrupt Descriptor Table (IDT), fault handlers, page tables, and a
Task State Segment (TSS) for the operating system, application or

executive.
11 Set the processor speed
12 Configure the GP bus timings
13 Configure the pin multiplexing
14 Configure the GP bus chip selects
15 Configure the Programmable Address Region (PAR) registers
16 Configure the interrupt mappings
17 Configure the programmable I/O (PIO) pins
18 Configure the PCI bus controller and arbitration mode
19 Initialize a periodic timer interrupt (if necessary)
20 Now, the BSP can initialize devices external to the ÉlanSC520

microcontroller and otherwise continue to start the operating system,

I/O drivers and application.

In the above e xample , th e s witch to simple prot ected mode (line 3) sets the pr ocessor CS
register and the CS descriptor cache. This disables the redirection of the reset region to

the reset segment (see “Reset Vector and Reset Segment” on page 3-5 for more
information).

In line 3 abov e, the term

simple protected mode

means that the protected mode environment
(GDT, LDT, IDT, and TSS) is the simplest kind possible. For example, both the LDT and
IDT can be empty and the TSS and GDT can contain minimal inf ormation. Or, alternativ ely ,
the IDT can be empty. This means that exceptions cannot be handl ed, b u t thi s should not
be a problem f or the short period that the initialization code runs. More importantly , the TSS
and GDT for simple protected mode can be contained in read-only memory (usually Flash)
and do not have to be created at runtime. Once the DRAM is operational, then more
extensiv e GDT, LDT, and IDT tables and one or more appropriate TSS can be setup in
DRAM.

1. There is no standard term for this component. Other terms for BSP are OEM Adaptation
Layer (OAL), Hardware Adaptation Layer (HAL), or Porting Layer. A BSP is like a BIOS, but is
almost always unique to a specific executive or RTOS. This is especially true for comercially

available RTOS products. A BSP for one vendor’s RTOS generally does not work with products
from another vendor. Also, where a BIOS is most often a 16-bit real-mode entity, a BSP is
usually a 32-bit protected mode entity. Lastly, operating systems and applications always
communicate with a BIOS using software interrupts (or other run-time mechanisms), but a BSP
is often linked directly to an executive or application to form a single executable and is called
directly using the CALL instruction.

3-2 Élan™SC520 Microcontroller User’s Manual

System Initialization

Some embedded systems execute from read-only memory (usually Flash) and only use
DRAM for data storage. This style of system architecture is supported by most RTOS
products. This i s reflected in line 7. Systems that e xecute o ut of Flash memory do not need
to copy the operati ng system and/or application to DRAM.

Another interesting point i s that once the DRAM controller is initializ ed, then the initialization
code can setup a stac k and fi nish the r eset of i ts work in a high-le v e l langu age (usuall y C).

3.1.2 BIOS Initialization Sequence

In contrast to a nativ e emb edded system, the flow of system initializati on with a BIOS
generally follows this sequence:

1 < Reset event >
2 Near Jump to reset handler from the reset vector
3 Map the Memory-Mapped Configuration Region (MMCR) to an address below

0010FFEFh (real-mode address limit)
4 Determine the cause of the reset
5 Initialize the DRAM controller and DRAM. Size the DRAM, record in CMOS
6 Copy the BIOS into DRAM (shadowing)
7 Execute a Far Jump within the BIOS code to start execution out of the

shadowed BIOS copy instead of the copy in ROM
8 Set up basic interrupt handlers for processor faults
9 Detect the CPU ID and display on the console
10 Set the processor speed
11 Configure the GP bus timings
12 Configure the pin multiplexing
13 Configure the GP bus chip selects
14 Configure the Programmable Address Region (PAR) registers
15 Configure the interrupt mappings
16 Configure the programmable I/O (PIO) pins
17 Configure the PCI bus controller and arbitration
18 Now, the BIOS can continue with standard PC-style syst em initialization

There are some important contrasts between the steps for a system with a PC BIOS and
those for a native embedded system.

■ Steps 1 through 6 are done in real mode whil e ex ecuting fr om the reset segment before

ex ecut ing the firs t Far Jump (JMP) instruction. This is in cont ra st t o the in iti aliz ation for
a native embedded system, which transitions to simple protected mode before these
steps.

■ The Memory-Mapped Configuration Region (MMCR) needs to be mapped to a region

below 00100000h so i t is accessible by real-mode softw are. 32-bit protected-mode native
embedded systems do not need to move the MMCR.

■ The remainder of the system initialization is done in real mode from the BIOS image

running from DRAM. This is in contrast to an embedded system, which does all of its
initialization from 32-bit protected mode (running either from DRAM or Flash).

3.1.3 Memory-Mapped Configuration Region (MMCR)

The Memory-Mapped Configuration Region (MMCR) is a 4-Kbyte area located at ph ysical
address FFFEF000h and contains various configuration and control registers for the

ÉlanSC520 microcontroller. Configuring and control li ng ma ny of the device’s features
requires accessing the MMCR registers. System initializat ion code f or a nativ e embedded
system can access this region dir ectly because most (o r all) initial ization tak es place f rom
32-bit protected mode.

Élan™SC520 Microcontroller User’s Manual 3-3

System Initialization

In contrast, real-mode code cannot access physi cal memory above 0010FFEFh (the real­mode addressing limit), and thus cannot access the default location of the MMCR. This
problem is easily resolv ed by programming the Configuration Base Address (CBAR) register
(Port FFFCh) to place the MMCR at an address somewhere below the real-mode
addressing limit. This allo ws real-mode initialization code to directly access the MMCR.
This is done in step 3 of the BIOS initiali zation sequence.

Note: Progr amming the
at an address other than its defa ult. Howe ve r , the MMCR region is alwa ys accessib le at its
default location of FFFEF000h, regardless of how the CBAR register is programmed.

3.1.4 Reset Event

The ÉlanSC520 microcontroller has three primary classes of resets.

■ System reset (often called a hard reset or power-on reset)

■ System reset with SDRAM retention (called programmable reset)

■ Soft reset (often called warm start)

For more infor m ation on resetting the ÉlanSC520 microcontroller, see Chapter 6, “Reset
Generation”, and “Initialization” on page 7-5.

Often, systems have a hardware reset button or other external devices that can cause a
reset. For the Élan SC520 microcontroller, all of these cause a system reset. Howe ver, there
are many wa ys to implement e xt ernal reset logic. After a re set (of an y kind), boot sof tware
can determine what caused the reset by examin ing various status bits.

A common and effect iv e method of han dling a reset is to determine the cause of the r eset
and record the ev ent in the CMOS memory , or in some other non-vol atile memory such as
an EEPROM, non-volatile DRAM, or Flash. Debugging or diagnostic software could then
examine and report the causes of the last f e w resets. This can be v ery helpful when trying
to determine the cause of system problems. Note that the system could record other
information as well; the time and date of the reset event is a good example.

Configuration Base Address (CBAR) register

can place the MMCR

When a system reset occurs ( regardl ess of the sour ce) i nt ernal registers and logi c b l oc ks
are set to their pow er-on reset stat e. Theref ore, i f a system reset occurs , the boot soft ware
must initialize the system from scratch.

There is one except ion to thi s, called

programmable res et

. This function is enab led via the
PRG_RST_ENB bit in the Reset Configuration (RESCFG) register (MMCR offset D72h).
If this bit is set, assertion of the PRGRESET pin, SYS_RST bit, watchdog timer system
reset ev ent, or AMDebug tec hnology s ystem reset e v ent while PWRGOOD is a sserted will
result in a system reset in which the SDRAM configuration (SDRAM type , number of banks,
refresh rate, etc.) is maintained so that the contents of SDRAM are preserved. SDRAM
controller parameters retai ned include the SDRAM type, number of banks, refresh rate,
and signal drive strength. This feature allows the system to be reset while guaranteeing
that the contents of SDRAM are not disturbed. This can be ve ry val uable for system
debugging or for systems that require minimal startup time. This reset condition can be
detected by software. Note that, once programmable reset has been enabled, all system
resets other than PRWGOOD deassertion are converted to this type.

When a soft reset occurs , t he syst em ma y be abl e to restart if the oper ating sys tem sa v ed
enough state information. For example, an old 80286-style operating system (e.g., OS/2)
causes a processor reset in order to return to real mode and call 16-bit BIOS routines.

Note: It is important to understand that, for most systems, a soft reset does not need to
be handled much diff erently than a system res et. For e xample, a system that d oes not need

3-4 Élan™SC520 Microcontroller User’s Manual

System Initialization

to explicitly perform a soft restart will simply cause a system reset when a soft reset is
detected.

Note that the watch dog timer can generate an interrupt (maskable or non-maskable) or a
system reset, or both. Handling watchdog timer time-outs can be comple x. For more

information on how the WDT operates, see Chapter 19, “Watchdog Timer”.

3.1.5 Reset Vector and Reset Segment

Immediately after a hard or soft reset, the Am5x86 CPU core begins executi on in real mode
at the address F000:FFF0. This real-mode address is called the
reset vector is a real-mode addr ess, it is a redirection of the ph ysical address FFFFFFF0h,
which is located at the top ph ysical address of the memory device selected by BOOTCS
This device is call ed the

After a hard or soft reset, the 64-Kbyte physical address space from FFFF0000 to
FFFFFFFFh (resident in the boot R OM device) is redirected into real-mode address space
from F000:0000 to F000:FFFF. This real-mode region is called the
region in the boot ROM de vice is called the
is called the

This redirection is not performed by the addressing unit, but is an artifact of the values
programmed into the CS descriptor cache b y the CPU at reset time. After any reset, the
CPU core sets the base value of CS Descriptor Cache register to FFFF0000h with a limit
of 0000FFFFh (64 Kbytes). The processor CS:EIP register pair is set to F000:0000FFF0.

reset handler

boot ROM device

.

.

reset region

reset vector

reset segment

. The code that resides in this area

. While the

. The

.

The redirection works because, in real mode, linear addresses for code fetches are
generated by taking the offset in EIP and adding it to the contents of the base register in
the CS descriptor cache. Since the pagi ng unit is disab led at reset, these l inear addresses
map directly to physical addresses.

This simple mechanism causes both the redirection of the reset code region to the reset
segment and the first instruction fetch to occur from the reset vector.

Note that none of the other segment registers (and internal descriptor registers) ha v e this

only

behavior. This behavior is
descriptor cache. For more information on the configuration of the proce ssor registers at
reset, see the

#17965).
What this means is that the artificial reset segment redir ection is only ac tiv e unti l the CPU

ex ecutes a F ar Jump (JMP) instruction. This is because a F ar J ump instruction causes the
CS Segment register to be reloade d. When a segment regist er is loaded in real mode, t he
processor sets the value of the corresponding descriptor cache base register to 16 times
the new value of the segment register. Since the processor is running in real mode, the
internal CS Descriptor registers are set to their normal real-mode values.

Since the reset vector is at F000:FFF0, there are only 16 bytes before the end of the
segment. That is only enough for a few instructions. So, regardless of how much (or how
little) the reset code does , t he instruction at the rese t v ector mu st be a
reset region.

Am486® DX/DX2 Microprocessor Hardware Ref erence Manual

applicable to the CS Segment register and its internal

, 1994 (order

Near Jump

into the

For e xample, as sho wn in Figure 3-1, if the reset handler is large , then the initial Nea r Jump
could be to F000:0000.

Élan™SC520 Microcontroller User’s Manual 3-5

System Initialization

Figure 3-1 Initial Near Jump Example

F000:FFFF
F000:FFF0

Reset Vector

Near
Jump

Reset
Handler

F000:0000

F000:C000

The reset vector Near Jump is not required to jump to F000:0000. It can jump anywhere
into the reset segment. For example, if the reset handler code is only 16 Kbyte s in size, it
could jump to F000:C000, lea ving more room on t he boot ROM de vice f or other c ode. This
allows the reset handler to be placed right up against the reset v ector, thus using the space
in the boot ROM device more efficiently.

Note: F or debugging using AMDebug technolog y , not only should this first Ju mp instruction
be a Near Jump, it should be a Jump Near Indirect instruction, which is opcode FF/4. In­circuit emulation and debug software that uses the internal trace cache searches for this
opcode to aid in determining when the reset event occurred.

As much or as little of the system initializ ation code can take place in the reset handler
while the system is executing from the reset segment (i.e., before the first Far Jump
instruction). F or exa mple, a nativ e embedded system us ing a 32-bit only R T OS will merel y
setup the protected mode data structures , switc h to protected mode, and jump di rectly into
system boot code (the boot ROM device is the device selected by BOOTCS

In contrast, a system with a PC-st yle BIOS woul d init ializ e the SDRAM cont roller, shadow
the BIOS to SDRAM, and then jump to the BIOS.

3.2 CONFIGURING THE SDRAM CONTROLLER

After a system reset, the SDRAM controll er configuration regist ers are reset to their def ault
states. All the SDRAM controller banks and SDRAM refresh are disabled by default. For
details on how to enable the SDRAM controller and the SDRAM configuration, see

“Initialization” on page 10-29.
Note that the ÉlanSC520 microcontroller can be reset in a manner that preserves the

operation of the SDRAM controller. This condition can be detected and handled properly
by the SDRAM initialization code.

If the Error Correction Code (ECC) logic for SDRAM is enabled, ECC operation requires
that SDRAM and its associated ECC memory be initialized. This is accomplished by the
boot code, which must write to e v ery location in SDRAM. This process initializ es the ECC
SDRAM to reflect the proper error-chec king codes. If this procedure i s not performed, fal se

).

3-6 Élan™SC520 Microcontroller User’s Manual

System Initialization

errors will occur when writing data smaller than a 32-bit doubleword. For a more detailed

discussion of ECC, see “Error Correction Code (ECC)” on page 10-16.

3.3 IDENTIFYING THE CPU CORE

Information about the integrated Am5x86 CPU core is available by reading the processor
DX register after a system reset and by using the CPUID instruction at an y time. The CPUID
instruction is av ailable on later model 32-bit processors from all leadi ng x86 vendors and
allows progr ams to determine information about the CPU , including the manufacturer , cache
type, and av ailability of a floating point unit (FPU). By using t he CPUID instruction, software
can determine the type of CPU running the system. For example, software could detect
that it is running on an Am5

The ÉlanSC520 Microcontroller Revis ion ID (REVID) register (MMCR offset 00h) can be
used to identify the revision of the device itself.

A user-modifiable bit in the CPU’s Flags register called the ID bit indicates support of the
CPUID instruction. The ID bit is reset to 0 at CPU hard or soft reset for compatibility with
existing processor designs.

The results reported by the CPUID instruction reflect the state of the processor at the last
CPU hard or soft reset. If the CPU cache write mode or core cloc k speed is changed, and
if the CPU encounters a soft reset fol lowing the change, then a subsequent CPUID
instruction will report the altered condition of the processor (i.e., the state at the time the
soft reset occurred). Af ter a hard CPU reset, the ÉlanSC520 microcontrol ler always reports
the cache mode as write-back and the clock speed as 100 MHz.

86 CPU and perform the appropriate action.

x

The CPUID instruction returns encodings shown in Table 3-1.

Table 3-1 CPUID Codes

CPU Clock Speed Write-Back Mode Write-Through Mode

Am5
Am5

86 CPU

x

86 CPU

x

100 MHz
133 MHz

0494h 0484h
04F4h 04E4h

3.4 SETTING THE CPU SPEED

The ÉlanSC520 microcontroller is available at multiple clock speeds. By default, the
ÉlanSC520 microcontroller core comes up from a system reset running at 100 MHz. See
Chapter 7, “Am5x86® CPU”, for more information.

Note: Not all ÉlanSC520 microcontroller de vices support all Am5x86 CPU clock rates. The
maximum supported clock rate for a device is i ndicat ed b y the part number printed on th e
package. The cloc ki ng circuitry can be prog rammed to run the de vice at higher than r ated
speeds. Howe v er , if an ÉlanSC520 microcontroller i s programmed to run at a higher clock
speed than that for which it is r a ted, then erroneous operation will result, and physical
damage to the device may occur.

3.5 CONFIGURING EXTERNAL GP BUS DEVICES

Programming the ÉlanSC520 microcontroller to support external peripherals on the GP
bus requires three steps.

1. Program the GP bus timing mechanism to control the b us timings f or the device . This is

done first so that the initial access to the device (after the chip selects and PARs are
programmed) will funct ion properly. The GP bus timings and bus cycles are discussed
in “Bus Cycles” on page 13-16.

Élan™SC520 Microcontroller User’s Manual 3-7

System Initialization

2. If needed, program the PIO pin logic to map the GP bus chip select signal and other

control signals to a physical pin.

3. Program a P AR register to map the external peripheral into physi cal address space and

to configure a chip select for the device.

For peripherals connected externally to the GP bus, the Programmable Address Region
registers control where they are mapped into the I/O or memory address space.
Programming and using these registe rs is discussed in Section 3.7.

3.6 CONFIGURING THE PIN MULTIPLEXING

The ÉlanSC520 microcontroller has se veral pins that are multiple xed to two functions. There
are no pins that hav e three functions. Most of the pins that are multiplexed are p rogrammable
input/output pins (PIOs).

To program a pin that is multiplexed with a PIO, its cor responding function bit must be set
in the PIO31–PIO16 Pin Function Select (PIOPFS31_16) register (MMCR offset C22h) or
the PIO15–PIO0 Pin Function Select (PIOPFS15_0) register (MMCR offset C20h).

Other pins with multiple programmable functions are all noted in Figure 2-2 on page 2-3.

3.7 CONFIGURING THE PROGRAMMABLE ADDRESS REGION (PAR) REGISTERS

The P AR regi sters provide a common progr amming interface t o configure physical memory
and I/O regions in an ÉlanSC520 microcontroller system. PAR registers are programmed
by atomically writing 32-bit v alues . See “Progr ammable Addres s Region (PAR) Registers”
on page 4-5 for more information on using the PAR registers. “Software Considerations”
on page 4-18 provides other important details.

The PAR registers are used to define four characteristics.

■ Target device

■ Attributes for the address region

■ Size of the address region

■ Start address for the region

It is important to note that the PAR registers are used to define

physical

address regions.
PAR registers are not used to define effective address regions or linear address regions.
For e xample, an ef fectiv e address (often called a logi cal or virtual address) gets transl ated
into a linear address by the Am5

86 CPU’s segmentati on unit. If the paging unit is enabled,

x

then linear addresses get translated into physical add resses and placed on the CPU’ s bus.
If the paging unit is not enab led, then the mapping from lin ear address to ph ysical address
is direct (one-to-one).

Depending on how your system is set up, driver software, system software and other
software that must be aware of physical addresses should be written to take the Am5

x

86
CPU addressing modes into account. This can be an e xtremely complex topic and is bey ond
the scope of this chapter.

The general format of the PAR registers is shown in Figure 3-2 on page 3-10. Provided as
a programming aid, Figure 3-3 on page 3-11 is a blank worksheet for calculating PAR
register values .

3-8 Élan™SC520 Microcontroller User’s Manual

System Initialization

3.7.1 Specifying Pages and Regions

For memory-mapped address regions, the Region Size/Start Address (SZ_ST_ADR) bit
field in the P AR regi sters specifies the number of 64-Kbyte or 4-Kb yte pages for the region.

Regions using a 64-Kbyte page size can have up to 2048 pages, for a maximum size of
128 Mbytes. Regions using a 4-Kb yte page size can hav e up to 128 pages, for a maximum
size of 512 Kbytes.

■ To specify the number of pages for a region, the value (page count minus 1) is

programmed into the SZ_ST_ADR field of the PAR register.

– For ex ample, to specify a 16-Kbyte region using a 4-Kbyte page size, the value 03h

(0000011b) would be programmed into bi ts 24–18 of a PAR register, i.e., one less
than the required number of pages.

– To specify a page count of one, all the bits in the SZ_ST_ADR field f or a PAR register

should be cleared to 0.

– To specify the maximum number of pages, either 2048 or 128, all the bits in the

SZ_ST_ADR field should be set to 1.

■ T o s pecify the 4-Kbyt e page size, the P age Siz e (PG_SZ) bit should be clear ed to 0. For

a 64-Kbyte page size, it should be set to 1.

The same holds true for GP bus I/O-mapped regions. The region size field specifies the
number of bytes in t he addressable region. F or exampl e, to specify a region size of 8 bytes,
the value 07h (0111b ) should be programmed into the SZ_ST_ADR field of the PAR register.

Note: F or GP bus I/O-mapped regions, the PAR registers’ PG_SZ bit is ignored. In gener al,
it should be cleared to 0 for GP bus I/O regions.

Élan™SC520 Microcontroller User’s Manual 3-9

System Initialization

Figure 3-2 Programmable Address Region (PAR) Register Format

Programmable Address Region Register

31–29 28–26 25 24–0

Target of the

PA R Window

(TARGET)

31 30 29 Target Device

0 0 0 Window disabled
0 0 1 GP bus I/O
0 1 0 GP bus memory
0 1 1 PCI bus (applies to

memory cycles to

PAR 0–PAR 1 only)
100BOOTCS
101ROMCS1
110ROMCS2
1 1 1 SDRAM

(ROM)

Attribute

(ATTR)

25 Memory Page Size

0 4-Kbyte memory page size on 4-Kbyte

1 64-Kbyte memory page size on 64-Kbyte

Memory

Cycle

When
[25]=0

Memory

Cycle

When
[25]=1

Pag e Size

(PG_SZ)

boundary, ignored for I/O cycles.

boundary, ignored for I/O cycles.

24–18 17–0 Size defines up to 128

Region Size

[6–0]

24–14 13–0 Size defines up to 2K pages

Region Size

[10–0]

Region Size/Start Address

Start Address

A[29–12]

Start Address

A[29–16]

(SZ_ST_ADR)

pages of 4-Kbyte size each,
on 4-Kbyte boundary, for a
512-Kbyte m aximum windo w
size.

of 64-Kbyte size each on 64­Kbyte boundary, for a 128­Mbyte maximum window
size.

If Target is GP bus

28 27 26 GP Bus Chip Select

0 0 0 GPCS0
0 0 1 GPCS1
0 1 0 GPCS2
0 1 1 GPCS3
1 0 0 GPCS4
1 0 1 GPCS5
1 1 0 GPCS6
1 1 1 GPCS7

I/O

Cycles

Only

24–16 15–0 Size defines up to 512 b ytes

Region Size

[8–0]

Start Address

A[15–0]

If Target is ROM or SDRAM

28 27 26 ROM/SDRAM Attribute

0 = Write-enabled region
1 = Write-protecte d region

0 = Cacheable region
1 = Noncacheable region

0 = Code execution permitted
1 = Code execution denied

with byte resolution in 64­Kbyte I/O space.

3-10 Élan™SC520 Microcontroller User’s Manual

System Initialization

Figure 3-3 Programmable Address Region (PAR) Register Worksheet

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Élan™SC520 Microcontroller User’s Manual 3-11

System Initialization

3.7.2 Address Region Attributes

The address region attributes (as specified in th e ATTR bit field of a PAR register) can be
used with ROM or SDRAM regions to control how the regions can be ac cessed. This section
includes some examples of how the attribut es can be used with SDRAM and R OM regions.

3.7.2.1 Write-Protect Attribute

When this feature is enabled for an address region in SDRAM or ROM, an interrupt is
generated when a write is performed to the region. This interrupt can be used to find
problems with errant software or to help debug Flash programming code.

3.7.2.2 Cacheability Control Attribute

The Cacheability Control Attribute bit in the PAR registers provides a simple mechanism
for controll ing the caching of memory regions. This mechanism is much easie r to use than
the Am5

For SDRAM regions, turning off caching can be useful f or regions that c ontain buff ers used
for DMA or for PCI bus mastering devices.

This feature is also useful for Flash regions. For some operations, it is necessary to turn
off caching for a Flash regi on. An example is when a Flash device needs to be erased or
programmed. Any t ime a Flash device’ s internal registers need to be read or written, cac hing
should be disabled for the de vice. F or example , the Flash sector erasing code nee ds to poll
the device to see when erases and other operations are complet e. If caching is not turned
off, then the sof tware will merely contin ue to read the value f rom the processor’ s cache and
not the correct v alue from the de vice . This is also true during the F lash progr amming write/
verify cycle. For more information, see page 12-12.

86 CPU’s paging unit.

x

3.7.2.3 Code Execution Attribute

Execution contr ol works in a similar manner to the Write-Protect Attribute bit. The difference
is that when this bit is set, any co de fetches b y the CPU to the defined region wi ll cause an
invalid opcode fetch fault to be generated. This is accomplished by returning an invalid
opcode to the CPU, instead of t he data resident in the device at the requested address.

This is very useful for debugging problems. Large areas of the address space can be
execute-protected. For example, the Flash for a file system could be protected from code
execution. Data reads and writes for the Flash file system would happen normally. But, if
a code erroneously jumped into this data area, an invalid opcode fet ch fault would be
generated immediately.

3.7.2.4 Performance Considerations

It is possible to control the same att ributes that the PAR registers provide using the native
mechanisms in the Am5

86 CPU core. For example, 4-Kb yte pages can be write-protected

x

using the paging unit and paging tab les. Noncached regions can also be created using th is
mechanism. Execution protection can also be perf o rmed using a segmented code model
and descriptor attributes.

Using the native x86 mechanisms will work, but using the address region attribut es in a
P AR register is easier and pr ovides higher performance. If the CPU’ s paging unit is enabled,
the entire system takes a small performance hit because all linear address must be
translated to physical address. Also, defining nonexecutable regions is very difficult to do
and requires 48-bit code point ers (huge pointers) and a fully seg mented 32-bit code model.
This is a high price to pay to ob tain ex ecute-only regions. These p erformance penalties are
not incurred when using the ÉlanSC520 microcontroller’s address region attribute
mechanism.

3-12 Élan™SC520 Microcontroller User’s Manual

System Initialization

3.7.3 PAR Register Priority

The PAR register mechanism is a very flexible and useful one. It is designed to allow the
system programmer to easily program the address decoding and set attributes for
addressable regions . One featur e of the PAR register system that ma y not be ob vious from
the examples included in this chapter is that the PAR registers hav e a priority mechanism.
The highest priority PAR register is PAR 0 and the lowest priority register is PAR 15. This
feature is not relevant unless two (or more) PAR regions overlap. If they do overlap, then
the higher priority PAR register takes precedence.

The PAR registers are used to modify and add to the default system addressing (see
Table 4-4 on page 4-4). Note that the system can function quite well with all of the PAR
registers disabled. For example, a system could start-up, use a PAR register to copy the

1

contents of Flash to SDRAM

, jump to the code in SDRAM, and then disable the PAR
register used for the copy . With all the P AR register s disabled, the normal address resolution
priorities in the system govern addressing of physical devices.

3.7.4 External GP Bus Devices

Devices on the GP b us can be addressed in two w a ys. Each i s controlled b y progr amming
the PAR registers.

■ By chip select, mapping the device into memory or I/O space

■ Devices can do their own memory or I/O address decoding.

Programming a PAR register with the GP bus as the target i s required to cause memory or
I/O cycles to be forw arded to the external GP bus. This is true for devices that use chip
selects and devic es that decode their own address (generate their own chip selects).
Programming a PAR register is necessary because, by default, memory and I/O cycles
generated by the Am5

86 CPU that are not decoded by an internal GP bus peripheral or

x

memory resources (like SDRAM, ROM, and the MMCR registers) go to the PCI bus.
For a de vice on the e xternal GP b us, prog ramming a PAR register configures the f ollo wing

characteristics:

■ Target device field—For either a GP bus memory-mapped cycle or an I/O cycle

■ Attribute field—For the particular GP bus chip select to which the device is attached

■ Memory page size field— Most peripherals use a 4-Kbyte granularity. Peripherals that

have v ery large memory address spaces, such as SDRAM or ROM, mi ght need to use
a 64-Kbyte granularity.

■ Region size and start address

For a de vice that requires a chip select from the ÉlanSC520 microcontroller, t he chip select
must be mapped to a physical pin usi ng the PIO registers. For devices that do their own
address decoding, the PAR register must still be programmed, and the chip sel ect should
be chosen; howe v er , the chip select from the PAR register does not need to be mapped to
a physical pin.

Note: All of the internal peripherals on the GP bus are decoded at fixed locations. The
locations for these peripherals cannot be changed by programming a PAR register. For
example, the int e rnal real-ti m e clock cannot be moved to a different location. No PAR

registers are required to access any of the internal peripheral devices on the ÉlanSC520
microcontroller

1. This is one way to shadow a BIOS to DRAM.

.

Élan™SC520 Microcontroller User’s Manual 3-13

System Initialization

3.7.4.1 Single Device (an A/D Converter) Using One Chip Select

In this example, an A/D converter has four 16-bit registers that need to be mapped into
I/O space on GPCS5

at I/O address 0500h. As shown in Table 3-2, the value to program

into a PAR register in this case is 34070500h.

Table 3-2 Example PAR Programming: Single Device Using One Chip Select

Bit Field Value Meaning

Target Device 001b GP bus I/O space
Attribute Field 101b GPCS5
Page Size 0b Clear to 0 (this bit not applicable to I/O space)
Region Size 7h Specifies an 8-byte region size
Start Address 0500h Physical address 0500h

3.7.4.2 Single Device That Performs Its Own Decode

In this example, an external memory-mapped 16-color 480 x 320 pixel LCD controller
performs its own add ress decoding. It needs a 128- Kbyte windo w mapped at 000C0000h.
A chip select must be used (specifi ed in the ATTR bit field of the PAR register), but it does
not need to be mapped to an ex ternal pin. GPCS7

is used here. As sho wn in Table 3-3, the

value to program into a PAR register in this case is 5E00400Ch.

Table 3-3 Example PAR Programming: Single Device That Performs Its Own Decode

Bit Field Value Meaning

Target Device 010b GP bus memory space
Attribute Field 111b GPCS7
Page Size 1b 64-Kbyte granularity
Region Size 1h Specifies two 64-Kbyte pages for a 128-Kbyte region size
Start Address 000Ch Physical address 000C0000h

3.7.4.3 Multiple Devices On One Chip Select

A single PAR register can be programmed for a larger range than is needed by a single
peripheral. For example, consider a bank of 16 memory-mapped A/D converters, each of
which has four 16-bit regist ers. An external P AL is prog rammed to do the address decoding
for each individual A/D converter. The converters will be memory-mapped to a range of

00020000–0002003Fh. The PAL generates the chip selects for each of the four con verters
by watching f or the appropriate memory read and write cycles and is qualified from GPCS2
from the ÉlanSC520 microcontroller. As shown in Table 3-4, the value to program into a
PAR register in this case is 48000020h.

Table 3-4 Example PAR Programming: Multiple Devices on One Chip Select

Bit Field Value Meaning

Target Device 010b GP bus memory space
Attribute Field 010b GPCS2
Page Size 0b 4-Kbyte granularity
Region Size 0h One 4-Kbyte page
Start Address 20h Physical address 00020000h

3-14 Élan™SC520 Microcontroller User’s Manual

3.7.5 PCI Bus Devices

Normally, devices on the PCI bus are mapped into memory space that is above the

configured amount of DRAM and just under 4 Gbytes (FFFEFFFFh). The ÉlanSC520
microcontroller’s address decode logic forwards all access to these memory locations to
the PCI bus.

Normally , memory cycles below the top address used b y SDRAM are forwa rded only to the
SDRAM controller , or to the GP bus if a PAR register is appropriately programmed. Ho wever ,
for Windows and DOS compatibility , some PCI peripherals need to be mapped into SDRAM
space. These regions usually fall below the real-mode address limit ( physical address
0010FFEFh
based network adapters. To allow this, the first two PAR registers support the PCI bus as
a target. Note PCI as a target can only be specified in PAR 0 and PAR 1.

For such devices, a PAR register must be programmed that allows addresses lower than
the highest SDRAM address to be forwar ded to the PCI bus. This is in addition to the normal
PCI bus device co nfiguration. The VGA contr oller example in Section 3.7.5.1 illustr ates this.

T ypicall y , all I/O space accesses ab ove the 1-Kb yte boundary are forwarded t o the PCI bus,
and all I/O space accesses below the 1-Kbyte boundary are forwarded to the GP bus.

■ With some minor exceptions f or the CBAR and PCI configuration registers, the I/O space

above the 1-Kbyte boundary can be redirected from the PCI to the GP bus using PAR
registers.

). Devices that can require thi s incl ude PCI-based VGA video cards and PCI-

System Initialization

■ The IO_HOLE_DEST bit in the Address Decode Control (ADDDECCTL) register (MMCR

all

offset 80h) can be programmed to allow

I/O space addresses below the 1-Kbyte

boundary that are not assigned to internal peripherals to be forwarded to the PCI bus.

■ Note that PAR registers can still be mapped in the lower 1-Kbyte I/O space to override

the IO_HOLE_DEST bit. This way, I/O devices in the lower 1-Kbyte space can reside
internally to the ÉlanSC520 microcontrol ler, on the external GP-Bus, and on the PCI bus.

3.7.5.1 VGA Controller on the PCI Bus

A VGA video controller’s 128 Kbytes of memory is normally mapped from 000A0000–
000BFFFFh (physical addresses). So, to support a PCI-based video controller, P AR 0 or
PAR 1 would need to be programmed t o 7200400Ah. This conf igures PAR 0 or P AR 1 with
the characteristics shown i n T able 3-5. The attribute fields are ignored f or the PCI bus target.
PCI regions are always writable, executable, and noncached.

Table 3-5 Example PAR Programming: VGA Controller on the PCI Bus

Bit Field Value Meaning

Target Device 011b PCI bus
Attribute Field 000b Not applicable
Page Size 1b 64-Kbyte granularity
Region Size 1h Specifies two 64-Kbyte pages for a 128-Kbyte region size
Start Address Ah Physical address 000A0000h

A PCI VGA video adapte r also requires PCI I/O from addresses 03B0–03BBh and 03C0–
03CFh. A PAR register is not requi red to map th ese I/O locations t o PCI space, but ins tead
the IO_HOLES_DEST bit must be set in the Address Decode Control (ADDDECCTL)

all

register (MMCR offset 80h). Thi s has the eff ect of mapping

external I/O accesses to PCI

space rather than to the GP bus. If t here are no external GP b us I/O devices , then no further

Élan™SC520 Microcontroller User’s Manual 3-15

System Initialization

P AR programming is required to support this configurati on. Note that the internal I/O devices
will still be correctly accessed when the IO_HOLES_DEST bit is set.

Howev er , if any e xternal GP bus device requir es I/O addresses, then a PAR register will be
required to allow access to this devi ce. As an example, assume an external 16550 UART
is used to implement a COM3 port.

The standard I/O locations for COM3 are 03E8–03EFh. As shown in Table 3-6, a PAR
register will be required with a setting of 340703E8hto enable external GP bus accesses
to this I/O range. In this e x ample, GPCS5
If another GPCS

x is required, then appropriate changes should be made to the P AR register

is used as a chip enab le f o r the external device.

setting.

Table 3-6 Example PAR Programming: COM3 with VGA Present on the PCI Bus

Bit Field Value Meaning

Target Device 001b GP bus I/O space
Attribute Field 101b GPCS5
Page Size 0b Clear to 0 (this bit not applicable to I/O space)
Region Size 7h Specifies an 8-byte region size
Start Address 03E8h Physical address 03E8h

3.7.5.2 Network Adapter for Remote Program Loading

A memory-mapped network adapter will usually reside in PCI space that is far above the
real-mode address limit. How ever , to perform Remote Progr am Loading (RPL), often called
network boot, ov er a net work, the 16-bi t BIOS needs to use the netw ork adapter. T o a v oid
writing 32-bit protected-mode BIOS code, PAR 0 or P AR 1 can be used to place a memory­mapped network adapter abov e the real-mode address limit. For thi s example, it is assumed
that the network adapter has 16 Kbytes of address space that needs to be placed at
000B0000h. This area is noncacheable because it is PCI address space. As shown in
Table 3-7, the value to configure PAR 0 or P AR 1 for this configuration is 600C00B0h.

Table 3-7 Example PAR Programming: Network Adapter for Remote Program Loading

Bit Field Value Meaning

Target Device 011b PCI bus
Attribute Field 000b Not applicable
Page Size 0b 4-Kbyte granularity
Region Size 03h Specifies four 4-Kbyte pages for a 16-Kbyte region size
Start Address B0h Physical address 000B0000h

Note that most network adapters will also require a small amount of PCI I/O space. The
location of this I/O space can usually be changed through a PCI configuration register on
the adapter and can be assigned b y an operating system through plug and pla y functionality .
Usually , this address can be set to any value and is t ypically above the 1-Kb yte I/O boundary
affected b y the IO_HOLES_DEST bit. Since I /O accesses abo ve 400h are always sent to
PCI space (unless ov erridden by a P AR register to go to the

GP bus), no special programming

is needed to allow I/O accesses for a typical PCI network adapter.

3-16 Élan™SC520 Microcontroller User’s Manual

System Initialization

3.7.6 External ROM Devices

The PAR registers can also be used to define the addressing f or R OM devices sel ected by
BOOTCS
devices , and ot her similar devices.

, ROMCS1, and ROMCS2. ROM devices include true ROMs, EEPROM, Flash

It is important to note that the top 64 Kbytes of the ROM de vice select ed by BOO TCS
boot device chip select) is

always

mapped to the physical addresses from FFFF0000–
FFFFFFFFh. This area is called the reset region. The reset region is cached, executable,
and not write-protected. This 64-Kbyte mapping is fix ed and alwa ys activ e, ev en if the boot
ROM device is mapped to another address using a PAR register. ROM devices attached
to BOOTCS

, ROMCS1, or ROMCS2 can be mappe d anywhere in ph ysi cal address space

below 40000000h (1 Gbyte).

3.7.6.1 Boot ROM Device Mapping for BIOS Shadowing

A 512-Kbyte Flash device is a common boot ROM device for systems with a BIOS. One
way to shad o w the BIOS is to map it belo w 00100 000h so t hat it can be acce ssed b y r eal­mode code. This is easily done wi th a single P AR regi ster. F or shadowing purposes, a good
place to park the boot ROM de vice is at 00001000h, whi ch is just abov e the interrupt vector
table. The v alue 89FC0001h configures the PAR register as shown in Table 3-8.

Table 3-8 Example PAR Programming: Boot ROM Device Mapping for BIOS Shadowing

Bit Field Value Meaning

Target Device 100b BOOTCS
Attribute Field 010b Write enable, noncacheable, code execution permitted
Page Size 0b 4-Kbyte granularity
Region Size 7Fh Specifies 128 4-Kbyte pages for a 512-Kbyte region size
Start Address 1h Physical address 00001000h

(the

3.7.6.2 Two Banks of Flash for an Execute-In-Place (XIP) Operating System

A system has eight 8-Mbit byte-wide Flash devices. Four are on ROMCS1 and four on
ROMCS2

. These devices will be mapped int o eight Mbytes of contiguous 32-bit address
space from 00400000–00BFFFFFh. This requires two PAR registers because two ROM
chip selects need to be used. This example uses PAR 4 and PAR 5. Note that in addition
to programming the PAR registers, the ROM chip selects need to be mapped to physical
pins.

The value A20FC040h for PAR 4 would setup ROMCS1

for the first bank of Flash. This
configures the PAR register with the characteristics shown in Table 3-9. The value
C20FC080h for PAR 5 would setup ROMCS2

for the first bank of Flash. This configures

the PAR register with the characteristics shown in Table 3-10.

Table 3-9 Example PAR Programming: First Bank of Flash for XIP Operating System

Bit Field Value Meaning

Target Device 101b ROMCS1
Attribute Field 000b Write enable, cacheable, code execution allowed
Page Size 1b 64-Kbyte granularity
Region Size 3Fh Specifies sixty-four 64-Kbyte pages for a 4-Mbyte region size
Start Address 40h Physical address 00400000h

Élan™SC520 Microcontroller User’s Manual 3-17

System Initialization

Table 3-10 Example PAR Programming: Second Bank of Flash for XIP Operating System

Bit Field Value Meaning

Target Device 110b ROMCS2
Attribute Field 000b Write enable, cacheable, code execution allowed
Page Size 1b 64-Kbyte granularity
Region Size 3Fh Specifies sixty-four 64-Kbyte pages for a 4-Mbyte region size
Start Address 80h Physical address 00800000h

3.7.7 SDRAM Regions

The P AR regi sters can also be used to define r egions of SDRAM and control the read/write,
cacheability, and execution attributes.

3.7.7.1 Setting Up DMA Buffers

Often PCI and GP bus devices use GP-DMA or PCI bus mastering to read and write data
directly from buf f ers in SDRAM. It is often useful to mark such b uffers as noncached. This

can be done using the CPU’s paging unit, but doing so is complex and may conflict with
how an operating system uses the page tables.

In any case, disab ling caching f or a region i s quite simple. Setting t he Cacheability Control
Attribute (bit 27) in a PAR register defines a buff er region. F or e xample, a 512-Kb yte region
can be defined to store transmit and receiv e buffers f or a fast Ethernet PCI controller . Since
this is a data-only area, the Code Execu tion Attribute (bit 28) is set.

Assuming that the region is l ocated at ph ysi cal address 00020000h, a PAR register would
be programmed with the value F9FC0020h. This configures the PAR register with the
characteristics shown in Table 3-11.

Table 3-11 Example PAR Programming: Setting Up DMA Buffers

Bit Field Value Meaning

Target Device 111b SDRAM
Attribute Field 110b Write enable, noncacheable, code execution denied
Page Size 0b 4-Kbyte granularity
Region Size 7Fh Specifies 128 4-Kbyte pages for a 512-Kbyte region size
Start Address 20h Physical address 00200000h

Of course, this is not absolutely neces sary. The cache controller in the ÉlanSC520
microcontroller alwa ys maintains the coherency between the cache an d SDRAM. For buff er
regions used by GP-DMA channels or PCI bus master s, disabling caching with a PAR
register is more efficient and pro vides better bus performance than allowi ng the CPU to
cache the buff er . This avoi ds the bus activity ( and latency) inv olved with k eeping the cache
and the SDRAM coherent.

3.7.7.2 Write-Protected Code Segments

In many embedded systems, all (or most) of the applications and operating system code
is contiguous in memory . In such cases, a si ngle PAR register can be used to write-protect
most (or all) of the code in a system. If errant code attempted to write to the protected
region, then an interrupt would be generate d. Note that the CPU completes the write cycle,
but the SDRAM or ROM controller (as appropriate) pre vents the write from occurring at the
device .

3-18 Élan™SC520 Microcontroller User’s Manual

System Initialization

Several actions could be taken, from merely preventing the write from taking place, to killing
the offending th read, or e v en restarting the system. Also , the e v ent could be recor ded and/
or reported to a debugging or diagnostic interface or console port. During debugging, a
breakpoint could be set at the front of the write-protect interrupt service routine.

Assuming the system code resides in the first 768 Kbytes of SDRAM at address 0, the
value E602C000h configures a PAR register with the values shown in Table 3-12.

Table 3-12 Example PAR Programming: Write-Protected Code Segments

Bit Field Value Meaning

Target Device 111b SDRAM
Attribute Field 001b Write disable, cacheable, code execution permitted
Page Size 1b 64-Kbyte granularity
Region Size Bh Specifies twelve 64-Kbyte pages for a 768-Kbyte region size
Start Address 0h Physical address 00000000h

3.8 CONFIGURING THE INTERRUPT MAPPING

The ÉlanSC520 microcontroller has very flexible interrupt routing and control capabil it y.
Each of the hardware interrupt sources can be mapped to any of the different interrupt
priority level s in the programmable inte rrupt controller (PIC).

In contrast to a basic PC , which has fixed interrupt mappings and operation, the ÉlanSC520
microcontroller has a very flexible interrupt management architecture. For full details on
this system, see Chapter 15, “Programmable Interrupt Controller”. The information in
“Interrupt Sources” on page 15-8 is of particular importance.

The followi ng sections discuss options to be considered for the software that configures
interrupts.

3.8.1 Edge-Sensitive or Level-Triggered Interrupts

Edge- and lev el-triggering can be progr ammed for eac h PIC or on an inter rupt-by-interrupt
basis.

For example, all of the interrupts on the Slave 2 interrupt contro ller could be programmed
for edge-triggered operation.

■ Setting the S2_GINT_MODE bit in the Interrupt Control (PICICR) register (MMCR offset

D00h) allows the LTIM bit in the Slav e 2 PIC Initiali zation Control W ord 1 (S2PI CICW1)
register (Port 0024h) to control how interrupts are triggered for that controller.

■ If the S2_GINT_MODE bit is cleared, then the edge- or level-triggered nature is controlled

for each interrupt input to the PIC individually using the Slave 2 PIC Interrupt Mode
(SL2PICMODE) register (MMCR offset D04h).

3.8.2 Interrupt Mapping

Using the Interrupt Mapping registers , each inte rrupt source can be mapped to one of the
interrupt channels in the PIC block, the NMI interrupt, or can be disabled as an interrupt
input. The flexibility of the ÉlanSC520 microcontroller allows any interrupt source in the
system to trigger either a regular interrupt or an NMI.

Élan™SC520 Microcontroller User’s Manual 3-19

System Initialization

3.8.3 Interrupt Polarity

Each of the interrupt controllers can recognize either a Low-to-High edge-triggered or an
active High level-sensitive interrupt request. To support external devices that generate
active Low interrupt requests (either edge or level), a programmable inversion of each of
the external interrupt requests is available.

Many devic es generate a Low-going interrupt signal using an open-collector output. These

devices are easil y supported on the ÉlanSC520 microcontroller by set ting the appropriate
bit in the Interrupt Pin Polarity (INTPINPOL) register (MMCR offset D10h). F or example, if
such a device wer e connected to GPIRQ8, t hen setti ng GPINT8_POL in th e Interrupt Pin
Pola rity (INTPINPOL) register would p rogr am t he interrupt for a Low-going interrupt input.

It is important to ensure that the polarity values for all internal interrupt sources are
programmed correctly at reset time.

3.9 CONFIGURING THE PROGRAMMABLE I/O PINS

An important part of the ÉlanSC520 microcontroller initialization is configuration of the
programmable I/O ( PIO) pins. These are general-purpose I/O pins that c an be programmed
as inputs or outputs. When configur ed as an input, the state of the input can be read using
the PIOx_DATA bit in the PIOx Data register.

The PIO pins can also be configured as outputs by sett ing their corresponding direction
bits in the PIOx Direction registers.

3.10 CONFIGURING THE PCI HOST BRIDGE AND ARBITRATION

The PCI Host Bridge must be configured and initialized
enumeration and de vice configuration tak e place. There are two parts to the PCI host bridge
configuration: ÉlanSC520 microcontroller-specific configuration and normal PCI bus
configuration.

1. Configure the PCI host bridge.

a.Program the desired ÉlanSC520 microcontroller arbitration mode , including

concurrency mode and PCI bus master arbitration priorities, etc. See “Initialization”
on page 8-22, for more detailed information on arbitration.

b.Program the Prog rammab le Address Region (PAR) registers, if required. If there are

one or two V GA video cont roll ers , PAR 0 and PAR 1 may need to be programmed to
place the VGA gr aphics memory in SDRAM space at PC-compatible locations . PAR
0 and PAR 1 could also be used for other PCI peripherals (such as a network card)
that require mapping below physical address 00100000h. See Chapter 4, “System
Address Mapping”, for detail s on programming PCI bus memory space.

c.Program the ÉlanSC520 microcontroller -specific PCI host bridge configuration (write

posting, retry time-out counter, interrupts, etc.). Note that write-posting must be
disabled while operat ing in nonconcu rrent arbitr ation mode. See Chapt er 8, “System
Arbitration”, for further details on nonconcurrent mode arbitration.

d.Program the standard PCI bus configuration registers. See “Configuration Information”

on page 9-9 for more inf ormation.

before

PCI operation such as

2. Configure the external PCI bus devices.
In general, PCI host bridge configuration bits should not be changed except during a PCI

bus initializat ion after a system or programmable reset.

3-20 Élan™SC520 Microcontroller User’s Manual

System Initialization

3.11 DISABLING INTERNAL PERIPHERALS

Most applications will use the ÉlanSC520 microcontr oller’s internal UART dev ices and its
internal real-time clock (RTC). However, some applications might need to use external
devices mapped to these same I/O locations. To use external devices , the corresponding
internal device must be disabled. Thi s is necessary because these internal peripherals are
at fixed I/O locations and cannot be re-mapped. If any internal devices are disabled,
accesses to the I/O addresses f or these periphera ls are f orw arded t o the e xternal GP b us.

Disabling these peripher als turns off their add ress decoding, so that e xt ernally connected
peripherals can be used in their place. If the addresses cannot be externally decoded
without a chip select, a PAR register must be mapped to allow a chip select to be asserted
for these addresses.

Using external de vices in place of the internal ones might be necessary for sev eral reasons.
A common reason would be to use a multifunction external chip that has parallel ports,
serial ports, floppy disk controller, an RTC, and other devices.

■ The internal RTC can be disabled by setting the RTC_DIS bit in the Address Decode

Control (ADDDECCTL) register (MMCR offset 80h).

■ UART 1 and UART 2 can be disabled b y setting the UART1_DIS and UART2_DIS bits

in the Address Decode Control (ADDDECCTL) register.

Note that, if the internal peripheral s are disabled, the e xternal peripheral’ s interrupt signals
will need to be connected to external interrupt lines, which then need to be routed to the
appropriate interrupt channel. For example, if an external UART is used to replace UART
2 (as COM2), then its interrupt could be connected to GPIRQ8, which would then need to
be routed to interrupt priority P3.

Also, in thi s scenario, the pin used for GPIRQ8 would need to be configured as a general­purpose IRQ (the interface function for the pin, not its default PIO func tion) by setting the
PIO15_FNC bit in the PIO15–PIO0 Pin Function Select (PIOPFS15_0) register (MMCR
offset C20h).

Note: When the internal peripherals are disabled, they are still fully functional. Disabling

only

the peripherals disables the addr ess decoding

for that device . For example , if the R TC
is programmed to generate interrupts and then subsequently disabled, it will continue to
generate interrupts b ut will no longer be accessib le. Before d isabling an internal peripheral,
be sure to turn off its interrupts.

Élan™SC520 Microcontroller User’s Manual 3-21

System Initialization

3-22 Élan™SC520 Microcontroller User’s Manual

CHAPTER

SYSTEM ADDRESS MAPPING

4

4.1 OVERVIEW

The ÉlanSC520 microcontroller includes fl exible memory and I/O address decoding with
features for both real-time operating systems (RTOS) and systems requiring PC/AT
functionality for Windows
memory controllers, GP bus controller, and PCI host bridge controller. The ÉlanSC5 20
microcontroller provides the following memory and I/O address mapping options.

■ The default SDRAM map is linear space starting at 00000000h through the top of

SDRAM (defined by the total s ize of the SDRAM array, up to a maximum of 256 Mbytes).

■ The default boot ROM/Flash chip select (BOO TCS pin) is mappe d in a 64-Kbyte linear

region at the top of CPU memory space from FFFF0000–FFFFFFFFh, and this entire
ROM space can be redir ected through configuration r egisters (address translat ion is not
supported).

■ All configuration registers tha t do not reside in PC/AT I/O space or PCI configuration

space are memory-mapped and are located in a 4-Kbyte region in memory address
space from FFFEF000–FFFEFFFFh.

compatibility. Address decoding is distributed between t he

– This 4-Kbyte region is called the
– The MMCR can optionally be relocat ed on any 4-Kbyte boundary in the lower 1-Gbyte

region via an I/O mapped register called the Configuration Base Address (CBAR)
register (Port FFFCh).

– The default MMCR region in high memory (below the boot space) is visible even if it

is aliased via the Configuration Base Address (CBAR) register.

■ The default PCI bus map is contiguous space starting directly above the top of SDRAM

through 4 Gbytes, minus th e 68 Kb ytes for the boot ROM/Flash region and the MMCR.

■ 16 general-purpose Programmable Address Region (PAR) windows allow address

mapping for a variety of applications, including operating systems requiring x86 real
mode support. Each window allows any memory region in the lower 1-Gby te region to
be directed to the following resources:

– Any of three ROM chip-selects with the ability to appl y cac heabili ty, write-protection,

and nonexecutable region attributes
– Any of eight GP b us chip-selects f or external memory or I/O peripherals on the GP bus
– Two PAR registers allow cycles to be for warded to the PCI bus for applications that

require PCI space to be overlaid on top of SDRAM. All accesses above the top of

SDRAM to the top of 32-bit memory space are

(with the exc eption of the ROM boot space and memory-mapped configur ation space).

memory-mapped configuration region (MMCR)

automatically

forwarded to PCI bus

.

– Accesses in normal SDRAM space (low er 256 Mbytes) can also be redirected to R OM,

the GP bus, or the PCI bus.
– PAR windows can be created in the SDRAM region to allow noncacheable, write-

protected, and/or nonexecutable buffers.

Élan™SC520 Microcontroller User’s Manual 4-1

System Address Mapping

■ Integrated PC/AT compatible peripherals are direct-mapped in normal PC I/O space

(i.e., the prog rammable interrupt controller, programmable interval timer, GP bus DMA
controller , RTC , and U ARTs). All remai ning integrated periphera ls are memory-mapped
(the watchdog timer, software timer, GP timers, and SSI).

■ As a PCI target, the PCI bus host bridge decodes normal SDRAM address space,

allowing external PCI bus master access of the entire SDRAM space. PCI bus I/O
accesses from PCI masters are not decoded by the PCI host bridge.

4.2 REGISTERS

Address decoding is controlled by the configuration registers listed in Table 4-1 and
Table 4-2.

Table 4-1 Address Decoding Registers—Memory-Mapped

MMCR
Offset

Register Mnemonic

Address Decode Control ADDDECCTL 80h RTC disable, UAR T 1 and UART 2 disables , write

Address Function

protect violation interrupt enable, I/O hole
access destination

Write-Protect Violation Status WPVSTA 82h Write-protect violation interrupt status, master,

window number
Programmable Address Region 0 PAR0 88h General-purpose resource decoding
Programmable Address Region 1 PAR1 8Ch General-purpose resource decoding
Programmable Address Region 2 PAR2 90h General-purpose resource decoding
Programmable Address Region 3 PAR3 94h General-purpose resource decoding
Programmable Address Region 4 PAR4 98h General-purpose resource decoding
Programmable Address Region 5 PAR5 9Ch General-purpose resource decoding
Programmable Address Region 6 PAR6 A0h General-purpose resource decoding
Programmable Address Region 7 PAR7 A4h General-purpose resource decoding
Programmable Address Region 8 PAR8 A8h General-purpose resource decoding
Programmable Address Region 9 PAR9 ACh General-purpose resource decoding
Programmable Address Region 10 P AR10 B0h General-purpose resource decoding
Programmable Address Region 11 P AR11 B4h General-purpose resource decoding
Programmable Address Region 12 P AR12 B8h General-purpose resource decoding
Programmable Address Region 13 P AR13 BCh General-purpose resource decoding
Programmable Address Region 14 P AR14 C0h General-purpose resource decoding
Programmable Address Region 15 P AR15 C4h General-purpose resource decoding

Table 4-2 Address Decoding Registers—Direct-Mapped

Register Mnemonic

Configuration Base Address CBAR FFFCh Base address for the alias of the MMCR

4-2 Élan™SC520 Microcontroller User’s Manual

I

I/O
Address Function

registers

4.3 OPERATION

There are three types of system b us masters supported on the ÉlanSC520 microcontroller:
the Am5

As shown in Table 4-3, each of the three bus masters can access speci fic types of address
space.

86 CPU, the PCI bus, and the GP bus DMA controller.

x

System Address Mapping

■ The Am5

86 CPU and the PCI bus each implement s eparate memory and I/O address

x

space.

■ The PCI bus further specifies a separate space f o r device configuration registers.

■ The GP bus DMA controller supports fly-by transfers between GP bus devices and

SDRAM; therefore, as a bus master, it supports memory space only.

Table 4-3 Bus Master Address Spaces

Integrated

Bus Master and

Address Space SDRAM ROM

CPU Memory ✔✔✔✔ ✔ ✔

I/O ✔✔ ✔ ✔

PCI
Bus

GP-

DMA

Notes:

1. Accessed indirectly by the CPU via the PCI configuration registers in I/O space.

Memory ✔✔
I/O ✔

Configuration
Memory ✔

1

GP

Bus

PCI

Bus

PC/AT

Peripherals

Integrated

Non-PC/AT

Peripherals

Memory-

Mapped

Registers

CBAR

Register

The Am5x86 CPU and PCI bus definition support separate memory and I/O address spaces
(I/O space is limited to 64 Kbytes on the CPU). The

, further defines a separate space for configuration registers.

2.2

PCI Local Bus Specification,

Revision

The ÉlanSC520 microcontroller divides these address spaces as follows:

■ Memory space

– ROM/Flash space f or data and code storage using up to three chip selects (accessible

only by the CPU)
– SDRAM space for data and code storage
– GP bus memory space (accessible only by the CPU)
– PCI bus memory space (accessible only by the CPU and PCI bus masters)
– Internal memory-mapped configuration region (MMCR) registers (accessib le only by

the CPU)

■ I/O space

– Integrated PC/AT-compatible peripherals (accessible only by the CPU)
– Configuration Base Addr ess (CBAR) register (P ort FFFCh) to set the MMCR’s base

address (accessible only by the CPU)

Élan™SC520 Microcontroller User’s Manual 4-3

System Address Mapping

– GP bus I/O space (accessible only by the CPU)
– PCI bus I/O space (accessible by the CPU and PCI masters)
– PCI bus configuration space (accessible only by the CPU)

Table 4-4 summarizes the organization of memory and I/O address regions in the
ÉlanSC520 microcontroller.

Table 4-4 Memory and I/O Space Summary

Device Memory Space I/O Space

SDRAM • Linear space starting at 00000000h to top

of SDRAM (maximum 256 Mbytes)

• PAR registers define noncacheable,
write-protected, nonexecutable regions

ROM/Flash • BOOTCS

from FFFF0000–FFFFFFFFh
(64 Kbytes)

• PAR registers define noncacheable,
write-protected, nonexecutable regions

PCI Bus Normal Space • Default above SDRAM to top of memory

address space (4 Gbytes), minus boot
space (64 K bytes) an d MMCR (4 K bytes)

• Two PAR registers can define any region
that overlays SDRAM space

PCI Bus Configuration
Space

GP Bus Defined via PAR registers in lower 1 Gbyte Defined via PAR registers in lower 64

Integrated PC/AT
Peripherals

MMCR Registers • Defaults to 4-Kbyte region starting at

Configuration Base
Address (CBAR) Register

N/A 0CF8–0CFFh

N/A 0000h-03FFh

FFFEF000h

• CBAR can alias this to any 4-Kbyte
boundary in lower 1 Gbyte

N/A FFFC–FFFFh

mapped to CPU boot space

N/A

N/A

Any space not claimed by CBAR, PC/A T
peripherals, GP bus (via P AR registers),
or PCI configuration registers (0CF8–
0CFFh)

Kbytes, except for integrated peripherals’
I/O space

N/A

4.3.1 Programming External Memory, Buses, and Chip Selects

Programming the e xternal memory, buses, and chip selects on the ÉlanSC520
microcontroller is accomplished in three steps:

1. Configure the address space and any required attributes for the specified region.

2. Configure the timing, when applicable, and any required attributes of the interface.

3. For chip selects, enab le the function on the desired pin by programming the pin
multiplexing in the PIO registers.

This chapter describes how to complete step 1. Programming the required timing and
attributes of the e xternal interface (i.e. , SDRAM, ROM, GP bus, or PCI bus) i s accomplished
by writing to registers that contr ol these interfaces . Finally , f or chip selects, see Chapter 23,

4-4 Élan™SC520 Microcontroller User’s Manual

System Address Mapping

“Programmabl e Input/Output”, which describes enabling the actual progra mmable I/O (PIO)
pins that can be shared with other functions.

4.3.2 Programmable Address Region (PAR) Registers

Programmable Address Region (PAR) registers provide a common programming inter face
to configure memory space and I/O space regions in an ÉlanSC520 microcontrol ler system.
As referenced in Table 4-4, the PAR registers are primarily used to define the address
regions of ROM and GP bus, as well as to set attributes for ROM and SDRAM regions .

The first two PAR registers (P AR 0 and PAR 1) also allow the user to redi rect CPU accesses
that normally fall into SDRAM space to the PCI bus, for special cases that require this
functionality . The ÉlanSC520 microcontroller pro vides a total of 16 PAR registers to provide
the user with flex ibility in or ganizing memory space and I/O space in t he system. The y are
organized in a priority scheme starting with the lowest register ( P AR 0). Thus, if overlapping
regions are programmed, the low est number PAR register takes priority. The P AR registers
are 32 bits each and reside in the MMCR space.

Since the ÉlanSC520 microcontroller supports PC/AT-compatible peripherals , the regions
required for these peripherals are fixed in I/O space and are not relocatable via PAR
registers. This includes the GP b us DMA controller , the programmab le interval timer (PIT),
the programmabl e interrupt controller (PIC), the two 16550-compatible UARTs, the real­time clock (RTC), and the PC/AT port logic.

Figure 4-1 illustrates the layout of the 32-bit PAR register. Note that the registers are
organized in four sections, as follows:

■ The Target (TARGET) bit field defines the destination of the cycle (i.e., ROM, GP bus,

etc.).

■ The Attribute (ATTR) bit field allows memory regions to be programmed with speci al

conditions such as write-protection and n oncacheability f or R OM or SDRAM access or
selects a specific chip select for GP bus accesses.

■ The Page Size (PG_SZ) bit defines the size of each memory page within the regions.

■ The Region Size/Start Address

(SZ_ST_ADR) bit field is used to define both the
beginning of the region and the total size of the regi on (in conjunction with the Page Size
bit).

The PAR register is used to define only the actual address space f or the targets; it does
not control the parameters f or t iming and bus wi dth required f or ROM and GP b us de vices.
Those controls must be programmed independently in the ROM controller and GP bus
controller configuration registers.

Note: If a PAR window is configured for PCI, AND the CBAR register is programmed to
overlap with this PAR window, AND the PAR window is placed below the top of DRAM, the
MMCR is not given priority ov er the PCI access . Thi s configu r ation could r esult i n system
errors due to concurrence of both PCI and internal MMCR accesses.

Élan™SC520 Microcontroller User’s Manual 4-5

System Address Mapping

Figure 4-1 Programmable Address Region (PAR) Register Format

Programmable Address Region Register

31–29 28–26 25 24–0

Target of the

PA R Window

(TARGET)

31 30 29 Target Device

0 0 0 Window disabled
0 0 1 GP bus I/O
0 1 0 GP bus memory
0 1 1 PCI bus (applies to

memory cycles to

PAR 0–PAR 1 only)
100BOOTCS
101ROMCS1
110ROMCS2
1 1 1 SDRAM

(ROM)

Attribute

(ATTR)

25 Memory Page Size

0 4-Kbyte memory page size on 4-Kbyte

1 64-Kbyte memory page size on 64-Kbyte

Memory

Cycle

When

[25]=0

Memory

Cycle

When

[25]=1

Pag e Size

(PG_SZ)

boundary, ignored for I/O cycles.

boundary, ignored for I/O cycles.

24–18 17–0 Size defines up to 128

Region Size

[6–0]

24–14 13–0 Size defines up to 2K pages

Region Size

[10–0]

Region Size/Start Address

Start Address

A[29–12]

Start Address

A[29–16]

(SZ_ST_ADR)

pages of 4-Kbyte size each,
on 4-Kbyte boundary, for a
512-Kbyte ma ximum window
size.

of 64-Kbyte size each on 64­Kbyte boundary, for a 128­Mbyte maximum window
size.

If Target is GP bus

28 27 26 GP Bus Chip Select

0 0 0 GPCS0
0 0 1 GPCS1
0 1 0 GPCS2
0 1 1 GPCS3
1 0 0 GPCS4
1 0 1 GPCS5
1 1 0 GPCS6
1 1 1 GPCS7

I/O

Cycles

Only

24–16 15–0 Size defines up to 512 bytes

Region Size

[8–0]

Start Address

A[15–0]

If Target is ROM or SDRAM

28 27 26 ROM/SDRAM Attribute

0 = Write-enabled region
1 = Write-protecte d region

0 = Cacheable region
1 = Noncacheable region

0 = Code execution permitted
1 = Code execution denied

with byte resolution in 64­Kbyte I/O space.

4-6 Élan™SC520 Microcontroller User’s Manual

4.3.3 Memory Space

e

R

R

h

Memory space in the ÉlanSC520 microcontroller includes SDRAM, ROM, PCI bus, GP
bus, and the MMCR registers. A system memory map is shown in Figure 4-2.

■ The CPU has access to the entire memory space.

■ PCI bus masters and the GP bus DMA controller have access to SDRAM space only.

Characteristics of these memory spaces are defined in subsequent sections.

Figure 4-2 System Memory Map

4 Gbytes

BOOT ROM Space

MMCR Space

System Address Mapping

FFFFFFFFh
FFFF0000h

FFFEFFFFh
FFFEF000h

Notes:

The boot ROM device
connected to BOOTCS
defaults to a 64-Kbyte region
at the top of memory.

1 Gbyte

256 Mbytes

Dedicated

PCI Bus

Space

Default PCI Bus

Space

Can also be

retargeted to

ROM or GP bus

Default is SDRAM up
to amount of SDRAM

installed. Def ault is PCI

from top of configured

amount of SDRAM to

256 Mbytes

0

3FFFFFFFh

0FFFFFFFh

00000000h

This space defaults to PCI
bus memory space, but
portions can be redirected
to ROM or GP bus via PAR
registers. Regions with
noncacheable, write­protected, and/or execute­protected ROM attributes
can be also be specified
with the P AR registers. Any
unused regions in this
space default to PCI.

This area is not decoded by

the ÉlanSC520
microcontroller’s host
bridge as a target.

This space defaults to
SDRAM, but portions can b
redirected to ROM, GP bus,
or PCI bus memory via P A
registers; or redirected to
MMCR space, via the CBA
register. ROM or SDRAM
regions wi th n on c ac he a ble,
write-protected, and/or
execute privilege attributes
can be also b e specified wit
the PAR registers.

Accesses from PCI bus
masters are allowed to
installed SDRAM only.

Élan™SC520 Microcontroller User’s Manual 4-7

4.3.3.1 SDRAM Space

SDRAM space in an ÉlanSC520 microcontro ller system def aults to a linea r region starting
at the lowest 32-bit memory address (00000000h) and ending at the top of SDRAM, which
is defined by the amount of SDRAM populated in the system and programmed in the
SDRAM controller’s configuration registers.

The maximum amount of SDRAM supported in an ÉlanSC520 microcontroller system is
256 Mbytes, in various configurations between one and four physical banks. Once the
SDRAM configuration registers are programmed and the individual banks are enabled,
SDRAM is immediately accessible.

The ÉlanSC520 microcontroller allows speci al attributes to be appli ed to any region within
SDRAM space. These attributes are not required for normal operation, however some
applications can benefit from their use . Programming PAR registers for SDRAM access is

only

required

if special attributes must be applied to specific SDRAM regions, as des cribed

below. There are three attributes that can be applied to any SDRAM region:

■ Noncacheable regions

■ Write-protected regions

■ Code execution control

System Address Mapping

In a typical system configurat ion, an external PCI bus master has full access to the ent ire
SDRAM region. The address decoding logic in the ÉlanSC520 microcontroller’s PCI host
bridge automatically claims cycles to this address space on the PCI bus generated by
external PCI bus masters and causes them to be dir ected to SDRAM. PCI bus master
cycles that are f orwarded to the memory controller al wa ys result in an SDRAM cycle , ev en
if a PAR register has been programmed to redirect the address to the GP bus or ROM.
Also, if a PCI bus master generates a memory write cycle that is f orwar ded to the memory
controller and a PAR has been programmed to write-protect the region, an SDRAM write
cycle will occur with the SDQM signals inactive, the data will be discarded, and the data
written into the PCI bridge FIFOs will be purged. The ÉlanSC520 microcontroller can be
programmed to generate an i nterrupt in this case to notify the CPU of such write pr otection
violations, and that a PCI bus master caused the violations. Any data written to the write
buffer prior to enabling write-protection will be successfully written to SDRAM.

4.3.3.2 ROM/Flash Space

The ÉlanSC520 microcontroller supports three separate address regio ns for ROM/Flash,
which are selected b y the PAR registers. The BOO TCS
the boot device and defaults to a 64-Kbyte linear region at the top of the 4- Gbyte CPU
space. During the boot process, the R OM code can co nfigure PAR registers to enable the
entire BOOTCS

ROM space and redirect it to the desired region. The default 64-Kbyte
region is alwa ys enabled, ho wev er . The PAR register accepts separate TARGET values for
each of the three ROM chip select regions (BOOTCS
space is accessible by the CPU only, regardless of PAR register programming.

ROM chip select must be used f or

, ROMCS1, and ROMCS2). ROM

ROM space is normally cacheable and writes to these regions are allowed (this is useful
for Flash devices). However, PAR registers can also be used to ena ble specific attributes ,
such as defining noncacheability and write-protected regions.

The ÉlanSC520 microcontroller supports multiple data widths in th e ROM arra y, as well as
programmable timing. These characteristics are configured independently of the address
space in the ÉlanSC520 microcontroller. See Chapter 12, “ROM/Flash Controller”, for a
description of these features and instructions for configuring the ROM chip select timing
and data widths.

4-8 Élan™SC520 Microcontroller User’s Manual

4.3.3.3 GP Bus Memory Space

GP bus memory space is enabled only through PAR registers and is accessible onl y by the
CPU. There ar e eight chip select s that can be sel ected b y the PAR registers. Note that the
PAR registers do not allow any attrib utes to be de fi ned in GP bus memory space regions,
and GP bus memory space is always noncacheable.

The P AR registers are used to select GP bus space and the sp ecific chip select, but separ ate
configuration registers within the GP bus controller block must be programmed to control
the width of the data b us and the timin g of the bus. There is no restriction on the mappin g
of memory address space to GP bus chip selects. F or example, if a noncontiguous memory
region is required f or a specific chip select, then multiple P AR registers c an be programmed
with the same chip select as the target, b ut with different address ranges.

Positive address decoding is also supported on the GP bus for devices that perform their
own address decoding and therefore do not require a chip select to be generated by the

ÉlanSC520 microcontroller. This is acc omplished simply by not choosing the corresponding
chip select in the pin multiplexing registers when the PAR register is set up (see step 3 in
“Programming External Memory , Buses, and Chip Selects” on page 4-4). The address and
control signals are still generated on the GP bus.

PCI bus masters are not permitted to access the GP bus i n an ÉlanSC520 microcontr oller
system. If a PCI bus master gener ates an address in normal SDRAM space that is claimed
by the ÉlanSC520 microcontroller , b ut the region has been redi rected to the GP b us via a
PAR register, the cycle wi ll still be sent to SDRAM and will be write-protected, regardless
of the cycle type, and the resultant data will be discarded.

System Address Mapping

4.3.3.4 PCI Bus Memory Space

The ÉlanSC520 microcontroller’ s address decoding logic automatically defaul ts all memory
space above co nfigured SDRAM to the PCI bus, with the e xception of the 4-Kb yte memory­mapped configuration space and the 64-Kbyte boot space. All CPU memory space
accesses in this address region are redirected to the PCI bus, and the ÉlanSC520
microcontroller does not claim accesses in this addre ss region tha t are gener ate d b y PCI
bus masters. The GP bus DMA controller cannot access this region.

The CPU can allocate space withi n the lo w er 1 Gb y te for GP bus or ROM, ov erla ying and
effectively eliminating parts of this PCI bus region. For example, a ROM device could be
mapped in memory between the top of SDRAM and 1 Gbyte, a region that would normally
default to PCI b us. In this case , only this particular region would be redi rected to ROM, b ut
the remaining region within the 4-Gb yte space would continue to be directed to the PCI bus.

Some system applications ma y requi re a region be lo w the top o f SDRAM to be redir ected
to the PCI bus. An example of this is a PCI bus video card mapped to the 000A0000h­000BFFFFh region in a PC/AT application. In this case, a PAR register must be used to
redirect the address from the CPU to the PCI bus instead of the SDRAM. Note that only
PAR 0 or PAR 1 can be used to select PCI as a target.

Note: If a PAR window is configured for PCI, AND the CBAR register is programmed to
overlap with this PAR window, AND the PAR window is placed below the top of DRAM, the
MMCR is not given priority ov er the PCI access . Thi s configu r ation could r esult i n system
errors due to concurrence of both PCI and internal MMCR accesses.

4.3.3.5 Memory-Mapped Configuration Region (MMCR) Registers Space

All integrated peripher als and configuration registers in the ÉlanSC520 microcontroller that
are not defined as PCI bus conf igu rat ion space , PC/AT peripheral configuration registers ,
or the Configuration Base Address (CBAR) register are memory-mapped in the ÉlanSC520

Élan™SC520 Microcontroller User’s Manual 4-9

System Address Mapping

microcontroller. These registers are accessed in a 4-Kbyte region near the top of CPU
address space at location FFFEF000h after reset, but can be additionally aliased to any
4-Kbyte boundary within the first 1-Gbyte of memory space (between 00000000h and
3FFFFFFFh) by perf orming an I/O write to the Configurati on Base Address (CBAR) register.
MMCR register space has a higher priority than the Programmable Address Region (PAR)
registers.

See Section 4.3.4.1 for details on programming the CBAR register.
Reading unimplemented registers in this 4-Kb yte region returns indeterminate data values.

Writing to unimplemented registers in this region has no effect.

Note: If a PAR window is configured for PCI, AND the CBAR register is programmed to
overlap with this PAR window, AND the PAR window is placed below the top of DRAM, the
MMCR is not given priority ov er the PCI access . Thi s configu r ation could r esult i n system
errors due to concurrence of both PCI and internal MMCR accesses.

4.3.3.5.1 Integrated Memory-Mapped Peripherals

The ÉlanSC520 microcontroller’s non-PC/AT integrated peripherals are located wi thin the
MMCR region, instead of being I/O mapped as ar e the i nteg r ate d PC/AT peripherals. The
peripherals located in the memory-mapped configuration region include:

■ Am5

■ SDRAM controller and SDRAM buffering

■ ROM controller

■ PCI host bridge

■ System arbitration

■ Memory and I/O space control

■ GP bus controller

■ PIO, pin multiplexing and clock control

■ Software timer

■ General-purpose timers 0, 1 and 2

■ Watchdog timer

■ Synchronous serial interface (SSI)

■ Feature enhancements to PC/AT-compatible peripherals

86 CPU extension registers

x

– Programmable interval timer (PIT) extension registers in the programmable input/

output (PIO) and programmable interrupt controller (PIC) blocks
– UART extensions
– Programmable interrupt controller (PIC) extensions
– Reset control
– GP-DMA controller extensions

4-10 Élan™SC520 Microcontroller User’s Manual

4.3.4 I/O Space

The ÉlanSC520 microcontroller’s I/O space is partitioned into five regions:

■ Configuration Base Address (CBAR) register

■ PCI bus configuration space

■ External PCI bus I/O devices

■ Integrated PC/AT-compatible peripherals

■ External GP bus I/O devices

Figure 4-3 shows the system I/O address space map for the ÉlanSC520 microcontroller.
Each of the regions is described in the foll owing sections.

Figure 4-3 System I/O Map

System Address Mapping

64 Kbytes

1 Kbyte

CBAR

Default PCI Bus

Space

Can also be

retargeted to GP bus

PCI Configuration

Registers

Default PCI Bus

Space

Can also be

retargeted to GP bus

PC/AT Peripherals

(See Table 4-5)

The “holes” default to

external GP bus, but

can be redirected to

PCI bus. See

Section 4.3.4.4

FFFFh

FFFCh

0CFFh
0CF8h

03FFh

0

0000h

4.3.4.1 Configuration Base Address (CBAR) Register

The Configuration Base Address (CBAR) regi ster (Port FFFCh) is a 32-bit register t hat is
used to relocate the integrated memory-mapped peripherals and MMCR registers, thus
allowing a more fle xible system memory map. The CBAR is fixed in I/O space at FFFCh
and is “keyed” to prevent accidental programming.

The CBAR allows an alias of the memory-mapped configuration registers (MMCR) to be
aliased anywhere in the f irst 1 Gbyte of add ress space on a 4-Kbyt e boundary . The MMCR
is alwa ys availab le in the memory space directly below the boot ROM space at FFFEF000h,
but the CBAR can be programmed to optionally allo w a copy of this region anywher e in the
lower 1-Gbyte space (on a 4-Kbyte boundary).

Élan™SC520 Microcontroller User’s Manual 4-11

System Address Mapping

4.3.4.2 PCI Configuration Space

PCI Local Bus Specification,

that occupies only eight byt es in I/O space from 0CF8–0CFFh, and this mechanism is
supported in the ÉlanSC520 microcontroller. The PCI bus conf iguration scheme uses two
32-bit I/O locations:

■ PCI Configuration Address (PCICFGADR) register (P ort 0CF8h) is the

where the actual address of the device’s register and the bus number is located.

■ PCI Configuration Data (PCICFGD A TA) register (Port 0CFCh) is the

the data of the specific register is written to or read from.

This PCI configuration space is accessible
microcontroller, and the I/O cycle is claimed by the PCI bus configuration register block.

As a target, the ÉlanSC520 microcontrolle r does not accept any PCI bus configuration
space accesses from other PCI bus master s.

Host-bridge-specific PCI configuration r egisters are described in the

Microcontroller Register Set Manual

Revision 2.2, f or details on PCI bus de vi ce configur ation regist er prog r amming.

4.3.4.3 PCI I/O Space

The CPU’s I/O cycles can be directed to the PCI bus for normal direct-mapped access of
devices, with the following restrictions:

■ I/O addresses claimed by the integrated PC/AT peripherals and the CBAR cannot be

forwar ded to the PCI bus under any conditions. See the I/O map in Figure 4-3 on
page 4-11 and Table 4-5 on page 4-14 for details of the I/O addresses th at are claimed
by the integrated peripherals.

Revision 2.2, defines an indirect-mapped configura tion space

only

by the CPU in the ÉlanSC520

address

data

register where

register

Élan™SC520

, order #22005. See also the

PCI Local Bus Specificatio n,

■ By default, the “holes” in this portion of the I/O address space (0000–03FFh) are

forwar ded to the external GP bus. The Addre ss Decode Control (ADDDECCTL) register
(MMCR offset 80h) can be configured to forward accesses to these holes to the PCI
bus. A PAR register is not required for this.

■ I/O addresses implemented by PCI bus configuration space (0CFC–0CFFh) are only

forwarded to the PCI b us as an I/O cy cle when the ENABLE bit i n the PCI Configu ration
Address (PCICFGADR) register is cleared to 0. Otherwise , they are f orw arded as a PCI
configuration cycle . Ports 0CF8–0CFBh are forw arded to the PCI bus a s I/O transactions
only for non-doub leword accesses to this region; otherwise , they are claimed by the host
bridge as a PCI configuration cycle.

All other CPU I/O cycles are, by default, forwarded to the PCI bus as normal PCI I/O
transactions. PAR registers can be enabled to direct portions of this region to the GP bus.

As a target, the ÉlanSC520 microcont roller d oes not accept a ny I /O space a ccesses from
PCI bus masters.

4-12 Élan™SC520 Microcontroller User’s Manual

System Address Mapping

4.3.4.4 PC/AT-Compatible I/O Peripherals Region

The ÉlanSC520 microcontroller includes several integrated peripheral cores that are
PC/AT compatible, including the DMA controller, programmable interrupt controller (PIC),
programmable int e rval timer (PIT), UARTs, real-time clock, and various control/status
registers. These I/O addresses are automat ically decoded by the ÉlanSC520
microcontroller’s address decoding logic and require no special setup or PAR registers.
Table 4-5 summarizes the I/O map for these integrated peripherals.

holes

There are

in this region, which are I/O transactions in the lower 1-Kbyte region that
not claimed by the ÉlanSC520 microcontroller’ s internal peripherals. These addresses can
be decoded externally, or, if a chip sel ect is required, a PAR register can be programmed
for these addresses.

■ By default, all of the accesses to holes in this portion of the I/O address space (0000h

to 03FFh) are forw arded to the external GP bus.

■ To forward all accesses to the PCI bus , the IO_HOLE_DEST bit in the Address Decode

Control (ADDDECCTL) register (MMCR offset 80h) can be set.

■ If necessary, PARx registers can be used to override sen ding accesse s to t he PCI bus

on an individual peripheral basis. In thi s way, accesses for individual peripherals can be
directed back to the external GP bus.

For example, some PCI cards (notably VGA cards) use legacy I/O locations. The
IO_HOLE_DEST bit allows the holes to be directed to either the PCI or to the GP bus . F or
a system requiring legacy GP bus peripherals along with legacy PCI peripherals (for
instance, a PCI VGA card and a GP bus keyboard controller), the IO_HOLE_DEST bit
would be set to 1 to di rect all accesses to the PCI bus. The l egacy GP bus keyboard controller
would then be configured via PAR registers to override this setting. See “VGA Contro ller
on the PCI Bus” on page 3-15 for another discussion of this topic.

Note: If a PARx register is configured to addres s GP bus I/O space within a hole, accesses
in the defined region are forwarded to the GP bus regardless of the IO_HOLE_DEST bit
value. It is the programmer’s responsibility to ensure that external peripherals are not

mapped over an y of the ÉlanSC520 microcontroller’ s internal peripherals. Normal operation
is not guaranteed in thi s case. See “Disab ling Internal P eripher als” on page 3-21 for more
information about this topic.

Élan™SC520 Microcontroller User’s Manual 4-13

System Address Mapping

Table 4-5 PC/AT Peripherals I/O Map

Peripheral Core I/O Address Range

Slave GP-DMA Controller 0000–000Fh
Master Interrupt Controller 0020–0021h
Slave 2 Interrupt Controller

• This controller is not defined in standard PC/AT architecture, but has been included
in the ÉlanSC520 microcontroller to provide additional interrupt request sources

Programmable Interval Timer (PIT) 0040–0043h
Keyboard Control A20M and Fast Reset (SCP)

• Accesses to these locations are always directed to the external GP bus, but are
also snooped internally for PC/AT functions.

System Control Port B/NMI Status

• Reads and writes to this location are directed to this register only and are not seen
on the external GP bus

Real-Time Clock (RTC) Index/Data 0070h, 0071h
General-Purpose Scratch Registers

• These are unused locations from the original DMA Page Register file and are
maintained for PC/AT compatibility. Writes to these locations update the
corresponding register and are also seen on the external GP bus. Reads to the
locations return the data from the corresponding register, but do not initiate a cycle
on the external GP bus.

General-Purpose Scratch Register

• This is an unused location from the original DMA Page Register file and is
maintained for PC/AT compatibility. Reads and writes to this location are directed
to this register only and are not seen on the external GP bus.

GP-DMA Page Registers

• Reads and writes to these locations are directed to these registers only and are not
seen on the external GP bus.

System Control Port A 0092h
Slave 1 Interrupt Controller 00A0–00A1h
Master GP Bus DMA Controller 00C0–00DEh

Floating Point Error Interrupt Clear 00F0h
UART 2 02F8–02FFh
UART 1 03F8–03FFh

0024–0025h

0060h, 0064h

0061h

0080h

0084–0086h

0088h

008C–008Eh

008Fh

0081–0083h

0087h

0089h-008Bh

(even addresses only)

The ÉlanSC520 microcontroller also allows the internal UARTs and the real-time clock
(RTC) to be di sabled, for applicati ons when an external device is pref erred. This is controlled
by configuration register bits in the Address Decode Control (ADDDECCTL) register
(MMCR offset 80h). When these peripherals are disabled, the I/O cycle is forwarded
externally to the GP bus. This all ows connection of external devices such as a standard
Super I/O chip.

Integrated PC/AT peripherals are not accessible by PCI bus master s.

4-14 Élan™SC520 Microcontroller User’s Manual

System Address Mapping

4.3.4.5 GP Bus I/O Region

The PAR registers must be used to address external I/O devices on the GP bus. GP bus
addressing is implemented with b yte granularity, to accommodate devices with v ery few
registers and very fragmented I/O maps that are typically found in PC/AT-compatible
systems.

When programming PAR registers for GP bus I/O space, it is best to configure the space
on doubleword boundaries. Note that when specifying unaligned byte regions for I/O access,
the software that acc esses the regions must directly address the cor rect byt e or bytes . Fo r
example, if a PAR is programmed with an I/O region, and the start address is xxx1h (i.e.,
byte #1), when the CPU perf orms a word or doubl eword access starting at xxx0h (i.e., byte
#0), the entire double word access is redirected to the PCI b us (byte #1 will not be accessed
on the GP bus as programmed). In this case, the b yte requested
by the CPU at I/O address xxx1h.

This region is not accessible by PCI bus masters.

4.3.5 Configuration Information

4.3.5.1 Configuring ROM/Flash Space

There are three ROM add ress regions that can be defined in the ÉlanSC520 microcontrol ler,
but only the BOOTCS
optional two regions, R OMCS1
configuration is described in Chapter 3, “System Initialization”. See “Programmable
Address Region (PAR) Registers” on page 4-5 for details on PAR register programming.

region is absolutely required for system boot up from reset. The

and ROMCS2 are configured via PAR registers. BOO TCS

must

be directly accessed

4.3.5.2 Configuring SDRAM Address Space

SDRAM space is determined at boot time when the SDRAM controller’s configuration
registers are progr ammed and individual bank s are enab led. A typical design can perf orm
an SDRAM sizing routine to determine the amount of memory installed in the system and
write the appropriate values to the configuration registers. For example, in a system that
contains 16 megabytes of SDRAM, initialization software defines the SDRAM address
region from 00000000–00FFFFFFh, and all accesses to this region are forwarded to the
SDRAM controller unless a PAR register has been programmed to o v erla y the regi on with
MMCR, ROM, PCI bus, or GP bus space.

4.3.5.2.1 Noncacheable, Write-Protected, or Nonexecutable SDRAM Regions

In the default condition, the entire SDRAM region is cacheable and e xecutab le by the CPU ,
and read/writable b y the CPU, PCI bus master, and GP b us DMA cont ro ller cycl es . Ther e
may be some system configur ations in which specific portions of SDRAM require restricted
access which can be accomplished by enabling speci fic attributes. A f ew common examples
follow:

■ An SDRAM region that contains only code can be marked as write-protected with an

attribute in the PAR register. This prevents the CPU and any bus master from illegally
writing over the code in SDRAM due to f aulty programming. In a ddition, an interrupt can
be generated to the CPU when a violation occurs to assi st in debug of the illegal write
condition.

■ An SDRAM region that contains only data can be marked as nonexecutable with an

attribute in the PAR register. If a softw a re task attempts to branch to that location and
resume execution due to a software bug, the CPU will read an illegal opcode, forcing an
exception. The exception handler will then f acilitate debugging the prog ram that caused
the illegal condition.

Élan™SC520 Microcontroller User’s Manual 4-15

System Address Mapping

4.3.5.3 Configuring GP Bus Peripheral Space

Configuring space for GP b us peripher als is accomplished vi a PAR register programming.
This section describes a few system configuration examples beyond the normal
programming of chip select regions.

4.3.5.3.1 Configuring a Chip Select for Noncontiguous Memory or I/O Space

Some peripheral subsystems may require a

single

chip select that must be asserted in
noncontiguous address locations. For example, an I/O device can contain multiple
integrated functions that are each addressed at separate, noncontiguous I/O addresses
(such as a custom ASIC). In this case multiple PAR registers can be used to define each
individual address region, b ut all can be mapped to t he same chip select b y prog ramming
the TARGET field to GP bus and t he ATTR field to the same chip sele ct. This is most usef ul
when working with a highly fragmented I/O map such as defined in PC/AT systems, where
there is little unused I/O address space.

single

This can also be accomplished by programming a

PAR register to cover the entire

range of addresses, which results in some wasted address space.

4.3.5.3.2 Positive Decoding Example

Some peripherals connected to the GP bus ma y perf orm their own address decodi ng from
the GP bus addresses and do not require a chip select. In this case, the same steps are
followed for programming the configuration regi sters, but the pin multiplexin g registers do
not need to be progr ammed to allow the actual chip select to be driv en on a pin, thus allowing
the pin to be used for other function s.

If multiple positive decoding regions are required in an application, the PAR registers for
each reason can be programmed to map to the same un used chip select, t o conserve pin
functions.

4.3.5.3.3 Configuring the Élan™SC520 Microcontroller to Use an External Super I/O Chip

It may be desirable to connect a commercially available Super I/O chip on the GP bus in

an ÉlanSC520 microcontroller system (for example, systems requiring a keyboard or I DE
drive can implement this device).

In this case, since the Super I/O implements tw o UAR Ts programmed at the same address
as the ÉlanSC520 microcontroller’ s in tegrated U ARTs , the internal UAR Ts can be disabled
to support the COM1 and COM2 ports in the Super I/O chip, if desired. In this case , when
the CPU performs I/O accesses to the U ART address re gions, the cycles will be f orwarded
out to the external GP bus. Also, the Super I/O is a positive decoding device , i.e., it does
not require a chip select because it performs the address decoding from the GP bus
addresses.

The I/O map for the Super I/O device is fragmented and may require the use of multiple
PAR registers for noncontiguous addres sing, as described in Section 4.3.5.3.1. If the
fragmented I/O space unused b y the Super I/O chip is not required elsewhere i n the system,
then a single PAR register can be used to map the enti re range of pe ripherals. In this case ,
the UAR T address spaces would be the highest used I/O spa ce internally in the ÉlanSC520
microcontroller, so the Super I /O peripherals would not be in confl ict, allowing a single PAR
register to define the entire range of Super I/ O peripherals from 01F0–07BEh.

See “Interfac ing with a Super I/O Contr oller” on pa ge 13-13, fo r an e xampl e of connectin g
the Super I/O chip to the ÉlanSC520 microcontroller’s GP bus.

4-16 Élan™SC520 Microcontroller User’s Manual

System Address Mapping

4.3.5.4 Configuring the Élan™SC520 Microcontroller for Windows

The ÉlanSC520 microcontroller can be configured to operate as a Windows compatible
microcontroller . This section describes some of the steps that may be required to configure
the memory and I/O addressing; howe ver, this will vary depending on the requir ements of
the system.

4.3.5.4.1 Memory Regions Above DOS 640-Kbyte Application Space

The ÉlanSC520 microcontroller can be progr ammed to accommodate the legacy PC/AT­compatible region abo ve the DOS 640-Kbyt e application space at 000A0000h area ending
at 000FFFFFh (1 Mbyte). This space def aults to SDRAM once the SDRAM banks are
enabled, but the PAR registers can be programmed to support the various requirements of
systems requiring Windows compatibility. The list below outlines some of the steps to
consider when buildi ng a memory map in the ÉlanSC520 microcontrol ler sys tem for such
compatibility.

■ Two 64-Kbyte video regions from 000A0000–000AFFFFh and 000B0000–000BFFFFh

default to SDRAM, but can be enabled as PCI bus space for PC/AT compatible video
cards on the PCI bus, via one of the PAR registers. The ÉlanSC520 microcontroller’ s
PCI bus host bridge (as a t arget) wi ll automati cally ignor e access es in thi s space when
either PAR 0 or PAR 1 are programmed to overlay SDRAM regions with the PCI bus.

®

Compatibility

■ The remaining area from 000C0000–000FFFFFh is normally sub-divided in a PC/AT

system into several different address regions for BIOS, and accesses to these regions
can be redirected to either ROM, the GP bus, or the PCI bus by programmi ng PAR
registers. Most systems will not requir e the use of all BIOS regions defined, since many
are for expansion ROMs intended f or various plug-in cards (such as network interface
cards). The following regions are normally defined:

– One BIOS region with 64-Kbyte granularity from 000F0000–000FFFFFh
– Four e xtended system BIOS regions, each with 16-Kbyte gr anularity from 000E00000–

000EFFFFFh

– 8 Expansion ROM regions, each wi th 16-Kbyte granularity, from 000C0000–

000DFFFFFh

4.3.5.4.2 Integrated Peripheral Mapping

Because the ÉlanSC520 microcontroller already provides standard PC/AT-compatible
peripherals that use direct I/O address mapping, there are no I/O address conflicts with
these devices. See Table 4-5 on page 4-14 for a summary of this I/O map.

The Configuration Base Address (CBAR) register (Port FFFCh) can be used to alias the
internal memory-mapped registers and peripherals to a conv enient location. F or e xample,
they could be mapped between 640 Kbyt es and 1 Mbyte for real mode operation. The
memory-mapped configuration region is always available in the upper CPU space
(4 Gbytes), but the aliased l ocation is only accessible wh en the CBAR is programmed and
the ENABLE bit has been set.

4.3.5.4.3 DMA Channel and Interrupt Request Steering

The ÉlanSC520 microcontroller pro vides a method to r oute interrupt r equest sources and
DMA request pins to the appropriate channels on the programmable interrupt controller
(PIC) and the GP-DMA controller, respectively.

See Chapter 15, “Programmable Interrupt Controller”, for further information on interrupt
request routing.

See Chapter 14, “GP Bus DMA Controller”, for f urther information on DMA request routing.

Élan™SC520 Microcontroller User’s Manual 4-17

System Address Mapping

4.3.5.5 Configuring PCI Bus Devices

PCI bus device configuration is accomplished in the ÉlanSC520 microcontr o ller with the
standard PCI Configuration Mech anism #1, as def ined in the
Revision 2.1. This configuration requires an indirect mapped I/O scheme in which the
address of the device is written to the PCI Configuration Address (PCICFGADR) register
(Port 0CF8h), and the data is accessed via the PCI Configuration Data (PCICFGDATA)
register (Port 0CFCh). See“Configuration Information” on page 9-9 for more information.
See also the

PCI Local Bus Specification,

4.3.6 Interrupts

The ÉlanSC520 microcontroll er can be programmed to generat e an interrupt request when
a write protection violation occurs, providing software with a debugging mechanism to
determine which task illegally attempted to write to the memory region marked with this
attribute. In this case, an interrupt request is generated to the programmable interrupt
controller (PIC) bl ock, where the request is routed to the appropriate type of interrupt
(maskable or non-maskable) and level, based on the programming of the configuration
registers. The P AR windo w that contains the address region where the write protect violation
occurred is latched i nt o a regi ster, as well as which bus owner caused the violatio n (C PU,
GP-DMA controller, or PCI bus master).

See Chapter 15, “Programmable Interrupt Controller”, for details of PIC programming.

PCI Local Bus Specification,

Revision 2.2.

4.3.7 Software Considerations

Since the ÉlanSC520 microcontroller provides some flexibility in defining the system
memory and I/O map, there are a n umber of software considerations that must be analyzed.
The list below describes some of the issues that must be consi dered when programming
the configuration register s to define the memory and I/O space in an ÉlanSC520
microcontroller system.

■ The Configuration Base Address (CBAR) register must be accessed as a 32-bit I/O

register to guarantee that all bits are written at the same time. The MATCH field of the
CBAR must be written with the correct pattern to enable

■ MMCR register space has higher p riority than the Programmable Addr ess Region (P AR)

registers.

■ The PAR registers are organized such that the lowest regi ster (PAR 0) is the highest

priority and the last P AR register (P AR15) is l owest priority . Therefore, if two P AR reg isters
are overlaid due to programming, the lowest numbered PAR takes priority.

■ PAR registers should not be programmed to conflict with any of the fixed I/O regions,

such as the Configuration Base Address (CBAR) register or the PCI bus configuration
space.The ÉlanSC520 microcontroller’s address decoding does not permit PAR
registers to overlay the integrated PC/AT peripherals.

■ In general, the PAR register start address and region size should not be programmed

to conflict with each other . It is possible to program the PAR registers such that the region
size is greater than the start address allows. For exampl e, if the region size is defined
as 64 Kbytes, but the start address is programmed to be the top of the 1-Gbyte region
(maximum address allo w ed b y PAR registers) minus 4 Kbytes, then the ad dress spac e
avail able will be the 4-Kbyte region starting at the start address.

or

disable the MMCR alias.

– Subsequent access past the 1-Gbyte boundary will still be to the PCI bus

not

– The remaining 60-Kbyte region will

4-18 Élan™SC520 Microcontroller User’s Manual

qualify as a PAR hit.

System Address Mapping

■ When programming the PAR registers for an SDRAM region, the PAR register start

address and region size should not confli ct with the pro grammed v alue that defines the
top of SDRAM in the system. F or e xample, if a PAR is setup for SDRAM and th e region
size is defined as 8 Kbytes, but the start address is programmed to be the top of the

not

SDRAM minus 4 Kbytes , then addresses above the top of SDRAM will

result in a hit

for this PAR.

■ If the TARGET field of any PAR register is defined as SDRAM, but no SDRAM has been

enabled via the SDRAM controller configuration registers, the memory space defaults
to the PCI bus.

■ Systems that configure another memory space resource to be ov erlaid on top of SDRAM

space do not have access to the SDRAM that was overlaid, since address tr anslation

is not supported in the ÉlanSC520 microcontroll er. For e xample, i f a PCI bus video card
is used in the 000A0000–000AFFFFh region (as in typ ical PC/A T oper ation), the system
will lose the 64 Kbyte s of SDRAM in t hat region as long as the PAR register is enabled.

■ Any region that is overlaid on default SDRAM space through a PAR register or CBAR

takes priority over the SDRAM region in the decoding block. In effect , a portion of SDRAM
becomes inaccessible when this is done. If a PCI bus master gener ates an address to
this overlaid address region, the cycles will be forwarded to SDRAM and will be write­protected.

■ Code execut ion from memory on the GP bus or the PCI bus is dis courag ed (after boot

code has ex ecuted ), since accesse s to these sp aces are not cacheab le and may result
in unacceptable l atencies under some conditions . Code execu tion is more efficient when
ex ecuting from SDRAM or from ROM devices that use BOO TCS

, ROMCS1, or ROMCS2,

because accesses to these resources are cacheable.

■ The ÉlanSC520 microcontroller guarantees coherency with SDRAM buffers that are

shared between the CPU and other bus master s, but it may be beneficial to mark these
regions as noncacheable to avoid the overhead with cache write-backs upon every
access by the bus master. This can be accomplished by programming a PAR register
and setting the noncacheable attribute. Cache snooping will continue; however, the
performance impact is negligible, since there will be no write-back cycles.

■ Care must be taken when programming configuration registers that affect address

decoding during normal system operation when either PCI b us master or GP b us DMA
activity is occurring.

– When writing to PAR registers, verify that the ÉlanSC520 microcontroller’s PCI host

bridge target FIFOs hav e been flushed and disable PCI bus master access of SDRAM
to prevent unexpected forwarding of accesses from other masters. An example of a
potential problem is modifyi ng a PAR register to redirect normal SDRAM region
accesses to the PCI bus , whi le a PCI bus master has already been granted the PCI
bus. In th is case, when the CPU completes the write to the PAR register, the post ed
PCI bus master access is f orwarded to the SDRAM controller because the bus w as
already granted to the PCI bus master. This problem can be alleviated by disabling
PCI bus master access to SDRAM (the d efault mode after reset) via the System Arbite r
Master Enable (SYSARBMENB) register (MMCR offset 72h), and perf orming a read
from an external PCI agent to flush the ÉlanSC520 microcontroller’s target FIFOs,
before writing to configuration registers that affec t addr ess decoding.

– The CPU cache should alwa ys be flushe d after the cacheabi lit y attrib ute i s changed

from cacheable to noncacheable for any memory region (by programming the PAR
register), or when the cache write poli cy is change d from write-bac k to write-t hrough.

Élan™SC520 Microcontroller User’s Manual 4-19

System Address Mapping

■ Programming the P AR r egister maximum region size and a page siz e of 64 Kbytes allows

a space up to 128 Mbyt es to be defined; howev er, the GP bus/R OM address pins support
a maximum of 64 Mb ytes per chip select. If a 128-Mbyte space i s progr ammed for a GP
bus or ROM chip select, the upper 64 Mbytes will be aliased with the lower 64-Mbyte
region.

■ When programming PAR registers for GP b us I/O space, it is best to configure the space

on doubleword boundaries. Note that when specifying unaligned b yte regions for I/O
access, the software that accesses the regions must directly address the correct byte
or bytes. F or exampl e, if a PAR is programmed with an I/O region, and the st art address
is xxx1h (i.e., b yte 1), when the CPU perf orms a word or doub lew ord access starting at
xxx0h (i.e., byte 0), the entire doubleword access is redirected to the PCI bus (byte 1
will not be accessed on the GP bus as programmed). In this case the byte requested

must

be directly accessed by the CPU at I/O address xxx1h.

■ A write-protection violation occurs when the CPU , an y PCI b us master, or the GP-DMA

controller attempts to write to any memory region that has been marked as write­protected by a PAR register attribute. When this occurs, the cycle is always forwarded
to SDRAM as a write cycle with the SDQM signals inactive, and the original dat a is
discarded. Any data that was written to the write b uffer prior t o enabling write-protecti on
is successfully written to SDRAM.

■ Software must include proper interrupt service routines and exception handlers when

enabling write-protection vi olation inter rupts and nonex ecutab le r egion attrib utes in the
Address Decode Control (ADDDECCTL) register (MMCR offset 80h). Note that in the
case of the write protection violation, the PAR register number that contains t he address
region of the violation is latched in the WPV_WINDOW bit field in the Write-Protect
Violation Status (WPVSTA) register (MMCR offset 82h) and retained until it is cleared
by software.

The PARx window number is latched when a write-protect violation occurs.

Subsequent write-protect violations are not capt ured until softw a re clears the inte rrupt
by writing a 1 to the WPV_STAT bit in the same register.

■ If two or more PAR registers are overlapping (programmed t o have some addr ess range

in common), the write-protection e xception is generated only if the higher priority PAR
has the attribute enabled. If the lower priority P AR has the write-protect attrib ute enabled
but the higher priority PAR has it disabled, then writes into the common address r a nge

not

shared by the two PAR registers will

generate an e xception. This d iscussion applies

to the cacheability control and code execution attributes, as well.

■ Access of ÉlanSC520 microcontroller internal configur ation registers:

– All integrated PC/AT peripherals mapped to I/O space must be accessed only as 8

bits unless otherwise specified.

– All memory-mapped integrated peripherals and configuration registers for PC/AT

peripherals must be accessed as specified in the

Register Set Manual

, order #22005.

Élan™SC520 Microcontroller

– PCI configuration r egisters should b e accessed as 32 bit s unless otherwise specified

Élan™SC520 Microcontroller Register Set Manual

in the

4-20 Élan™SC520 Microcontroller User’s Manual

, order #22005.

4.4 INITIALIZATION

The ÉlanSC520 microcontroller’s address decoding is cleared to the default state by a
system reset.

■ The BOOTCS decoding is enabled for the 64-Kb yte region from FFFF0000–FFFFFFFFh

■ SDRAM address space is disabled.

■ All PAR registers are disabled and cleared to zeros, which means there are no e xternal

GP bus address spaces enabled. Note that I/O holes below 1 Kbyte will be directed to
the external GP bus. Howev er , no chip selects are enabled, and pos itive decodes wou ld
be required.

■ Integrated PC/AT peripheral I/O space is enab led as defined in Table 4-5 on page 4-14.

■ The Configuration Base Address (CBAR) r egister is ad dressed in I /O space at FFFCh.

Memory-mapped configuration register space is enabled at FFFEF000–FFFEFFFFh
(below CPU boot space address).

■ The PCI bus is disabled, and the configuration registers are defaulted to the values

specified in
enabled in I/O space at ports 0CF8h and 0CFCh (PCICFGADR and PCICFGDATA).

See “Programmable Address Regi on (PAR) Registers” on page 4-5 for information on
configuring these registers. See “Configuration Information” on page 4-15 for additional
detail on configuring the various address spaces included on the ÉlanSC520
microcontroller.

PCI Local Bus Specification,

System Address Mapping

Revision 2.2. PCI configuration space is

Élan™SC520 Microcontroller User’s Manual 4-21

System Address Mapping

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