AMD SB710 databook

AMD SB710 Databook

Technical Reference Manual

P/N: 45215_sb710_ds_pub

Rev. 1.60

42133

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Revision History

Date Revision Description

Nov, 2009 1.60  Updated Figure 3-1, “SB710 Power Up/Down Sequence”: Corrected

SLP_S5#/SLP_S3# timing diagram.

Aug, 2009 1.40  Updated Section 1.1, “Features of the SB710”: Added support for SATA hot

plug.

 Updated Figure 12-1, “SB710 FCBGA Package Outline” with a picture of

better quality.

 Updated Table 9-5, “RTC X1 Clock AC Specifications”: Removed cycle-to-

cycle jitter requirement.

 Updated Section 7.13, “SMBus Interface/GPOC”: Noted that SCL and SDA

pins are OD when configured as SMBus pins.

July, 2009 1.25  Updated Table 9-5, “RTC X1 Clock AC Specifications”: Corrected unit for

T62 to T65 to µS.

June, 2009 1.10  First release of the public version.

AMD SB710 Databook

45215 Rev. 1.60 November 09

Table of Contents

1 Introduction ............................................................................................................. 8

1.1 Features of the SB710.................................................................................................................... 8

1.2 Part Number and Branding........................................................................................................... 11

2 SB710 Block Diagram ........................................................................................... 12

3 SB710 Power on Sequence and Timing .............................................................. 13

3.1 Power Up and Down Sequences..................................................................................................13

4 SB710 Strap Information ...................................................................................... 18

5 Integrated Resistor and External Pull-up/Pull-down Resistor Requirements .. 22

6 SB710 Ballout Map ................................................................................................ 29

7 Signal Description................................................................................................. 31

7.1 CPU Interface ...............................................................................................................................31

7.2 LPC Interface................................................................................................................................31

7.3 A-Link Express II Interface ...........................................................................................................32

7.4 PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge).......................................................... 32

7.5 USB Interface ...............................................................................................................................33

7.6 ATA66/100/133............................................................................................................................. 33

7.7 Serial ATA Interface .....................................................................................................................34

7.8 HD Audio Interface .......................................................................................................................35

7.9 Real Time Clock Interface ............................................................................................................ 35

7.10 Hardware Monitor .........................................................................................................................35

7.11 SPI ROM Interface........................................................................................................................36

7.12 Northbridge / Power Management Interface ................................................................................ 36

7.13 SMBus Interface / General Purpose Open Collector.................................................................... 38

7.14 External Event / General Event / General Power Management / General Purpose Open Collector

39

7.15 General Purpose I/O..................................................................................................................... 41

7.16 Integrated Micro-Controller (IMC).................................................................................................45

7.17 Reset / Clocks / ATE.....................................................................................................................46

7.18 Intruder Alert .................................................................................................................................47

7.19 Power and Ground........................................................................................................................ 47

8 Functional Description ......................................................................................... 49

8.1 EHCI USB 2.0 and OHCI USB 1.1 Controllers............................................................................. 49

8.1.1 USB Power Management.....................................................................................................................50

8.2 SMI#/SCI Generation ...................................................................................................................51

8.3 LPC ISA Bridge.............................................................................................................................52

8.3.1 LPC Interface Overview .......................................................................................................................52

8.3.2 LPC Module Block Diagram .................................................................................................................54

8.4 Integrated Micro-Controller (IMC).................................................................................................54

8.4.1 Consumer Infrared Controller...............................................................................................................54

8.5 Real Time Clock ...........................................................................................................................55

4 Table of Contents

45215 Rev. 1.60 November 09

8.5.1 Functional Blocks of RTC.....................................................................................................................55

8.6 PATA Controller............................................................................................................................ 56

8.7 SATA (Serial ATA) Controller ....................................................................................................... 57

8.8 PCI Bridge ....................................................................................................................................58

8.9 High Definition Audio ....................................................................................................................58

8.9.1 HD Audio Codec Connections..............................................................................................................58

8.10 Power management/ACPI ............................................................................................................ 58

8.11 General Events and GPIOs ..........................................................................................................59

8.12 Hardware Monitor Interface ..........................................................................................................59

AMD SB710 Databook

9 System Clock Specifications................................................................................ 61

9.1 System Clock Descriptions and Frequency Specifications .......................................................... 61

9.2 System Clock AC Specifications ..................................................................................................62

10 States of Power Rails during ACPI S1 to S5 States ........................................... 65

11 Electrical Characteristics ..................................................................................... 66

11.1 Absolute Maximum Ratings.......................................................................................................... 66

11.2 Functional Operating Range for Signal Input ...............................................................................66

11.3 DC Characteristics........................................................................................................................67

11.4 Reset Signal Requirements ..........................................................................................................72

11.5 RTC Battery Current Consumption...............................................................................................72

12 Package Information ............................................................................................. 73

12.1 Physical Dimensions.....................................................................................................................73

12.2 Pressure Specification.................................................................................................................. 74

13 Thermal Information.............................................................................................. 74

14 Testability .............................................................................................................. 75

14.1 Test Control Signals ..................................................................................................................... 75

14.2 XOR Chain Test Mode .................................................................................................................76

14.2.1 Brief Description of an XOR Chain.......................................................................................................76

14.2.2 Description of the SB710 XOR Chain...................................................................................................77

Appendix A: Pin Listing.............................................................................................. 82

Table of Contents 5

AMD SB710 Databook

45215 Rev. 1.60 November 09

List of Figures

Figure 1-1: SB710 Branding Diagram ..........................................................................................................................11

Figure 2-1: SB710 Block Diagram Showing the Internal PCI Devices and Major Function Blocks ..............................12

Figure 3-1: SB710 Power Up/Down Sequence ............................................................................................................14

Figure 3-2: SB710 S3/S0 Power Up/Down Sequence .................................................................................................15

Figure 3-3: Circuit for Maintaining Proper Relationship between +V5_VREF and VDDQ ............................................16

Figure 3-4: Timing for SB PWR_GOOD De-asserted to RSMRST# De-asserted........................................................17

Figure 3-5: Timing for LDT_STP# assertion on first power up (G3  S5) ...................................................................17

Figure 3-6: S5_3.3V Power Down Sequence Requirement .........................................................................................17

Figure 4-1: Straps Capture...........................................................................................................................................18

Figure 4-2: Type II Straps Capture timing ....................................................................................................................18

Figure 4-3: Type I Straps Capture timing .....................................................................................................................19

Figure 6-1: SB710 Ball-out Assignment (Left) ..............................................................................................................29

Figure 6-2: SB710 Ball-out Assignment (Right) ...........................................................................................................30

Figure 8-1: SB710 USB 2.0 System Block Diagram.....................................................................................................49

Figure 8-2: A Typical LPC Bus System........................................................................................................................52

Figure 8-3: LPC control signals diagram (TBA)............................................................................................................52

Figure 8-4: Block Diagram of LPC Module...................................................................................................................54

Figure 8-5: Block Diagram of the integrated micro-controller Module (TBA) ................................................................54

Figure 8-6: Block Diagram of Internal RTC ..................................................................................................................56

Figure 8-7: Block Diagram for the SATA Module .........................................................................................................57

Figure 8-8: HD Audio Codec Connections ...................................................................................................................58

Figure 9-1: Timing Labels for AC Specifications of the SB710 Clocks .........................................................................62

Figure 9-2: Timing Labels for AC Specifications of the SB710 Diff Clocks...................................................................62

Figure 9-3: SB710 Diff Clocks Rise and Fall Time Measurement ................................................................................62

Figure 12-1: SB710 21 mm x 21 mm 0.8 mm Pitch 528-FCBGA Package Outline ......................................................73

Figure 14-1: Test Mode Capturing Sequence Timing...................................................................................................76

Figure 14-2: A Generic XOR Chain..............................................................................................................................76

Figure 14-3: On-chip XOR Chain connectivity .............................................................................................................77

6 List of Figures

45215 Rev. 1.60 November 09

AMD SB710 Databook

List of Tables

Table 1-1: SB710 Part Numbers ..................................................................................................................................11

Table 3-1: SB710 Power Up/Down Sequence Timing..................................................................................................13

Table 4-1: Standard Straps ..........................................................................................................................................19

Table 4-2: Debug Straps ..............................................................................................................................................20

Table 4-3: Additional Straps .........................................................................................................................................21

Table 5-1: External Resistor Requirements and Integrated Pull-Up/Down...................................................................22

Table 8-1: EHCI Support for Power Management States.............................................................................................50

Table 8-2: EHCI Power State Summary.......................................................................................................................50

Table 8-3: Causes of SMI# and SCI.............................................................................................................................51

Table 8-4: LPC Cycle List and Data Direction..............................................................................................................53

Table 8-5: SMI, SCI, and Wake Event Support by GPIO and General Event Pins ......................................................59

Table 8-6: Functionality of the General Events and GPIOs across ACPI States..........................................................59

Table 9-1: SB710 System Clock Descriptions..............................................................................................................61

Table 9-2: SB710 System Clock Input Frequency Specifications ................................................................................61

Table 9-3: SB710 System Clock Output Frequency Specifications..............................................................................61

Table 9-4: 48MHz USB/SIO Clock AC Specifications ..................................................................................................63

Table 9-5: RTC X1 Clock AC Specifications ................................................................................................................63

Table 9-6: LPC Clock AC Specifications ......................................................................................................................63

Table 9-7: PCI Clock AC Specifications .......................................................................................................................64

Table 9-8: PCI-E Clock AC Specifications ...................................................................................................................64

Table 9-9: RTC 32-KHz Output Clock AC Specifications .............................................................................................64

Table 10-1: State of Each Power Rail during ACPI S1 to S5 States ............................................................................65

Table 11-1: Absolute Maximum Rating ........................................................................................................................66

Table 11-2: DC Characteristics for Power Supplies to the SB710 ...............................................................................67

Table 11-3: DC Characteristics for Interfaces on the SB710........................................................................................67

Table 11-4: GPIO/GEVENT Input DC Characteristics..................................................................................................68

Table 11-5: GPIO/GEVENT Output DC Characteristics...............................................................................................71

Table 11-6: RTC Clock Output DC Characteristics ......................................................................................................71

Table 11-7: Reset Signal Requirements ......................................................................................................................72

Table 11-8: RTC Battery Current Consumption ...........................................................................................................72

Table 12-1: SB710 21 mm x 21 mm 0.8 mm Pitch 528-FCBGA Physical Dimensions ................................................73

Table 13-1 SB710 Thermal Limits................................................................................................................................74

Table 14-1: Signals for the Test Controller of the SB710 .............................................................................................75

Table 14-2: Test Mode Signals ....................................................................................................................................75

Table 14-3: TEST0 Bit Sequence.................................................................................................................................75

Table 14-4: Truth Table for an XOR Chain ..................................................................................................................77

Table 14-5: List of Pins on the SB710 XOR Chain and the Order of Connection.........................................................77

Table 14-6: Pins Excluded from the XOR Chain ..........................................................................................................81

List of Tables 7

AMD SB710 Databook

45215 Rev. 1.60 Nov 09

1 Introduction

AMD’s SB710 is a Southbridge that integrates key I/O, communication, and audio features required in a state-of-the-art PC into a single device. Over and beyond the features supported by the SB700, the SB710 also supports a number of hardware monitoring features and AMD’s Advanced Clock Calibration utility. It is specifically designed to operate with AMD’s integrated graphics processors (IGPs) and Northbridges in desktop and mobile PCs.

1.1 Features of the SB710

CPU Interface

 Supports AMD Athlon™ 64 and Athlon 64

FX , Opteron™, Dual-Core Opteron™ Sempron™, Mobile Sempron™, Athlon XPM, and Turion™ processors. Dual-core CPUs are supported.

A-Link Express II interface to AMD Northbridges

 1 / 2 / 4-lane A-Link Express II interface

 Dynamic detection of lane configuration

 High data transfer bandwidth (up to 2.5 Gb/s

/ Lane)

PCI Host Bus Controller

 Supports PCI bus at 33 MHz

 PCI Rev. 2.3 specification support

 Supports up to 6 bus master devices

SMBus Controller

 SMBus Rev. 2.0 compliant

 Support SMBALERT # signal / GPIO

Interrupt Controller

 Supports IOAPIC/X-IO APIC mode for 24

channels of interrupts

 Supports 8259 legacy mode for 15 interrupts

 Supports programmable level/edge

triggering on each channels

 Supports serial interrupt on quiet and

continuous modes

DMA Controller

 Two cascaded 8237 DMA controllers

 Supports PC/PCI DMA

 Supports 40-bit addressing

 Interrupt steering supported for plug-n-play

devices

 BIOS / Hardware support to hide PCI device

 Spread spectrum support

USB Controllers

 5 OHCI and 2 EHCI Host controllers to

supports 12 USB 2.0 ports and 2 dedicated USB 1.1 ports

 ACPI S1 ~ S5 supported

 Legacy Keyboard/Mouse support

 USB debug port

 Port disable supported with individual control

 Supports LPC DMA

 Supports type F DMA

LPC Host Bus Controller

 Supports LPC based super I/O and flash

 Two Master/DMA devices supported

 Support for TPM version 1.1/1.2 devices

 Supports SPI devices

SATA Controller

 Supports six SATA ports with transfer rates

 Complies with SATA 2.5 specification

8 Introduction

devices

up to 3 Gb/s

45215 Rev. 1.60 November 09

 Supports both SATA 1.5 and SATA 3.0

compliance devices

 Two modes of operation are supported

 Legacy Mode using I/O space

 AHCI mode using the Memory space

 Parallel ATA emulation supported to allow

seamless support for IDE software.

 Supports e-SATA

 Supports hot plug for AHCI mode

Legacy IDE Emulation Support

 Legacy Mode using I/O space

 Parallel ATA emulation supported to allow

seamless support for IDE software.

AMD RAID Support

 Supports integrated RAID 0, RAID 1, and

RAID 10 (requires use of 4 or more SATA ports) functionalities across all 6 ports.

AHCI Support

 AHCI mode using the memory space

AMD SB710 Databook

 4 Independent input streams (DMA)

 Multiple channels of audio output per stream

 Support up to 4 codec’s

 Up to 192 kHz Sample Rate and 32-bit

Audio

 64-bit addressing capability for DMA Bus

Master

 Unified Audio Architecture (UAA) compatible

 HD Audio registers can be located anywhere

in the 64-bit address space

Timers

 8254 compatible timer

 Microsoft High Precision Event Timer

(HPET)

 ACPI power management timer

 Watchdog timer

RTC (Real Time Clock)

 256-byte battery-backed CMOS RAM

 Hardware supported century rollover

 RTC battery monitoring feature

 Supports AHCI hardware assist to support

advanced features such as NCQ (Native Command Queuing), Hot Plug, and Device or Host initiated power Management (DIPM /HIPM)

IDE Controller

 Single PATA channel support

 Supports PIO, Multi-word DMA, and Ultra

DMA 33/66/100/133 modes.

 32x32-byte buffers each channel for

buffering

 Swap bay support by tri-state IDE signals

 Supports Message Signaled Interrupt

(MSI).

 Integrated IDE series resistor

High Definition Audio

 4 Independent output streams (DMA)

Power Management

 ACPI specification 3.0 compliant power

management schemes

 Supports C1e, C2, C3 and C3 pop-up

 Supports S0, S1, S3, S4, and S5

 Wakeup events for S1, S3, S4/S5 generated

by:

 Any GEVENT pin

 Any GPM pin

 USB

 Power Button

 Internal RTC wakeup

 SMI# event

 Full support for On-Now

 CPU SMM support, generating SMI# signal

upon power management events

 GPIO supports on external wake up events

Introduction 9

AMD SB710 Databook

 CLKRUN# supported on PCI power

management

 ALPM (HIPM) on SATA

 DIPM on SATA

Note: Advanced Power Management (APM) is not supported.

Hardware Monitor

 Hardware monitoring support for voltage

sensors, fan control, and digital TSI to AM3 processors. Note: Temperature monitoring is NOT supported.

Integrated Micro-Controller (IMC)*

 Supports integrated IR transceivers for

Media Center applications.

45215 Rev. 1.60 November 09

* Note: While the IMC block on the SB710 has to be enabled for infrared controller interface support, no IMC advanced features (like keyboard scan matrix, PS2, or power management controllers) are supported by the SB710 even if the term "IMC" may appear in block name, pin names, register names, or register field names, etc., of the device.

Over Clocking

 Provides support for enhanced CPU

performance tuning using the AMD Advanced Clock Calibration (ACC) performance tuning utility.

10 Introduction

45215 Rev. 1.60 November 09

1.2 Part Number and Branding

AMD SB710 Databook

Figure 1-1: SB710 Branding Diagram

Note 1: Marketing logo

Note 2: AMD product type

Note 3: Date Code (YYWW). YY-assembly start year, WW-assembly start week.

Note 4: COO. Country of origin (assembly site)

Note 5: This is wafer foundry’s lot number for the product.

Note 6: AMD part number (see Table 1-1 below)

Table 1-1: S

Substrate

Revision

C A14 218-0660017

710 Part Numbers

B

ASIC

Revision

AMD Part Number

Introduction 11

AMD SB710 Databook

2 SB710 Block Diagram

45215 Rev. 1.60 November 09

Figure 2-1: SB710 Block Diagram Showing the Internal PCI Devices and Major Function Blocks

12 SB710 Block Diagram

45215 Rev. 1.60 November 09

AMD SB710 Databook

3 SB710 Power on Sequence and Timing

3.1 Power Up and Down Sequences

Simple diagrams of the SB710 power up sequences are shown in Fi gure 3-1 and Figure 3-2 below. A

power detection circuit is integrated into the SB710. This circuit will monitor SB PWR_GOOD and will assert A_RST# and LDT_RST# for as long as SB PWR_GOOD is false. After SB PWR_GOOD has been

asserted, A_RST#, followed by LDT_RST#, will be de-asserted. Table 4-1 shows the timing requirements referenced in Figure 3-1 th

rough Figure 3-5

the ramp time for any rail be less than 40ms.

Table 3-1: SB710 Power Up/Down Sequence Timing

Symbol Min. Max. Description

T1 T2 10 ms – +3.3V_S5 to resume reset (RSMRST#).

T2A – 50 ms

T3 32 ms – RSMRST# de-asserted to Start of RTCCLK output from SB710. T4 50 ns SB PWR_GOOD de-assertion to NB_PWRGD de-assertion delay.

T7 0 ns 30 ns

T7A – 50 ms

T7B – 1 ms SB PWR_GOOD fall time.

T8A

T8B – T8C 1.0 ms 2.3 ms PCIRST# to LDT_RST#. T8D 98 ms 108 ms NB_PWRGD to LDT_PG.

T9 101 ms 113 ms SB PWR_GOOD to PCIRST#. T9A 101 ms 113 ms SB PWR_GOOD to A_RST# (T9-T8A). T9B 31 ms – T10 -31 ms – PCIE_CLKP/N stable time before SB PWRGOOD assertion. T11 36 ms 41 ms

T13

T13A 80 ns –

T14 1 ns –

T15 5 s –

T16A 40 µs – LDT_STP# assertion to LDT_RST# assertion. T16B 4 µs – LDT_RST# assertion to SLP_S3# assertion.

Note 1

0 ns

Note 4

– 15 ns Wake Event (except PwrButton) to SLP_S3# / SLP_S5#.

200 ns – Wake Event (PwrButton) to SLP_S3# / SLP_S5# (S5/S4/S3  S0)

8 ns -- Wake Event (PwrButton) to SLP_S3# / SLP_S5# (G3  S5  S0)

100 ns A_RST# (PCI host bus reset) to PCIRST#.

Note 5

+3.3V_S5 to +1.2V_S5

Resume reset (RSMRST#) rise time (10% to 90%). SB710 has a Schmitt trigger input with de-bouncing logic on this pin, so the value is relaxed relative to earlier AMD SB designs.

SB PWR_GOOD assertion to NB_PWRGD assertion delay when using the SB710 NB_PWRGD output. This parameter is the internal delay of the SB. The system board design may add additional delay due to loading and trace length. The acceptable delay including system layout / loading is 1 ms maximum..

SB PWR_GOOD rise time (10% to 90 %). See Note 3. SB710 has a Schmitt trigger with de-bouncing logic on this pin, so the value is relaxed relative to earlier AMD SB designs.

KBRST# to A_RST#.

SB PWR_GOOD to LDT_STP#. See Note 11

SB PWR_GOOD to stable PCICLK 33 MHz. See Note 8.

SB PWR_GOOD must be de-asserted before VDD (PS PWOK) drops more than 5% off the nominal value. See Note 9.

SB PWR_GOOD de-assertion to Resume Reset (RSMRST#) assertion. See Note 10.

[Not illustrated] VBAT to +3.3V_S5 to +1.2V_S5. Must be greater than 5 seconds to allow start time for the internal RTC.

. Besides the illustrated requirements, it is also required that

See Notes 1 to 12 in the Power Up Sequence Timing Notes section following the timing diagrams.

SB710 Power on Sequence and Timing 13

AMD SB710 Databook

S5

PWR_BTN#

WAKE#

SLP_S5#/ SLP_S3#

VBAT

RTC clock In

VBAT

Wake Event

45215 Rev. 1.60 November 09

S0

S5 G3G3

+3.3V_S5

1.2V_ S5

RSMRST#

RTCCLK out

PS PWOK

S 0 power rails

System clocks

SB PWR_ GOOD

NB_ PWRGD

LDT_PG

A_ RST#

KBRST#

PCIRST#

( See Note 1)

( See Note 1 & 2)

T1

T2A

S 5 STRAPS

T2

T3

T13A

T7A

T7

S 0 STRAPS

( See Note 6)

T8B

( See Note 5)

T8A

T9

( See Note 4)

T8C

T4

T7B

LDT_ RST#

PCIE_ RCLKP/N

PCICLK[5:0]

ALLOW_ LDTSTP

LDT_STP#

( Note 8)

Note 11

T11

T9B

Figure 3-1: SB710 Power Up/Down Sequence

14 SB710 Power on Sequence and Timing

45215 Rev. 1.60 November 09

PWR_BTN#

WAKE#

SLP_S3#

S3

Wake Event

S0

AMD SB710 Databook

S3

SLP_S5#

VBAT

RTC clock

+3.3V_S5

+1.2V_S5

RSMRST#

PS PWOK

S0 power rails

System clocks

SB PWRGOOD

NB_PWRGD

LDT_PG

A_RST#

KBRST#

PCIRST#

LDT_RST#

GND

(See Note 1 & 2)

T7A

T10

T13A

T7

T8B

(See Note 5)

T8A

(See Note 4)

T9

T8C

T7B

PCIE_RCLKP/N

ALLOW_LDTSTP

PCICLK[5:0]

LDT_STP#

T11

(Note 8)

T9B

Figure 3-2: SB710 S3/S0 Power Up/Down Sequence

SB710 Power on Sequence and Timing 15

AMD SB710 Databook

45215 Rev. 1.60 November 09

Power up Sequence Timing Notes

Note 1: There is no specific power sequencing requirement other than those indicated in Note

2 below. The SB710 power rails are grouped in four different voltages:

I. +5 V, which includes V5_VREF

II. +3.3 V, which includes VDDQ, VDD33_18 (IDE mode)

III. +1.2 V, which includes AVDDCK_1.2V, AVDD_SATA, PLLVDD_SATA, PCIE_PVDD,

PCIE_VDDR, CKVDD_1.2V

IV. +1.8 V

Note 2: V5_VREF is used in the SB710 for the 5-V PCI signal tolerance. VDDQ (+3.3 V) & VDD33_18 (3.3 V) must not exceed V5_VREF by more than 0.6 V at any time during ramp up, steady state, or ramp down. The suggested circuit below should be used to maintain relationship between V5_VREF and VDDQ and VDD33_18.

Figure 3-3: Circuit for Maintaining Proper Relationship between +V5_VREF and VDDQ

Note 3: The SB710 will latch the straps after rising edge of SB PWR_GOOD only once. With

debouncing of SB PWR_GOOD, the latching of strap will occur at approximately ~10ms after the rising edge of SB PWR_GOOD.

Note 4: Typical time between A_RST# and PCIRST# is 75 ns. The measurement should be done at 10% of both signals. Loading on the motherboard may cause the measurement at 90% be more than the spec.

Note 5: The KBRST# should be de-asserted before A_RST# (LDT_RST#) is de-asserted.

Note 6: Type II Standard and Debug straps will be latched after SB PWR_GOOD is asserted.

Type I straps are latched on resume reset rising edge. Refer to Section 4: SB710 Strap

Information for stra

Note 7: The SB710 will not monitor the ALLOW_LDTSTP signal on power up. This signal is only used on C3 transitions.

Note 8: The PCI Clock may be stable before T11 min. under some conditions; however in all cases, the PCI Clock is guaranteed to be stable only between T11 min and max.

Note 9: The SB710 will monitor internally the power down events and protect the internal circuit during the power down event. This includes power down during the S3, S4, and S5 states. During an unexpected power failure or G3 state, the relationship between the 1.2 V (VDD) and SB Power Good should be maintained to protect the internal logic of the SB710.

p timing.

Note 10: The following figure shows the timing of SB PWR_GOOD de-asserted to RSMRST# de-asserted during a power down sequence. However, this timing only applies to S0 to G3 state transition, because G3 state is where both signals are inactivated.

16 SB710 Power on Sequence and Timing

45215 Rev. 1.60 November 09

AMD SB710 Databook

Figure 3-4: Timing for SB PWR_GOOD De-asserted to RSMRST# De-asserted

Note 11: On first power up, G3  S5, or after RSMRST# assertion, the LDT_STP# will be asserted

with CPU_VDDIO power. On subsequent power up, S5  S0, the timing on T9B will apply.

Figure 3-5: Timing for LDT_STP# assertion on first power up (G3  S5)

Note 12: The S5_3.3V ramp down should be controlled to achieve a slew rate of 8mV/ µS or lower.

Figure 3-6: S5_3.3V Power Down Sequence Requirement

SB710 Power on Sequence and Timing 17

AMD SB710 Databook

45215 Rev. 1.60 November 09

4 SB710 Strap Information

There are two kinds of strap-latching logic, Type I and Type II. Type I straps will be latched on G3 to S5 transition on rising edge of RSMRST#. Type II straps are latched on S5 to S0 transition after rising edge of PWR_GOOD assertion.

Straps I Capture

S5_1.2V

RsmRst#

STRAPs (board)

VDD

PwrGood

Straps Type I

Straps Type II

Undefined

Don' t care

Straps I

Figure 4-1: Straps Capture

Straps II Capture

Straps Type I

Straps II

Straps Type II

Figure 4-2: Type II Straps Capture timing

18 SB710 Strap Information

45215 Rev. 1.60 November 09

AMD SB710 Databook

Figure 4-3: Type I Straps Capture timing

Straps are also classified in two groups, standard and debug. Straps in the standard group are used for selecting on power up the desired modes of ASIC operation and additional optional features. Straps in debug group are for debugging at the system-level, mainly during the pre-production stage. Debug straps should have provision for PU or PD so they can be configured to either option when required for debug purposes.

Table 4-1 an

d Table 4

-2 show the function of every strap signal in the design. All straps are defined such

that in the most likely scenario of operation, they will be set to the recommended (or safest) values. The values shown in the Description column are the external board strap values, with 3.3V being a pull-up (PU) and 0V a pull-down (PD).

Table 4-1: Standard Straps

Pad Name Strap Name Type Description

ROM_TYPE_1 ROM_TYPE_0 ROM Type

3.3 V 3.3 V Reserved

3.3 V 0 V SPI ROM

{IMCGPIO17, IMCGPIO16 }

{ ROM_TYPE_1,

ROM_TYPE_0 }

0 V 3.3 V LPC ROM (Supports

I

0 V 0 V Firmware Hub

both LPC and PMC ROM types)

These two strap pins should be configured to the corresponding state that matches the Hardware ROM type installed.

SB710 Strap Information 19

AMD SB710 Databook

Pad Name Strap Name Type Description

IMC_ENABLE

Integrated Microcontroller (IMC)

I

0 V – Disable IMC

3.3 V – Enable IMC. Required for IR controller support.

45215 Rev. 1.60 November 09

LPCCLK0

PCI_ROM_BOOT

LPCCLK1

AZ_RST#

PCICLK5 Reserved — Reserved PCICLK4 Reserved — Reserved

PCIE_PLL_ENAB

LE

IMC_ENABLE

PCI_ROM_BOOT

Revision A11 strap defination Booting from PCI memory

0 V – disable PCI ROM boot (Default)

II

I

II

3.3 V – enable PCI ROM boot

Note: This feature is for debug pupose only. After a G3  S5 transition the system will allow boot from PCI memory only once. Subsequent S5  S0 transition will not boot from PCI memory.

Enable PCI-E PLL

0 V – Normal operation. PCI-E clock enabled for internal PLL reference clock.

3.3 V – Test / debug. PCI-E clock disconnected from internal PLL.

Revision A11 strap defination Integrated Microcontroller (IMC)

0 V – disable IMC

3.3 V – enable IMC

Booting from PCI memory

0 V – disable PCI ROM boot (Default)

3.3 V – enable PCI ROM boot

Note: This feature is for debug pupose only. After a G3  S5 transition the system will allow boot from PCI memory only once. Subsequent S5  S0 transition will not boot from PCI memory.

Enable/Disable additional straps for debugging (see

Table 4-2)

PCICLK3

PCICLK2 Watchdog_Enable

Debug_Straps

II

0 V – use hardcoded defaults for Debug Straps (Default)

3.3 V – enable additional Debug Straps

Watchdog function

0 V – disable watchdog function on NB_PWRGD ball

3.3 V – enable watchdog function on NB_PWRGD ball

Table 4-2: Debug Straps

Pad Name Strap Name Type Description

PCI_AD30 Reserved — PCI_AD29 Reserved —

PCI_AD28 Reset_Length

Reserved (Internal PU of 15 k) Reserved (Internal PU of 15 k) Generate a short reset

II

0 V – Use short reset (reserved, do not use)

3.3 V – Use long reset (Default) (Internal PU of 15 k)

20 SB710 Strap Information

45215 Rev. 1.60 November 09

Pad Name Strap Name Type Description

Bypass PCI PLL

0 V – Bypass internal PLL clock . Use REQ3# as A-Link bypass clock

PCI_AD27 PCI_PLL

PCI_AD26 ACPI_BCLK

PCI_AD25 IDE_PLL

PCI_AD24 PCIE_EEPROM

PCI_AD23 Reserved —

II

Use GNT3# as B-Link bypass clock

3.3 V – Use internal PLL-generated PLL CLK (Default) (Internal PU of 15 k)

Bypass ACPI_BCLK

0 V – Bypass internal generated acpi_bclk. GNT0# as acpi_bclk bypass clock.

3.3 V – Use internal generated acpi_bclk (Default)

(Internal PU of 15 k) Bypass IDE CLK 0 V – Bypass internal Ide Clk Use GNT2# as Ide 66-MHz bypass clock. Use REQ2# as Ide 50-MHz bypass clock. Use REQ1# as Ide 33-MHz bypass clock.

3.3 V – Use internal PLL Ide Clk (Default) (Internal PU of 15 k). A-Link Express-II core strap from I2C ROM enable

0 V – Use EEPROM PCI-E straps, getting the value

from I2C EPROM.

I2C EPROM ADDRESS set to all zeroes.

Use GNT4# as SDA

Use REQ4# as SCL.

3.3 V – Use default PCI-E straps (Default)

(Internal PU of 15 k) Reserved (Internal PU of 15 k)

AMD SB710 Databook

Table 4-3: Additional Straps

The following strap is not captured by the straps logic, but is required to make the internal RTC work properly.

Pad Name Strap Name Description

The pin should be pulled-up to S5_3.3V and a crystal should be put

RTCCLK —

on X1/X2 to enable the internal RTC. Otherwise, the internal RTC may not function properly

SB710 Strap Information 21

AMD SB710 Databook

45215 Rev. 1.60 November 09

5 Integrated Resistor and External Pull-up/Pull-down

Resistor Requirements

Table 5-1: External Resistor Requirements and Integrated Pull-Up/Down

Interface Signal Name

IDE

IDE_DRQ Integrated 5.6 K Pull-down —

IDE_IORDY Integrated 4.7 K Pull-up —

IDE_IRQ Integrated 10 K Pull-down —

IDE_D7/GPIO22

IDE_D[15:0]/GPIO[30:23, 21:15]

IDE_A[2:0]

IDE_CS[3,1]#

IDE_DACK#, IOW#, IOR#,

PCIE_CALRP

PCIE_CALRN External 2.05 K ( 1%

Value of Integrated / External Resistor

Integrated 27  + integrated 10 K

Integrated 27 

External 562  ( 1% tolerance ) Reference resistor for the Tx termination.

tolerance ) Reference resistor for the Rx termination

Resistor Type

Series + Pulldown

Series

Series —

Series ——

Pull-down to VSS_PCIE

Pull-UP to VDD_PCIE

Register for programming the integrated PU/PD

(See GPIO section below)

PCI-E

—

USB

HD Audio

NB ALLOW_LDTSTP External Pull-up Pull-up —

Processor

PCI

USB HSD[11:0]P Integrated 15 K Pull-down —

USB_HSD[11:0]N Integrated 15 K Pull-down —

USB_FSD[13:12]P Integrated 15 K Pull-down —

USB_FSD[13:12]N Integrated 15 K Pull-down —

AZ_SDIN[2:0]/ GPIO[44:42]

AZ_SDIN3/GPIO46 Integrated 50 K Pull-down (See GPIO section

LDT_PG External Pull-up Pull-up —

LDT_STP# External Pull-up Pull-up —

LDT_RST# External Pull-up Pull-up —

INTE#/GPIO33 Integrated 8.2 K Pull-up (See GPIO section

INTF#/GPIO34 Integrated 8.2 K Pull-up (See GPIO section

INTG#/GPIO35 Integrated 8.2 K Pull-up (See GPIO section

INTH#/GPIO36 Integrated 8.2 K Pull-up (See GPIO section

Integrated 50 K Pull-down (See GPIO section

below)

22 Integrated Resistor and External Pull-up/Pull-down Resistor

Requirements

45215 Rev. 1.60 November 09

Interface Signal Name

AD[31:23] Integrated 15 K Pull-up PM_REG 41h /

FRAME# Integrated 8.2 K Pull-up —

TRDY#/ROMOE# Integrated 8.2 K Pull-up —

IRDY# Integrated 8.2 K Pull-up —

DEVSEL#/ROMA0 Integrated 8.2 K Pull-up —

STOP# Integrated 8.2 K Pull-up —

SERR # Integrated 8.2 K Pull-up —

PCI_PERR# Integrated 8.2 K Pull-up —

LOCK# Integrated 8.2 K Pull-up —

CLKRUN# Integrated 8.2 K Pull-up —

REQ0# Integrated 15 K Pull-up —

REQ1# Integrated 15 K Pull-up —

REQ2# Integrated 15 K Pull-up —

REQ3#/GPIO70 Integrated 15 K Pull-up (See GPIO section

REQ4#/GPIO71 Integrated 15 K Pull-up (See GPIO section

BMREQ#/REQ5#/GPIO65 External Pull-up if used

LPC/ SIO/ SPI

Power Management

LAD[3:0] Integrated 15 K Pull-up —

LDRQ0# Integrated 15 K Pull-up —

LDRQ1#/GNT5#/GPIO68 Integrated 15 K Pull-up (See GPIO section

LPC_SMI#/EXTEVNT1# Integrated 10 K Pull-up (See GEVENT

SERIRQ Integrated 8.2 K Pull-up —

GA20IN Integrated 8.2 K Pull-up —

KBRST# Integrated 8.2 K Pull-up —

SPI_CLK/GPIO47 Integrated 10 K Pull-down (See GPIO section

SPI_DI/GPIO12 Integrated 10 K Pull-down (See GPIO section

SPI_DO/GPIO11 Integrated 10 K Pull-down (See GPIO section

SPI_HOLD#/GPIO31 Integrated 10 K Pull-up —

SPI_CS1#/GPIO32 Integrated 10 K Pull-up —

SPI_CS2#/IMC_GPIO2 Integrated 10 K Pull-up LPC PCI config

SLP_S2/ GPM9#

PWR_BTN# Integrated 10 K Pull-up —

Value of Integrated / External Resistor

as REQ5#

Integrated 10 K Pull-down PM2_Rg F8h

Resistor Type

Pull-up (See GPIO section

AMD SB710 Databook

Register for programming the integrated PU/PD

PM_REG 40h Default: Pull-up enabled

below)

section below)

below)

CEh; default Pull-up disabled

Default: Pull-down enabled

Integrated Resistor and External Pull-up/Pull-down Resistor

23

Requirements

AMD SB710 Databook

Interface Signal Name

PWR_GOOD Integrated 10 K Pull-up —

TEST[1:0] Integrated 10 K Pull-down —

TEST2 Integrated 10 K Pull-down —

RTCCLK Integrated 10 K Pull-up PM_Reg: 0Eh

FANOUT0/GPIO3 Integrated 10 K Pull-up —

FANOUT1/GPIO48 Integrated 8.2 K Pull-up —

FANOUT2/GPIO49 Integrated 8.2 K Pull-up —

RSMRST# Integrated 10 K Pull-up —

General Events/ GPM/ GPIO

RI#/EXTEVNT0# Integrated 10 K Pull-up PM2_Rg F5h

LPC_SMI#/EXTEVNT1# Integrated 8.2 K Pull-up PM2_Rg F5h

SMBALERT#/THRMTRIP#/ GEVENT2#

LPC_PME#/GEVENT3# Integrated 10 K Pull-up PM2_Rg F3h

PCI_PME#/GEVENT4# Integrated 10 K Pull-up PM2_Rg F4h

S3_STATE/GEVENT5# GEVENT5#: Integrated

USB_OC6#/GEVENT6# Integrated 10 K Pull-up PM2_Rg F4h

GEVENT7# Integrated 10 K Pull-up PM2_Rg F4h

WAKE#/GEVENT8# Integrated 10 K Pull-up PM2_Rg F5h

USB_OC0#/GPM0# Integrated 10 K Pull-up PM2_Rg F6h

USB_OC1#/GPM1# Integrated 10 K Pull-up PM2_Rg F6h

USB_OC2#/GPM2# Integrated 10 K Pull-up PM2_Rg F6h

USB_OC3#/GPM3# Integrated 10 K Pull-up PM2_Rg F6h

Value of Integrated / External Resistor

Integrated 10 K Pull-up PM2_Rg F3h

10 K S3_STATE: Push/Pull

Resistor Type

Pull-up PM2_Rg F4h

45215 Rev. 1.60 November 09

Register for programming the integrated PU/PD

Default: Pull-up enabled.

Default: Pull-up enabled

24 Integrated Resistor and External Pull-up/Pull-down Resistor

Requirements

45215 Rev. 1.60 November 09

Interface Signal Name

USB_OC4#/GPM4# Integrated 10 K Pull-up PM2_Rg F7h

USB_OC5#/GPM5# Integrated 10 K Pull-up PM2_Rg F7h

BLINK/GPM6# Integrated 10 K Pull-up PM2_Rg F7h

SYS_RESET#/GPM7# Integrated 10 K Pull-up PM2_Rg F7h

USB_OC8#/AZ_DOCK_RST#/ GPM8#

SLP_S2/ GPM9#

GPIO

CLK_REQ0#/SATA_IS3#/ GPIO0

SPKR/GPIO2 Integrated 8.2 K Pull-up PM2_Rg E0h

FANOUT0/GPIO3 Integrated 8.2 K Pull-up PM2_Rg E0h

SMARTVOLT1/SATA_IS2#/ GPIO4

SMARTVOLT2/SHUTDOWN#/ GPIO5

CLK_REQ3#/SATA_IS1#/GPIO6 Integrated 8.2 K

NB_PWRGD Integrated 10 K

DDC1_SDA/GPIO8 Integrated 8.2 K

DDC1_SCL/GPIO9 Integrated 8.2 K

SATA_IS0#/GPIO10 Integrated 8.2 K

SPI_DO/GPIO11 Integrated 10 K Pull down PM2_Rg E2h

Value of Integrated / External Resistor

Integrated 10 K Pull-up PM2_Rg F8h

Integrated 10 K Pull-down PM2_Rg F8h

Integrated 10 K Pull-down PM2_Rg E0h

Integrated 8.2 K

Resistor Type

See Note

AMD SB710 Databook

Register for programming the integrated PU/PD

Default: Pull-up enabled

Default: Pull-up not enabled

Default: Pull-up enabled

Default: Pull-down enabled

Default: Pull-up/Pulldown not enabled

Default: Pull-up enabled

PM2_Rg E1h Default: Pull-up/Pulldown not enabled

PM2_Rg E2h Default: Pull-up/Pulldown not enabled

Default: Pull-down Enabled

Integrated Resistor and External Pull-up/Pull-down Resistor

25

Requirements

AMD SB710 Databook

Interface Signal Name

SPI_DI/GPIO12 Integrated 10 K Pull down PM2_Rg E3h

LAN_RST#/GPIO13 Integrated 8.2 K

ROM_RST#/GPIO14 Integrated 10 K

IDE_D0/FC_ADQ0/GPIO15

IDE_D1/FC_ADQ1/GPIO16

IDE_D2/FC_ADQ2/GPIO17

IDE_D3/FC_ADQ3/GPIO18

IDE_D4/FC_ADQ4/GPIO19

IDE_D5/FC_ADQ5/GPIO20

IDE_D6/FC_ADQ6/GPIO21

IDE_D7/FC_ADQ7/GPIO22

IDE_D8/FC_ADQ8/GPIO23

IDE_D9/FC_ADQ9/GPIO24

IDE_D10/FC_ADQ10/GPIO25

IDE_D11/FC_ADQ11/GPIO26

IDE_D12/FC_ADQ12/GPIO27

IDE_D13/FC_ADQ13/GPIO28

Value of Integrated / External Resistor

Integrated 27 

Integrated 27  + integrated 10 K

Integrated 27 

Resistor Type

See Note

Series PM2_Rg E3h

Series PM2_Rg E4h

Series PM2_Rg E5h

Series + Pulldown

Series PM2_Rg E5h

Series PM2_Rg E6h

Series PM2_Rg E7h

45215 Rev. 1.60 November 09

Register for programming the integrated PU/PD

Default: Pull-down Enabled

PM2_Rg E3h Default: Pull-up/Pulldown not enabled

Default: Pull-up/Pulldown not enabled

Default: Pull-down not enabled

Default: Pull-up/Pulldown not enabled

PM2_Rg E5h Default: Pull-down not enabled

Default: Pull-down not enabled

Default: Pull-up/Pulldown not enabled

26 Integrated Resistor and External Pull-up/Pull-down Resistor

Requirements

45215 Rev. 1.60 November 09

Interface Signal Name

IDE_D14/FC_ADQ14/GPIO29

IDE_D15/FC_ADQ15/GPIO30

SPI_HOLD#/GPIO31 Integrated 10 K Pull-Up PM2_Rg E7h

SPI_CS1#/GPIO32 Integrated 10 K Pull-up PM2_Rg E8h

INTE#/GPIO33 Integrated 8.2 K Pull-up PM2_Rg E8h

INTF#/GPIO34 Integrated 8.2 K Pull-up PM2_Rg E8h

INTG#/GPIO35 Integrated 8.2 K Pull-up PM2_Rg E8h

INTH#/GPIO36 Integrated 8.2 K Pull-up PM2_Rg E9h

CLK_REQ1#/SATA_IS4/ FANOUT3/GPIO39

CLK_REQ2#/SATA_IS5/ FANIN3/GPIO40

AZ_SDIN[2:0]/ GPIO[44:42]

AZ_SDIN3/GPIO46 Integrated 50 K Pull-down PM2_Rg EBh.

SPI_CLK/GPIO47 Integrated 10 K Pull-down PM2_Rg EBh.

FANOUT1/GPIO48 Integrated 8.2 K Pull-up PM2_Rg ECh.

FANOUT2/GPIO49 Integrated 8.2 K Pull-up PM2_Rg ECh.

GPIO 64:50 Integrated 10 K

BMREQ#/REQ5#/GPIO65 Integrated 8.2 K

Value of Integrated / External Resistor

Integrated 27 

Integrated 8.2 K Pull-down PM2_Rg E9h

Integrated 8.2 K Pull-down PM2_Rg EAh

Integrated 50 K Pull-down PM2_Rg EAh

Resistor Type

Series PM2_Rg E7h

See Note

AMD SB710 Databook

Register for programming the integrated PU/PD

Default: Pull-up/Pulldown not enabled

Default: Pull-up enabled

Default: Pull-down enabled

Default: Pull-up enabled

PM2_rg F0h:ECh Default: Pull-up/Pulldown not enabled

PM2_Rg F0h Default: Pull-up/Pulldown not enabled

Integrated Resistor and External Pull-up/Pull-down Resistor

27

Requirements

AMD SB710 databook

Specifications and Main Features

Frequently Asked Questions

User Manual