5
4
3
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1
Berry Discrete/UMA Schematics Document
D D
AMD Danube CPU S1g4
AMD GPU Madison-LP/M96-LP M2
C C
RS880M + SB820M
2010-03-08
B B
REV : A00
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
DY : Nopop Component
5
4
3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Cover Page
Cover Page
Cover Page
1 95 Monday, March 08, 2010
1 95 Monday, March 08, 2010
1 95 Monday, March 08, 2010
1
A00
A00
A00
5
4
3
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1
CHARGER
Project code :91.4HH01.001
Berry DG15 Discrete/UMA Block Diagram
PCB P/N :
Revision :X-Build
AMD Champlain
D D
VRAM
64Mx16bx8 (1GB)
85,86,87,88
4
CPU S1G4
35W Max
8,9,10,11
DDR III 1333
DDR III 1333
DDRIII
800/1066/1333
DDRIII
800/1066/1333
DDR3
800MHz
OUT
AMD Graphic
M96-M2 LP
HDMI
C C
LCD Conn
(LVDS & Camera Conn.)
57
54
HDMI(Share PCIe x 4)
LVDS(Dual Channel)
80,81,82,83
PCIe x 16
North Bridge
CPU I/F
AMD RS880M
LVDS, CRT I/F
INTEGRATED GRAHPICS
HyperTransport
16X16
IN
12,13,14,15
SIDE-PORT
64Mx16bx1 (1GB)
A-LINK
4X4
CRT
RGB CRT
South Bridge
AMD SB820M
CRT Board
USB x 2
B B
CardReader
Connector
77
Realtek
RTS5159
USB2.0 x 2
Card Reader
Connector
78
USB2.0
14 USB 2.0 ports
ETHERNET (10/100/1000Mb)
High Definition Audio
2 PCIE GPP
6 SATA ports
ACPI 1.1
LPC I/F
PCI/PCI BRIDGE
20,21,22,23,24
USB 2.0
LPC Bus
SD/SDIO/MMC
MS/MS Pro/xD
Azalia
Internal Analog MIC
MIC IN
A A
HP1
CODEC
&
OP AMP
IDT 92HD79B1
AZALIA
30
SATA
HDD
59 59
SATA
ODD
SPI
Flash ROM
2MB
NUVOTON
NPCE781BA0DX
Touch
62 68 25
PAD
2CH SPEAKER
5
4
3
DIMM1
DIMM2
VRAM
PCIE x 1
USB 2.0 x 1
SATA x 1
PCIE x 2& USB 2.0 x 2
KBC
68
KB
18
19
14
37
USB 2.0 x 1
USB 2.0 x 1
Thermal Int.
EMC2102
Fan
58
2
I/O Board
Connector
76
Camera Conn
(LVDS & Camera Conn.)
Bluetooth Conn
39
RJ45
CONN
10/100 NIC
Realtek RTL8103T
USB x 1
E-SATA/USB
COMBO
MiniCard x 2
WLAN&WWAN
54
73
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
BQ24745
INPUTS
+DC_IN_SS
+VCHGR
OUTPUTS
+PWR_SRC
SYSTEM DC/DC
RT8205B
INPUTS
+PWR_SRC
OUTPUTS
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
CPU VDDR
RT9025
INPUTS OUTPUTS
+1.5V_SUS
+CPU_VDDR
CPU CORE
ISL6265AHRTZ-T-GP
INPUTS
+PWR_SRC
OUTPUTS
+VCC_CORE
+VDDNB
AMD RS880M CORE
RT8209
INPUTS OUTPUTS
+PWR_SRC
+NB_VDDC
AMD SB820M S5 POWER
RT9025
INPUTS
+3.3V_ALW
OUTPUTS
+1.1V_ALW
DDR III SUS&VTT
RT8207
INPUTS
+PWR_SRC
OUTPUTS
+1.5V_SUS
DDR III SUS&VTT
RT8207
INPUTS
+PWR_SRC
OUTPUTS
+0.75V_DDR_VTT
AMD GPU CORE
RT8208B
INPUTS
OUTPUTS
+VGA_CORE +PWR_SRC
PCB LAYER
L1: Top
L2: VCC
L3: Signal
L4: Signal
L5: GND
L6: Bottom
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
2 95 Thursday, March 04 , 2010
2 95 Thursday, March 04 , 2010
2 95 Thursday, March 04 , 2010
1
46
48
47
50
48
49
49
89
A00
A00
A00
45
A
B
C
D
E
Power Shape
Regulator LDO Switch
Power Block Diagram
4 4
Adapter
+PWR_SRC
ISL6265AHRTZ RT8209EGQW RT8207
RT8208B
AO4407A
Charger
BQ24745
Battery
3 3
+3.3V_RTC_LDO
2 2
+VCHGR
UP7534
+5V_USB1
RESISTER
RT8205B
+5V_ALW
AO4468
+5V_RUN
RESISTER
+VCC_CORE
UP7534
+5V_USB2
+VDDNB(CPU)
SI2301BDS
G5285T11U
AO4468
+3.3V_RUN
RTS5159
+1.1V_RUN
+3.3V_ALW
RT9013-25PB
PA102FMG
+3.3V_LAN
RTL8103T
+1.5V_SUS +VGA_CORE
AO4468
+1.5V_RUN
+1.8V_RUN
AO4468 APL5930
+1.5V_RUN_VGA +1.0V_RUN_VGA
APL5930
APL5930
+1.8V_RUN_VGA
RT9025
VDDR(CPU)
RT9025
+1.1V_ALW
+PVDD
1 1
A
+AVDD
+3.3V_RUN_VGA
B
+LCDVDD
+3.3V_RUN_CARD
+2.5V_RUN
C
+1.2V_LOM
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Power Block Diagram
Power Block Diagram
Power Block Diagram
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
3 95 Thursday, March 04 , 2010
3 95 Thursday, March 04 , 2010
3 95 Thursday, March 04 , 2010
E
A00
A00
A00
5
4
3
2
1
SB820M SMBus Block Diagram
D D
+3.3V_RUN
CLK GEN
SB_SMBCLK
SRN2K2J
SB820M
C C
B B
SCL0
SDA0
SCL1
SDA1
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
SMB_CLK
SMB_DATA
CPU_SIC
CPU_SID
SB_SMBCLK_R
SB_SMBDATA_R
+3.3V_ALW
SRN10KJ-5-GP
SRN1KJ-7-GP
SB_SMBDATA
+1.5V_SUS
SCL
SDA
SMBus Address:0xD2
SB_SMBCLK
SB_SMBDATA
DIMM 1
SCL
SDA
SMBus Address:0xA0,0x30
SB_SMBCLK
SB_SMBDATA
DIMM 2
SCL
SDA
SMBus Address:0xA4,0x34
WWAN
MINI CARD
SB_SMBCLK
SMB_CLK
SB_SMBDATA
SMB_DATA
SMBus address:
WLAN
MINI CARD
SMB_CLKSB_SMBCLK
SMB_DATA
SB_SMBDATA
SMBus address:
CPU S1G4
SIC
CPU_SIC
SID
CPU_SID
NPCE781
KBC SMBus Block Diagram
+5V_RUN
SRN10KJ-5-GP
TPDATA
KBC
GPIO61/SCL2
GPIO62/SDA2
PSDAT1
SCL1
SDA1
TPCLKPSCLK1
BAT_SCL
BAT_SDA
KBC_SCL1
KBC_S
DA1
+KBC_PWR
+3.3V_ALW
SRN4K7J-8-GP
SRN4K7J-8-GP
SRN100J-3-GP
2N7002SPT
PBAT_SMBCLK1
PBAT_SMBDAT1
+3.3V_RUN
TPDATA
TPCLK
+3.3V_RUN
TouchPad Conn.
TPDATA
TPCLK
SMBus address:
Battery Conn.
CLK_SMB
DAT_SMB
BQ24745RHDR
SCL
SDA
SMBus address:0x12
SRN4K7J-8-GP
THERM_SCL
THERM_SDA
SMBus address:0x7A
Thermal
SCL
SDA
SMBus address:
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
4 95 Thursday, March 0 4, 2010
4 95 Thursday, March 0 4, 2010
4 95 Thursday, March 0 4, 2010
A00
A00
A00
5
Title
Title
Title
SMBUS BLOCK DIAGRAM
SMBUS BLOCK DIAGRAM
SMBUS BLOCK DIAGRAM
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
4
3
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Date: Sheet of
5
4
3
2
1
Thermal Block Diagram
D D
CPU
H_THERMDA
DP1
SC470P50V3JN-2GP
H_THERMDC
C C
DN1
Thermal
EMC2102
DP2
VGA_THERMDA
SC470P50V3JN-2GP
DN2
VGA_THERMDC
THERMDA
THERMDC
DPLUS
DMINUS
GPU
PMBS3904
Audio Block Diagram
SPKR_PORT_D_L+
SPKR_PORT_D_L-
SPKR_PORT_D_R-
SPKR_PORT_D_R+
HP1_PORT_B_L
HP1_PORT_B_R
Codec
92HD79B1
VREFOUT_A_OR_F
HP0_PORT_A_L
HP0_PORT_A_R
AUD_SPK_L+
AUD_SPK_L-
AUD_SPK_R-
AUD_SPK_R+
AUD_HP1_JACK_L
P1_JACK_R
AUD_H
AUD_VREFOUT_B
AUD_EXT_MIC_L
AUD_EXT_MIC_R
60D4R2F
60D4R2F
4K7R2J-2-GP
AUD_HP1_JACK_L1
Bead
AUD_HP1_JACK_R1
Bead
4K7R2J-2-GP
SPEAKER
60
HP
OUT
60
MIC
IN
60
B B
SC1U10V3KX-3GP
EMC2102_DP3
DP3
PMBS3904
DN3
SC470P50V3JN-2GP
EMC2102_DN3
System sensor, put
between CPU and NB.
A A
5
4
3
PORT_C_L
PORT_C_R
VREFOUT_C
AUD_INT_MIC_R_L
AUD_INT_MIC_R_L
AUD_VREFOUT_C
30
4K7R2J-2-GP
2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
INT_MIC_L_R
Internal
MIC
60
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
THERMAL/AUDIO BLOCK DIAGRAM
THERMAL/AUDIO BLOCK DIAGRAM
THERMAL/AUDIO BLOCK DIAGRAM
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5 95 Thursday, March 04 , 2010
5 95 Thursday, March 04 , 2010
5 95 Thursday, March 04 , 2010
1
A00
A00
A00
5
4
3
2
1
SB820M Strapping
Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide
Name Strap Name Schematic Note
LPCCLK0
D D
EC_PWM3
EC_PWM2
LPCCLK1
PCICLK1
C C
ECEnableStrap
{ROMTYPE_1,
T
YPE_0 }
ROM
CLKGEN
BIF_GEN2_
COMPLIANCE_Strap
PCICLK2 BootFailTmrEn
PCICLK3 DefaultStrapMode
PCICLK4 CPUClkSel
AZ_SDOUT CoreSpeedMode
B B
Embedded Controller (EC)
0 V – Disabled
*
3.3 V - Enabled
ROMTYPE_1 ROMTYPE_0 ROM TYPE
3.3V 0V
3.3V
3.3V
0V 0V
0V 3.3V
*
SPI ROM
Reserved
Firmware Hub
LPC ROM
(supports both LPC and PMC ROM types)
Defines clock generator
*
External clock mode: Use 100-M Hz PCIeR
0V –
3.3V–
k as reference clock and gener ate i
cloc
nternal clocks only.
Integrated clock mode: Use 25- MHz crystal
clock and generate both intern al and external clocks
Set PCIe to Gen II mode
Force PCIe interface at Gen I mode
0V–
PCIe interfacce is at Gen II m ode
*
3.3V-
Not Applicable to SB820M but p rovision for
pull-down is required.
Watchdog function
*
*
Disable the boot fail timer fu nction
0V–
Enable the boot fail timer fu nction
3.3V-
Default Debug Straps
Disable Debug Straps.
0V–
Select external Debug Straps
3.3V–
CPU/NB HT Clock Selection
Reserved.
0V–
*
Required setting for integrate d clock mode.
3.3V–
This strap is not used if the strap CLKGEN is
configured for external clock generator mode.
Slow down core clock for low power platform.
0V–
3.3V-
Performance mode
Low Power mode
*
RS880M Strapping
Capture from 46113_rs880m_ds_nda_1.03
DAC_VSYNC
DAC_HSYNC
SUS_STAT#
STRAP_DEBUG_BUS_GPIO
_ENABLE#
SIDE_PORT_EN#
LOAD_EEPROM_STRAPS#
USB Table PCIE
Pair
USB
Device
USB0 (I/O Board/ESATA)
0
USB1 (I/O Board)
1
USB2 (CRT Board)
2
USB3 (CRT Board)
3
WLAN USB
4
WWAN USB
5
RESERVED
6
RESERVED
7
RESERVED
8
BLUETOOTH
9
CARD READER
10
CAMERA (LVDS CONN)
11
RESERVED
12
RESERVED
13
Schematic Note Strap Function Name
Enables debug bus access
through memory I/O pads and GPIOs.
0: Enable
1: Disable
*
Indicates if memory side-port is available or not
0: Available(UMA)
1: Not available(Discrete)
Selects loading of strap values from EEPROM.
0: I2C master can load strap values from EEPROM if
connected, or use default values if EEPROM is not
connected. Please refer to RS880M's reference
schematics for system level implementation details.
1: Use default values
*
Routing
RS880M
MiniCard WLAN LANE0
LANE1
LANE2
LAN
MiniCard WWAN
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
6 95 Thursday, March 0 4, 2010
6 95 Thursday, March 0 4, 2010
6 95 Thursday, March 0 4, 2010
A00
A00
A00
5
Title
Title
Title
Table of Content
Table of Content
Table of Content
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
5
4
3
2
1
+3.3V_CL K_VDD +3.3V_RU N
R702
R702
1 2
0R0603-P AD
0R0603-P AD
1231-1
D D
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
C701
C701
9/22
+3.3V_RU N +3.3V_ CLK_VDDIO
R703
R703
1 2
0R0603-P AD
0R0603-P AD
1231-1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
C710
C710
DY
DY
9/22
+3.3V_RU N +3.3V_ CLK_VDDREF
R701
R701
1 2
0R0603-P AD
0R0603-P AD
C C
1231-1
1119-3
SB_PW RGD (21 ,41)
WLAN
(100MHz)
WWAN(100MHz)
LAN(100MHz)
B B
VGA(27MHz)
NB(100MHz)
SB(100MHz)
TP701 TP701
TP702 TP702
TP703 TP703
TP704 TP704
TP705 TP705
TP706 TP706
A A
TP707 TP707
TP709 TP709
TP708 TP708
TP_CLK_ SRC6
1
TP_CLK_ SRC6#
1
TP_CLKR EQ0#
1
TP_CLKR EQ3#
1
TP_CLKR EQ4#
1
TP_CLK_ SRC4
1
TP_CLK_ SRC4#
1
R_NB_GP P_CLK
1
R_NB_GP P_CLK#
1
CLK_PCIE_ WLAN (76)
CLK_PCIE_ WLAN# (76)
CLK_PCIE_ WWAN (76)
CLK_PCIE_ WWAN# (76)
CLK_PCIE_ LAN (76)
CLK_PCIE_ LAN# (76)
CLK_VGA _27M_SS (82)
CLK_VGA _27M_NSS (82)
NB_GPPS B_CLK (13)
NB_GPPS B_CLK# (13)
SB_PCIE_C LK (20)
SB_PCIE_C LK# (20)
CLK_NBH T_CLK (13)
CLK_NBH T_CLK# (13)
5
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
9/22
C721
C721
1113-2
+3.3V_CLK_VDD (40 mils)
1 2
1 2
C703
C703
C704
C704
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C712
C712
C713
C713
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R706
R706
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
RN702
RN702
2 3
1
0R4P2R-P AD
0R4P2R-P AD
RN710
RN710
2 3
1
0R4P2R-P AD
0R4P2R-P AD
RN703
RN703
2 3
1
0R4P2R- P AD
0R4P2R- P AD
R713 47R2J-2-G P
R713 47R2J-2-G P
1 2
R714 33R2J-2-G P
R714 33R2J-2-G P
1 2
RN704
RN704
2 3
1
0R4P2R-P AD
0R4P2R-P AD
RN705
RN705
2 3
1
0R4P2R-P AD
0R4P2R-P AD
RN706
RN706
2 3
1
0R4P2R-P AD
0R4P2R-P AD
10/1
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+3.3V_RU N
10KR2J-3-GP
10KR2J-3-GP
RN
RN
RN
RN
R N
R N
DIS
DIS
DIS
DIS
RN
RN
RN
RN
RN
RN
1 2
C705
C705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C714
C714
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
R705
R705
EC702
EC702
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
DY
DY
4
4
10/5
4
10/5
4
4
4
1 2
C706
C706
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C715
C715
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+3.3V_CL K_VDDREF
1 2
1 2
C708
C708
C707
C707
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1119-3
1 2
C717
C717
C716
C716
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+3.3V_CL K_VDDIO
CLKGEN_ PD#
R_VGA_2 7M_SS_CLK
R_VGA_2 7M_NSS_CLK
NB_GPPS B_CLK_R
NB_GPPS B_CLK#_R
SB_PCIE_C LK_R
SB_PCIE_C LK#_R
CLK_NBH T_CLK_R
CLK_NBH T_CLK#_R
1119-3
1 2
C709
C709
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+3.3V_CL K_VDD
R_NB_GP P_CLK
R_NB_GP P_CLK#
CLK_MINI1_R
CLK_MINI1#_R
CLK_SRC 2
CLK_SRC 2#
LAN_CLK _R
LAN_CLK #_R
TP_CLK_ SRC4
TP_CLK_ SRC4#
TP_CLK_ SRC6
TP_CLK_ SRC6#
4
U701
U701
26
VDDATIG
25
VDDATIG_IO
48
VDDCPU
47
VDDCPU_IO
16
VDDSRC
17
VDDSRC_IO
11
VDDSRC_IO
35
VDDSB_SRC
34
VDDSB_SRC_IO
40
VDDSATA
4
VDD
55
VDDHTT
56
VDDREF
63
VDD48
51
PD#
22
SRC0T_LPRS
21
SRC0C_LPRS
20
SRC1T_LPRS
19
SRC1C_LPRS
15
SRC2T_LPRS
14
SRC2C_LPRS
13
SRC3T_LPRS
12
SRC3C_LPRS
9
SRC4T_LPRS
8
SRC4C_LPRS
SRC6T/SATAT_LPRS42GNDSATA
41
SRC6C/SATAC_LPRS
6
SRC7T_LPRS/27MHZ_SS
5
SRC7C_LPRS/27MHZ_NS
37
SB_SRC0T_LPRS
36
SB_SRC0C_LPRS
32
SB_SRC1T_LPRS
31
SB_SRC1C_LPRS
54
HTT0T_LPRS/66M
53
HTT0C_LPRS/66M
ICS9LPRS4 80BKLFT-GP
ICS9LPRS4 80BKLFT-GP
71.09480.A03
71.09480.A03
1st 71.09480.A03
2nd 71.08628.003
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
CPUKG0T_LPRS
CPUKG0C_LPRS
REF0/SEL_HTT66
REF1/SEL_SATA
NB ALINK
(100MHz)
SB PCIE
(100MHz)
VGA Madison
(27MHz)
SMBCLK
SMBDAT
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
48MHZ_0
REF2/SEL_27
GNDATIG
GND
GNDHTT
GNDREF
GNDCPU
GND48
GNDSRC
GNDSRC
GNDSB_SRC
GND
X1
X2
61
62
2
3
30
29
28
27
23
45
44
39
38
50
49
64
59
58
57
43
24
7
52
60
46
1
10
18
33
65
SEL_HTT66
FS0
SEL_SATA
FS1
SEL_27MHz
S2
F
* default
3
CLKGEN_ X1
CLKGEN_ X2
SB_SMBC LK_CK
SB_SMBD ATA_CK
GFX_CLK P
GFX_CLK N
NB_GFX_ CLK_R
NB_GFX_ CLK_R#
10/2
TP_CLKR EQ0#
WLAN _CLK_REQ#
WW AN_CLK_REQ #
TP_CLKR EQ3#
TP_CLKR EQ4#
CPU_HT_ CLK
CPU_HT_ CLK#
48M_CLK
FS0
SB_14M_ CLK
FS2
1
*0
1*
0
1
*
0
X-14D31818M-37GP
1 2
R704
R704
DY
DY
RN712
RN712
4
SRN33J-5 -GP-U
SRN33J-5 -GP-U
RN709
RN709
4
SRN0J-6-G P
SRN0J-6-G P
4
X-14D31818M-37GP
1 2
10/1
0114-2
1
2 3
1
DIS
DIS
2 3
0R4P2R-P AD
0R4P2R-P AD
1
2 3
RN707
RN707
1MR2J-L2-GP
1MR2J-L2-GP
RN
RN
9/23
RN
RN
0R4P2R-P AD
0R4P2R-P AD
1
4
2 3
RN708
RN708
R710 22R2J-2-G P R710 22R2J -2-GP
1 2
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1116-9
EC703
EC703
1 2
DY
DY
R715 158R2F-G P R715 158R2F-G P
MHz 3.3V single ended HTT clock
66
100 MHz differential HTT clock
100 MHz non-spreading differential SRC clock
100 MHz spreading differential SRC clock
27MHz non-spreading singled clock on pin 5
27MHz spread clock on pin 6
and
100MHz differential spreading SRC clock
For EMI
1 2
Place together
C718
C718
1 2
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
X701
X701
C719
C719
1 2
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
SB_SMBC LK_R (18,21)
SB_SMBD ATA_R (18,21)
CLK_PCIE_ VGA (8 0)
CLK_PCIE_ VGA# (80)
NB_GFX_ CLK (13)
NB_GFX_ CLK# (13)
WLAN _CLK_REQ# (76)
WW AN_CLK_REQ # (76)
CPU_CLK (10)
CPU_CLK # (10)
USB_48M _CLK (21)
CLKREQ# MAP
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
0107-1
SB_SMBC LK_CK
SB_SMBD ATA_CK
VGA(100MHz)
CPU_CLK(200MHz)
SB820M_USB(48MHz)
+3.3V_RU N
8K2R2J-3-GP
8K2R2J-3-GP
8K2R2J-3-GP
8K2R2J-3-GP
1 2
1 2
R711
R711
R712
R712
0105-3
90D9R2F-1-GP
90D9R2F-1-GP
8K2R2J-3-GP
8K2R2J-3-GP
1 2
1 2
R718
R718
R717
R717
DY
DY
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Clock Generator ICS9LPRS480
Clock Generator ICS9LPRS480
Clock Generator ICS9LPRS480
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
No use
CLKSRC1 WLAN
CLKSRC2 WWAN
CLKSRC3 LAN
No u
se
1 2
C722 SC 47P50V 2JN-3GP C722 SC 47P50V 2JN-3GP
1 2
C723 SC47P50V 2JN-3GP C723 SC47P50V 2JN-3GP
Need External PU Resistor
CPU_CLK
CPU_CLK #
SC10P50V2JN-4GPDYEC704
SC10P50V2JN-4GP
WLAN _CLK_REQ#
WW AN_CLK_REQ #
EC704
1 2
DY
1 2
DY
EC705
SC10P50V2JN-4GPDYEC705
SC10P50V2JN-4GP
1
2 3
SRN10KJ -5-GP
SRN10KJ -5-GP
0105-1
RN711
RN711
+3.3V_RU N
4
0225-2
NB_14M_ CLK (13)
SB_14M_ CLK (21)
ocument Nu mber Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
NB OSCIN(14MHz)
SB OSCIN(14MHz)
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
7 95 Thursday, March 04 , 2010
7 95 Thursday, March 04 , 2010
7 95 Thursday, March 04 , 2010
1
A00
A00
A00
5
4
3
2
1
+1.1V_RUN
SSID = CPU
D D
C C
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C801
C801
1 2
SKT-BGA638H176
B B
1'nd 62.10055.111
2'nd
62.10055.171
Place close to socket
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C802
C802
DY
DY
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C803
C803
1 2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C804
C804
1 2
1119-3
HT_NB_CPU_CAD_H0 (12)
HT_NB_CPU_CAD_L0 (12)
HT_NB_CPU_CAD_H1 (12)
HT_NB_CPU_CAD_L1 (12)
HT_NB_CPU_CAD_H2 (12)
HT_NB_CPU_CAD_L2 (12)
HT_NB_CPU_CAD_H3 (12)
HT_NB_CPU_CAD_L3 (12)
HT_NB_CPU_CAD_H4 (12)
HT_NB_CPU_CAD_L4 (12)
HT_NB_CPU_CAD_H5 (12)
HT_NB_CPU_CAD_L5 (12)
HT_NB_CPU_CAD_H6 (12)
HT_NB_CPU_CAD_L6 (12)
HT_NB_CPU_CAD_H7 (12)
HT_NB_CPU_CAD_L7 (12)
HT_NB_CPU_CAD_H8 (12)
HT_NB_CPU_CAD_L8 (12)
HT_NB_CPU_CAD_H9 (12)
HT_NB_CPU_CAD_L9 (12)
HT_NB_CPU_CAD_H10 (12)
HT_NB_CPU_CAD_L10 (12)
HT_NB_CPU_CAD_H11 (12)
HT_NB_CPU_CAD_L11 (12)
HT_NB_CPU_CAD_H12 (12)
HT_NB_CPU_CAD_L12 (12)
HT_NB_CPU_CAD_H13 (12)
HT_NB_CPU_CAD_L13 (12)
HT_NB_CPU_CAD_H14 (12)
HT_NB_CPU_CAD_L14 (12)
HT_NB_CPU_CAD_H15 (12)
HT_NB_CPU_CAD_L15 (12)
HT_NB_CPU_CLK_H0 (12)
HT_NB_CPU_CLK_L0 (12)
HT_NB_CPU_CLK_H1 (12)
HT_NB_CPU_CLK_L1 (12)
HT_NB_CPU_CTL_H0 (12)
HT_NB_CPU_CTL_L0 (12)
HT_NB_CPU_CTL_H1 (12)
HT_NB_CPU_CTL_L1 (12)
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C805
C805
1 2
DY
DY
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C806
C806
1 2
C807
C807
1 2
1.1V(1.5A) for VLDT
CPU1A
CPU1A
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
DANUBE
DANUBE
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
1 OF 6
1 OF 6
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
HT_CPU_NB_CAD_H0 (12)
HT_CPU_NB_CAD_L0 (12)
HT_CPU_NB_CAD_H1 (12)
HT_CPU_NB_CAD_L1 (12)
HT_CPU_NB_CAD_H2 (12)
HT_CPU_NB_CAD_L2 (12)
HT_CPU_NB_CAD_H3 (12)
HT_CPU_NB_CAD_L3 (12)
HT_CPU_NB_CAD_H4 (12)
HT_CPU_NB_CAD_L4 (12)
HT_CPU_NB_CAD_H5 (12)
HT_CPU_NB_CAD_L5 (12)
HT_CPU_NB_CAD_H6 (12)
HT_CPU_NB_CAD_L6 (12)
HT_CPU_NB_CAD_H7 (12)
HT_CPU_NB_CAD_L7 (12)
HT_CPU_NB_CAD_H8 (12)
HT_CPU_NB_CAD_L8 (12)
HT_CPU_NB_CAD_H9 (12)
HT_CPU_NB_CAD_L9 (12)
HT_CPU_NB_CAD_H10 (12)
HT_CPU_NB_CAD_L10 (12)
HT_CPU_NB_CAD_H11 (12)
HT_CPU_NB_CAD_L11 (12)
HT_CPU_NB_CAD_H12 (12)
HT_CPU_NB_CAD_L12 (12)
HT_CPU_NB_CAD_H13 (12)
HT_CPU_NB_CAD_L13 (12)
HT_CPU_NB_CAD_H14 (12)
HT_CPU_NB_CAD_L14 (12)
HT_CPU_NB_CAD_H15 (12)
HT_CPU_NB_CAD_L15 (12)
HT_CPU_NB_CLK_H0 (12)
HT_CPU_NB_CLK_L0 (12)
HT_CPU_NB_CLK_H1 (12)
HT_CPU_NB_CLK_L1 (12)
HT_CPU_NB_CTL_H0 (12)
HT_CPU_NB_CTL_L0 (12)
HT_CPU_NB_CTL_H1 (12)
HT_CPU_NB_CTL_L1 (12)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
CPU_HT_LINK I/F_(1/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
5
A4
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
8 95 Thursday, March 04, 2010
8 95 Thursday, March 04, 2010
8 95 Thursday, March 04, 2010
1
5
SSID = CPU
1231-2
Set empty: C905,C906,C903,C909,C913,C910,C915
D D
+CPU_VD DR
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C901
C901
1 2
C C
+1.5V_SU S
R901 39D2R2F -L-GP R901 39D2R2F -L-GP
R903 39D2R2F -L-GP R903 39D2R2F -L-GP
1 2
C917
C917
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
B B
MEM_MA_ ADD[0..15] (18) MEM_MB_ ADD[0..15] (19)
A A
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C902
C902
1 2
1 2
1 2
DDR3_A_ DRAMRST# (18)
MEM_MA0 _ODT0 (18 )
MEM_MA0 _ODT1 (18 )
MEM_MA0 _CS#0 (18)
MEM_MA0 _CS#1 (18)
MEM_MA_ CKE0 (18)
MEM_MA_ CKE1 (18)
MEM_MA_ CLK0_P (18)
MEM_MA_ CLK0_N (18 )
MEM_MA_ CLK1_P (18)
MEM_MA_ CLK1_N (18 )
MEM_MA_ BANK0 (18)
MEM_MA_ BANK1 (18)
MEM_MA_ BANK2 (18)
MEM_MA_ RAS# (18)
MEM_MA_ CAS# (18)
MEM_MA_ WE# (18)
5
C903
C903
1 2
DY
DY
Place near to CPU
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C913
C913
C904
1 2
DY
DY
C904
1 2
+CPU_VD DR
MEMZN
MEM_MA_ ADD0
MEM_MA_ ADD1
MEM_MA_ ADD2
MEM_MA_ ADD3
MEM_MA_ ADD4
MEM_MA_ ADD5
MEM_MA_ ADD6
MEM_MA_ ADD7
MEM_MA_ ADD8
MEM_MA_ ADD9
MEM_MA_ ADD10
MEM_MA_ ADD11
MEM_MA_ ADD12
MEM_MA_ ADD13
MEM_MA_ ADD14
MEM_MA_ ADD15
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C914
C914
1 2
1119-3
D10
C10
B10
AD10
AF10
AE10
H16
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
R20
R23
J21
R19
T22
T24
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C905
C905
1 2
1 2
DY
DY
DY
DY
0.9V, 1.25A--DDR1066
1.05V, 1.75A---DDR1333
CPU1B
CPU1B
VDDR
VDDR
VDDR
VDDR
MEMZP
MEMZN
MA_RESET#
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS#0
MA0_CS#1
MA1_CS#0
MA1_CS#1
MA_CKE0
MA_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS#
MA_CAS#
MA_WE#
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C906
C906
1231-2
DANUBE
DANUBE
VDDR_SENSE
4
SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
C907
C907
1 2
2 OF 6
2 OF 6
VDDR
VDDR
VDDR
VDDR
VDDR
MEMVREF
MB_RESET#
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS#0
MB0_CS#1
MB1_CS#0
MB_CKE0
MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS#
MB_CAS#
MB_WE#
4
C915
C915
1 2
DY
DY
W10
AC10
AB10
AA10
A10
Y10
W17
B18
W26
W23
Y26
V26
W25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
R24
U26
J26
U25
U24
U23
SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
SC1000P50V3JN-GP-U
C908
C908
1 2
1 2
DY
DY
TP_CPU_ VDDR_SENSE
MEM_MB_ ADD0
MEM_MB_ ADD1
MEM_MB_ ADD2
MEM_MB_ ADD3
MEM_MB_ ADD4
MEM_MB_ ADD5
MEM_MB_ ADD6
MEM_MB_ ADD7
MEM_MB_ ADD8
MEM_MB_ ADD9
MEM_MB_ ADD10
MEM_MB_ ADD11
MEM_MB_ ADD12
MEM_MB_ ADD13
MEM_MB_ ADD14
MEM_MB_ ADD15
4.7UF*4
0.22UF*4
1000PF*4
180PF*4
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C909
C909
C910
C910
1 2
DY
DY
+0.75V_S US_CPU_M_VRE F
TP901DYTP901
1
DY
DDR3_B_ DRAMRST# (19 )
MEM_MB0 _ODT0 (19)
MEM_MB0 _ODT1 (19)
MEM_MB0 _CS#0 (19)
MEM_MB0 _CS#1 (19)
MEM_MB_ CKE0 (19)
MEM_MB_ CKE1 (19)
MEM_MB_ CLK0_P (19)
MEM_MB_ CLK0_N (1 9)
MEM_MB_ CLK1_P (19)
MEM_MB_ CLK1_N (1 9)
MEM_MB_ BANK0 (19)
MEM_MB_ BANK1 (19)
MEM_MB_ BANK2 (19)
MEM_MB_ RAS# (19)
MEM_MB_ CAS# (19)
MEM_MB_ WE# (19)
1 2
SC180P50V2JN-1GP
SC180P50V2JN-1GP
C911
C911
1119-1
C916
C916
1 2
1119-3
SC1000P50 V3JN-GP-U
SC1000P50V3JN-GP-U
1 2
3
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C919
C919
3
C912
C912
1 2
+1.5V_SU S
1KR3F-GP
1KR3F-GP
1 2
C918
C918
R902
1 2
1 2
R902
1KR3F-GP
1KR3F-GP
1 2
R905
R905
C920
C920
CLOSE TO CPU
M_A_DQ[6 3..0] (18)
1117-8
Remove
M_A_DM[7 ..0] (18)
2
3 OF 6
3 OF 6
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ1 0
M_A_DQ1 1
M_A_DQ1 2
M_A_DQ1 3
M_A_DQ1 4
M_A_DQ1 5
M_A_DQ1 6
M_A_DQ1 7
M_A_DQ1 8
M_A_DQ1 9
M_A_DQ2 0
M_A_DQ2 1
M_A_DQ2 2
M_A_DQ2 3
M_A_DQ2 4
M_A_DQ2 5
M_A_DQ2 6
M_A_DQ2 7
M_A_DQ2 8
M_A_DQ2 9
M_A_DQ3 0
M_A_DQ3 1
M_A_DQ3 2
M_A_DQ3 3
M_A_DQ3 4
M_A_DQ3 5
M_A_DQ3 6
M_A_DQ3 7
M_A_DQ3 8
M_A_DQ3 9
M_A_DQ4 0
M_A_DQ4 1
M_A_DQ4 2
M_A_DQ4 3
M_A_DQ4 4
M_A_DQ4 5 MEMZP
M_A_DQ4 6
M_A_DQ4 7
M_A_DQ4 8
M_A_DQ4 9
M_A_DQ5 0
M_A_DQ5 1
M_A_DQ5 2
M_A_DQ5 3
M_A_DQ5 4
M_A_DQ5 5
M_A_DQ5 6
M_A_DQ5 7
M_A_DQ5 8
M_A_DQ5 9
M_A_DQ6 0
M_A_DQ6 1
M_A_DQ6 2
M_A_DQ6 3
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS 0 (18)
M_A_DQS #0 (18)
M_A_DQS 1 (18)
M_A_DQS #1 (18)
M_A_DQS 2 (18)
M_A_DQS #2 (18)
M_A_DQS 3 (18)
M_A_DQS #3 (18)
M_A_DQS 4 (18)
M_A_DQS #4 (18)
M_A_DQS 5 (18)
M_A_DQS #5 (18)
M_A_DQS 6 (18)
M_A_DQS #6 (18)
M_A_DQS 7 (18)
M_A_DQS #7 (18)
G12
MA_DATA0
F12
MA_DATA1
H14
MA_DATA2
G14
MA_DATA3
H11
MA_DATA4
H12
MA_DATA5
C13
MA_DATA6
E13
MA_DATA7
H15
MA_DATA8
E15
MA_DATA9
E17
MA_DATA10
H17
MA_DATA11
E14
MA_DATA12
F14
MA_DATA13
C17
MA_DATA14
G17
MA_DATA15
G18
MA_DATA16
C19
MA_DATA17
D22
MA_DATA18
E20
MA_DATA19
E18
MA_DATA20
F18
MA_DATA21
B22
MA_DATA22
C23
MA_DATA23
F20
MA_DATA24
F22
MA_DATA25
H24
MA_DATA26
J19
MA_DATA27
E21
MA_DATA28
E22
MA_DATA29
H20
MA_DATA30
H22
MA_DATA31
Y24
MA_DATA32
AB24
MA_DATA33
AB22
MA_DATA34
AA21
MA_DATA35
W22
MA_DATA36
W21
MA_DATA37
Y22
MA_DATA38
AA22
MA_DATA39
Y20
MA_DATA40
AA20
MA_DATA41
AA18
MA_DATA42
AB18
MA_DATA43
AB21
MA_DATA44
AD21
MA_DATA45
AD19
MA_DATA46
Y18
MA_DATA47
AD17
MA_DATA48
W16
MA_DATA49
W14
MA_DATA50
Y14
MA_DATA51
Y17
MA_DATA52
AB17
MA_DATA53
AB15
MA_DATA54
AD15
MA_DATA55
AB13
MA_DATA56
AD13
MA_DATA57
Y12
MA_DATA58
W11
MA_DATA59
AB14
MA_DATA60
AA14
MA_DATA61
AB12
MA_DATA62
AA12
MA_DATA63
E12
MA_DM0
C15
MA_DM1
E19
MA_DM2
F24
MA_DM3
AC24
MA_DM4
Y19
MA_DM5
AB16
MA_DM6
Y13
MA_DM7
G13
MA_DQS_H0
H13
MA_DQS_L0
G16
MA_DQS_H1
G15
MA_DQS_L1
C22
MA_DQS_H2
C21
MA_DQS_L2
G22
MA_DQS_H3
G21
MA_DQS_L3
AD23
MA_DQS_H4
AC23
MA_DQS_L4
AB19
MA_DQS_H5
AB20
MA_DQS_L5
Y15
MA_DQS_H6
W15
MA_DQS_L6
W12
MA_DQS_H7
W13
MA_DQS_L7
2
CPU1C
CPU1C
M_B_DQ0
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
DANUBE
DANUBE
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
C11
M_B_DQ1
A11
M_B_DQ2
A14
M_B_DQ3
B14
M_B_DQ4
G11
M_B_DQ5
E11
M_B_DQ6
D12
M_B_DQ7
A13
M_B_DQ8
A15
M_B_DQ9
A16
M_B_DQ1 0
A19
M_B_DQ1 1
A20
M_B_DQ1 2
C14
M_B_DQ1 3
D14
M_B_DQ1 4
C18
M_B_DQ1 5
D18
M_B_DQ1 6
D20
M_B_DQ1 7
A21
M_B_DQ1 8
D24
M_B_DQ1 9
C25
M_B_DQ2 0
B20
M_B_DQ2 1
C20
M_B_DQ2 2
B24
M_B_DQ2 3
C24
M_B_DQ2 4
E23
M_B_DQ2 5
E24
M_B_DQ2 6
G25
M_B_DQ2 7
G26
M_B_DQ2 8
C26
M_B_DQ2 9
D26
M_B_DQ3 0
G23
M_B_DQ3 1
G24
M_B_DQ3 2
AA24
M_B_DQ3 3
AA23
M_B_DQ3 4
AD24
M_B_DQ3 5
AE24
M_B_DQ3 6
AA26
M_B_DQ3 7
AA25
M_B_DQ3 8
AD26
M_B_DQ3 9
AE25
M_B_DQ4 0
AC22
M_B_DQ4 1
AD22
M_B_DQ4 2
AE20
M_B_DQ4 3
AF20
M_B_DQ4 4
AF24
M_B_DQ4 5
AF23
M_B_DQ4 6
AC20
M_B_DQ4 7
AD20
M_B_DQ4 8
AD18
M_B_DQ4 9
AE18
M_B_DQ5 0
AC14
M_B_DQ5 1
AD14
M_B_DQ5 2
AF19
M_B_DQ5 3
AC18
M_B_DQ5 4
AF16
M_B_DQ5 5
AF15
M_B_DQ5 6
AF13
M_B_DQ5 7
AC12
M_B_DQ5 8
AB11
M_B_DQ5 9
Y11
M_B_DQ6 0
AE14
M_B_DQ6 1
AF14
M_B_DQ6 2
AF11
M_B_DQ6 3
AD11
M_B_DM0
A12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
CPU_DDR_(2/4)
CPU_DDR_(2/4)
CPU_DDR_(2/4)
M_B_DM1
B16
M_B_DM2
A22
M_B_DM3
E25
M_B_DM4
AB26
M_B_DM5
AE22
M_B_DM6
AC16
M_B_DM7
AD12
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
M_B_DQ[6 3..0] (19)
M_B_DM[7 ..0] (19)
M_B_DQS 0 (19)
M_B_DQS #0 (19)
M_B_DQS 1 (19)
M_B_DQS #1 (19)
M_B_DQS 2 (19)
M_B_DQS #2 (19)
M_B_DQS 3 (19)
M_B_DQS #3 (19)
M_B_DQS 4 (19)
M_B_DQS #4 (19)
M_B_DQS 5 (19)
M_B_DQS #5 (19)
M_B_DQS 6 (19)
M_B_DQS #6 (19)
M_B_DQS 7 (19)
M_B_DQS #7 (19)
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
9 95 Thursday, March 04 , 2010
9 95 Thursday, March 04 , 2010
9 95 Thursday, March 04 , 2010
1
A00
A00
A00
5
4
3
2
1
SSID = CPU
1119-1
L1001
L1001
1 2
SC180P50V2JN-1GP
SC180P50V2JN-1GP
PBY160808 T-330Y-N-GP
D D
+1.5V_RU N
10/5
4
RN1001
RN1001
SRN300J -3-GP
SRN300J -3-GP
1
2 3
CPU_LDT _RST# (20)
CPU_LDT _PWRGD (20,42)
CPU_LDT _STOP# (13 ,20)
C C
1 2
R1001 0R0402-P AD R1001 0R0402-P AD
1 2
R1002 0R0402-P AD R1002 0R0402-P AD
1 2
R1003 0R0402-P AD R1003 0R0402-P AD
CPU_CLK(200MHz)
For HDT DBG
1231-1
CPU_R_L DT_RST#
CPU_R_L DT_PWRGD
CPU_R_L DT_STOP#
11/6
CPU_R_L DT_RST#
HDT_RST _R#
C1008
SC10P50V2JN-4GP
C1008
SC10P50V2JN-4GP
1 2
9/11 S1g4 no support LDTREQ#
+1.5V_RU N
R1012 300R2J-4-GP
R1012 300R2J-4-GP
1 2
DY
DY
R1013 300R2J-4-GP
R1013 300R2J-4-GP
1 2
DY
DY
R1014 300R2J-4-GP
R1014 300R2J-4-GP
1 2
DY
DY
R1016 300R2J-4-GP
R1016 300R2J-4-GP
1 2
DY
DY
R1017 1KR2J-1-GP R1017 1KR2J-1-GP
1 2
R1025 1KR2J-1-GP R1025 1KR2J-1-GP
1 2
RN1002 SRN1KJ-7 -GP RN1 002 SRN1KJ-7 -GP
1
2 3
RN1004
RN1004
1
2
3
4 5
SRN1KJ-8 - G P
B B
+1.5V_SU S
R1026
R1026
1KR2J-1-G P
1KR2J-1-G P
1 2
CPU_TES T27
R1029
R1029
300R2J-4 -GP
300R2J-4 -GP
DY
DY
1 2
SRN1KJ-8 -GP
TP1001 TP1001
TP1003 TP1003
TP1004 TP1004
TP1005 TP1005
TP1006 TP1006
TP1007 TP1007
TP1008 TP1008
TP1009 TP1009
TP1010 TP1010
TP1011 TP1011
1229-1
A A
CPU_PRO CHOT#_EC (37)
5
CPU_LDT _REQ#
CPU_DBR DY
TP_CPU_ TEST14
TP_CPU_ TEST15
CPU_TES T23
CPU_TES T12
4
8
7
6
1
1
1
1
1
1
1
1
1
1
+3.3V_RU N
CPU_TES T18
CPU_TES T19
CPU_TES T20
CPU_TES T21
CPU_TES T24
CPU_TES T22
TP_CPU_ VDDIO_SUS_FB_H
TP_CPU_ VDDIO_SUS_FB_L
TP_CPU_ TEST28_H
TP_CPU_ TEST28_L
TP_CPU_ TEST17
TP_CPU_ TEST16
TP_CPU_ TEST15
TP_CPU_ TEST14
TP_CPU_ TEST8
TP_CPU_ TEST7
8K2R2J-3-GP
8K2R2J-3-GP
1 2
R1040
R1040
+1.5V_RU N
2K2R2J-2-GP
2K2R2J-2-GP
1 2
1
2
Q1005
Q1005
PMBS390 4-1-GP
PMBS390 4-1-GP
R1039
R1039
3
1129-1
510R2F-L -GP
510R2F-L -GP
CPU_SIC (21)
CPU_SID (21)
TALERT# (21,39)
CPU_PRO CHOT#
CPU_CLK (7)
CPU_CLK # (7)
R1009
R1009
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
EC1001
1 2
DY
1231-2
+1.5V_SU S
1 2
1 2
R1018
R1018
DY
DY
1 2
1 2
R1020
R1020
510R2F-L -GP
510R2F-L -GP
For old HDT tool (3.3V level)
9/22
RN1005
RN1005
SRN1KJ-7 -GP
SRN1KJ-7 -GP
4
DY
DY
+1.5V_SU S
PBY160808 T-330Y-N-GP
C1001
C1001
33R, 3A
1 2
11/6
Cloce To CPU
C1005 SC3900P 50V2KX-2GP C 1005 SC3900P50V2KX -2GP
C1006 SC3900P 50V2KX-2GP C 1006 SC3900P50V2KX -2GP
R1008 1 69R2F-GP R1008 1 69R2F-GP
1 2
1 2
0108-5
Close CPU
SCD01U16V2KX-3GPDYEC1001
SCD01U16V2KX-3GP
R1019
R1019
510R2F-L -GP
510R2F-L -GP
R1022
R1022
510R2F-L -GP
510R2F-L -GP
4
1
2 3
10KR2J-3-GP
10KR2J-3-GP
1 2
DY
DY
+1.1V_RU N
R1010 44D2R2F -GP R1010 44D2R2F -GP
R1011 44D2R2F -GP R1011 44D2R2F -GP
CPU_VDD 0_RUN_FB_H (47)
CPU_VDD 0_RUN_FB_L (47)
CPU_VDD 1_RUN_FB_H (47)
CPU_VDD 1_RUN_FB_L (47)
1231-1
312
PMBS390 4-1-GP
PMBS390 4-1-GP
R1037
R1037
Q1004 P MBS3904-1-GP
Q1004 P MBS3904-1-GP
LYAOUT:ROUTE VDDA TRACE APPROX.
50mils WIDE(USE 2X25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
+2.5V_RU N_VDDA +2.5V_RU N
2.5V(250mA) for VDDA
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C1002
2K2R2J-2-GP
2K2R2J-2-GP
Q1001
Q1001
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
1 2
1 2
R1032
R1032
+1.8V_RU N +3.3V_R UN
2K2R2J-2-GP
2K2R2J-2-GP
DY
DY
312
DY
DY
C1007
C1007
1 2
DY
DY
R1023
R1023
0R0402-P AD
0R0402-P AD
1231-1 1231-1
11/6
1KR2J-1-GP
1KR2J-1-GP
1 2
R1036
R1036
C1002
1 2
CPU_R_L DT_PWRGD
CPU_R_L DT_STOP#
CPU_LDT _REQ#
CPU_SIC
CPU_SID
CPU_ALE RT#
CPU_DBR DY
CPU_TMS
CPU_TCK
CPU_TRS T#
CPU_TDI
CPU_TES T23
CPU_TES T18
CPU_TES T19
CPU_TES T25_H
CPU_TES T25_L
CPU_TES T21
CPU_TES T20
CPU_TES T24
CPU_TES T22
CPU_TES T12
CPU_TES T27
CPU_TES T9
1 2
R1033
R1033
CPU_ALE RT#
HDT_RST _R# HDT_RST #
1 2
CPU_SIC
CPU_SID
SC3300P50V3KX-1GP
SC3300P50V3KX-1GP
C1003
C1003
CPUCLK_ IN
CPUCLK_ IN#
CPU_HTR EF0
CPU_HTR EF1
3
C1004
C1004
1 2
F10
AF4
AF5
AE6
AB6
G10
AA9
AC9
AD9
AF9
AD7
H10
AB8
AF7
AE7
AE8
AC8
AF8
AA6
F8
F9
A9
A8
B7
A7
C6
R6
P6
F6
E6
Y6
G9
E9
E8
C2
A3
A5
B3
B5
C1
CPU_PW RGD_SVID_REG (47)
CPU1D
CPU1D
VDDA
VDDA
CLKIN_H
CLKIN_L
RESET#
PWROK
LDTSTOP#
LDTREQ#
SIC
SID
ALERT#
HT_REF0
HT_REF1
VDD0_FB_H
VDD0_FB_L
VDD1_FB_H
VDD1_FB_L
DBRDY
TMS
TCK
TRST#
TDI
TEST23
TEST18
TEST19
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6
RSVD#A3
RSVD#A5
RSVD#B3
RSVD#B5
RSVD#C1
H_THERM TRIP# (21,37,39,4 2,82)
DANUBE
DANUBE
THERMTRIP#
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
+KBC_PW R
10KR2J-3-GP
10KR2J-3-GP
RSVD#W18
PROCHOT#
MEMHOT#
THERMDC
THERMDA
TEST28_H
TEST28_L
TEST29_H
TEST29_L
RSVD#H18
RSVD#H19
RSVD#AA7
RSVD#D5
RSVD#C5
8K2R2J-3-GP
8K2R2J-3-GP
4 OF 6
4 OF 6
M11
VSS
W18
A6
SVC
A4
SVD
AF6
AC7
AA8
W7
W8
W9
Y9
H6
G6
E10
DBREQ#
AE9
TDO
J7
H8
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
C3
TEST7
K8
TEST10
C4
TEST8
C9
C8
H18
H19
AA7
D5
C5
11/11
+1.5V_RU N
2K2R2J-2-GP
R1027
R1027
312
PMBS390 4-1-GP
PMBS390 4-1-GP
+1.8V_RU N +3.3V_RU N
2K2R2J-2-GP
2K2R2J-2-GP
R1034
R1034
Q1003 PM BS3904-1-GP Q1003 PMBS390 4-1-GP
312
1 2
DY
DY
2K2R2J-2-GP
Q1002
Q1002
1 2
DY
DY
1 2
R1041 0R2J-2-GP
R1041 0R2J-2-GP
1225-4
+1.5V_SU S
9/25
4
RN1006
RN1006
SRN1KJ-7 -GP
SRN1KJ-7 -GP
1
2 3
CPU_PRO CHOT#
CPU_MEM HOT#
TP_CPU_ VDDIO_SUS_FB_H
TP_CPU_ VDDIO_SUS_FB_L
R1015
CPU_DBR EQ#
CPU_TDO
TP_CPU_ TEST28_H
TP_CPU_ TEST28_L
TP_CPU_ TEST17
TP_CPU_ TEST16
TP_CPU_ TEST15
TP_CPU_ TEST14
TP_CPU_ TEST7
CPU_TES T10
TP_CPU_ TEST8
CPU_TES T29H
CPU_TES T29L
1 2
1 2
R1035
R1035
R1015
1 2
300R2J-4 -GP
300R2J-4 -GP
1 2
R1021 300R3-GP
R1021 300R3-GP
1 2
R1024 80D6R2F-L-GP R 1024 80D6R2F -L-GP
R1028
R1028
CPU_THE RMTRIP#
CPU_R_L DT_PWRGD
0112-2
2
+1.5V_SU S
9/14
300R2J-4-GP
300R2J-4-GP
1KR2J-1-GP
1KR2J-1-GP
1 2
1 2
R1007
R1007
R1006
R1006
CPU_SVC (47)
CPU_SVD (47)
CPU_THE RMTRIP#
1
TP1002 TP1002
S1G4 not support MEMHOT
H_THERM DC (39)
H_THERM DA (39)
CPU_VDD NB_RUN_FB_H (47)
CPU_VDD NB_RUN_FB_L (47 )
+1.5V_SU S
+1.1V_RU N
DY
DY
CPU_PRO CHOT# (20)
LAYOUT: Route FBCLKOUT_H/L
differentially impedance 80
HDT Connectors
CPU_DBR EQ#
CPU_DBR DY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRS T#
CPU_TDO C PU_TDO
CPU_R_L DT_RST#
1.5V
HDT_RST #
.3V
3
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
CPU_Control&Debug_(3/4)
CPU_Control&Debug_(3/4)
CPU_Control&Debug_(3/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.5V_SU S
1 2
DY
DY
R1038 0R2J-2-GP
R1038 0R2J-2-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
HDT1
HDT1
1
DY
DY
3
5
7
9
11
13
15
17
19
21
23
SMC-CONN 26A-FP
SMC-CONN 26A-FP
10 95 Thu rsday, March 04, 2010
10 95 Thu rsday, March 04, 2010
10 95 Thu rsday, March 04, 2010
2
4
6
8
10
12
14
16
18
20
22
24
26
A00
A00
A00
5
4
3
2
1
SSID = CPU
D D
6 OF 6
6 OF 6
CPU1F
CPU1F
AA4
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
AA19
VSS
AB2
VSS
AB7
VSS
AB9
VSS
AB23
VSS
AB25
VSS
AC11
VSS
AC13
VSS
AC15
VSS
AC17
VSS
AC19
VSS
AC21
VSS
AD6
C C
B B
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B11
B13
B15
B17
B19
B21
B23
B25
D11
D13
D15
D17
D19
D21
D23
D25
H21
H23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B4
VSS
B6
VSS
B8
VSS
B9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D6
VSS
D8
VSS
D9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E4
VSS
F2
VSS
F11
VSS
F13
VSS
F15
VSS
F17
VSS
F19
VSS
F21
VSS
F23
VSS
F25
VSS
H7
VSS
H9
VSS
VSS
VSS
J4
VSS
VSS
VSS
VSS
DANUBE
DANUBE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
+1.5V_SU S
1231-2
(36A) for 35W S1G4 VDD
+VCC_CO RE +VCC_CO RE
+VDDNB
Bottom Side Decoupling Bottom Side Decoupling
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD22U10V2KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C1103
C1103
C1101
DY
DY
C1101
1 2
1 2
1 2
1231-2 1231-2
22uF *2
10uF *2
0.22uF *1
0.01uF *1
180pF *1
0.9V(4A) for VDDNB
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1115
C1115
C1116
C1116
1 2
1 2
SCD22U10V2KX-1GP
C1104
C1104
C1105
C1105
1 2
1 2
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C1102
C1102
C1107
C1107
C1106
C1106
1 2
1 2
1119-3
C1117
C1117
22UF *3
1231-2
1.5V(
3A) for VDDIO
Bottom Side Decoupling
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C1131
C1131
C1130
C1130
1 2
1 2
DY
DY
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SCD1U10V2KX-5GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C1132
C1132
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1119-1
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C1120
C1133
C1133
C1120
C1135
C1134
C1134
1 2
C1135
1 2
1 2
CPU1E
CPU1E
G4
VDD
H2
VDD
J9
VDD
J11
VDD
J13
VDD
J15
VDD
K6
VDD
K10
VDD
K12
VDD
K14
VDD
L4
VDD
L7
VDD
L9
VDD
L11
VDD
L13
VDD
L15
VDD
M2
VDD
M6
VDD
M8
VDD
M10
VDD
N7
VDD
N9
VDD
N11
VDD
K16
VDDNB
M16
VDDNB
P16
VDDNB
T16
VDDNB
V16
VDDNB
H25
VDDIO
J17
VDDIO
K18
VDDIO
K21
VDDIO
K23
VDDIO
K25
VDDIO
L17
VDDIO
M18
VDDIO
M21
VDDIO
M23
VDDIO
M25
VDDIO
N17
VDDIO
C1121
C1121
1 2
5 OF 6
5 OF 6
DANUBE
DANUBE
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DY
DY
1 2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C1108
C1108
1 2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C1110
C1110
C1109
C1109
1 2
1 2
DY
DY
1119-3
22uF *2
10uF *2
0.22uF *1
0.01uF *1
180pF *1
Place near to CPU
SC180P50V2JN-1GP
SC180P50V2JN-1GP
SC180P50V2JN-1GP
DY
DY
SC180P50V2JN-1GP
C1118
C1118
1 2
1 2
DY
DY
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C1119
C1119
C1122
C1122
1 2
DY
DY
DY
DY
1119-3
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C1111
C1111
1 2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C1123
C1123
1 2
0.01UF *1
0.1UF *2
0.22UF *4
4.7UF *4
180PF *2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1112
C1112
C1141
C1141
1 2
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C1125
C1125
C1124
C1124
1 2
1 2
DY
DY
DY
DY
1231-2 1231-2
1119-3
10UF *2
0.22UF *2
180PF *1
C1114
C1114
+1.5V_SU S
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C1129
C1126
C1126
C1127
C1127
1 2
1 2
DY
DY
C1129
C1128
C1128
1 2
1 2
9/14
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_Power_(4/4)
CPU_Power_(4/4)
CPU_Power_(4/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
of
11 95 Thu rsday, March 04, 2010
11 95 Thu rsday, March 04, 2010
11 95 Thu rsday, March 04, 2010
A00
A00
A00
5
HT_CPU_ NB_CAD_H0 (8)
SSID = N.B
RS880M : 71.RS880.M05
D D
C C
Place < 100mils from pin C23 and A24
B B
9/11
WLAN
LAN
WWAN
A A
A-LINK
5
ALINK_NBR X_SBTX_P0 (20)
ALINK_NBR X_SBTX_N0 (20)
ALINK_NBR X_SBTX_P1 (20)
ALINK_NBR X_SBTX_N1 (20)
ALINK_NBR X_SBTX_P2 (20)
ALINK_NBR X_SBTX_N2 (20)
ALINK_NBR X_SBTX_P3 (20)
ALINK_NBR X_SBTX_N3 (20)
HT_CPU_ NB_CAD_L0 (8)
HT_CPU_ NB_CAD_H1 (8 )
HT_CPU_ NB_CAD_L1 (8)
HT_CPU_ NB_CAD_H2 (8 )
HT_CPU_ NB_CAD_L2 (8)
HT_CPU_ NB_CAD_H3 (8 )
HT_CPU_ NB_CAD_L3 (8)
HT_CPU_ NB_CAD_H4 (8 )
HT_CPU_ NB_CAD_L4 (8)
HT_CPU_ NB_CAD_H5 (8 )
HT_CPU_ NB_CAD_L5 (8)
HT_CPU_ NB_CAD_H6 (8 )
HT_CPU_ NB_CAD_L6 (8)
HT_CPU_ NB_CAD_H7 (8 )
HT_CPU_ NB_CAD_L7 (8)
HT_CPU_ NB_CAD_H8 (8 )
HT_CPU_ NB_CAD_L8 (8)
HT_CPU_ NB_CAD_H9 (8 )
HT_CPU_ NB_CAD_L9 (8)
HT_CPU_ NB_CAD_H10 (8)
HT_CPU_ NB_CAD_L10 (8)
HT_CPU_ NB_CAD_H11 (8)
HT_CPU_ NB_CAD_L11 (8)
HT_CPU_ NB_CAD_H12 (8)
HT_CPU_ NB_CAD_L12 (8)
HT_CPU_ NB_CAD_H13 (8)
HT_CPU_ NB_CAD_L13 (8)
HT_CPU_ NB_CAD_H14 (8)
HT_CPU_ NB_CAD_L14 (8)
HT_CPU_ NB_CAD_H15 (8)
HT_CPU_ NB_CAD_L15 (8)
HT_CPU_ NB_CLK_H0 (8)
HT_CPU_ NB_CLK_L0 (8)
HT_CPU_ NB_CLK_H1 (8)
HT_CPU_ NB_CLK_L1 (8)
HT_CPU_ NB_CTL_H0 (8)
HT_CPU_ NB_CTL_L0 (8)
HT_CPU_ NB_CTL_H1 (8)
HT_CPU_ NB_CTL_L1 (8)
R1201 301R2F-GP R 1201 301 R2F-GP
1 2
9/15
PCIE_NRX_ GTX_P15
PCIE_NRX_ GTX_N15
PCIE_NRX_ GTX_P14
PCIE_NRX_ GTX_N14
PCIE_NRX_ GTX_P13
PCIE_NRX_ GTX_N13
PCIE_NRX_ GTX_P12
PCIE_NRX_ GTX_N12
PCIE_NRX_ GTX_P11
PCIE_NRX_ GTX_N11
PCIE_NRX_ GTX_P10
PCIE_NRX_ GTX_N10
PCIE_NRX_ GTX_P9
PCIE_NRX_ GTX_N9
PCIE_NRX_ GTX_P8
PCIE_NRX_ GTX_N8
PCIE_NRX_ GTX_P7
PCIE_NRX_ GTX_N7
PCIE_NRX_ GTX_P6
PCIE_NRX_ GTX_N6
PCIE_NRX_ GTX_P5
PCIE_NRX_ GTX_N5
LANE REVERSAL
PCIE_NRX_ GTX_P4
PCIE_NRX_ GTX_N4
PCIE_NRX_ GTX_P3
PCIE_NRX_ GTX_N3
PCIE_NRX_ GTX_P2
PCIE_NRX_ GTX_N2
PCIE_NRX_ GTX_P1
PCIE_NRX_ GTX_N1
PCIE_NRX_ GTX_P0
PCIE_NRX_ GTX_N0
PCIE_RXP0 (7 6)
PCIE_RXN0 (76)
PCIE_RXP1 (7 6)
PCIE_RXN1 (76)
PCIE_RXP2 (7 6)
PCIE_RXN2 (76)
4
U1A
U1A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCA LP HT_TXCA LP
HT_RXCA LN
C23
A24
RS880M-1 -GP
RS880M-1 -GP
U1B
U1B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS880M-1-GP
RS880M-1-GP
4
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
PART 1 OF 6
PART 1 OF 6
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
A5
GFX_TX0P
B5
GFX_TX0N
A4
GFX_TX1P
B4
GFX_TX1N
C3
GFX_TX2P
B2
GFX_TX2N
D1
GFX_TX3P
D2
GFX_TX3N
E2
GFX_TX4P
E1
GFX_TX4N
F4
GFX_TX5P
F3
GFX_TX5N
F1
GFX_TX6P
F2
GFX_TX6N
H4
GFX_TX7P
H3
GFX_TX7N
H1
GFX_TX8P
H2
GFX_TX8N
J2
GFX_TX9P
J1
GFX_TX9N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
PCE_CALRP
PCE_CALRN
3
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
HT_TXCA LN
B25
Place < 100mils from pin B25 and B24
PCIE_NTX_ GRX_C_P15
PCIE_NTX_ GRX_C_N15
PCIE_NTX_ GRX_C_P14
PCIE_NTX_ GRX_C_N14
PCIE_NTX_ GRX_C_P13
PCIE_NTX_ GRX_C_N13
PCIE_NTX_ GRX_C_P12
PCIE_NTX_ GRX_C_N12
PCIE_NTX_ GRX_C_P11
PCIE_NTX_ GRX_C_N11
PCIE_NTX_ GRX_C_P10
PCIE_NTX_ GRX_C_N10
PCIE_NTX_ GRX_C_P9
PCIE_NTX_ GRX_C_N9
PCIE_NTX_ GRX_C_P8
PCIE_NTX_ GRX_C_N8
PCIE_NTX_ GRX_C_P7
PCIE_NTX_ GRX_C_N7
PCIE_NTX_ GRX_C_P6
PCIE_NTX_ GRX_C_N6
PCIE_NTX_ GRX_C_P5
PCIE_NTX_ GRX_C_N5
PCIE_NTX_ GRX_C_P4
PCIE_NTX_ GRX_C_N4
PCIE_NTX_ GRX_C_P3
PCIE_NTX_ GRX_C_N3
PCIE_NTX_ GRX_C_P2
PCIE_NTX_ GRX_C_N2
PCIE_NTX_ GRX_C_P1
PCIE_NTX_ GRX_C_N1
PCIE_NTX_ GRX_C_P0
PCIE_NTX_ GRX_C_N0
PCIE_C_TX P0
PCIE_C_TX N0
PCIE_C_TX P1
PCIE_C_TX N1
PCIE_C_TX P2
PCIE_C_TX N2
ALINK_NBT X_SBRX_C_P0
ALINK_NBT X_SBRX_C_N0
ALINK_NBT X_SBRX_C_P1
ALINK_NBT X_SBRX_C_N1
ALINK_NBT X_SBRX_C_P2
ALINK_NBT X_SBRX_C_N2
ALINK_NBT X_SBRX_C_P3
ALINK_NBT X_SBRX_C_N3
PCE_PCA L
PCE_NCA L
Place < 100mils from pin AC8 and AB8
3
HT_NB_C PU_CAD_H0 (8)
HT_NB_C PU_CAD_L0 (8)
HT_NB_C PU_CAD_H1 (8)
HT_NB_C PU_CAD_L1 (8)
HT_NB_C PU_CAD_H2 (8)
HT_NB_C PU_CAD_L2 (8)
HT_NB_C PU_CAD_H3 (8)
HT_NB_C PU_CAD_L3 (8)
HT_NB_C PU_CAD_H4 (8)
HT_NB_C PU_CAD_L4 (8)
HT_NB_C PU_CAD_H5 (8)
HT_NB_C PU_CAD_L5 (8)
HT_NB_C PU_CAD_H6 (8)
HT_NB_C PU_CAD_L6 (8)
HT_NB_C PU_CAD_H7 (8)
HT_NB_C PU_CAD_L7 (8)
HT_NB_C PU_CAD_H8 (8)
HT_NB_C PU_CAD_L8 (8)
HT_NB_C PU_CAD_H9 (8)
HT_NB_C PU_CAD_L9 (8)
HT_NB_C PU_CAD_H10 (8)
HT_NB_C PU_CAD_L10 (8)
HT_NB_C PU_CAD_H11 (8)
HT_NB_C PU_CAD_L11 (8)
HT_NB_C PU_CAD_H12 (8)
HT_NB_C PU_CAD_L12 (8)
HT_NB_C PU_CAD_H13 (8)
HT_NB_C PU_CAD_L13 (8)
HT_NB_C PU_CAD_H14 (8)
HT_NB_C PU_CAD_L14 (8)
HT_NB_C PU_CAD_H15 (8)
HT_NB_C PU_CAD_L15 (8)
HT_NB_C PU_CLK_H0 (8)
HT_NB_C PU_CLK_L0 (8)
HT_NB_C PU_CLK_H1 (8)
HT_NB_C PU_CLK_L1 (8)
HT_NB_C PU_CTL_H0 (8)
HT_NB_C PU_CTL_L0 (8)
HT_NB_C PU_CTL_H1 (8)
HT_NB_C PU_CTL_L1 (8)
R1202 301R2F-GP R 1202 301 R2F-GP
1 2
1119-3
C1231 SCD1U10 V2KX-5GP C 1231 SCD1U 10V2KX-5GP
1 2
C1232 SCD1U10 V2KX-5GP C 1232 SCD1U 10V2KX-5GP
1 2
C1229 SCD1U10 V2KX-5GP C 1229 SCD1U 10V2KX-5GP
1 2
C1230 SCD1U10 V2KX-5GP C 1230 SCD1U 10V2KX-5GP
1 2
C1227 SCD1U10 V2KX-5GP C 1227 SCD1U 10V2KX-5GP
1 2
C1228 SCD1U10 V2KX-5GP C 1228 SCD1U 10V2KX-5GP
1 2
C1225 SCD1U10 V2KX-5GP C 1225 SCD1U 10V2KX-5GP
1 2
C1226 SCD1U10 V2KX-5GP C 1226 SCD1U 10V2KX-5GP
1 2
C1223 SCD1U10 V2KX-5GP
C1223 SCD1U10 V2KX-5GP
1 2
C1224 SCD1U10 V2KX-5GP
C1224 SCD1U10 V2KX-5GP
1 2
C1221 SCD1U10 V2KX-5GP
C1221 SCD1U10 V2KX-5GP
1 2
C1222 SCD1U10 V2KX-5GP
C1222 SCD1U10 V2KX-5GP
1 2
C1219 SCD1U10 V2KX-5GP
C1219 SCD1U10 V2KX-5GP
1 2
C1220 SCD1U10 V2KX-5GP
C1220 SCD1U10 V2KX-5GP
1 2
C1217 SCD1U10 V2KX-5GP
C1217 SCD1U10 V2KX-5GP
1 2
C1218 SCD1U10 V2KX-5GP
C1218 SCD1U10 V2KX-5GP
1 2
C1215 SCD1U10 V2KX-5GP
C1215 SCD1U10 V2KX-5GP
1 2
C1216 SCD1U10 V2KX-5GP
C1216 SCD1U10 V2KX-5GP
1 2
C1213 SCD1U10 V2KX-5GP
C1213 SCD1U10 V2KX-5GP
1 2
C1214 SCD1U10 V2KX-5GP
C1214 SCD1U10 V2KX-5GP
1 2
C1211 SCD1U10 V2KX-5GP
C1211 SCD1U10 V2KX-5GP
1 2
C1212 SCD1U10 V2KX-5GP
C1212 SCD1U10 V2KX-5GP
1 2
C1209 SCD1U10 V2KX-5GP
C1209 SCD1U10 V2KX-5GP
1 2
C1210 SCD1U10 V2KX-5GP
C1210 SCD1U10 V2KX-5GP
1 2
C1207 SCD1U10 V2KX-5GP
C1207 SCD1U10 V2KX-5GP
1 2
C1208 SCD1U10 V2KX-5GP
C1208 SCD1U10 V2KX-5GP
1 2
C1205 SCD1U10 V2KX-5GP
C1205 SCD1U10 V2KX-5GP
1 2
C1206 SCD1U10 V2KX-5GP
C1206 SCD1U10 V2KX-5GP
1 2
C1203 SCD1U10 V2KX-5GP
C1203 SCD1U10 V2KX-5GP
1 2
C1204 SCD1U10 V2KX-5GP
C1204 SCD1U10 V2KX-5GP
1 2
C1201 SCD1U10 V2KX-5GP
C1201 SCD1U10 V2KX-5GP
1 2
C1202 SCD1U10 V2KX-5GP
C1202 SCD1U10 V2KX-5GP
1 2
C1264 SCD1U10 V2KX-5GP C 1264 SCD1U 10V2KX-5GP
1 2
C1261 SCD1U10 V2KX-5GP C 1261 SCD1U 10V2KX-5GP
1 2
C1266 SCD1U10 V2KX-5GP C 1266 SCD1U 10V2KX-5GP
1 2
C1262 SCD1U10 V2KX-5GP C 1262 SCD1U 10V2KX-5GP
1 2
C1265 SCD1U10 V2KX-5GP C 1265 SCD1U 10V2KX-5GP
1 2
C1263 SCD1U10 V2KX-5GP C 1263 SCD1U 10V2KX-5GP
1 2
9/11
C1237 SCD1U10 V2KX-5GP C 1237 SCD1U 10V2KX-5GP
1 2
C1238 SCD1U10 V2KX-5GP C 1238 SCD1U 10V2KX-5GP
1 2
C1239 SCD1U10 V2KX-5GP C 1239 SCD1U 10V2KX-5GP
1 2
C1240 SCD1U10 V2KX-5GP C 1240 SCD1U 10V2KX-5GP
1 2
C1241 SCD1U10 V2KX-5GP C 1241 SCD1U 10V2KX-5GP
1 2
C1242 SCD1U10 V2KX-5GP C 1242 SCD1U 10V2KX-5GP
1 2
C1243 SCD1U10 V2KX-5GP C 1243 SCD1U 10V2KX-5GP
1 2
C1244 SCD1U10 V2KX-5GP C 1244 SCD1U 10V2KX-5GP
R1203 1K27R2F-L-GP R1203 1K27R2F-L-GP
1 2
R1204 2KR2F-3-GP R1204 2 KR2F-3-GP
1 2
1 2
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
PCIE_NTX_ GRX_P[12..15]
PCIE_NTX_ GRX_N[12..15]
PCIE_NTX_ GRX_P[0..11]
PCIE_NTX_ GRX_N[0..11]
PCIE_NRX_ GTX_P[0..15]
PCIE_NRX_ GTX_N[0..15]
PCIE_NTX_ GRX_P15
PCIE_NTX_ GRX_N15
PCIE_NTX_ GRX_P14
PCIE_NTX_ GRX_N14
PCIE_NTX_ GRX_P13
PCIE_NTX_ GRX_N13
PCIE_NTX_ GRX_P12
PCIE_NTX_ GRX_N12
PCIE_NTX_ GRX_P11
PCIE_NTX_ GRX_N11
PCIE_NTX_ GRX_P10
PCIE_NTX_ GRX_N10
PCIE_NTX_ GRX_P9
PCIE_NTX_ GRX_N9
PCIE_NTX_ GRX_P8
PCIE_NTX_ GRX_N8
PCIE_NTX_ GRX_P7
PCIE_NTX_ GRX_N7
PCIE_NTX_ GRX_P6
PCIE_NTX_ GRX_N6
PCIE_NTX_ GRX_P5
PCIE_NTX_ GRX_N5
PCIE_NTX_ GRX_P4
PCIE_NTX_ GRX_N4
PCIE_NTX_ GRX_P3
PCIE_NTX_ GRX_N3
PCIE_NTX_ GRX_P2
PCIE_NTX_ GRX_N2
PCIE_NTX_ GRX_P1
PCIE_NTX_ GRX_N1
PCIE_NTX_ GRX_P0
PCIE_NTX_ GRX_N0
PCIE_TXP0 (76)
PCIE_TXN0 (76)
PCIE_TXP1 (76)
PCIE_TXN1 (76)
PCIE_TXP2 (76)
PCIE_TXN2 (76)
ALINK_NBT X_SBRX_P0 (20)
ALINK_NBT X_SBRX_N0 (20 )
ALINK_NBT X_SBRX_P1 (20)
ALINK_NBT X_SBRX_N1 (20 )
ALINK_NBT X_SBRX_P2 (20)
ALINK_NBT X_SBRX_N2 (20 )
ALINK_NBT X_SBRX_P3 (20)
ALINK_NBT X_SBRX_N3 (20 )
+1.1V_RU N_VDDPCIE
2
A-LINK
2
PCIE_NTX_ GRX_P[12..15] (57)
PCIE_NTX_ GRX_N[12..15] (57)
PCIE_NTX_ GRX_P[0..11] (80 )
PCIE_NTX_ GRX_N[0..11] (80)
PCIE_NRX_ GTX_P[0..15] (80 )
PCIE_NRX_ GTX_N[0..15] (80)
9/15
LANE REVERSAL
WLAN
LAN
WWAN
1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
AMD-RS880M_HT LINK&PCIe(1/4)
AMD-RS880M_HT LINK&PCIe(1/4)
AMD-RS880M_HT LINK&PCIe(1/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
12 95 Thu rsday, March 04, 2010
12 95 Thu rsday, March 04, 2010
12 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
UMA DAC Signal:
SSID = N.B
RS880M : 71.RS880.M05
+1.1V_RU N
D D
C C
1 2
UMA
UMA
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
+1.8V_RU N
1 2
UMA
UMA
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
+1.8V_RU N
1 2
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
220R, 0.3A
220R, 0.3A
220R, 0.3A
1.1V, 65mA
L1308
L1308
L1307
L1307
L1301
L1301
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
UMA/DIS
UMA/DIS
1.8V, 20mA
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
UMA/DIS
UMA/DIS
Layout Note
Trace at least 15 mil
1.8V, 20mA
+1.8V_VD DA18HTPLL
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
PLLVDD
C1312
C1312
10/8
PLLVDD1 8
C1311
C1311
C1302
C1302
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1119-3
1 2
C1303
C1303
GREEN/BLUE: Connected to GND through two separate
1% resistors.
150-
RED: Connected to GND through two separate 133resistors.(For match resistor on CRT/B 150- 1%)
+3.3V_RU N +3.3V_RU N_AVDD
R1342
R1342
1 2
0R3J-0-U-G P
0R3J-0-U-G P
0106-2
+1.8V_RU N
R1333
R1333
1 2
0R3J-0-U-G P
0R3J-0-U-G P
+1.8V_RU N
1119-1
R1344
R1344
UMA
UMA
0R3J-0-U-G P
0R3J-0-U-G P
UMA: DAC_CLK and DATA
with
not need level shift
10/8
9/22
R1343
R1343
1 2
0R0603-P AD
0R0603-P AD
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C1301
C1301
1 2
B B
CPU_LDT _STOP# (10 ,20)
A A
ALLOW _LDTSTOP (20)
1.8V, 120mA
+1.8V_VD DA18PCIEPLL
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
R1309
R1309
300R2J-4 -GP
300R2J-4 -GP
5
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1305
C1304
C1304
1 2
C1305
1 2
1119-3
9/25
1 2
R1322 0R2J-2-GP
R1322 0R2J-2-GP
1 2
U1301
U1301
1
A1
2
GND
A23Y2
1 2
R1316
R1316
0R0402-P AD
0R0402-P AD
ALLOW_LDTSTOP:
1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted
DY
DY
6
Y1
5
VCC
4
NC7W Z07P6X-1GP
NC7W Z07P6X-1GP
+1.8V_RU N
1 2
R1315
R1315
1KR2J-1-G P
1KR2J-1-G P
NB_ALLO W_LDTSTOP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+1.8V_RU N +1.5V_RU N
1 2
4K7R2F-G P
4K7R2F-G P
4K7R2F-G P
4K7R2F-G P
1 2
C1314
C1314
+1.1V_RU N
R1312
R1312
R1313
R1313
R1311
R1311
2K2R2J-2 -GP
2K2R2J-2 -GP
NB_LDT_ STOP#
4
UMA
UMA
+1.8V_RU N_AVDDDI
UMA
UMA
+1.8V_RU N_AVDDDQ
1 2
M_RED (77)
M_GREEN (77)
M_BLUE (77)
5V-tolerant.
Trace at least 10 mil
PLTRST# _NB_GPU (20,37,80 )
NB_PW RGD_IN (41)
SC180P5 0V2JN-1GP
SC180P5 0V2JN-1GP
NB_14M_ CLK (7)
1231-2
LDDC_CL K (55 )
LDDC_DA TA (55)
NB_DDC_ DATA0 (57)
NB_DDC_ CLK0 (57)
1 2
1 2
9/15
9/15
4
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3.3V, 110mA
C1307
C1307
1 2
UMA/DIS
UMA/DIS
10/8
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1.8V, 20mA
C1306
C1306
1 2
UMA/DIS
UMA/DIS
1.8V, 4mA
1 2
C1308
C1308
SC2D2U6 D3V3KX-GP
SC2D2U6 D3V3KX-GP
UMA/DIS
UMA/DIS
VGA_HSYNC (77)
VGA_VSYNC (77)
DDC_CLK _CON (77 )
DDC_DAT A_CON (77 )
1 2
EC1301
EC1301
1 2
R1341 0R0402-P AD R1341 0R 0402-PAD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
10/7
1 2
R1318
R1318
2KR2J-1-G P
2KR2J-1-G P
1%
9/22
UMA
UMA
R1326 1 50R2F-1-GP
R1326 1 50R2F-1-GP
1 2
UMA
UMA
1 2
R1327 1 50R2F-1-GP
R1327 1 50R2F-1-GP
UMA
UMA
1 2
R1328 1 50R2F-1-GP
R1328 1 50R2F-1-GP
12
SC180P5 0V2JN-1GP
SC180P5 0V2JN-1GP
C1315
C1315
1 2
DY
DY
VGA_HSYNC
VGA_VSYNC
DDC_CLK _CON
DDC_DAT A_CON
1 2
R1306 7 15R2F-GP R1306 7 15R2F-GP
+1.8V_VD DA18HTPLL
+1.8V_VD DA18PCIEPLL
9/16
EC1302
EC1302
10/2
NB_LDT_ STOP#
NB_ALLO W_LDTSTOP
CLK_NBH T_CLK (7)
CLK_NBH T_CLK# (7)
NB_GFX_ CLK (7)
NB_GFX_ CLK# (7)
TP1306 TP1306
TP1307 TP1307
NB_GPPS B_CLK (7)
NB_GPPS B_CLK# (7)
TP1305 TP1305
1 2
R1319 150R2F-1 -GP R 1319 150R2 F-1-GP
3
DAC_RSE T
PLLVDD
PLLVDD1 8
NB_REFC LK_P
NB_REFC LK_N
NB_GFX_ CLK
NB_GFX_ CLK#
NB_GPP_ CLK
1
NB_GPP_ CLK#
1
1120-6
STRP_DA TA
TP_NB_R ESERVED
1
RS780_A UX_CAL
3
SPM_Disable
SPM_Disable
SPM_Enable
SPM_Enable
U1C
U1C
F12
AVDD1
E12
AVDD2
F14
AVDDDI
G15
AVSSDI
H15
AVDDQ
H14
AVSSQ
E17
C_Pr
F17
Y
F15
COMP_Pb
G18
RED
G17
REDb
E18
GREEN
F18
GREENb
E19
BLUE
F19
BLUEb
A11
DAC_HSYNC
B11
DAC_VSYNC
F8
DAC_SCL
E8
DAC_SDA
G14
DAC_RSET
A12
PLLVDD
D14
PLLVDD18
B12
PLLVSS
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESET#
A10
POWERGOOD
C10
LDTSTOP#
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN
F11
REFCLK_N
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP
V3
GPPSB_REFCLKN
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N
A8
DDC_CLK0/AUX0P
B7
DDC_CLK1/AUX1P
A7
DDC_DATA1/AUX1N
B10
STRP_DATA
G11
RESERVED
C8
AUX_CAL
RS880M-1-GP
RS880M-1-GP
+3.3V_RU N
3KR2J-2-GP
3KR2J-2-GP
1 2
3KR2J-2-GP
3KR2J-2-GP
1 2
R1302
R1302
R1304
R1304
3KR2J-2-GP
3KR2J-2-GP
3KR2J-2-GP
3KR2J-2-GP
DY
DY
1 2
1 2
R1303
R1303
VGA_VSYNC
VGA_HSYNC
R1305
R1305
PART 3 OF 6
PART 3 OF 6
CRT/TVOUT
CRT/TVOUT
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
*DEFAULT
LVTM
LVTM
11/6
R1314
R1314
4K7R2J-2 -GP
4K7R2J-2 -GP
NB_SUS_ STAT#
R1321
R1321
3KR2J-2-G P
3KR2J-2-G P
2
1
STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use DAC_VSYNC)
Enables debug bus access through memory I/O pads and GPIOs.
1 : Disable
*
0 : Enable
SIDE_PORT_EN# ( RS880M use DAC_HSYNC)
1 = Memory Side port Not available
0 = Memory Side port available
DIS
UMA_SPM
LOAD_EEPROM_STRAPS#(RS880M use SUS_STAT#)
Selects Loading of STRAPS From EEPROM
1 : use Default Values
*
0 : I2C Master can load strap values from EEPROM if connected,
or use default values if not connected
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
VDDLTP18
VSSLTP18
VDDLT18_1
VDDLT18_2
VDDLT33_1
VDDLT33_2
VSSLT1
VSSLT2
VSSLT3
VSSLT4
VSSLT5
VSSLT6
VSSLT7
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13
B13
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
VDDLTP1 8_R
VDDLT18 _R
VGA_TXA OUT0+ (55)
VGA_TXA OUT0- (55)
VGA_TXA OUT1+ (55)
VGA_TXA OUT1- (55)
VGA_TXA OUT2+ (55)
VGA_TXA OUT2- (55)
VGA_TXB OUT0+ (55)
VGA_TXB OUT0- (55)
VGA_TXB OUT1+ (55)
VGA_TXB OUT1- (55)
VGA_TXB OUT2+ (55)
VGA_TXB OUT2- (55)
VGA_TXA CLK+ (55)
VGA_TXA CLK- (55)
VGA_TXB CLK+ (55)
VGA_TXB CLK- (55)
1.8V, 15mA
1.8V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C1310
C1310
1 2
UMA
UMA
, 300mA
C1313
C1313
1 2
UMA/DIS
UMA/DIS
1119-1
220R, 0.3A
L1305
L1305
1 2
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
L1306
L1306
1 2
PBY160808 T-221Y-N-GP
PBY160808 T-221Y-N-GP
1 2
220R, 2A
C1309
C1309
SC2D2U6 D3V3KX-GP
SC2D2U6 D3V3KX-GP
UMA/DIS
UMA/DIS
11/12-4
LVDS_DIGON
LVDS_BLON
LVDS_ENA_BL
TMDS_HPD
HPD
SUS_STAT#
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
+3.3V_RU N
1 2
1 2
DY
DY
2
E9
F7
G12
RN1301
RN1301
1
2 3
UMA
UMA
SRN10KJ -5-GP
TP_TMDS _HPD
D9
HDMI_HPD_ DET
D10
NB_SUS_ STAT#
D12
AE8
AD8
TESTMOD E_NB
D13
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
SRN10KJ -5-GP
TP1308 TP1308
1
R1317
R1317
1 2
0R2J-2-GP
0R2J-2-GP
1K8R2F-GP
1K8R2F-GP
1 2
R1320
R1320
AMD-RS880M_LVDS&CRT_(2/4)
AMD-RS880M_LVDS&CRT_(2/4)
AMD-RS880M_LVDS&CRT_(2/4)
NB_LCDP WR_EN (55)
NB_BL_P WM (55 )
NB_BL_E N (55)
9/22
4
0225-1
UMA
UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
HDMI_HPD_ DET (57,82)
SUS_STA T# (21)
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
13 95 Thu rsday, March 04, 2010
13 95 Thu rsday, March 04, 2010
13 95 Thu rsday, March 04, 2010
1
+1.8V_RU N
UMA
UMA
UMA
UMA
A00
A00
A00
5
SSID = N.B
4
3
2
1
MEM_VDD Q
U1401
D D
SPM_VRE F1
SPM_VRE F2
R1408 2 43R2F-2-GP
R1408 2 43R2F-2-GP
1 2
UMA_SPM
UMA_SPM
C C
B B
SPM_ZQ
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
SPM_BA0
SPM_BA1
SPM_BA2
SPM_CLK P
SPM_CLK N
SPM_CKE
SPM_DM1
SPM_DM0
SPM_W E#
SPM_CAS #
SPM_RAS #
U1401
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
UMA_SPM_Samsung
UMA_SPM_Samsung
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
SPM_DQ2
E3
SPM_DQ1
F7
SPM_DQ5
F2
SPM_DQ3
F8
SPM_DQ7
H3
SPM_DQ0
H8
SPM_DQ4
G2
SPM_DQ6
H7
SPM_DQ1 3
D7
SPM_DQ8
C3
SPM_DQ1 0
C8
SPM_DQ1 2
C2
SPM_DQ1 5
A7
SPM_DQ1 1
A2
SPM_DQ1 4
B8
SPM_DQ9
A3
SPM_DQS 1P
C7
SPM_DQS 1N
B7
SPM_DQS 0P
F3
SPM_DQS 0N
G3
SPM_ODT
K1
SPM_CS#
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
MEM_VDD Q
1 2
R1411
R1411
10KR2J-3 -GP
10KR2J-3 -GP
UMA_SPM
UMA_SPM
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1415
C1415
1 2
DY
DY
10/7
SP_DDR3 _RST# (21)
9/15
MEM_VDD Q
SPM_CLK P
SPM_CLK N
UMA_SPM
UMA_SPM
R1409 40D2R2F -GP
R1409 40D2R2F -GP
1 2
R1410 40D2R2F -GP
R1410 40D2R2F -GP
1 2
UMA_SPM
UMA_SPM
R1401 100R2F-L 1-GP-U
R1401 100R2F-L 1-GP-U
1 2
DY
DY
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
SPM_BA0
SPM_BA1
SPM_BA2
SPM_RAS #
SPM_CAS #
SPM_W E#
SPM_CS#
SPM_CKE
S PM_ODT
MEM_COM PP
MEM_COM PN
U1D
U1D
AB12
MEM_A0
AE16
MEM_A1
V11
MEM_A2
AE15
MEM_A3
AA12
MEM_A4
AB16
MEM_A5
AB14
MEM_A6
AD14
MEM_A7
AD13
MEM_A8
AD15
MEM_A9
AC16
MEM_A10
AE13
MEM_A11
AC14
MEM_A12
Y14
MEM_A13
AD16
MEM_BA0
AE17
MEM_BA1
AD17
MEM_BA2
W12
MEM_RAS#
Y12
MEM_CAS#
AD18
MEM_WE#
AB13
MEM_CS#
AB18
MEM_CKE
V14
MEM_ODT
V15
MEM_CKP
W14
MEM_CKN
AE12
MEM_COMPP
AD12
MEM_COMPN
RS880M-1 -GP
RS880M-1 -GP
1.8V(0.015A) for IOPLLVDD18
1.1V(0.026A) for IOPLLVDD
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC
MEM_DQ1/DVO_HSYNC
MEM_DQS0P/DVO_IDCKP
MEM_DQS0N/DVO_IDCKN
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD1 8
IOPLLVDD
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
C1401
C1401
1 2
UMA_SPM
UMA_SPM
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
C1402
C1402
1 2
UMA_SPM
UMA_SPM
MEM_DQ2/DVO_DE
MEM_DQ3/DVO_D0
MEM_DQ5/DVO_D1
MEM_DQ6/DVO_D2
MEM_DQ7/DVO_D4
MEM_DQ8/DVO_D3
MEM_DQ9/DVO_D5
MEM_DQ10/DVO_D6
MEM_DQ11/DVO_D7
MEM_DQ12
MEM_DQ13/DVO_D9
MEM_DQ14/DVO_D10
MEM_DQ15/DVO_D11
MEM_DQS1P
MEM_DQS1N
MEM_DM1/DVO_D8
IOPLLVDD18
MEM_VREF
L1401
L1401
1 2
0R0402-P AD
0R0402-P AD
L1402
L1402
1 2
0R0402-P AD
0R0402-P AD
MEM_DQ4
MEM_DM0
IOPLLVDD
IOPLLVSS
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
+1.8V_RU N
1231-1
+1.1V_RU N
1231-1
SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ1 0
SPM_DQ1 1
SPM_DQ1 2
SPM_DQ1 3
SPM_DQ1 4
SPM_DQ1 5
SPM_DQS 0P
SPM_DQS 0N
SPM_DQS 1P
SPM_DQS 1N
SPM_DM0
SPM_DM1
IOPLLVDD1 8
IOPLLVDD
SPM_VRE F0
MEM_VDD Q
1KR3F-GP
1KR3F-GP
1 2
R1402
R1402
UMA_S PM
SPM_VRE F0
UMA_SPM
1KR3F-GP
1KR3F-GP
1 2
R1405
R1405
UMA_S PM
UMA_SPM
UMA_SPM/DIS_NOSPM
UMA_SPM/DIS_NOSPM
A A
C1404
C1404
1 2
UMA_SPM
UMA_SPM
C1403
C1403
1 2
5
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SPM_VRE F1
MEM_VDD Q
R1403
R1403
UMA_S PM
UMA_SPM
R1406
R1406
UMA_S PM
UMA_SPM
1KR3F-GP
1KR3F-GP
1 2
1KR3F-GP
1KR3F-GP
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1406
C1406
1 2
UMA_SPM
UMA_SPM
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1405
C1405
1 2
UMA_SPM
UMA_SPM
MEM_VDD Q
SCD1U10V2KX-5GP
1KR3F-GP
1KR3F-GP
1 2
R1404
R1404
UMA_S PM
UMA_SPM
SPM_VRE F2
UMA_S PM
UMA_SPM
4
1KR3F-GP
1KR3F-GP
1 2
R1407
R1407
SCD1U10V2KX-5GP
C1408
C1408
1 2
UMA_SPM
UMA_SPM
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1407
C1407
1 2
UMA_SPM
UMA_SPM
1.5V(0.35A) for IOPLLVDD
SCD1U10V2KX - 5GP
C1413
C1413
SCD1U10V2KX-5GP
C1410
C1410
C1409
C1409
1 2
UMA_SPM
UMA_SPM
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1414
C1414
1 2
UMA_SPM
UMA_SPM
3
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
UMA_SPM
UMA_SPM
SCD1U10V2KX - 5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
1 2
UMA_SPM
UMA_SPM
UMA_SPM
UMA_SPM
MEM_VDD Q
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1411
C1411
1 2
UMA_SPM
UMA_SPM
C1412
C1412
R1412
R1412
1 2
UMA_SPM
UMA_SPM
0R3J-0-U-G P
0R3J-0-U-G P
+1.5V_RU N
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
AMD-RS880M_SidePort_(3/4)
AMD-RS880M_SidePort_(3/4)
AMD-RS880M_SidePort_(3/4)
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
14 95 Thu rsday, March 04, 2010
14 95 Thu rsday, March 04, 2010
14 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = N.B
D D
+1.1V_RU N
+1.1V_RU N
C C
+1.1V_RU N
B B
A A
1231-1
R1501
R1501
1 2
0R0603-P AD
0R0603-P AD
R1505
R1505
1 2
0R0603-P AD
0R0603-P AD
R1503
R1503
1 2
0R0603-P AD
0R0603-P AD
+1.8V_RU N
L1505
L1505
1 2
PBY160808 T-221Y-N-GP
PBY160808 T-221Y-N-GP
220R, 2A
1119-1
+1.8V_RU N
+1.8V_RU N
UMA
UMA
R1502
R1502
1 2
0R3J-0-U-G P
0R3J-0-U-G P
40 mils
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1501
C1501
1 2
40 mils
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1511
C1511
1 2
1231-2
20 mils
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1514
C1514
1 2
DY
DY
40 mils
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C1528
C1528
1 2
15 mils
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1534
C1534
1 2
15 mils
SC1U10V3KX-3GP
SC1U10V3KX-3GP
C1542
C1542
1 2
UMA /DIS
UMA/DIS
9/15
Layout Note
5
1.1V(0.6A) for VDDHT
+1.1V_RU N_VDDHT
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1502
C1502
1 2
1 2
DY
DY
1.1V(0.7A) for VDDHTRX
+1.1V_RU N_VDDHTRX
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1507
C1507
1 2
1 2
DY
DY
1.1V(
+1.2V_RU N_VDDHTTX
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1515
C1515
1 2
1 2
DY
DY
C1503
C1503
C1506
C1506
1 2
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1513
C1513
C1512
C1512
1 2
DY
DY
0.4A) for VDDHTTX
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1517
C1517
C1516
C1516
1 2
1 2
1231-2
1.8V(0.7A) for VDDA18PCIE
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1529
C1529
1 2
DY
DY
+1.8V_RU N_VDDA18PCIE
C1530
C1530
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1531
C1531
1 2
1 2
DY
DY
1.8V(0.01A) for VDD18
1.8V(0.025A) for VDD18
C1518
C1518
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1532
C1532
VDD18_M EM
U1F
U1F
A25
M20
W22
W24
W25
AD25
M14
W11
W15
AC12
AA14
AB11
AB15
AB17
AB19
AE20
AB21
D23
E22
G22
G24
G25
H19
N22
P20
R19
R22
R24
R25
H20
U22
V19
Y21
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
Y18
K11
J22
L17
L22
L24
L25
L12
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
RS880M-1 -GP
RS880M-1 -GP
PART 6/6
PART 6/6
U1E
U1E
J17
VDDHT_1
K16
L16
M16
P16
R16
T16
H18
G19
F20
E21
D22
B23
A23
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
J10
P10
K10
C1533
C1533
1 2
M10
R10
AA9
AB9
AD9
AE9
U10
AE11
AD11
L10
W9
H9
T10
Y9
F9
G9
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1
VDD18_MEM2
RS880M-1 -GP
RS880M-1 -GP
PART 5/6
PART 5/6
POWER
POWER
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD33_1
VDD33_2
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
1.1V(2.5A) for VDDPCIE
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
DY
DY
SC1U6D3V2KX-GP
C1504
C1504
C1509
1 2
C1509
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C1508
C1508
1 2
1231-2 1231-2
0.95~1.1V(12A) for VDDC
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C1520
C1520
C1519
C1519
10/8 10/8
1 2
SBD MEM ENABLE
1.5V(0.1A) for VDD_MEM
VDD_MEM _SDP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
UMA_SPM/DIS_NOSPM
UMA_SPM/DIS_NOSPM
C1541
C1541
1 2
1 2
UMA_SPM
UMA_SPM
3.3V
(0.06A) for VDD33
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1535
C1535
1 2
1 2
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1537
C1537
1 2
DY
DY
UMA_SPM
UMA_SPM
1231-2
C1536
C1536
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1538
C1538
+1.1V_RU N_VDDPCIE
C1510
C1510
C1522
C1522
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
130 mils
C1505
C1505
550 mils
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
1231-2 1231-2
1 2
C1540
C1540
15 mils
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1539
C1539
1 2
UMA_SPM
UMA_SPM
15 mils
Layout Note
1215-1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1525
C1525
C1524
C1524
1 2
+1.1V_RU N
G1501
G1501
1 2
GAP-CLOS E-PWR-3-GP
GAP-CLOS E-PWR-3-GP
G1502
G1502
1 2
GAP-CLOS E-PWR-3-GP
GAP-CLOS E-PWR-3-GP
G1503
G1503
1 2
GAP-CLOS E-PWR-3-GP
GAP-CLOS E-PWR-3-GP
G1504
G1504
1 2
GAP-CLOS E-PWR-3-GP
GAP-CLOS E-PWR-3-GP
+NB_VCORE
+NB_VDD C
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1526
C1526
1 2
+1.5V_RU N
R1506
R1506
0R3J-0-U-G P
0R3J-0-U-G P
1 2
UMA_SPM
UMA_SPM
+3.3V_RU N
1 2
10/5
9/11
C1527
C1527
GROUND
GROUND
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
1231-2
1117-2
0104-1
R1507
R1507
1 2
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
R1508
R1508
1 2
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
R1509
R1509
1 2
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
R1510
R1510
1 2
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
R1511
R1511
1 2
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
4
3
2
+1.1V_RU N +NB_VDD C
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
AMD-RS880M_PWR&GD_(4/4)
AMD-RS880M_PWR&GD_(4/4)
AMD-RS880M_PWR&GD_(4/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
A00
A00
15 95 Thu rsday, March 04, 2010
15 95 Thu rsday, March 04, 2010
15 95 Thu rsday, March 04, 2010
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
16 95 Thu rsday, March 04, 2010
16 95 Thu rsday, March 04, 2010
16 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
17 95 Thu rsday, March 04, 2010
17 95 Thu rsday, March 04, 2010
17 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
SSID = MEMORY
11/10
DM1
C1822
C1822
DM1
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P- 41-GP-U
DDR3-204P- 41-GP-U
62.10017.N41
H =5.2mm
4
RAS#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0#
CK1#
EVENT#
VDDSPD
NC#1
NC#2
NC#/TEST
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
NP1
NP1
NP2
NP2
110
113
WE#
115
114
121
73
74
101
CK0
103
102
CK1
104
M_A_DM0
11
DM0
M_A_DM1
28
DM1
M_A_DM2
46
DM2
M_A_DM3
63
DM3
M_A_DM4
136
DM4
M_A_DM5
153
DM5
M_A_DM6
170
DM6
M_A_DM7
187
DM7
SB_SMBDATA
200
SDA
SB_SMBCLK
202
SCL
PM_EXTTS#0
198
199
197
SA0
201
SA1
77
122
125
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
1.5V, 3.5A
+1.5V_SUS
MEM_MA_RAS# (9)
MEM_MA_WE# (9)
MEM_MA_CAS# (9)
MEM_MA0_CS#0 ( 9)
MEM_MA0_CS#1 ( 9)
MEM_MA_CKE0 (9)
MEM_MA_CKE1 (9)
MEM_MA_CLK0_P (9)
MEM_MA_CLK0_N (9)
MEM_MA_CLK1_P (9)
MEM_MA_CLK1_N (9)
M_A_DM[7..0] (9)
9/23
Note:
SA0 = 0, SA1 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
Layout Note:
Place these Caps near
SO-DIMMA.
+1.5V_SUS
PM_EXTTS#0
1 2
DY
R1806 4K7R2J -2-GPDYR1806 4K7R2J -2-GP
0107-4
SB_SMBDATA (19,76)
+3.3V_RUN
3.3V, 2mA
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1802
C1802
1 2
9/23
SB_SMBCLK (19,76)
SB_SMBCLK
SB_SMBDATA
RN
RN
0R4P2R-PAD
0R4P2R-PAD
1
4
2 3
RN1801
RN1801
DY
DY
1 2
C1823 SC 10P50V2JN -4GP
C1823 SC 10P50V2JN -4GP
1 2
C1824 SC10P50V2JN -4GP
C1824 SC10P50V2JN -4GP
DY
DY
SB_SMBDATA_R (7,21)
SB_SMBCLK_R (7,21)
SODIMM A DECOUPLING (ONE CAP PER POWER PIN)
+1.5V_SUS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C1812
C1812
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
DY
DY
3
C1813
C1813
C1806
C1806
C1805
C1805
C1804
C1804
1 2
1 2
C1814
C1814
C1815
C1815
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
1 2
DY
DY
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1808
C1808
C1809
C1809
C1807
C1807
1 2
1 2
1 2
1225-1
SE330U2VDM-L-GP
SE330U2VDM-L-GP
TC1801
TC1801
C1817
C1817
C1816
C1816
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
1 2
1 2
1 2
DY
DY
DY
DY
DY
DY
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O.C.
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
18 95 Thursday, March 04, 2010
18 95 Thursday, March 04, 2010
18 95 Thursday, March 04, 2010
A00
A00
A00
MEM_MA_ADD[0..15] (9)
D D
MEM_MA_BANK2 (9)
MEM_MA_BANK0 (9)
MEM_MA_BANK1 (9)
M_A_DQ[63..0] (9)
C C
M_A_DQS#0 (9)
M_A_DQS#1 (9)
M_A_DQS#2 (9)
M_A_DQS#3 (9)
B B
+V_DDR_RE F
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD01U50V3KX-4GP
SCD01U50V3KX-4GP
SCD1U10V2KX-5GP
9/14
C1825
C1825
1 2
SCD1U10V2KX-5GP
C1810
C1810
1 2
M_A_DQS#4 (9)
M_A_DQS#5 (9)
M_A_DQS#6 (9)
M_A_DQS#7 (9)
M_A_DQS0 (9)
M_A_DQS1 (9)
M_A_DQS2 (9)
M_A_DQS3 (9)
M_A_DQS4 (9)
M_A_DQS5 (9)
M_A_DQS6 (9)
M_A_DQS7 (9)
MEM_MA0_ODT0 (9)
MEM_MA0_ODT1 (9)
9/23
C1811
C1811
1 2
DDR3_A_DR AMRST# (9)
0108-3
10/7
+0.75V_DDR_VT T
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
0.75V, 0.5A
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1819
C1819
C1820
C1820
C1821
Place these caps
close to VTT1 and
A A
VTT2.
5
1 2
1231-2
C1821
1 2
1 2
DY
DY
DY
DY
5
+V_DDR_RE F
SCD01U50V3KX-4GP
SCD01U50V3KX-4GP
1 2
MEM_MB_ADD[0..15] (9)
MEM_MB_BANK2 (9)
MEM_MB_BANK0 (9)
MEM_MB_BANK1 (9)
M_B_DQ[63..0] (9)
M_B_DQS#0 (9)
M_B_DQS#1 (9)
M_B_DQS#2 (9)
M_B_DQS#3 (9)
M_B_DQS#4 (9)
M_B_DQS#5 (9)
M_B_DQS#6 (9)
M_B_DQS#7 (9)
M_B_DQS0 (9)
M_B_DQS1 (9)
M_B_DQS2 (9)
M_B_DQS3 (9)
M_B_DQS4 (9)
M_B_DQS5 (9)
M_B_DQS6 (9)
M_B_DQS7 (9)
MEM_MB0_ODT0 (9)
MEM_MB0_ODT1 (9)
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1905
C1905
C1904
C1904
1 2
DDR3_B_DR AMRST# (9)
10/7
+0.75V_DDR_VT T
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1918
C1918
C1919
C1919
1 2
1 2
DY
DY
DY
DY
SSID = MEMORY
D D
C C
B B
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
9/14 9/23
C1922
C1922
1 2
0108-3
Place these caps
close to VTT1 and
VTT2.
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
0.75V, 0.5A
C1920
C1920
1 2
4
C1921
C1921
DM2
DM2
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12
119
A13
80
A14
78
A15
79
A16/BA2
109
BA0
108
BA1
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
10
DQS0#
27
DQS1#
45
DQS2#
62
DQS3#
135
DQS4#
152
DQS5#
169
DQS6#
186
DQS7#
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
116
ODT0
120
ODT1
126
VREF_CA
1
VREF_DQ
30
RESET#
203
VTT1
204
VTT2
DDR3-204P- 40-GP-U
DDR3-204P- 40-GP-U
H = 9.2mm
11/10
NP1
NP1
NP2
NP2
110
RAS#
113
WE#
115
CAS#
114
CS0#
121
CS1#
73
CKE0
74
CKE1
101
CK0
103
CK0#
102
CK1
104
CK1#
M_B_DM0
11
DM0
M_B_DM1
28
DM1
M_B_DM2
46
DM2
M_B_DM3
63
DM3
M_B_DM4
136
DM4
M_B_DM5
153
DM5
M_B_DM6
170
DM6
M_B_DM7
187
DM7
SB_SMBDATA
200
SDA
SB_SMBCLK
202
SCL
PM_EXTTS#1
198
EVENT#
199
VDDSPD
197
SA0
201
SA1
77
NC#1
122
NC#2
125
NC#/TEST
1.5V
, 3.5A
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VSS
65
VSS
66
VSS
71
VSS
72
VSS
127
VSS
128
VSS
133
VSS
134
VSS
138
VSS
139
VSS
144
VSS
145
VSS
150
VSS
151
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
172
VSS
173
VSS
178
VSS
179
VSS
184
VSS
185
VSS
189
VSS
190
VSS
195
VSS
196
VSS
205
VSS
206
VSS
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
+1.5V_SUS
MEM_MB_RAS# (9)
MEM_MB_WE# (9)
MEM_MB_CAS# (9)
MEM_MB0_CS#0 ( 9)
MEM_MB0_CS#1 ( 9)
MEM_MB_CKE0 (9)
MEM_MB_CKE1 (9)
MEM_MB_CLK0_P (9)
MEM_MB_CLK0_N (9)
MEM_MB_CLK1_P (9)
MEM_MB_CLK1_N (9)
M_B_DM[7..0] (9)
9/23
+3.3V_RUN
9/23
3
SB_SMBDATA ( 18,76)
SB_SMBCLK (18,76)
3.3V, 2mA
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1902
C1902
1 2
9/23
Note:
SA0 = 0, SA1 = 1
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
Layout Note:
Place these Caps near
SO-DIMMB.
+3.3V_RUN
C1912
C1912
+1.5V_SUS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
DY
DY
2
+1.5V_SUS
PM_EXTTS#1
1 2
DY
R1906 4K7R 2J-2-GPDYR1906 4K7R 2J-2-GP
SODIMM B DECOUPLING (ONE CAP PER POWER PIN)
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1909
C1909
C1910
C1910
C1911
1 2
C1916
C1916
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
DY
DY
C1911
1 2
1 2
C1917
C1917
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
1 2
DY
DY
DY
DY
C1913
C1913
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1907
C1907
C1906
C1906
C1908
C1908
1 2
1 2
C1915
C1915
C1914
C1914
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
1 2
DY
DY
DY
DY
1
1231-2
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
19 95 Thursday, March 04, 2010
19 95 Thursday, March 04, 2010
19 95 Thursday, March 04, 2010
A00
A00
A00
5
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
5
SSID = S.B
C2001 SC150P5 0V2KX-GP C20 01 SC150P5 0V2KX-GP
1 2
ALINK_NBR X_SBTX_P0 (12)
ALINK_NBR X_SBTX_N0 (12)
ALINK_NBR X_SBTX_P1 (12)
D D
Place R <100mils form
pins AD29,AD28
C C
ALINK_NBR X_SBTX_N1 (12)
ALINK_NBR X_SBTX_P2 (12)
ALINK_NBR X_SBTX_N2 (12)
ALINK_NBR X_SBTX_P3 (12)
ALINK_NBR X_SBTX_N3 (12)
ALINK_NBT X_SBRX_P0 (12)
ALINK_NBT X_SBRX_N0 (12)
ALINK_NBT X_SBRX_P1 (12)
ALINK_NBT X_SBRX_N1 (12)
ALINK_NBT X_SBRX_P2 (12)
ALINK_NBT X_SBRX_N2 (12)
ALINK_NBT X_SBRX_P3 (12)
ALINK_NBT X_SBRX_N3 (12)
+1.1V_RU N_PCIE_VDDR
NOTE: SB8XX ONLY SUPPORTS 2 GPP
PORT
2 AND 3 IS NOT SUPPORTED. (From CRB)
SB820M : 71.SB820.M02
R2024 22R2J-2-G P R2024 22R2J -2-GP
C2002 S CD1U10V2KX-5G P C2002 S CD1U10V2KX-5G P
1 2
C2003 S CD1U10V2KX-5G P C2003 S CD1U10V2KX-5G P
1 2
C2004 S CD1U10V2KX-5G P C2004 S CD1U10V2KX-5G P
1 2
C2005 S CD1U10V2KX-5G P C2005 S CD1U10V2KX-5G P
1 2
C2006 S CD1U10V2KX-5G P C2006 S CD1U10V2KX-5G P
1 2
C2007 S CD1U10V2KX-5G P C2007 S CD1U10V2KX-5G P
1 2
C2008 S CD1U10V2KX-5G P C2008 S CD1U10V2KX-5G P
1 2
C2009 S CD1U10V2KX-5G P C2009 S CD1U10V2KX-5G P
1 2
1 2
R2002 590R2F-GP R 2002 590 R2F-GP
1 2
R2007 2KR2F-3-GP R2007 2 KR2F-3-GP
1 2
ALINK_NBR X_SBTX_C_P0
ALINK_NBR X_SBTX_C_N0
ALINK_NBR X_SBTX_C_P1
ALINK_NBR X_SBTX_C_N1
ALINK_NBR X_SBTX_C_P2
ALINK_NBR X_SBTX_C_N2
ALINK_NBR X_SBTX_C_P3
ALINK_NBR X_SBTX_C_N3
9/23
SB_PCIE_C LK (7)
SB_PCIE_C LK# (7 )
B B
1nd 82.30020.791
82.30020.851
A A
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
R2017 1MR2J-1-G P R2017 1MR2J-1-GP
1 2
X2001
X2001
1 2
XTAL-25M HZ-96GP
C2014
C2014
1113-1
1 2
XTAL-25M HZ-96GP
5
1 2
2nd
25M_X1
25M_X2
C2015
C2015
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
4
PCIE_RST# _SB
A_RST#_ R A_RST#
SB_PCIE_C ALRP
SB_PCIE_C ALRN
SB_PCIE_C LK
SB_PCIE_C LK#
25M_X1
25M_X2
4
9/11
U2A
U2A
P1
PCIE_RST#
L1
A_RST#
AD26
A_TX0P
AD27
A_TX0N
AC28
A_TX1P
AC29
A_TX1N
AB29
A_TX2P
AB28
A_TX2N
AB26
A_TX3P
AB27
A_TX3N
AE24
A_RX0P
AE23
A_RX0N
AD25
A_RX1P
AD24
A_RX1N
AC24
A_RX2P
AC25
A_RX2N
AB25
A_RX3P
AB24
A_RX3N
AD29
PCIE_CALRP
AD28
PCIE_CALRN
AA28
GPP_TX0P
AA29
GPP_TX0N
Y29
GPP_TX1P
Y28
GPP_TX1N
Y26
GPP_TX2P
Y27
GPP_TX2N
W28
GPP_TX3P
W29
GPP_TX3N
AA22
GPP_RX0P
Y21
GPP_RX0N
AA25
GPP_RX1P
AA24
GPP_RX1N
W23
GPP_RX2P
V24
GPP_RX2N
W24
GPP_RX3P
W25
GPP_RX3N
M23
PCIE_RCLKP/NB_LNK_CLKP
P23
PCIE_RCLKN/NB_LNK_CLKN
U29
NB_DISP_CLKP
U28
NB_DISP_CLKN
T26
NB_HT_CLKP
T27
NB_HT_CLKN
V21
CPU_HT_CLKP
T21
CPU_HT_CLKN
V23
SLT_GFX_CLKP
T23
SLT_GFX_CLKN
L29
GPP_CLK0P
L28
GPP_CLK0N
N29
GPP_CLK1P
N28
GPP_CLK1N
M29
GPP_CLK2P
M28
GPP_CLK2N
T25
GPP_CLK3P
V25
GPP_CLK3N
L24
GPP_CLK4P
L23
GPP_CLK4N
P25
GPP_CLK5P
M25
GPP_CLK5N
P29
GPP_CLK6P
P28
GPP_CLK6N
N26
GPP_CLK7P
N27
GPP_CLK7N
T29
GPP_CLK8P
T28
GPP_CLK8N
L25
14M_25M_48M_OSC
L26
25M_X1
L27
25M_X2
SB820M-1-GP
SB820M-1-GP
Part 1 of 5
Part 1 of 5
PCICLK4/14M_OSC/GPO39
PCI CLKS
PCI CLKS
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
REQ2#/CLK_REQ8#/GPIO41
PCI INTERFACE LPC
PCI INTERFACE LPC
REQ3#/CLK_REQ5#/GPIO42
GNT3#/CLK_REQ7#/GPIO46
LDRQ1#/CLK_REQ6#/GPIO49
ALLOW_LDTSTP/DMA_ACTIVE#
CLOCK GENERATOR
CLOCK GENERATOR
CPU
CPU
RTC
RTC
3
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
GNT0#
GNT1#/GPO44
GNT2#/GPO45
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
SERIRQ/GPIO48
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
32K_X1
32K_X2
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
3
W2
W1
W3
W4
PCLK_FW H_R
Y1
PCI_RST#
V2
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
1119-1
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
SB_GPIO46
AB12
AB11
AD7
AJ6
AG6
AG4
AJ4
LPCCLK0 _R
H24
LPCCLK1 _R
H25
LPC_LAD 0
J27
LPC_LAD 1
J26
LPC_LAD 2
H29
LPC_LAD 3
H28
G28
TP_LPC_ LDRQ0#
J25
TP_LPC_ LDRQ1#
AA18
AB19
G21
H21
K19
G22
J24
32K_X1
C1
32K_X2_ R
C2
RTC_CLK
D2
INTRUDER_ ALERT#
B2
B1
1
TP_PCI_AD 28
TP_PCI_AD 29
R2029 22R2J-2-G P
R2029 22R2J-2-G P
1 2
DY
DY
TP2008 TP2008
9/24
9/16
PCI_AD23 (24)
PCI_AD25 (24)
PCI_AD26 (24)
PCI_AD27 (24)
1
TP2009 TP2009
1
TP2001 TP2001
9/25
GP_PCIE_R ST# (2 1)
A_RST#
TP2004 TP2004
1
9/23
1118-2
RN2008
RN2008
1
4
2 3
SRN22-3-G P
SRN22-3-G P
1
TP2005 TP2005
1
R2018 1 0R2J-2-GP R2018 10R2 J-2-GP
1
TP2007 TP2007
to EC
TP2006 TP2006
ALLOW _LDTSTOP (13)
CPU_PRO CHOT# (10)
CPU_LDT _PWRGD (10,4 2)
CPU_LDT _STOP# (10,13)
CPU_LDT _RST# (10)
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2017
C2017
1 2
DY
DY
2
PCI_CLK1 (24)
PCI_CLK2 (24)
PCI_CLK3 (24)
PCLK_FW H (24 ,70)
11/6
R2025
R2025
22R2J-2-G P
PCIE_RST# _SB PLTRST# _LAN_WLAN
22R2J-2-G P
STRAP PIN
1 2
C2013
C2013
SC150P5 0V2KX-GP
SC150P5 0V2KX-GP
DY
DY
1 2
9/22
VDDR_SE L (24,51)
+3.3V_AL W
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2010
C2010
U2001
U2001
1
DY
DY
B
VCC
2
A
3
PM_CLKR UN# (37 )
1 2
C2018 SC10P50 V2JN-4GP
C2018 SC10P50 V2JN-4GP
LPCCLK1 (24)
LPC_LAD 0 (3 7,70)
LPC_LAD 1 (3 7,70)
LPC_LAD 2 (3 7,70)
LPC_LAD 3 (3 7,70)
LPC_LFR AME# (37,70 )
+RTC_CE LL
Y
GND
74LVC1G 08GW-1-GP
74LVC1G 08GW-1-GP
1 2
R2021
R2021
0R0402-P AD
0R0402-P AD
DY
DY
LPC Bus Routing first connects to
MINICARD then connects to KBC
INT_SERIRQ (37)
RTCCLK_ KBC (37 )
RTC_CLK (39)
2
5
4
1231-1
1 2
DY
DY
PLTRST#
11/6
9/23
PCLK_KB C (24,37)
32K_X1
32K_X2_ R 32K_X2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
SB820M_PCIE&PCI_(1/5)
SB820M_PCIE&PCI_(1/5)
SB820M_PCIE&PCI_(1/5)
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3.3V_RU N
11/6
1 2
R2026
R2026
10KR2J-3 -GP
10KR2J-3 -GP
11/6
R2028
R2028
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
1231-1
R2005
R2005
1 2
0R0402-P AD
0R0402-P AD
R2008
R2008
0R0402-P AD
0R0402-P AD
R2016
R2016
1 2
0R0402-P AD
0R0402-P AD
1231-1
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
PLTRST# _NB_GPU (13,3 7,80)
1 2
PLTRST# _EC (37)
1 2
R2014
R2014
20MR3-GP
20MR3-GP
X-32D768 KHZ-38GPU
X-32D768 KHZ-38GPU
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
PLTRST# _LAN_WLAN (70,76,78)
1119-1
GPU,
NB
KBC
11/12-1
1 2
C2011
C2011
SC18P50 V2JN-1-GP
SC18P50 V2JN-1-GP
4
1
2 3
X2002
X2002
1 2
C2012
C2012
SC15P50 V2JN-2-GP
SC15P50 V2JN-2-GP
11/12-1
20 95 Friday, March 0 5, 2010
20 95 Friday, March 0 5, 2010
20 95 Friday, March 0 5, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = S.B
+3.3V_RU N
D D
+3.3V_AL W
C C
B B
+3.3V_AL W
A A
1119-5
RN2101
RN2101
1
2 3
SRN4K7J -8-GP
SRN4K7J -8-GP
4
9/23
9/22
RN2103
RN2103
1
4
2 3
SRN10KJ -5-GP
SRN10KJ -5-GP
R2132
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VRAMUMA_SPM_Hynix
VRAMUMA_SPM_Hynix
R2132
10KR2J-3 -GP
10KR2J-3 -GP
R2108
R2108
DY
DY
2K2R2J-2 -GP
2K2R2J-2 -GP
R2110
R2110
DY
DY
2K2R2J-2 -GP
2K2R2J-2 -GP
R2112
R2112
DY
DY
2K2R2J-2 -GP
2K2R2J-2 -GP
R2113
R2113
10KR2J-3 -GP
10KR2J-3 -GP
R2114
R2114
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R2115
R2115
10KR2J-3 -GP
10KR2J-3 -GP
R2116
R2116
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R2117
R2117
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R2118
R2118
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R2119
R2119
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R2133
R2133
0R2J-2-GP
0R2J-2-GP
10/1
RN2102
RN2102
1
8
2
7
3
6
4 5
SRN10KJ -6-G P
SRN10KJ -6-GP
R2124 1 0KR2J-3-GP R2124 1 0KR2J-3-GP
1 2
RN2104
RN2104
1
4
2 3
SRN10KJ -5-GP
SRN10KJ -5-GP
9/23
SB_SMBDATA_R
SB_SMBC LK_R
SMB_DAT A
SMB_CLK
9/22
TALERT#
SB_TEST 2
SB_TEST 1
SB_TEST 0
PCIE_W AKE#
KBC_RSM RST#
SIO_EXT_W AKE#
SIO_EXT_S CI#
SIO_EXT_S MI#
SB_SDIN_C ODEC
ACZ_BIT_C LK
SP_VRAM _SEL
0225-4
GBE_COL
GBE_CRS
GBE_RXE RR
GBE_MDIO
GBE_PHY_INTR
SCL2
SDA2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2104
C2104
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2103
C2103
1 2
1116-3
SB_AZ_C ODEC_BITCLK (30)
SB_AZ_C ODEC_SDOUT (30)
SB_AZ_C ODEC_SYNC (30)
SB_AZ_C ODEC_RST# (30)
0113-1
SIO_RCIN#
1 2
C2105
C2105
SCD047U 10V2KX-2GP
SCD047U 10V2KX-2GP
SB_SDIN_C ODEC (30)
9/25
9/16
R2106 0R04 02-PAD R2106 0R 0402-PAD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2101
C2101
1 2
DY
DY
R2128 0R 2J-2-GP
R2128 0R 2J-2-GP
GbE MAC Not Enabled
TP_PCI_PM E#
1
PM_PW RBTN#_R
SUS_STA T#
SB_TEST 0
SB_TEST 1
SB_TEST 2
SYS_RESET #
1
SB_THER MTRIP#
PM_RSMR ST#_R
Close SB
9/23
SB_SMBC LK_R
SB_SMBD ATA_R
SMB_CLK
SMB_DAT A
CLK_REQ 2#
1
SP_VRAM _SEL
SB_GPIO51
1
GEVENT7 #
SB_OSCIN SB_ OSCIN
9/23
USB_OC7 #
1
USB_OC6 #
1
USB_OC4 #
1
USB_OC3 #
1
USB_OC2 #
1
USB_OC# 2_3
USB_OC# 0_1
ACZ_BIT_C LK
ACZ_SYNC_ R
ACZ_RST #_R
GBE_COL
GBE_CRS
GBE_MDIO
GBE_RXE RR
GBE_PHY_INTR
SPI_CS2#
1
GPO160
1
SIO_EXT_W AKE# (37)
PM_SLP_ S3# (37,41,42,4 9,52,89)
PM_SLP_ S5# (37 ,49)
PM_PW RBTN# (37)
SB_PW RGD (7,41)
SUS_STA T# (13)
10/7 10/7
SIO_A20GA TE (37)
SIO_RCIN# (37)
SIO_EXT_S CI# (3 7)
SIO_EXT_S MI# (37)
PCIE_W AKE# (76)
H_THERM TRIP# (1 0,37,39,42,82)
NB_PW RGD (41 )
KBC_RSM RST# (37)
GP_PCIE_R ST# (20 )
ACZ_SPK R (30)
SB_SMBC LK_R (7,18 )
SB_SMBD ATA_R (7,18 )
SP_DDR3 _RST# (14)
SB_14M_ CLK (7)
1 2
C2102 SC180P5 0V2JN-1GP
C2102 SC180P5 0V2JN-1GP
R2111
R2111
0R0402-P AD
0R0402-P AD
1231-1
GP_PCIE_R ST# GP_PCIE_R ST#
R2131
R2131
9/22
USB_OC# 2_3 (63)
USB_OC# 0_1 (63)
ACZ_SDA TAOUT_R (24)
33R2J-2-G PR2120 33R2J-2-G PR2120
33R2J-2-G PR2121 33R2J-2-G PR2121
9/16
EC2101
EC2101
1 2
SC180P5 0V2JN-1GP
SC180P5 0V2JN-1GP
33R2J-2-G PR2122 33R2J-2-G PR2122
33R2J-2-G PR2123 33R2J-2-G PR2123
TP2135 TP2135
TP2134 TP2134
SC180P50V2JN-1GP
SC180P50V2JN-1GP
DY
DY
1 2
1 2
DY
DY
1 2
1 2
EC2102
EC2102
1 2
TP2101 TP2101
9/23
1 2
1231-1
DY
DY
TP2120 TP2120
1 2
R2109 0R0402-P AD R2109 0R0402-P AD
1 2
TP2127 TP2127
TP2113 TP2113
1 2
UMA_SPM
UMA_SPM
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
TP2133 TP2133
TP2129 TP2129
TALERT# (10,39)
TP2132 TP2132
TP2131 TP2131
TP2130 TP2130
9/24
TP_DEBU G_DAT
1
TP_DEBU G_CLK
1
TP2116 TP2116
TP2117 TP2117
EC Not Implemented
5
4
U2D
U2D
J2
PCI_PME#/GEVENT4#
K1
RI#/GEVENT22#
D3
SPI_CS3#/GBE_STAT1/GEVENT21#
F1
SLP_S3#
H1
SLP_S5#
F2
PWR_BTN#
H5
PWR_GOOD
G6
SUS_STAT#
B3
TEST0
C4
TEST1/TMS
F6
TEST2
AD21
GA20IN/GEVENT0#
AE21
KBRST#/GEVENT1#
K2
LPC_PME#/GEVENT3#
J29
LPC_SMI#/GEVENT23#
H2
GEVENT5#
J1
SYS_RESET#/GEVENT19#
H6
WAKE#/GEVENT8#
F3
IR_RX1/GEVENT20#
J6
THRMTRIP#/SMBALERT#/GEVENT2#
AC19
NB_PWRGD
G1
RSMRST#
AD19
CLK_REQ4#/SATA_IS0#/GPIO64
AA16
CLK_REQ3#/SATA_IS1#/GPIO63
AB21
SMARTVOLT1/SATA_IS2#/GPIO50
AC18
CLK_REQ0#/SATA_IS3#/GPIO60
AF20
SATA_IS4#/FANOUT3/GPIO55
AE19
SATA_IS5#/FANIN3/GPIO59
AF19
SPKR/GPIO66
AD22
SCL0/GPIO43
AE22
SDA0/GPIO47
F5
SCL1/GPIO227
F4
SDA1/GPIO228
AH21
CLK_REQ2#/FANIN4/GPIO62
AB18
CLK_REQ1#/FANOUT4/GPIO61
E1
IR_LED#/LLB#/GPIO184
AJ21
SMARTVOLT2/SHUTDOWN#/GPIO51
H4
DDR3_RST#/GEVENT7#
D5
GBE_LED0/GPIO183
D7
GBE_LED1/GEVENT9#
G5
GBE_LED2/GEVENT10#
K3
GBE_STAT0/GEVENT11#
AA20
CLK_REQG#/GPIO65/OSCIN/IDLEEXT#
H3
BLINK/USB_OC7#/GEVENT18#
D1
USB_OC6#/IR_TX1/GEVENT6#
E4
USB_OC5#/IR_TX0/GEVENT17#
D4
USB_OC4#/IR_RX0/GEVENT16#
E8
USB_OC3#/AC_PRES/TDO/GEVENT15#
F7
USB_OC2#/TCK/GEVENT14#
E7
USB_OC1#/TDI/GEVENT13#
F8
USB_OC0#/TRST#/GEVENT12#
M3
AZ_BITCLK
N1
AZ_SDOUT
L2
AZ_SDIN0/GPIO167
M2
AZ_SDIN1/GPIO168
M1
AZ_SDIN2/GPIO169
M4
AZ_SDIN3/GPIO170
N2
AZ_SYNC
P2
AZ_RST#
T1
GBE_COL
T4
GBE_CRS
L6
GBE_MDCK
L5
GBE_MDIO
T9
GBE_RXCLK
U1
GBE_RXD3
U3
GBE_RXD2
T2
GBE_RXD1
U2
GBE_RXD0
T5
GBE_RXCTL/RXDV
V5
GBE_RXERR
P5
GBE_TXCLK
M5
GBE_TXD3
P9
GBE_TXD2
T7
GBE_TXD1
P7
GBE_TXD0
M7
GBE_TXCTL/TXEN
P4
GBE_PHY_PD
M9
GBE_PHY_RST#
V7
GBE_PHY_INTR
E23
PS2_DAT/SDA4/GPIO187
E24
PS2_CLK/SCL4/GPIO188
F21
SPI_CS2#/GBE_STAT2/GPIO166
G29
FC_RST#/GPO160
D27
PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
F29
PS2M_DAT/GPIO191
E27
PS2M_CLK/GPIO192
SB820M-1 -GP
SB820M-1 -GP
3
Part 4 of 5
Part 4 of 5
HD AUDIO
HD AUDIO
GBE LAN
GBE LAN
USBCLK/14M_25M_48M_OSC
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB 1.1 USB MISC EMBEDDED CTRL
USB 1.1 USB MISC EMBEDDED CTRL
USB_HSD12P
ACPI / WAKE UP EVENTS
ACPI / WAKE UP EVENTS
GPIO
GPIO
USB OC
USB OC
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
EMBEDDED CTRL
EMBEDDED CTRL
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB 2.0
USB 2.0
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
A10
G19
J10
H11
H9
J8
B12
A12
F11
E11
E14
E12
J12
J14
A13
B13
D13
C13
G12
G14
G16
G18
D16
C16
B14
A14
E18
E16
J16
J18
B17
A17
A16
B16
D25
F23
B26
E26
F25
E22
F22
E21
G24
G25
E28
E29
D29
D28
C29
C28
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
USB_48M _CLK
USB_RCO MP
USB_PP5
USB_PN5
USB_PP1
USB_PN1
SCL2
SDA2
EC Not Implemented
2
USB_48M _CLK (7)
SC180P50V2JN-1GP
USB_PP5 (76)
USB_PN5 (76)
SC180P50V2JN-1GP
DY
DY
EC2103
EC2103
1 2
USB
Pair
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Device
USB0 (I/O Board/ESATA)
USB1 (I/O Board)
USB2 (CRT Board)
USB3 (CRT Board)
WLAN USB
WWAN USB
RESERVED
RESERVED
RESERVED
BLUETOOTH
CARD READER
CAMERA (LVDS CONN)
RESERVED
RESERVED
1 2
R2102
R2102
11K8R2F -GP
11K8R2F -GP
USB_PP1 1 (54)
USB_PN1 1 (54)
USB_PP1 0 (78)
USB_PN1 0 (78)
USB_PP9 (73)
USB_PN9 (73)
USB_PP4 (76)
USB_PN4 (76)
USB_PP3 (77)
USB_PN3 (77)
USB_PP2 (77)
USB_PN2 (77)
USB_PP1 (76)
USB_PN1 (76)
USB_PP0 (76)
USB_PN0 (76)
Not use
CPU_SIC (10)
CPU_SID (10 )
SB_GPO1 99 (24)
SB_GPO2 00 (24)
Strap Pin / define to use LPC or SPI ROM
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
SB820M_USB&GPIO_(2/5)
SB820M_USB&GPIO_(2/5)
SB820M_USB&GPIO_(2/5)
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
1
A00
A00
21 95 Thu rsday, March 04, 2010
21 95 Thu rsday, March 04, 2010
21 95 Thu rsday, March 04, 2010
A00
SSID = S.B
9/15
XTAL
1'nd 82.30020.851
DY
DY
C2209
C2209
1 2
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
DY
DY
C2210
C2210
1 2
SC12P50 V2JN-3GP
SC12P50 V2JN-3GP
2'nd 82.30020.791
XTAL-25MHZ-102-GP
XTAL-25MHZ-102-GP
1 2
DY
DY
10MR2J-L-GP
10MR2J-L-GP
X2201
X2201
SATA HDD
SATA ODD
E-SATA
1 2
R2204
R2204
DY
DY
SATA_TX P0 (59)
SATA_TX N0 (59)
SATA_RX N0 (59)
SATA_RX P0 (5 9)
SATA_TX P1 (59)
SATA_TX N1 (59)
SATA_RX N1 (59)
SATA_RX P1 (5 9)
SATA_TX P2 (76)
SATA_TX N2 (76)
SATA_RX N2 (76)
SATA_RX P2 (7 6)
PLACE SATA AC DECOUPLING
CAPS CLOSE TO SB820M
+1.1V_RU N_AVDD_SATA
SATA_X1
SATA_X2
C2201 SCD01U5 0V2ZY-1GP C2 201 SCD0 1U50V2ZY-1GP
1 2
C2202 SCD01U5 0V2ZY-1GP C2 202 SCD0 1U50V2ZY-1GP
1 2
C2203 SCD01U5 0V2ZY-1GP C2 203 SCD0 1U50V2ZY-1GP
1 2
C2204 SCD01U5 0V2ZY-1GP C2 204 SCD0 1U50V2ZY-1GP
1 2
C2205 SCD01U5 0V2ZY-1GP C2 205 SCD0 1U50V2ZY-1GP
1 2
C2206 SCD01U5 0V2ZY-1GP C2 206 SCD0 1U50V2ZY-1GP
1 2
C2208 SCD01U5 0V2ZY-1GP C2 208 SCD0 1U50V2ZY-1GP
1 2
C2207 SCD01U5 0V2ZY-1GP C2 207 SCD0 1U50V2ZY-1GP
1 2
C2211 SCD01U5 0V2ZY-1GP C2 211 SCD0 1U50V2ZY-1GP
1 2
C2214 SCD01U5 0V2ZY-1GP C2 214 SCD0 1U50V2ZY-1GP
1 2
SATA_TX P0_C
SATA_TX N0_C
SATA_RX N0_C
SATA_RX P0_C
SATA_TX P1_C
SATA_TX N1_C
SATA_RX N1_C
SATA_RX P1_C
SATA_TX P2_C
SATA_TX N2_C
SATA_RX N2
SATA_RX P2
10/6
Very Close
to SB820
1KR2F-3-G P
1KR2F-3-G P
R2201
R2201
1 2
1 2
R2202 931R2F-1 -GP R2202 931R2F-1 -GP
SATA_LE D# (66)
SATA_X1
SATA_X2
SPI ROM in KBC side
SATA_CA LP
SATA_CA LN
AH10
AJ10
AG10
AF10
AG12
AF12
AJ12
AH12
AH14
AJ14
AG14
AF14
AG17
AF17
AJ17
AH17
AJ18
AH18
AH19
AJ19
AB14
AA14
AD11
AD16
AC16
9/24
U2B
U2B
AH9
SATA_TX0P
AJ9
SATA_TX0N
AJ8
SATA_RX0N
AH8
SATA_RX0P
SATA_TX1P
SATA_TX1N
SATA_RX1N
SATA_RX1P
SATA_TX2P
SATA_TX2N
SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N
SATA_RX3N
SATA_RX3P
SATA_TX4P
SATA_TX4N
SATA_RX4N
SATA_RX4P
SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
SATA_CALRP
SATA_CALRN
SATA_ACT#/GPIO67
SATA_X1
SATA_X2
J5
SPI_DI/GPIO164
E2
SPI_DO/GPIO163
K4
SPI_CLK/GPIO162
K9
SPI_CS1#/GPIO165
G2
ROM_RST#/GPIO161
SB820M-1-GP
SB820M-1-GP
Part 2 of 5
Part 2 of 5
SERIAL ATA
SERIAL ATA
HW MONITOR
HW MONITOR
SPI ROM
SPI ROM
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
FLASH
FLASH
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
NC#G27
NC2#Y2
AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
W5
W6
Y9
W7
V9
W8
B6
A6
A5
B5
C7
A3
B4
A4
C5
A7
B7
B8
A8
G27
Y2
50:128] are open drain GPIO pins
GPIOD[1
where as GPO160 is an open drain GPO pin.
These pins are not programmed to GPIO mode by default.
If use as GPIO, need to pull up to 1.8V_RUN
TEMPIN0
TEMPIN1
TEMPIN2
TEMPIN3
VIN0
VIN1
VIN2
VIN3
MEM_1V5
VIN5
VIN6
VIN7
10/9
MEM_1V5 (51)
9/22
1119-1
Move to P.51
TEMPIN0
TEMPIN1
TEMPIN2
TEMPIN3
9/16
1
2
3
4 5
10/1
VIN2
VIN0
VIN1
VIN3
10/9
VIN7
VIN6
VIN5
1
2
3
4 5
1
2
3
4 5
RN2201
RN2201
8
7
6
SRN10KJ -6-GP
SRN10KJ -6-GP
RN2202
RN2202
8
7
6
SRN10KJ -6-GP
SRN10KJ -6-GP
RN2203
RN2203
8
7
6
SRN10KJ -6-GP
SRN10KJ -6-GP
+3.3V_AL W
+3.3V_AL W
+3.3V_AL W
1116-1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
SB820M_SATA-IDE_(3/5)
SB820M_SATA-IDE_(3/5)
SB820M_SATA-IDE_(3/5)
ocument Nu mber Rev
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
22 95 Thu rsday, March 04, 2010
22 95 Thu rsday, March 04, 2010
22 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
+3.3V_RU N
1231-1
D D
+1.8V_RU N
1231-1
+3.3V_RU N
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
1119-1
9/15
+1.1V_RU N +1.1V_RUN _PCIE_VDDR
C C
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
+3.3V_RU N
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
1119-1
9/15
+1.1V_RU N +1.1V_RUN _AVDD_SATA
1 2
PBY160808 T-330Y-N-GP
PBY160808 T-330Y-N-GP
33R, 3A
B B
1119-1
+3.3V_AL W +3.3V_AVD D_USB
1 2
PBY160808 T-221Y-N-GP
PBY160808 T-221Y-N-GP
220R, 2A
+1.1V_AL W +1.1V_AVD D_USB
1 2
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
220R, 0.3A
R2301
R2301
1 2
0R0603-P AD
0R0603-P AD
R2302
R2302
1 2
0R0603-P AD
0R0603-P AD
L2301
L2301
1 2
220R, 0.3A
L2303
L2303
1 2
33R, 3A
L2304
L2304
1 2
220R, 0.3A
L2305
L2305
L2307
L2307
L2309
L2309
+3.3V_SB _VDDIO
+1.8V_SB _VDDIO_FC
9/17
+3.3V_VD DPL_PCIE
+3.3V_VD DPL_SATA
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
TC2301
TC2301
1 2
Removed
C2313
C2313
1 2
TC2303
TC2303
1 2
C2325
C2325
1 2
TC2304
TC2304
1 2
C2337
C2337
1 2
C2343
C2343
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
DY
DY
DY
DY
DY
DY
78mA
SCD1U10V2KX-5GP
DY
DY
C2320
C2320
C2331
C2331
C2339
C2339
C2302
C2302
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-5GP
DY
DY
0.15mA
C2307
C2307
1 2
DY
DY
11mA
690m
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2321
C2321
1 2
DY
DY
15mA
1350mA
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2332
C2332
1 2
534mA
C2340
C2340
1 2
88mA
C2303
C2303
1 2
AC21
AA19
AE25
AC22
AE28
A
C2322
C2322
1 2
AD14
AH20
AG19
AE18
AD18
AE16
C2333
C2333
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2301
C2301
1 2
C2314
C2314
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2319
C2319
1 2
1 2
DY
DY
C2326
C2326
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2330
C2330
1 2
1 2
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C2338
C2338
1 2
1 2
C2344
C2344
1 2
SSID = S.B
U2C
U2C
AH1
VDDIO_33_PCIGP
V6
VDDIO_33_PCIGP
Y19
VDDIO_33_PCIGP
AE5
VDDIO_33_PCIGP
VDDIO_33_PCIGP
AA2
VDDIO_33_PCIGP
AB4
VDDIO_33_PCIGP
AC8
VDDIO_33_PCIGP
AA7
VDDIO_33_PCIGP
AA9
VDDIO_33_PCIGP
AF7
VDDIO_33_PCIGP
VDDIO_33_PCIGP
AF22
VDDIO_18_FC
VDDIO_18_FC
AF24
VDDIO_18_FC
VDDIO_18_FC
POWER
POWER
VDDPL_33_PCIE
U26
VDDAN_11_PCIE
V22
VDDAN_11_PCIE
V26
VDDAN_11_PCIE
V27
VDDAN_11_PCIE
V28
VDDAN_11_PCIE
V29
VDDAN_11_PCIE
W22
VDDAN_11_PCIE
W26
VDDAN_11_PCIE
VDDPL_33_SATA
AJ20
VDDAN_11_SATA
AF18
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
A18
VDDAN_33_USB_S
A19
VDDAN_33_USB_S
A20
VDDAN_33_USB_S
B18
VDDAN_33_USB_S
B19
VDDAN_33_USB_S
B20
VDDAN_33_USB_S
C18
VDDAN_33_USB_S
C20
VDDAN_33_USB_S
D18
VDDAN_33_USB_S
D19
VDDAN_33_USB_S
D20
VDDAN_33_USB_S
E19
VDDAN_33_USB_S
C11
VDDAN_11_USB_S
D11
VDDAN_11_USB_S
SB820M-1 -GP
SB820M-1 -GP
Part 3 of 5
Part 3 of 5
PCI/GPIO I/O
PCI/GPIO I/O
FLASH I/O
FLASH I/O
GBE LAN
GBE LAN
PCI EXPRESS SERIAL ATA
PCI EXPRESS SERIAL ATA
USB I/O
USB I/O
PLL CLKGEN I/O
PLL CLKGEN I/O
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
CORE S0 3.3V_S5 I/O
CORE S0 3.3V_S5 I/O
VDDCR_11
VDDCR_11
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDRF_GBE_S
VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S
VDDIO_GBE_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDCR_11_S
VDDCR_11_S
VDDIO_AZ_S
CORE S5
CORE S5
VDDCR_11_USB_S
VDDCR_11_USB_S
VDDPL_33_SYS
VDDPL_11_SYS_S
VDDPL_33_USB_S
VDDAN_33_HWM_S
VDDXL_33_S
N13
R15
N17
U13
U17
V12
V18
W12
W18
K28
K29
J28
K26
J21
J20
K21
J22
V1
M10
GBE PHY not used
L7
L9
M6
P8
A21
D21
B21
K10
L10
J9
T6
T8
F26
G26
+3.3VALW _VDDIO_AZ
M8
A11
B11
3.3V_RUN _VDDPL
M21
1.1V_ALW _VDDPL
L22
F19
D6
3.3V_ALW _VDDXL
L20
790mA
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
382mA
49mA
113mA
58mA
C2304
C2304
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2315
C2315
1 2
15mA
1 2
R2303
R2303
1231-1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
0R0402-P AD
0R0402-P AD
U2E
U2E
Part 5 of 5
Y14
VSSIO_SATA
Y16
VSSIO_SATA
AB16
VSSIO_SATA
AC14
+1.1V_RU N
SC10U6D3V5KX-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
SC10U6D3V5KX-1GP
C2311
C2318
C2318
C2323
C2323
C2327
C2327
C2335
C2335
C2311
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
+3.3V_AL W
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
+1.1V_AL W
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
TC2302
TC2302
C2324
C2324
C2328
C2328
C2336
C2336
+1.1V_RU N +1.1V_RU N_SB_CLKGEN
1 2
R2304 0R0603-P AD R2 304 0R0603-PA D
1231-1
+1.1V_AL W +1.1V_AL W_VDDR_US B
L2306
L2306
1 2
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
220R, 0.3A
C2310
C2310
1 2
1 2
1 2
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2308
C2308
C2316
C2316
1 2
C2309
C2309
1 2
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
+3.3V_AL W
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
SC1U6D3V2KX-GP
C2317
C2317
C2329
C2329
C2334
C2334
1119-1
9/17
16mA
+3.3V_AV DD_USB
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2347
C2347
1 2
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
C2348
C2348
1 2
AE12
AE14
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ11
AJ13
AJ16
G11
M19
M22
M24
M26
AF9
AJ7
B10
K11
D10
D12
D14
D17
F12
F14
F16
F18
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
P21
P20
P22
P24
P26
T20
T22
T24
V20
J23
A9
B9
E9
F9
C9
D9
Y4
D8
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
EFUSE
VSSAN_HWM
VSSXL
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
SB820M-1 -GP
SB820M-1 -GP
Part 5 of 5
GROUND
GROUND
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSPL_SYS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
M20
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
A A
3.3V_ALW _VDDXL
9/15
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
DY
DY
C2341
C2341
1 2
5
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
1 2
1 2
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
C2342
C2342
220R, 0.3A
L2308
L2308
+3.3V_AL W
5mA
65mA 46mA
+1.1V_AL W +3.3V_RU N
L2312
1.1V_ALW _VDDPL 3.3V_RUN _VDDPL
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
L2312
1 2
C2349
C2349
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
1 2
4
1 2
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
C2350
C2350
BLM15AG 221SS1D-GP
BLM15AG 221SS1D-GP
1 2
L2313
L2313
220R, 0.3A 220R, 0.3A
12mA
10/1
Removed
3
+3.3V_AL W
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DY
DY
2
C2345
C2345
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
SB820M_POWER&GND_(4/5)
SB820M_POWER&GND_(4/5)
SB820M_POWER&GND_(4/5)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
23 95 Thu rsday, March 04, 2010
23 95 Thu rsday, March 04, 2010
23 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
SSID = S.B
4
3
2
1
REQUIRED STRAPS
D D
9/15
PCI_CLK1 (2 0)
PCI_CLK2 (2 0)
PCI_CLK3 (2 0)
9/23
C C
PCLK_KB C (20 ,37)
PCLK_FW H (20,70)
LPCCLK1 (20)
SB_GPO2 00 (21 )
SB_GPO1 99 (21 )
ACZ_SDA TAOUT_R (21)
+3.3V_RU N +3.3V_ ALW
R2404 10KR2J-3-GPDYR2404 10KR2J-3-GP
R2401 10KR2J-3-GPDYR2401 10KR2J-3-GP
R2403 10KR2J-3-GPDYR2403 10KR2J-3-GP
R2402 10KR2J-3-GPDYR2402 10KR2J-3-GP
R2416 10KR2J-3-GPDYR2416 10KR2J-3-GP
1 2
DY
1 2
R2417 10KR2J-3-GP R2417 10KR2J-3-GP
1 2
DY
1 2
R2418 10KR2J-3-GP R2418 10KR2J-3-GP
DY
DY
1 2
R2419 10KR2J-3-GPDYR2419 10KR2J-3-GP
1 2
1 2
DY
1 2
DY
DY
R2405 10KR2J-3-GPDYR2405 10KR2J-3-GP
1 2
R2420 10KR2J-3-GP R2420 10KR2J-3-GP
1 2
DY
9/15
R2408 2K2R2F-GP R2408 2K2R2F-GP
R2407 2K2R2F-GPDYR2407 2K2R2F-GP
R2406 10KR2J-3-GPDYR2406 10KR2J-3-GP
1 2
R2421 10KR2J-3-GP R2421 10KR2J-3-GP
1 2
DY
R2409 10KR2J-3-GPDYR2409 10KR2J-3-GP
1 2
1 2
1 2
DY
R2423 2K2R2F-GPDYR2423 2K2R2F-GP
R2422 2K2R2F-GP R2422 2K2R2F-GP
R2424 10KR2J-3-GP R2424 10KR2J-3-GP
1 2
1 2
1 2
DY
DEBUG STRAPS
PCI_AD23 (20)
PCI_AD25 (20)
PCI_AD26 (20)
PCI_AD27 (20)
1119-1 Removed
R2414 2K2R2J-2-GPDYR2414 2K2R2J-2-GP
R2413 2K2R2J-2-GPDYR2413 2K2R2J-2-GP
DY
R2412 2K2R2J-2-GPDYR2412 2K2R2J-2-GP
R2411 2K2R2J-2-GPDYR2411 2K2R2J-2-GP
1 2
DY
R2415 2K2R2J-2-GPDYR2415 2K2R2J-2-GP
12
12
12
DY
DY
1 2
DY
9/22
VDDR_SE L (20,51)
B B
REQUIRED SYSTEM STRAPS
PCLK_KBC PCLK_FWH
(PCI_CLK4) (PCI_CLK3)
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
non_Fusion
CLOCK mode
DEFAULT
Fusion
CLOCK mode
PULL
HIGH
PULL
LOW
AZ_SDOUT#
LOW POWER
MODE
PERFORMANCE
MODE
DEFAULT
PCI_CLK1
Allow
PCIE GEN2
DEFAULT
Force
PCIE GEN1
PCI_CLK2
WatchDOG
(NB_PWRGD)
ENABLED
WatchDog
(NB_PWRGD)
DISABLED
DEFAULT
USE this pin to determine INT/EXT CLK
LPCCLK0
ENABLE EC
DISABLE EC
DEFAULT
LPCCLK1
CLKGEN
ENABLED
(Use Internal)
DEFAULT
CLKGEN
DISABLED
(Use External)
SB_GPO200 , SB_GPO199
ROM TYPE:
H, H = Reserved
H, L = SPI ROM
L, H = LPC ROM
L, L = FWH ROM
DEFAULT
PULL
HIGH
PULL
LOW
USE PCI
PLL
BYPASS
PCI PLL
PCI_AD26 PCI_AD27
Disable ILA
AUTORUN
Enable ILA
AUTORUN
PCI_AD25 PCI_AD23
USE FC
PLL
BYPASS FC
PLL
PCI_AD24
USE DEFAULT
PCIE STRAPS
USE EEPROM
PCIE STRAPS
Disable PCI
MEM BOOT
(DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT)
Enable PCI
MEM BOOT
Note: SB820M has 15K internal PU FOR PCI_AD[27:23]
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
Date: Sheet of
Date: Sheet of
Date: Sheet of
SB820M_STRAPPING_(5/5)
SB820M_STRAPPING_(5/5)
SB820M_STRAPPING_(5/5)
ocument Nu mber Rev
A3
A3
A3
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
24 95 Friday, March 0 5, 2010
24 95 Friday, March 0 5, 2010
24 95 Friday, March 0 5, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Reserved
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
25 95 Thursday, March 04, 2010
25 95 Thursday, March 04, 2010
25 95 Thursday, March 04, 2010
1
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Reserved
Reserved
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Reserved
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
26 95 Thu rsday, March 04, 2010
26 95 Thu rsday, March 04, 2010
26 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
27 95 Thu rsday, March 04, 2010
27 95 Thu rsday, March 04, 2010
27 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
28 95 Thu rsday, March 04, 2010
28 95 Thu rsday, March 04, 2010
28 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
29 95 Thu rsday, March 04, 2010
29 95 Thu rsday, March 04, 2010
29 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
SSID = AUDIO
3.3V, 25mA
+3.3V_RUN
D D
9/23
+3.3V_RUN
1 2
R3008
R3008
10KR2J-3-GP
10KR2J-3-GP
C C
AMP_MUTE#
+3.3V_RUN
Close to codec
1 2
1 2
C3001
C3001
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SB_AZ_CODEC _BITCLK (21)
SB_SDIN_CODE C (21)
SB_AZ_CODEC _SDOUT (21)
SB_AZ_CODEC _SYNC (21)
SB_AZ_CODEC _RST# ( 21)
1 2
C3002
C3002
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
SC2D2U6D3V 3KX-GP
SC2D2U6D3V 3KX-GP
11/9
AMP_MUTE# (37)
C3004
C3004
TP3001 TP3001
TP3002 TP3002
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C3014
C3014
Close to codec
33R2J-2-GPR 3001 33R2J-2-GPR3001
1
1
1 2
AUD_DVDD CORE
1 2
C3003
C3003
SC10U6D3V5KX- 1GP
SC10U6D3V5KX- 1GP
SB_AZ_CODEC _BITCLK
SB_SDIN_CODE C_C0
SB_AZ_CODEC _SDOUT
SB_AZ_CODEC _SYNC
SB_AZ_CODEC _RST#
AUD_DMIC_CLK
AUD_DMIC_IN0
AMP_MUTE#
PUMP_CAPN
PUMP_CAPP
AUD_AGND
U3001
U3001
1
DVDD_CORE
9
DVDD
3
DVDD_IO
6
HDA_BITCLK
8
HDA_SDI
5
HDA_SDO
10
HDA_SYNC
11
HDA_RST#
2
DMIC_CLK/GPIO1
4
DMIC0/GPIO2
46
DMIC1/GPIO0/SPDIF_OUT_1
48
SPDIF_OUT_0
47
EAPD
35
CAP-
36
CAP+
7
DVSS
33
AVSS
30
AVSS
26
AVSS
42
PVSS
49
GND
92HD79B1A5NLG XTAX-GP
92HD79B1A5NLG XTAX-GP
AVDD
AVDD
PVDD
PVDD
SENSE_A
SENSE_B
HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F
HP1_PORT_B_L
HP1_PORT_B_R
PORT_C_L
PORT_C_R
VREFOUT_C
SPKR_PORT_D_L+
SPKR_PORT_D_L-
SPKR_PORT_D_R-
SPKR_PORT_D_R+
PORT_E_L
PORT_E_R
PORT_F_L
PORT_F_R
PC_BEEP
MONO_OUT
CAP2
VREFFILT
VREG
V-
27
38
39
45
13
14
28
29
23
31
32
AUD_INT_MIC_R_L
19
20
AUD_VREFO UT_C
24
40
41
43
44
15
16
17
18
12
25
22
21
34
37
AUD_SENSE_A
AUD_SENSE_B
AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFO UT_B
AUD_HP1_JAC K_L
AUD_HP1_JAC K_R
AUD_SPK_L+
AUD_SPK_L-
AUD_SPK_RAUD_SPK_R+
AUD_CAP2
AUD_VREFF LT
AUD_V_B
AUD_VREG
+AVDD
84mA
1 2
1 2
C3005
C3005
C 3006
C3006
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AUD_AGND
AUD_EXT_MIC_L (60)
AUD_EXT_MIC_R (60)
R3005 60D4R2F-G P R 3005 60D4R2F-GP
1 2
R3006 60D4R2F-G P R 3006 60D4R2F-GP
1 2
C3011 SC1U10V3KX-3GP C3011 SC1U10V3KX- 3GP
1 2
R3007 2K2R2J-2-GP R3007 2K2R2J-2-G P
1 2
AUD_SPK_L+ (60)
AUD_SPK_L- (60)
AUD_SPK_R- (60)
AUD_SPK_R+ (60)
AUD_PC_BEEP
AUD_PC_BEEP
Trac
e width>15 mils
1 2
1 2
C3016
C3016
C 3017
C3017
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AUD_AGND AUD _AGND AUD_AGND AUD _AGND
Close to codec
1231-1
R3002
R3002
1 2
0R0603-PAD
0R0603-PAD
1.4A
1 2
1129-2
1 2
C 3018
C3018
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C3008
C3008
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
+5V_RUN
1 2
C3015
C3015
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C 3009
C3009
SC1U10V3KX-3GP
SC1U10V3KX-3GP
AUD_AGND
1231-1
+PVDD
1 2
1 2
1 2
C 3010
C3010
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
AUD_VREFO UT_B (60)
AUD_HP1_JAC K_L2 (6 0)
AUD_HP1_JAC K_R2 (60)
INT_MIC_L_R (60 )
C3012
C3012
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
1 2
1 2
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
C3013
C3013
R3003
R3003
0R0603-PAD
0R0603-PAD
R3004
R3004
0R0603-PAD
0R0603-PAD
+5V_RUN
SB_SPKR_R
KBC_BEEP_R
9/17
R3009
R3009
120KR2F-L- GP
120KR2F-L-GP
1 2
1 2
R3010
R3010
499KR2F-1-GP
499KR2F-1-GP
From SB
From
Reserve
ACZ_SPKR (21)
KBC_BEEP (37)
EC
AUD_HP1_JAC K_R2
Q3002
Q3002
P8503BMG-GP
P8503BMG-GP
AUD_HP1_JAC K_L2
D S
DY
DY
G
D S
Q3003
Q3003
P8503BMG-GP
P8503BMG-GP
DY
DY
G
CODEC_Q2601 _03
G
+15V_ALW
DY
DY
DY
DY
P8503BMG-GP
P8503BMG-GP
1 2
R3013
R3013
100KR2J-1-GP
100KR2J-1-GP
HP_CODEC _MUTE
Q3001
Q3001
2N7002A-7-GP
2N7002A-7-GP
S D
B B
Azalia I/F EMI
SB_AZ_CODEC _SDOUT
1 2
R3015
R3015
47R2J-2-GP
47R2J-2-GP
DY
DY
SB_AZ_CODEC_SDOUT1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C3020
C3020
1 2
DY
DY
A A
5
AUD_SENSE_A
+AVDD
1 2
1 2
AUD_AGND
R3018
R3018
2K49R2F-GP
2K49R2F-GP
C3019
C3019
SC1000P50V3JN- GP-U
SC1000P50V3JN- GP-U
Close to Pin13
1 2
4
R3016
R3016
20KR2F-L-GP
20KR2F-L-GP
R3022
R3022
39K2R2F-L-GP
39K2R2F-L-GP
AUD_HP1_JD # (60)
1 2
EXT_MIC_JD# (60)
+AVDD
1 2
AUD_SENSE_B
1 2
AUD_AGND
Close to Pin14
R3019
R3019
2K49R2F-GP
2K49R2F-GP
R3021
R3021
20KR2F-L-GP
20KR2F-L-GP
3
1231-1
R3014
R3014
0R0603-PAD
0R0603-PAD
R3017
R3017
0R0603-PAD
0R0603-PAD
R3020
R3020
0R0603-PAD
0R0603-PAD
1 2
1 2
1 2
AUD_AGND
AMP_MUTE#
2
Q3004
Q3004
G
DY
DY
D S
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
ocument Numb er Rev
Size Document Num ber Rev
Size Document Num ber Rev
Size D
A2
A2
A2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Date: Sheet of
Date: Sheet of
Date: Sheet of
CODEC_Q2602 _04
G
DY
DY
P8503BMG-GP
P8503BMG-GP
Q3005
Q3005
D S
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Audio Codec 92HD79B1
Audio Codec 92HD79B1
Audio Codec 92HD79B1
30 95 Thursday, March 04, 2010
30 95 Thursday, March 04, 2010
1
30 95 Thursday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
31 95 Thu rsday, March 04, 2010
31 95 Thu rsday, March 04, 2010
31 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Reserved
Reserved
Reserved
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
32 95 Thursday, March 04, 2010
32 95 Thursday, March 04, 2010
32 95 Thursday, March 04, 2010
1
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
33 95 Thu rsday, March 04, 2010
33 95 Thu rsday, March 04, 2010
33 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
34 95 Thu rsday, March 04, 2010
34 95 Thu rsday, March 04, 2010
34 95 Thu rsday, March 04, 2010
A00
A00
A00
A
4 4
3 3
B
C
D
E
(Blanking)
2 2
1 1
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
E
35 95 Thu rsday, March 04, 2010
35 95 Thu rsday, March 04, 2010
35 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
36 95 Thu rsday, March 04, 2010
36 95 Thu rsday, March 04, 2010
36 95 Thu rsday, March 04, 2010
A00
A00
A00
5
+KBC_PWR +KBC_PWR
Reserved
D D
+KBC_PWR
PD for Berry Keyboard Matrix
PU for DJ Keyboard Matrix
+KBC_PWR
PU for Discrete
Internal PL for UMA
PM_SLP_S5#
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C3717
C3717
1 2
0108-5
C C
9/16
R3701
R3701
1 2
0R3J-0-U-G P
0R3J-0-U-G P
L3701 B LM18AG601SN-3GP L3701 B LM18AG601SN-3GP
1 2
C3701
C3701
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
+KBC_PWR
THERMTRIP_VG A# (82)
CPU_PROC HOT#_EC (10)
AMBER_LED#_KBC (6 6)
1.0V_RUN_VGA _EN (90)
1 2
H_THERMT RIP# ( 10,21,39,42,82)
PM_SLP_S3# (21,41,42,49,52,89)
LID_CLOSE# (69)
1.5V_RUN_EN (42,49)
PWR_BTN _LED# (66)
KB_LED_BL_DET (68)
KBC_RSMRST # (21)
PM_SLP_S5# (21,49 )
EC_RESET_OU T (39,41)
EC_SPI_WP#_R (62)
IMVP_VR_ON (47)
PSID_DISABLE# (76)
GFX_CORE_E N (89)
USB_PWR _EN# (63)
1 2
C3704
C3704
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
10KR2J-3-GP
10KR2J-3-GP
PSID_EC (76)
C3718 SCD1U 10V2KX-5GP C 3718 SCD1U10V2KX -5GP
8103_GPO ( 76)
1216-2
PWRLED # (66)
3V_5V_POK (46,50)
BLON_OUT (54)
1 2
0108-5
DY
DY
C3705
C3705
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R3707
R3707
1 2
1 2
1 2
1 2
C3706
C3706
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
R3751 0R 2J-2-GP
R3751 0R 2J-2-GP
R3712
R3712
1 2
2K2R2J-2-GP
2K2R2J-2-GP
R3715 2K2R2J-2- GP
R3715 2K2R2J-2- GP
R3747 0R0402-PAD R3747 0R040 2-PAD
0105-4
C3707
C3707
11/6
DY
DY
DY
DY
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
S0_LKG_DET
10KR2J-3-GP
10KR2J-3-GP
DIS
DIS
+3.3V_RTC_LD O
C3708
C3708
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
KBC_AGND
R3705
R3705
1 2
1 2
1 2
1 2
CAP close to VCC-GND pin pair
1119-1
1 2
C3709
C3709
AD_IA_KBC
DISCRETE_ID
KBC_THERM TRIP#
1229-1
KB_DET_KBC
PCB_VER2
KBC_PWRBTN_EC#
AC_IN#_KBC
PCB_VER0
KBC_BIOS_ID
PCB_VER1
PWR_BTN _LED#
KBC_PLTRST _DELAY#
SYS_PWRGD
EC_SHUTD OWN#
VBAT
3.3V, 23mA
1 2
C3710
C3710
U3701A
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
U3701A
104
VREF
97
GPI90/AD0
98
GPI91/AD1
99
GPI92/AD2
100
GPI93/AD3
108
GPIO05
96
GPIO04
101
GPI94
105
GPI95
106
GPI96
107
GPI97
64
GPIO01/TB2
95
GPIO03
93
GPIO06
94
GPIO07
119
GPIO23
6
GPIO24
109
GPIO30
120
GPIO31
65
GPIO32/D_PWM
66
GPIO33/H_PWM
16
GPIO40/F_PWM
17
GPIO42/TCK
20
GPIO43/TMS
21
GPIO44/TDI
22
GPIO45/E_PWM
23
GPIO46/TRST#
24
GPIO47
25
GPIO50/TDO
26
GPIO51
27
GPIO52/RDY#
28
GPIO53
73
GPIO70
74
GPIO71
75
GPIO72
110
GPO82/TRIS#
NPCE781BA0DX -GP
NPCE781BA0DX -GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
9/14
Remove reserved crystal.
B B
+3.3V_RUN
R3731
10KR2J-3-GPDYR3731
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
1 2
1 2
R3730
DY
DY
1 2
1 2
DY
DY
E51_TxD
R3741
R3741
4K7R2J-2-GP
4K7R2J-2-GP
R3730
1 2
R3734
R3734
DY
DY
DY
1 2
R3735
R3735
10KR2J-3-GP
10KR2J-3-GP
1 2
MB VERSION
ID
X00
X01
10KR2J-3-GP
10KR2J-3-GP
X02
A00
KBC CLK
EMI
10/7
VER2
0 0
0
0
0
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C3715
C3715
1 2
PCLK_KBC
VER1
0
1
1
1117-5
VER0
0
1
0
1
0112-1
1118-2
AD_IA (45)
PSID_EC
1 2
C3719
C3719
SC56P50V2JN-2G P
SC56P50V2JN-2G P
5
R3729
R3729
10KR2J-3-GP
10KR2J-3-GP
PCB_VER0
PCB_VER1
PCB_VER2
R3733
R3733
10KR2J-3-GP
10KR2J-3-GP
A A
4
88
115
VCC19VCC46VCC76VCC
VCC
A/D
A/D
D/A
D/A
GPIO
GPIO
116
AD_IA_KBC
1 2
R3757
R3757
0R0402-PAD
0R0402-PAD
C3724
C3724
SC10P50V2JN-4G P
SC10P50V2JN-4G P
0108-4
+PWR_SR C +3.3V_RUN
4
102
4
80
VDD
AVCC
GPIO41
GPIO10/LPCPD#
LPC
LPC
GPIO11/CLKRUN#
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#
GPIO74/SDA2
SMB
SMB
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1
SP
SP
GPIO66/G_PWM
SPI
SPI
GPIO76/SHBM
GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
SER/IR
SER/IR
GND5GND18GND45GND78GND89GND
AGND
103
KBC_AGND
KBC_AGND
R3732
R3732
1 2
0R2J-2-GP
0R2J-2-GP
DY
DY
1 2
C3721
C3721
1 2
DY
DY
SC56P50V2JN-2G P
SC56P50V2JN-2G P
C3722
C3722
1 2
DY
DY
SC56P50V2JN-2G P
SC56P50V2JN-2G P
3.3V, 2mA
1 OF 2
1 OF 2
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
KBRST#
GA20
GPIO77
GPIO75
GPIO81
GPIO16
GPIO34
GPIO36
VCORF
124
7
2
3
126
127
128
1
125
8
122
121
29
9
123
68
67
69
70
81
84
83
82
91
111
113
112
114
14
15
44
+3.3V_RUN
1 2
KBC_VCORF
C3702
C3702
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PLTRST#_EC
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
ECSCI#_KBC
ECSWI#_KBC
KBC_SDA1
KBC_SCL1
ECSMI#_KBC
NB_VDDC_E N
E51_TxD
E51_RxD
1 2
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1 2
C3703
C3703
SC2D2U10V3KX- 1GP
SC2D2U10V3KX- 1GP
R3714 10KR 2J-3-GP R 3714 10KR2J-3- GP
1
C3711
C3711
BAT_IN# (44)
1 2
TP3714 TP3714
3
WWAN _RADIO_DIS# (76)
PCLK_KBC (20,24)
LPC_LFRAME# (20,70)
LPC_LAD0 (20,70)
LPC_LAD1 (20,70)
LPC_LAD2 (20,70)
LPC_LAD3 (20,70)
INT_SERIRQ (20)
PM_CLKRUN # (20)
SIO_RCIN# ( 21)
SIO_A20GATE (21)
PANEL_BKEN (55)
BAT_SDA (44,45 )
BAT_SCL (44,45)
1.8V_VGA_RUN _EN ( 52,90)
BLUETOOTH _EN (73)
WIFI_RF_EN (76)
E51_TxD (76)
E51_RxD (76)
3.3V_RUN_VGA _EN (9 0)
PM_LAN_ENABLE ( 76)
VDDC_PW RGD (41,48)
S5_ENABLE (42)
PURE_HW _SHUTDOW N# (39,4 2)
3
1120-5
9/24
THERM_SDA (39)
DY
DY
1 2
C3725 SCD1U 10V2KX-5GP
C3725 SCD1U 10V2KX-5GP
0113-1
PLTRST#_NB_G PU (13,20,80)
IMVP_PWRGD (41,47,48,51)
WHITE_LED #_KBC (66)
LCD_CBL_DE T# (54)
THERMTRIP_VG A_GATE (82)
1 2
C3723 SCD1U 10V2KX-5GP C 3723 SCD1U10V2KX -5GP
SIO_EXT_WAKE # (21)
RTCCLK_KBC ( 20)
AMP_MUTE# (30)
PM_PWRBT N# (21)
LCD_TST_EN (54)
KBC_BEEP (30)
KB_BL_CTRL (68)
KB_DET# (68)
LCD_TST (54)
TPDATA (68)
EC_SPI_DI (62)
EC_SPI_DO (62)
EC_SPI_CS# (62)
EC_SPI_CLK (62)
1217-1
U3703
U3703
1
GND
2
RESET#
G690L293T73UF-G P
G690L293T73UF-G P
0108-5
KBC_SCL1
SIO_EXT_SCI# (21)
SIO_EXT_SMI# (21)
1119-1
PLTRST#_EC
TPCLK (68)
1 2
DY
DY
C3716 SC10P50V 2JN-4GP
C3716 SC10P50V 2JN-4GP
10/7
0208-2
EC_SPI_DI
EC_SPI_DO
EC_SPI_CS#
EC_SPI_CLK
+KBC_PWR
3
VCC
DY
DY
SSID = KBC
1 2
DY
DY
R3702 0R2J-2-G P
R3702 0R2J-2-G P
U3702
U3702
23 45
1
6
DMN66D0LDW -7-GP
DMN66D0LDW -7-GP
R3708
R3708
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
D3701
D3701
1
2
BAS16PT-GP
BAS16PT-GP
D3704
D3704
1
2
BAS16PT-GP
BAS16PT-GP
D3705
D3705
1
2
BAS16PT-GP
BAS16PT-GP
0R2J-2-GP
0R2J-2-GP
R3739
R3739
1 2
DY
DY
9/24
C3713
C3713
SC470P50V3JN-2 GP
SC470P50V3JN-2 GP
1 2
DY
DY
1 2
R3737 33R2J-2-G P R3737 3 3R2J-2-GP
1117-5
R3743
R3743
1 2
4K7R2J-2-GP
4K7R2J-2-GP
1231-1
1 2
R3744 0R0 402-PAD R3744 0R0402-PAD
+3.3V_RUN
KBC_SDA1
ECSWI#_KBC
3
ECSCI#_KBC
3
ECSMI#_KBC
3
KBC_PLTRST _DELAY#
TP3713 TP3713
THERMTRIP_VG A_GATE
ECRST#_C
Q3701
Q3701
PMBS3906-GP
PMBS3906-GP
2
THERM_SCL (39)
PLTRST#_EC (20)
GPIO02
1
EC_SPI_CLK_C
1
2
2
3
ECRST#
117
118
DY
DY
U3701B
U3701B
77
32KX1/32KCLKIN
79
32KX2
30
GPIO55/CLKOUT
63
GPIO14/TB1
GPIO20/TA2
31
GPIO56/TA1
32
GPIO15/A_PWM
GPIO21/B_PWM
62
GPIO13/C_PWM
13
GPIO12/PSDAT3
12
GPIO25/PSCLK3
11
GPIO27/PSDAT2
10
GPIO26/PSCLK2
71
GPIO35/PSDAT1
72
GPIO37/PSCLK1
86
F_SDI
87
F_SDO
90
F_CS0#
92
F_SCK
NPCE781BA0DX -GP
NPCE781BA0DX -GP
1 2
C3714
C3714
SC1U10V3KX-3G P
SC1U10V3KX-3G P
KBC_PWR BTN# ( 66)
+3.3V_RTC_LD O
+KBC_PWR
KBC_SCL1
KBC_SDA1
BAT_SDA
BAT_SCL
AC_IN#_KBC
LCD_CBL_DE T#
KB_DET#
E51_RxD
SIO_A20GATE
SIO_RCIN#
VDDC_PW RGD
EC_RESET_OU T
S0_LKG_DET
KBC_PWR BTN#
PS/2
PS/2
FIU
FIU
Internal PU
R3709
R3709
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
3
D3702
D3702
BAT54C-U-G P
BAT54C-U-G P
Q3703
Q3703
SI2301CDS-T1-G E3-GP
SI2301CDS-T1-G E3-GP
KBC_ON_R#
G
C3720
D S
9/15
C3720
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
1 2
Close to Q3703
1231-1
8
7
6
1 2
R3749 100KR2J-1-GP R3749 100KR2J- 1-GP
2 3
1
1231-1
1 2
R3710 10KR2J-3-GP
R3710 10KR2J-3-GP
1 2
R3711 10KR2J-3-GP
R3711 10KR2J-3-GP
1 2
R3713 10KR2J-3-GP
R3713 10KR2J-3-GP
1 2
10KR2J-3-GP
10KR2J-3-GP
R3753
R3753
1 2
R3752 100KR2J-1-GP R3752 100KR2J- 1-GP
1 2
R3754 100KR2J-1-GP R3754 100KR2J- 1-GP
1 2
R3716 100KR2J-1-GP
R3716 100KR2J-1-GP
KBC
KBC
KBSOUT15/GPIO61/XOR_OUT
RN3704
RN3704
1
2
3
4 5
SRN4K7J-10- GP
SRN4K7J-10- GP
RN3702
RN3702
4
SRN100KJ-6- GP
SRN100KJ-6- GP
DY
DY
DY
DY
DY
DY
DY
DY
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
GPIO60/KBSOUT16
GPIO57/KBSOUT17
VCC_POR#
9/11
11/10
2 OF 2
2 OF 2
KBSOUT7
KBSOUT8
KBSOUT9
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
+KBC_PWR
R3704
R3704
10KR2J-3-GP
10KR2J-3-GP
KBC_ON#
1205-1
1
Q3705
Q3705
2N7002A-7-GP
2N7002A-7-GP
D3703
D3703
BAT54C-U-G P
BAT54C-U-G P
S5_ENABLE
KCOL0
BLUETOOTH _EN
IMVP_VR_ON
+KBC_PWR
G
EC_SHUTD OWN#
S D
1 2
R3750
R3750
0R2J-2-GP
0R2J-2-GP
3
DY
DY
AC_IN#_KBC
1 2
1 2
R3723 10KR2J-3-G P R3723 10KR2J- 3-GP
1 2
DY
DY
R3724 10KR2J-3-G P
R3724 10KR2J-3-G P
1 2
R3726 10KR2J-3-G P R3726 10KR2J- 3-GP
1 2
R3727 10KR2J-3-G P R3727 10KR2J- 3-GP
1 2
R3703
R3703
100KR2J-1-GP
100KR2J-1-GP
KBC_PWR BTN_EC#
+3.3V_RTC_LD O
1 2
R3756
R3756
1 2
10KR2J-3-GP
10KR2J-3-GP
+3.3V_RUN
1 2
1119-1
+3.3V_RTC_LD O
KCOL0
53
KCOL1
52
KCOL2
51
KCOL3
50
KCOL4
49
KCOL5
48
KCOL6
47
KCOL7
43
KCOL8
42
KCOL9
41
KCOL10
40
KCOL11
39
KCOL12
38
KCOL13
37
KCOL14
36
KCOL15
35
KCOL16
34
KCOL17
33
KROW0
54
KROW1
55
KROW2
56
KROW3
57
KROW4
58
KROW5
59
KROW6
60
KROW7
61
ECRST#
85
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
KBC Nuvoton NPCE781BA0DX
KBC Nuvoton NPCE781BA0DX
KBC Nuvoton NPCE781BA0DX
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
KCOL[0..16] (68)
TP3705 TP3705
1
KROW[0..7] (68)
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
37 95 Friday, March 05, 2010
37 95 Friday, March 05, 2010
37 95 Friday, March 05, 2010
1
AC_IN# (45)
A00
A00
A00
5
D D
4
3
2
1
(Blanking)
C C
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
38 95 Thursday, March 04, 2010
38 95 Thursday, March 04, 2010
38 95 Thursday, March 04, 2010
1
A00
A00
A00
5
SSID = Thermal
SC10U10 V5KX-2GP
SC10U10 V5KX-2GP
D D
+3.3V_RU N
1.For CPU Sensor Pleace near to CPU side
Layout notice :
Both H_THERMDA and THERMDC routing
H_THERM DC (10 )
SC470P5 0V3JN-2GP
SC470P5 0V3JN-2GP
H_THERM DA (10)
C C
VGA_THE RMDC (82)
C3910
C3910
DY
DY
0107-5
1 2
Removed
VGA_THE RMDA (8 2)
2
UMA
UMA
Q3904
Q3904
PMBS390 4-1-GP
PMBS390 4-1-GP
Q3901
Q3901
PMBS390 4-1-GP
PMBS390 4-1-GP
B B
3
2
3
3.HW T8 sensor
Layout notice :
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.
1
1
VGA_THE RMDC
0107-3
VGA_THE RMDA
C3906
C3906
SC470P5 0V3JN-2GP
SC470P5 0V3JN-2GP
DY
DY
10 mil trace width and 10 mil spacing
1 2
C3904
C3904
SC470P5 0V3JN-2GP
SC470P5 0V3JN-2GP
C3905
C3905
1 2
SC470P5 0V3JN-2GP
SC470P5 0V3JN-2GP
2.VGA Sensor
Layout notice :
Both VGA_THERMDA and VGA_THERMDC routing
10 mil trace width and 10 mil spacing.
C3907
C3907
SC470P5 0V3JN-2GP
SC470P5 0V3JN-2GP
1 2
4
+5V_RUN
5V, 600mA
1 2
12
C3902
C3901
C3901
R3902
R3902
49D9R2F -GP
49D9R2F -GP
1 2
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
GND = Fan is OFF
OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale
C3902
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
3.3V, 0.75mA
EMC2102 _VDD_3D3
C3903
C3903
1 2
EMC2102 _DN3
EMC2102 _DP3
GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled
+3.3V_RU N
R3905
R3905
1 2
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R3907
R3907
1 2
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
R3910
R3910
0R0402-P AD
0R0402-P AD
1 2
U3901
U3901
1
2
3
4
5
6
7
VDD_3V
DN1
DP1
DN2
DP2
DN3
DP3
+3.3V_RU N
1 2
R3901
R3901
10KR2J-3 -GP
10KR2J-3 -GP
29
EMC2102 _SHDN
EMC2102 _FAN_mode
28
GND
8
EMC2102 _FAN_TACH_1
EMC2102 _FAN_DRIVE
27
26
TACH
NC#8
FANb25FANa
VDD_5Va
EMC2102
EMC2102
SHDN_SEL9FAN_MODE10TRIP_SET11SYS_SHDN#12THERMTRIP#13POWER_OK#
3
24
23
SMCLK
VDD_5Vb
+3.3V_RU N
THERM_SYS_SHDN#
S D
R3915
R3915
1 2
0R2J-2-GP
0R2J-2-GP
D3901
D3901
2 1
CH751H-4 0PT-GP
CH751H-4 0PT-GP
RN3901
RN3901
4
SRN4K7J -8-GP
SRN4K7J -8-GP
22
SMDATA
NC#21
GND
ALERT#
CLK_IN
CLK_SEL
RESET#
NC#15
EMC2102 -DZK-GP
EMC2102 -DZK-GP
14
THERM_P OWER_OK#
THERMTR IP#
1 2
R3908
R3908
10KR2J-3 -GP
10KR2J-3 -GP
THERMAL _P_HW_SHT
G
Q3902
Q3902
2N7002A -7-GP
2N7002A -7-GP
DY
DY
2 3
+3.3V_RU N
1
THERM_S CL (37 )
THERM_S DA (37)
21
20
ALERT#
19
CLK_32K
18
17
EM2102_ RESET#
16
15
1119-1
+KBC_PW R
+5V_RUN
10KR2J-3-GP
10KR2J-3-GP
1 2
R3916
R3916
DY
DY
9/25
R3903 0R2J-2-GP
R3903 0R2J-2-GP
0105-4 Remove
R3914 0R2J-2-GP
R3914 0R2J-2-GP
+3.3V_RU N
R3909
R3909
10KR2J-3 -GP
10KR2J-3 -GP
1 2
2
EMC2102 _FAN_TACH (58)
EMC2102 _FAN_DRIVE (58)
+3.3V_RU N
1 2
DY
DY
1 2
DY
DY
1
2 3
RN3902
RN3902
SRN10KJ -5-GP
SRN10KJ -5-GP
4
R3906 0R2J-2-GP
R3906 0R2J-2-GP
1 2
DY
DY
PURE_HW _SHUTDOW N# (37,42)
1
TALERT# (10,21)
GND = Internal Oscillator Selected
+3.3V = External 32.768kHz Clock Selected
EC_RESE T_OUT (37,41)
0226-1
H_THERM TRIP# (10 ,21,37,42,82)
+3.3V_RU N
1 2
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
V_DEGRE E
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
C3908
C3908
C3909
C3909
1 2
1 2
R3911
R3911
10KR2F-2 -GP
10KR2F-2 -GP
TRIP_SET Pin Voltage
V_DEGREE=(((Degree-75)/21)
T8 shutdown is 88 deg-C.
1 2
R3912
R3912
2K37R2F -GP
2K37R2F -GP
32K suspend clock output
Q3903
Q3903
2N7002A -7-GP
2N7002A -7-GP
A A
RTC_CLK (20)
RUN_ENA BLE (42)
5
S D
G
4
R3913
R3913
1 2
10R2J-2-G P
10R2J-2-G P
CLK_32K CLK_32K _R
CLK_32K
1 2
C3911
C3911
DY
DY
SC4D7P5 0V2CN-1GP
SC4D7P5 0V2CN-1GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Thermal/Fan Controllor EMC2102
Thermal/Fan Controllor EMC2102
Thermal/Fan Controllor EMC2102
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
39 95 Thu rsday, March 04, 2010
39 95 Thu rsday, March 04, 2010
39 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
40 95 Thu rsday, March 04, 2010
40 95 Thu rsday, March 04, 2010
40 95 Thu rsday, March 04, 2010
A00
A00
A00
5
SSID = Reset.Suspend
4
3
2
1
2 1
+3.3V_RUN
100KR2J-1-GP
100KR2J-1-GP
1 2
DY
DY
R4102
R4102
SB_PWRGD_D
+1.8V_RUN +1.8V_RUN
300R2J-4-GP
300R2J-4-GP
1 2
R4103
R4103
U4101
U4101
1
NC#1
2
A
3
GND
DY
DY
SNAUC1G17DCKR-1GP
SNAUC1G17DCKR-1GP
NB_PWRGD (21)
5
VCC
4
Y
R4104
R4104
1 2
0R0402-PAD
0R0402-PAD
NB_PWRGD_IN (13)
0105-4
D D
+3.3V_RUN
10KR2J-3-GP
10KR2J-3-GP
1 2
R4101
9/28
D4103
D4103
VDDC_PWRGD (37,48)
PM_SLP_S3# (21,37,42,49,52,89)
C C
C4101 SCD1U10V2KX-5GP C4101 SCD1U10V2KX-5GP
C4102 SCD1U10V2KX-5GP C4102 SCD1U10V2KX-5GP
1 2
1 2
EC_RESET_OUT (37,39)
IMVP_PWRGD (37,47,48,51)
VDDC_PWRGD
IMVP_PWRGD
1
2
D4102
D4102
1
2
3
BAT54APT-GP
BAT54APT-GP
3
BAT54APT-GP
BAT54APT-GP
R4101
1
2
3
SB_PWRGD_R
U4102
U4102
NC#1
A
DY
DY
GND
SNAUC1G17DCKR-1GP
SNAUC1G17DCKR-1GP
1 2
+3.3V_ALW
5
VCC
4
Y
R4106
R4106
0R0402-PAD
0R0402-PAD
D4101
D4101
DY
DY
C H751H-40PT-GP
CH751H-40PT-GP
SB_PWRGD (7,21)
1116-5
R4105
R4105
B B
VDDC_PWRGD (37,48)
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
EC_RESET_OUT (37,39)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Power On Logic
Power On Logic
Power On Logic
cument Number Rev
A4
A4
A4
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Do
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
41 95 Thursday, March 04, 2010
41 95 Thursday, March 04, 2010
41 95 Thursday, March 04, 2010
1
5
4
3
2
1
SSID = Reset.Suspend
R4201
R4201
R4203
R4203
200KR2J-L1-GP
200KR2J-L1-GP
1 2
+3.3V_RU N
1 2
1 2
DY
DY
1KR2J-1-G P
1KR2J-1-G P
C4202
C4202
SC10U10 V5KX-2GP
SC10U10 V5KX-2GP
C4204
C4204
SC10U6D 3V5KX-1GP
SC10U6D 3V5KX-1GP
CPU_LDT _PWRGD (10,20)
D D
3V_5V_E N (46)
1 2
12
C4217
SCD047U 10V2KX-2GP
SCD047U 10V2KX-2GP
C4217
DY
DY
0222-2
Run Power
+3.3V_RT C_LDO
100KR2J -1-GP
100KR2J -1-GP
R4204
R4204
RUN_ON_ 5V#
C C
B B
1 2
PM_SLP_ S3# (21,37,41,4 9,52,89)
RUN_ENA BLE (39)
6
123 4
S
S
5
GG DD
U4207
U4207
DMN66D0 LDW-7-GP
DMN66D0 LDW-7-GP
RUN_ENA BLE
+15V_AL W
1 2
R4205
R4205
100KR2J -1-GP
100KR2J -1-GP
1 2
10KR2J-3 -GP
10KR2J-3 -GP
1 2
10KR2J-3 -GP
10KR2J-3 -GP
R4206
R4206
R4207
R4207
+5V_ALW +5V_RUN
5V_RUN_ ENABLE
1 2
C4201
C4201
SC6800P 25V2KX-1GP
SC6800P 25V2KX-1GP
+3.3V_AL W
3.3V_RUN _ENABLE
1 2
C4203
C4203
SCD01U5 0V2KX-1GP
SCD01U5 0V2KX-1GP
U4201
U4201
D
D
8
D
D
7
D
D
6
U4202
U4202
D
D
8
D
D
7
D
D
6
AO4468-G P
AO4468-G P
AO4468-G P
AO4468-G P
S
S
1
S
S
2
S
S
3
G D
G D
4 5
S
S
1
S
S
2
S
S
3
G D
G D
4 5
H_PW RGD_R
2
D4201
D4201
3
1
BAS16PT -GP
BAS16PT -GP
0226-1
1 2
R4202 1KR2J-1-G P R4202 1KR2J-1-GP
SCD1U10V2KX-5GPDYC4216
SCD1U10V2KX-5GP
1 2
DY
B
C4216
DY
DY
E
Q4201
Q4201
C
CHT2222 APT-GP
CHT2222 APT-GP
H_THERM TRIP# (10 ,21,37,39,82)
PURE_HW _SHUTDOW N# (37,39)
S5_ENAB LE (37 )
1117-2
Remove
+1.5V_RU N
1 2
DY
DY
R4226
R4226
10R3J-3-G P
10R3J-3-G P
+3.3V_RT C_LDO
100KR2J -1-GP
100KR2J -1-GP
R4211
R4211
RUN_ON_ 1.5V# RUN_ON_ 1.5V#
1 2
S
5
6
U4209
U4209
DMN66D0 LDW-7-GP
DMN66D0 LDW-7-GP
123 4
GG DD
S
A A
1.5V_RUN _EN (37,49 )
5
1.5V_RUN _ENABLE_R
+15V_AL W
1 2
R4212
R4212
100KR2J -1-GP
100KR2J -1-GP
1 2
R4213
R4213
0R0402-P AD
0R0402-P AD
1.5V_RUN _ENABLE
1 2
C4207
C4207
SCD01U5 0V2KX-1GP
SCD01U5 0V2KX-1GP
4
U4204
U4204
D
D
8
D
D
7
D
D
6
AO4468-G P
AO4468-G P
+1.5V_RU N +1.5 V_SUS
S
S
1
S
S
2
S
S
3
G D
G D
4 5
1 2
C4208
C4208
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3
2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Power Plane Enable
Power Plane Enable
Size D
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Power Plane Enable
ocument Nu mber Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
G
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
DY
DY
42 95 Thu rsday, March 04, 2010
42 95 Thu rsday, March 04, 2010
42 95 Thu rsday, March 04, 2010
S D
Q4207
Q4207
2N7002A -7-GP
2N7002A -7-GP
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
43 95 Thu rsday, March 04, 2010
43 95 Thu rsday, March 04, 2010
43 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
SSID = BATT CONN
+VCHGR
PG4401
PG4401
D D
BATT_SENSE (45)
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
BAT_SCL (37,45)
BAT_SDA (37,45)
BAT_IN# (37)
+KBC_PWR
1 2
470KR2J-2-GP
470KR2J-2-GP
PR4401
PR4401
SCD1U50V3KX-GP
SCD1U50V3KX-GP
4
1 2
PC4402
PC4402
PRN4401
PRN4401
SRN100J-3-GP
SRN100J-3-GP
1
2 3
0222-2
C C
1 2
1 2
PC4401
PC4401
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
PBAT_SMBCLK1
PBAT_SMBDAT1
100R2J-2-GP
1 2
SC47P50V2JN-3GP
SC47P50V2JN-3GP
C4402
C4402
DY
DY
SC47P50V2JN-3GP
SC47P50V2JN-3GP
C4401
1 2
DY
DY
C4401
1 2
100R2J-2-GP
PR4402
PR4402
AFTP4401 AFTP4401
PBAT_PRES1#
BAT_ALERT
1
For actual location, need to be swap all pin
Batt Connecter
10/7
BATT1
BATT1
10
1
2
3
4
5
6
7
8
9
11
ALP-CON9-2-GP-U
ALP-CON9-2-GP-U
20.81316.009
Close to Batt Connector
BAT_IN#
BAT_SDA
BAT_SCL
AFTP4402 AFTP4402
AFTP4403 AFTP4403
5
AFTP4404 AFTP4404
AFTP4405 AFTP4405
B B
A A
PBAT_PRES1#
1
PBAT_SMBDAT1
1
PBAT_SMBCLK1
1
+VCHGR
1
4
3
PD4402
PD4402
BAV99-4-GP
BAV99-4-GP
1
2
3
PD4403
PD4403
BAV99-4-GP
BAV99-4-GP
1
2
3
3
PD4401
PD4401
BAV99-4-GP
BAV99-4-GP
1
2
+KBC_PWR
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
BATT CONN
BATT CONN
Size Document Number Rev
Size Document Number Rev
Size Do
Date: Sheet of
Date: Sheet of
Date: Sheet of
cument Number Rev
A4
A4
A4
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
BATT CONN
44 95 Thursday, March 04, 2010
44 95 Thursday, March 04, 2010
44 95 Thursday, March 04, 2010
A00
A00
A00
1
5
4
3
2
1
SSID = Charger
1 2
DY
DY
PR4507
PR4507
0R2J-2-GP
0R2J-2-GP
PC4505
PC4505
1 2
PR4517
PR4517
1 2
0R0603-PAD
0R0603-PAD
1 2
0R0603-PAD
0R0603-PAD
0R0402-PAD
0R0402-PAD
1 2
1 2
PR4510
PR4510
PR4518
PR4518
PR4528
PR4528
PC4532
PC4532
0R2J-2-GP
0R2J-2-GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
+PWR_SR C
1 2
PG4503
PG4503
GAP-CLOSE-P WR-3-GP
GAP-CLOSE-P WR-3-GP
PR4524_03
1 2
PC4504
PC4504
1 2
DY
DY
CHG_AGND
BQ24745_BST1
PC4514
PC4514
SC220P50V2JN-3 GP
SC220P50V2JN-3 GP
1 2
1 2
DY
DY
CHG_AGND
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PR4513
PR4513
PD4501
PD4501
K A
SD103AWS-1-GP
SD103AWS-1-GP
1 2
PC4512
PC4512
SCD1U50V3KX- GP
SCD1U50V3KX- GP
1 2
DY
DY
1 2
PC4520
PC4520
SCD1U50V3KX-GP
SCD1U50V3KX-GP
CHG_AGND
PC4523
PC4523
BATT_SENSE (4 4)
PR4530
PR4530
1K8R6J-GP
1K8R6J-GP
1 2
DY
DY
33R3J-2-GP
33R3J-2-GP
PC4511
PC4511
SCD1U50V3KX- GP
SCD1U50V3KX- GP
1 2
SCD1U50 V3KX-GP
SCD1U50V3KX-GP
1 2
DY
DY
CHG_A GND
1 2
DY
DY
1 2
1 2
PG4506
PG4506
PG4501
PG4501
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PC4506
PC4506
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
65MOS
65MOS
1 2
PC4513
PC4513
SC3300P50V3KX-1G P
SC3300P50V3KX-1G P
65MOS
65MOS
PR4523
PR4523
1 2
0R0402-PAD
0R0402-PAD
PG4504
PG4504
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
678
DDD
DDD
G D
G D
4 5
BQ24745_LX1
678
DDD
DDD
G D
G D
4 5
1 2
SSS
SSS
123
SSS
SSS
123
1 2
PG4505
PG4505
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
CHAGER_SR C
PU4504
PU4504
SI4800BDY-T1-GP
SI4800BDY-T1-GP
PU4505
PU4505
SI4800BDY-T1-GP
SI4800BDY-T1-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
CHAGER_SR C
1 2
1 2
PC4507
PC4507
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PL4501
PL4501
1 2
IND-5D6UH- 52-GP
IND-5D6UH- 52-GP
0114-1
BQ24745_CSOP
BQ24745_CSON
+DC_IN_SS
1 2
PR4506
PR4506
470KR2J-2-GP
470KR2J-2-GP
1 2
PC4509
PC4509
PC4508
PC4508
SC10U25V6KX-1GP
SC10U25V6KX-1GP
DY
DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
Charger Current=1.4~3.6A
1124 Change P/N
+VCHGR1
PR4519
PR4519
1 2
D01R2512F-4-G P
D01R2512F-4-G P
1 2
PG4510
PG4510
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4502
PG4502
1 2
PC4502
PC4502
SCD1U50V3KX- GP
SCD1U50V3KX- GP
CSSP
CSSN
ICOUT
BOOT
VDDP
UGATE
PHASE
LGATE
PGND
CSOP
CSON
NC#16
VFB
PR4529
PR4529
0R0402-PAD
0R0402-PAD
+SDC_IN
PR4502
PR4502
D01R2512F-4-G P
D01R2512F-4-G P
1 2
PR4533_02
1 2
0R2J-2-GP
0R2J-2-GP
PR4508
PR4508
BQ24745_CSSP
28
SCD1U50V3KX- GP
SCD1U50V3KX- GP
BQ24745_CSSN
27
BQ24745_ICOUT
26
BQ24745_BOOT_1
25
BQ24745_LDO
21
BQ24745_CHARG ER_UGATE
24
23
BQ24745_PHASE_GN D
BQ24745_LGATE_1
20
19
BQ24745_CSOP_1
18
17
16
15
BAT_SENSE
1 2
DY
DY
CHG_AGND
PU4502
PU4502
S
D
S
D
1
PR4504
PR4504
1 2
10KR2J-3-GP
10KR2J-3-GP
PQ4502_03
BQ24745_ACOK
PR4511
PR4511
1 2
0R0402-PAD
0R0402-PAD
SCD1U50V3KX- GP
SCD1U50V3KX- GP
1 2
PC4501
PC4501
SCD1U10V2KX- 4GP
SCD1U10V2KX- 4GP
PG4507 GAP- CLOSE-PWR -3-GPPG4507 GAP-CLOSE-PWR-3- GP
PG4508 GAP- CLOSE-PWR -3-GPPG4508 GAP-CLOSE-PWR-3- GP
PR4522
PR4522
200KR2F-L-GP
200KR2F-L-GP
1 2
PR4526
PR4526
PR4526_01
7K5R2F-1-GP
7K5R2F-1-GP
1 2
PC4525
PC4525
1 2
SC56P50V2JN-2G P
SC56P50V2JN-2G P
SCD01U50V2KX- 1GP
SCD01U50V2KX- 1GP
S D
8
S
D
S
D
2
7
S
D
S
D
3
6
G D
G D
4 5
AO4407A-GP
AO4407A-GP
Id=-12A
Qg=-25nC
Rdson=10~38mohm
PQ4501
PQ4501
3 4
2
5
1
6
DMN66D0LDW -7-GP
DMN66D0LDW -7-GP
1 2
PC4503
PC4503
PR4512
PR4512
1 2
0R0402-PAD
0R0402-PAD
1 2
1 2
1 2
1 2
PR4527
PR4527
1 2
0R0402-PAD
0R0402-PAD
1 2
DY
DY
PC4528
PC4528
PC4529
PC4529
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
2N7002A-7-GP
2N7002A-7-GP
PQ4502
PQ4502
ACAV_IN
G
PR4513_03
1 2
BQ24745_DCIN
BQ24745_ACIN
BQ24745_ACOK
BAT_SCL_1
BAT_SDA_1
CHG_AGND
BQ24745_VICM
BQ24745_FBO
BQ24745_EAI
BQ24745_EAO
BQ24745_REF
1 2
DY
DY
PR4505
PR4505
PQ4502_05
10KR2F-2-GP
10KR2F-2-GP
BQ24745_CE
BQ24745_CE
PC4530
PC4530
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CHG_AGND
1 2
PR4503
PR4503
100KR2J-1-GP
100KR2J-1-GP
CHG_AGND
22
DCIN
2
ACIN
11
VDDSMB
13
ACOK
10
SCL
9
SDA
14
NC#14
8
VICM
6
FBO
5
EAI
4
EAO
3
VREF
7
CE
12
GND
PU4501
PU4501
BQ24745RHDR -GP
BQ24745RHDR -GP
GAP-CLOSE-P WR-3-GP
GAP-CLOSE-P WR-3-GP
1
ICREF
GND
29
+DC_IN_SS
D D
+DC_IN_SS
1 2
PR4509
316KR3F-2-GP
PR4509
316KR3F-2-GP
BQ24745_REF
DY
DY
10KR2F-2-GP
10KR2F-2-GP
PR4515
PR4515
DY
DY
15K8R3F-GP
15K8R3F-GP
PR4520
PR4520
SC220P50V2JN-3GP
SC220P50V2JN-3GP
1 2
1 2
PR4516
PR4516
10KR2F-2-GP
10KR2F-2-GP
1 2
1 2
4K7R2J-2-GP
4K7R2J-2-GP
PR4521
PR4521
1 2
PC4521
PC4521
SC150P50V2JN-3 G P
SC150P50V2JN-3 G P
BQ24745_FBO1
1 2
DY
DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
DY
DY
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
+KBC_PWR
CHG_AGND
BAT_SCL (37,44)
BAT_SDA (37,44)
PC4522
PC4522
SC2200P50V2KX-2G P
SC2200P50V2KX-2G P
1 2
PC4527
PC4527
DY
DY
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1 2
PC4533
PC4533
BQ24745_LDO
1 2
12
PC 4510
PC4510
ACAV_IN
PR4514 48K7R3F-1-GP PR4514 48K7R3F-1-GP
SCD01U50V2KX-1GP
CHG_AGND
AD_IA (37)
This Resistor
must be 1%
tolerance.
SCD01U50V2KX-1GP
PR4501
PR4501
0R2J-2-GP
0R2J-2-GP
1 2
PR4525
PR4525
8K45R2F-2-GP
8K45R2F-2-GP
DY
DY
1 2
1 2
PC4524
PC4524
PC4526
PC4526
AC_IN# (37)
C C
B B
2009/08/04
PU4503
PU4503
AO4407A-GP
AO4407A-GP
S
S
1
S
S
2
S
S
3
G D
G D
4 5
Id=-12A
Qg=Rdson=10~38mohm
1 2
1 2
EC4501
EC4501
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
1 2
1 2
PG4509
PG4509
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
BQ24745_PR4505
PR4524
PR4524
1 2
DY
DY
1 2
CHG_AGND
modify +VCHGR
+VCHGR
D
D
8
D
D
7
D
D
6
25nC
1117-7
EC4502
EC4502
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
modify +VCHGR
+VCHGR
1 2
1 2
PC 4515
PC4515
PC4517
PC4517
PC4516
PC4516
SC10U2 5V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
0R2J-2-GP
0R2J-2-GP
PC4531
PC4531
SCD1U50V3KX-GP
SCD1U50V3KX-GP
K A
1 2
1 2
DY
DY
PC4518
PC4518
PC4519
PC4519
DY
DY
PD4502
PD4502
1SMA18AT3G-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1SMA18AT3G-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
CHARGER BQ24745
CHARGER BQ24745
CHARGER BQ24745
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
45 95 Monday, March 08, 2010
45 95 Monday, March 08, 2010
45 95 Monday, March 08, 2010
A00
A00
A00
5
Title
Title
Title
ocument Numb er Rev
Size Document Num ber Rev
Size Document Num ber Rev
Size D
A2
A2
A2
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
A
+3D3V_PWR
+3.3V_ALW
PG4601
PG4601
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4602
PG4602
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4603
PG4603
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4606
PG4606
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4607
PG4607
4 4
Design Current =7.57A
11.89A<OCP<14.053A
3 3
2 2
1 1
+3D3V_PWR +5V_PWR
1118-2
1 2
PC4618
PC4618
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
I/P cap: 10U 25V K1206 X5R/ 78 .10622.52L
Inductor: 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =1 3.5Arms 68.3R310.20A
O/P cap: 220U 6.3V PSLV0J227M (25) 25mOhm 2.236Arms NEC_TOK IN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J10 7M(45)8R 45mOhm 1.374Arms NEC _TOKIN/77.C1071.081
H/S: FDS8884 23mohm/30mOhm@4.5 Vgs/ 84.08884.037
L/S: FDS6690AS 12mOhm/15mOhm@4 .5Vgs/ 84.06690.E37
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4609
PG4609
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4611
PG4611
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4613
PG4613
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4614
PG4614
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4615
PG4615
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
1 2
1 2
PTC4602
PTC4602
PTC4601
PTC4601
ST220U6D3VDM-15GP
ST220U6D3VDM-15GP
ST100U6D3VBM-5GP
ST100U6D3VBM-5GP
DY
DY
PR4609
PR4609
6K65R2F-GP
6K65R2F-GP
PR4613
PR4613
10KR2F-2-GP
10KR2F-2-GP
Close to VFB Pin (pin5)
A
COIL-3D3UH- 15-GP
COIL-3D3UH- 15-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
PG4623
PG4623
1 2
1 2
DY
DY
51125_FB2_R
1 2
DY
DY
1 2
SSID = PWR.Plane.Regulator_3p3v5v
PC4609
PC4609
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1 2
PC4621
PC4621
PG4604
PG4604
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4605
PG4605
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4608
PG4608
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4610
PG4610
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PC4610
PC4610
1 2
1 2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1 2
DY
DY
1 2
DY
DY
+PWR_SR C_3D3V
D
678
DDD
DDD
65MOS
65MOS
SSS
G D
SSS
G D
123
4 5
S G
D
678
DDD
DDD
65MOS
65MOS
SSS
G D
SSS
G D
123
4 5
G
S
51125_VREF
+3.3V_ALW_2
51125_VREF
+3.3V_ALW_2
TPS51125 RT8205B
PR4604
PU4602
PU4602
FDS8884-GP
FDS8884-GP
PC4616
PC4616
SCD1U25V3KX- GP
SCD1U25V3KX- GP
51125_VBST2_1 51125_VBST1_1
1 2
PU4604
PU4604
FDS6690AS-GP
FDS6690AS-GP
0R0402-PAD
0R0402-PAD
DY
DY
DY
DY
PR4619
PR4619
0R0402-PAD
0R0402-PAD
TPS51125:
GND
VREF
VREG3
VREG5
RT8205B(74.08208.A73):
GND
VREF
VREG3
VREG5
TPS51125
RT8208BGQW
+PWR_SR C
+PWR_SR C_3D3V
0114-1
PL4601
PL4601
PR4606
PR4606
2D2R5F-2-G P
2D2R5F-2-G P
SC330P50V2KX-3GP
SC330P50V2KX-3GP
0210-1
PR4610
PR4610
0R2J-2-GP
0R2J-2-GP
PC4623
PC4623
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
3V_5V_EN (42)
TPS51125 RT8205B
PR4622
DY ASM
51125_EN
0R3J 4R7
PR4604
PR4604
4D7R3F-L-G P
4D7R3F-L-G P
1 2
1 2
DY
DY
PR4608 820KR2F -GP
PR4608 820KR2F -GP
51125_VREF
PC4622
SCD22U10V2KX-1GP
PC4622
SCD22U10V2KX-1GP
1 2
PR4616
PR4616
1 2
PR4617
PR4617
1 2
0R2J-2-GP
0R2J-2-GP
PR4618
PR4618
1 2
0R2J-2-GP
0R2J-2-GP
1 2
PR4621
PR4621
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
PR4617 ASM
200kHz
245kHz
300kHz
365kHz
200kHz
300kHz
365kHz
74.51125.073
74.08208.A73
B
G
PR4622
PR4622
1 2
820KR3J-GP
820KR3J-GP
51125_VBST2
51125_DRVH2
51125_LL2
51125_DRVL2
51125_VO2
51125_FB2
51125_EN
51125_ENTIP2
51125_TONSEL
51125_SKIPSEL
+3.3V_ALW_2
GAP-CLOSE-P WR-3 - G P
GAP-CLOSE-P WR-3-GP
1225-3
TPS51125
DY PR4616
B
51125_ENTRIP
PQ4601
PQ4601
2N7002A-7-GP
2N7002A-7-GP
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
S D
+PWR_SR C
PU4601
PU4601
9
BOOT2
10
UGATE2
11
PHASE2
LGATE212LGATE1
7
VOUT2
5
FB2
13
EN
6
ENTRIP2
3
REF
4
TONSEL
14
SKIPSEL
RT8205BGQW -GP
RT8205BGQW -GP
PG4631
PG4631
1 2
PC4625
PC4625
3D3V_AUX_S5_5_51125
1 2
SC4D7U10V5KX-4GP
SC4D7U10V5KX-4GP
RT8205B
ASM
DY
SKIPSEL GND VREG3 or VREG5
CH2 CH1 TONSEL
Operating
265kHz
Mode
305kHz
375kHz
460kHz
Operating
Mode
CH2 CH1 TONSEL
250kHz
375kHz
460kHz 365kHz
460kHz
1 2
PC4601
PC4601
DY
DY
0.55mA
PC4611
PC4611
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1 2
1 2
DY
DY
16
VIN
22
BOOT1
21
UGATE1
20
PHASE1
19
24
VOUT1
2
FB1
23
PGOOD
1
ENTRIP1
15
PGND
25
GND
18
LG1_CP
VREG38VREG5
17
+5V_ALW2
1 2
1 2
PC4626
PC4626
SC10U10V5KX-2GP
SC10U10V5KX-2GP
OOA Auto Skip Auto Skip
enable both
LDOs, VCLK on
and ready to
turn on
switcher
channels
+3.3V_ALW_2
1 2
PR4602
PR4602
100KR2J-1-GP
100KR2J-1-GP
51125_ENTIP1
1 2
PR4601
PR4601
127KR2F-GP
PC4612
PC4612
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
51125_VBST1
51125_DRVH1
51125_LL1
51125_DRVL1
51125_VO1
51125_FB1
3V_5V_POK
51125_ENTIP1
51125_VCLK 51125_V CLK 51125_VCLK 5 1125_VCLK 51125_VCLK 51125_VCLK 51 125_VCLK 51125_VCLK 51125_VCLK 5112 5_VCLK
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC4627
PC4627
+3.3V_ALW_2
127KR2F-GP
PR4605
PR4605
PR4605
4D7R3F-L-G P
4D7R3F-L-G P
1 2
PR4620
PR4620
1 2
0R0402-PAD
0R0402-PAD
0105-5
5
6
123 4
TPS51125 RT8205B
0R3J 4R7
+3.3V_RTC_LD O
VREF(2V)
Open EN0 820kΩ to GND
enable both LDOs,
VCLK off and
ready to turn on
switcher channels
PU4606
PU4606
DMN66D0LDW -7-GP
DMN66D0LDW -7-GP
51125_ENTIP2
1 2
DY
DY
PC4605
PC4605
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
+KBC_PWR
SCD1U25V3KX- GP
SCD1U25V3KX- GP
PC4617
PC4617
1 2
1 2
PR4614
PR4614
100KR2J-1-GP
100KR2J-1-GP
PWM only
C
1 2
PR4603
PR4603
127KR2F-GP
127KR2F-GP
1225-2
+PWR_SR C_5V
51125_VCLK 51125_V CLK 51125_VCLK 5 1125_VCLK 51125_VCLK 51125_VCLK 51 125_VCLK 51125_VCLK 51125_VCLK 5112 5_VCLK
GAP-CLOSE-P WR-3-GP
GAP-CLOSE-P WR-3-GP
1 2
PG4612
PG4612
51125_VCLK 51125_V CLK
1 2
PC4602
SC1KP50V2KX-1GP
PC4602
SC1KP50V2KX-1GP
PD4601
PD4601
BAT54S-5-GP
BAT54S-5-GP
PD3903_2
PD3903_1
2
1 2
PC4606
PC4606
SC1U25V3KX-1- GP
SC1U25V3KX-1- GP
D
1 2
PC4603
PC4603
SCD1U25V3KX- GP
SCD1U25V3KX- GP
3
1
2
PD3903_04
1 2
1117-7 1117-7
PC4614
PC4614
PC4613
PC4613
D
1 2
1 2
678
DDD
DDD
PU4603
PU4603
PU4605
PU4605
3V_5V_POK (37 ,50)
I/P cap: 10U 25V K1206 X5R/ 78 .10622.52L
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =1 4Arms 68.2R210.20B
O/P cap: 220U 6.3V PSLV0J227M (25) 25mOhm 2.236Arms NEC_TOK IN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J10 7M(45)8R 45mOhm 1.374Arms NEC _TOKIN/77.C1071.081
H/S: FDS8884 23mohm/30mOhm@4.5 Vgs/ 84.08884.037
L/S: FDS6690AS 12mOhm/15mOhm@4 .5Vgs/ 84.06690.E37
G
G D
65MOS
G D
65MOS
4 5
65MOS
65MOS
G D
G D
4 5
678
FDS8884-GP
FDS8884-GP
SSS
SSS
123
S
D
DDD
DDD
FDS6690AS-GP
FDS6690AS-GP
SSS
SSS
123
S G
GND
disable all
circuit
C
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1 2
IND-2D2UH- 46-GP-U
IND-2D2UH- 46-GP-U
1 2
PR4607
PR4607
2D2R5F-2-G P
2D2R5F-2-G P
1125-1
1 2
PC4620
PC4620
SC560P50V-GP
SC560P50V-GP
0R2J-2-GP
0R2J-2-GP
PC4624
PC4624
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
PL4602
PL4602
1 2
PR4611
PR4611
PC4615
PC4615
SCD1U25V2KX-GP
SCD1U25V2KX-GP
0210-1
1 2
DY
DY
51125_FB1_R
1 2
DY
DY
Design Current = 7.3A
11.45A<OCP< 16A
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
PG4626
PG4626
1 2
1 2
1 2
PC4619
PC4619
DY
DY
PR4612
PR4612
33KR2F-GP
33KR2F-GP
PR4615
PR4615
21K5R2F-GP
21K5R2F-GP
Close to VFB Pin (pin2)
1124 Change P/N
1 2
PTC4603
PTC4603
ST220U6D3VDM -15GP
ST220U6D3VDM -15GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
D
1 2
PC4604
PC4604
SCD1U25V3KX- GP
SCD1U25V3KX- GP
PD3904_1
3
PD4602
PD4602
BAT54S-5-GP
BAT54S-5-GP
1
+5V_PWR +15V_ALW
PC4608
PC4608
SCD1U25V3KX- GP
SCD1U25V3KX- GP
1 2
PC4607
PC4607
SCD1U25V3KX- GP
SCD1U25V3KX- GP
+PWR_SR C
PG4616
PG4616
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4620
PG4620
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4622
PG4622
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4624
PG4624
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4628
PG4628
GAP-CLOSE-P WR
GAP-CLOSE-P WR
E
+5V_PWR
+PWR_SR C_5V
1 2
1 2
1 2
1 2
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size D
ocument Numb er Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Date: Sheet of
Date: Sheet of
Date: Sheet of
+5V_ALW
PG4618
PG4618
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4617
PG4617
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4619
PG4619
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4621
PG4621
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4625
PG4625
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4627
PG4627
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4629
PG4629
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
PG4630
PG4630
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
RT8205B_5V/3D3V
RT8205B_5V/3D3V
RT8205B_5V/3D3V
E
A00
A00
46 95 Thursday, March 04, 2010
46 95 Thursday, March 04, 2010
46 95 Thursday, March 04, 2010
A00
5
4
3
2
1
SSID = CPU.Regulator
PC4702
PC4702
PR4702
PR4702
1 2
44K2R2F-1-GP
44K2R2F-1-GP
PC4704
PC4704
SC1KP50V2KX-1G P
SC1KP50V2KX-1G P
PR4704
PR4704
1 2
22KR2F-GP
22KR2F-GP
6265_COMP_NB
6265_FSET_NB
CPU_VDDNB_RUN_FB_H_R
42
44
43
45
FB_NB
FSET_NB
VSEN_NB
COMP_NB
6265_FB1
6265_VDIFF1
6265_RTN1
6265_VSEN1
PC4727
PC4727
SC180P50V2JN-1 GP
SC180P50V2JN-1 GP
54K9R2F-L-GP
54K9R2F-L-GP
1 2
PR4743
PR4743
DY
DY
SC33P50V2JN-3G P
SC33P50V2JN-3G P
1 2
1 2
8K06R2F-GP
8K06R2F-GP
1125-1
PHASE_NB_R
39
40
41
RTN_NB
PGND_NB
LGATE_NB
OCSET_NB
6265_VW1
6265_COMP1
1 2
DY
DY
6265_FB1_R
4
1 2
6265_FB_NB_R
0R0402-PAD
0R0402-PAD
PR4706
PR4706
1 2
PR4707
PR4707
CPU_VDDN B_RUN_FB_L_R
38
37
PHASE_NB
UGATE_NB
BOOT_NB
UGATE0
PHASE0
PGND0
LGATE0
LGATE1
PGND1
PHASE1
UGATE1
24
SC1200P50V2KX-1GP
SC1200P50V2KX-1GP
1 2
DY
DY
+5V_RUN
PR4701
PR4701
1 2
2R3J-GP
2R3J-GP
D D
+3.3V_RUN
10KR2J-3-GP
10KR2J-3-GP
1 2
PR4713
PR4713
IMVP_PWRGD
CPU_PW RGD_SVID_REG (10)
CPU_SVD (10)
CPU_SVC (10)
IMVP_VR_ON (37)
C C
GNDA_VCOR E
B B
6265_FB0_C
PC4723
PC4723
PR4737
PR4737
1 2
1 2
249R2F-GP
249R2F-GP
SC4700P50V2KX-1G P
SC4700P50V2KX-1G P
PR4739
PR4739
1 2
1KR2F-3-GP
1KR2F-3-GP
A A
54K9R2F-L-GP
54K9R2F-L-GP
1 2
PR4744
PR4744
PR4719
PR4719
1 2
0R0402-PAD
0R0402-PAD
PR4721
PR4721
1 2
24KR2F-GP
24KR2F-GP
CPU_VDD0_R UN_FB_H (10)
CPU_VDD0_R UN_FB_L (10)
CPU_VDD1_R UN_FB_L (10)
CPU_VDD1_R UN_FB_H (10)
PC4724
PC4724
1 2
SC180P50V2JN-1 GP
SC180P50V2JN-1 GP
6265_FB0_R
5
+PWR_SR C
+5V_RUN +3.3V_ RUN
1 2
0R0402-PAD
0R0402-PAD
PR4709
PR4709
10KR2J-3-GP
10KR2J-3-GP
1 2
PR4714
PR4714
DY
DY
PR4717 0R0402- PAD PR4717 0 R0402-PAD
1 2
PR4718 0R0402- PAD PR4718 0 R0402-PAD
1 2
PR4720 93K1R 2F-L-GP PR4720 93K1 R2F-L-GP
1 2
PC4718
PC4718
1 2
1%
+VCC_COR E
10R2J-2-GP
10R2J-2-GP
1 2
CPU_VDD1_R UN_FB_H
10R2J-2-GP
10R2J-2-GP
1 2
1229-2
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
DY
DY
Close to CPU socket
PC4725
PC4725
1 2
SC1KP50V2KX-1G P
SC1KP50V2KX-1G P
PR4740
PR4740
1 2
SC1200P50V2KX-1GP
SC1200P50V2KX-1GP
PC4728
PC4728
6K81R2F-1-GP
6K81R2F-1-GP
1 2
1 2
0R2J-2-GPDYPR4710
0R2J-2-GP
DY
0R2J-2-GP
0R2J-2-GP
DY
DY
GNDA_VCOR E
1 2
GAP-CLOSE-P WR
GAP-CLOSE-P WR
+VCC_COR E
0R2J-2-GP
0R2J-2-GP
PR4726
PR4726
0114-1
10R2J-2-GP
10R2J-2-GP
PR4735
PR4735
PR4703
PR4703
2R3J-GP
2R3J-GP
1 2
1 2
PG4701
PG4701
1 2
1 2
DY
DY
PR4710
PR4715
PR4715
PR4727
PR4727
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1 2
GNDA_VCOR E
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1 2
GNDA_VCOR E
GNDA_VCOR E
6265_OFS/VFIXEN
CPU_SVD_R
CPU_SVC_R
VCC_CORE _EN
6265_RBIAS
6265_OCSET
6265_VDIFF0
6265_FB0
10
6265_COMP0
11
6265_VW0
12
GNDA_VCOR E
+1.8V_RUN
1KR2J-1-GP
1KR2J-1-GP
1 2
PR4723
PR4723
PR4729 0R0402-PAD PR4729 0R0402-PAD
PR4730 0R0402-PAD PR4730 0R0402-PAD
PR4733 0R0402-PAD PR4733 0R0402-PAD
PR4734 0R0402-PAD PR4734 0R0402-PAD
PR4736
PR4736
Parallel
PR4738
PR4738
1 2
DY
DY
249R2F-GP
249R2F-GP
5V, 10mA
PC4701
PC4701
PC4707
PC4707
PU4701
PU4701
1
OFS/VFIXEN
2
PGOOD
3
PWROK
4
SVD
5
SVC
6
ENABLE
7
RBIAS
8
OCSET
9
VDIFF0
FB0
COMP0
VW0
ISP0
ISN0
1 2
1 2
1 2
1 2
6265_FB1_C
SC4700P50V2KX-1G P
SC4700P50V2KX-1G P
PR4741
PR4741
1 2
DY
DY
1KR2F-3-GP
1KR2F-3-GP
6265_VIN
6265_FB_NB
6265_VCC
47
46
49
48
VIN
VCC
GND
ISL6265AHRTZ-T -GP
ISL6265AHRTZ-T -GP
ISP013ISN014VSEN015RTN016RTN117VSEN118VDIFF119FB120COMP121VW122ISP123ISN1
6265_VSEN0
6265_RTN0
PC4726
PC4726
1 2
DY
DY
ISL6265HRTZ-T for +VCC_CORE&+VDDNB
I/P cap: 10U 25V K1206 X5R/ 78 .10622.52L
Inductor:4.7uH PCMC063T-4R7MN 35mohm Isat =10Arms CYNTEC/68 .4R710.20D
PC4703
PC4703
1 2
SC1200P50V2KX-1G P
SC1200P50V2KX-1G P
+VDDNB
10R2J-2-GP
10R2J-2-GP
PHASE_NB
9/15
LGATE_NB
PHASE_NB
UGATE_NB
36
35
BOOT0
34
33
32
31
30
PVCC
29
28
27
26
25
BOOT1
ISN1
PC4722
PC4722
1 2
DY
DY
SC1KP50V2KX-1G P
SC1KP50V2KX-1G P
PR4742
PR4742
1 2
DY
DY
PC4733
PC4733
6K81R2F-1-GP
6K81R2F-1-GP
1 2
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33 719.L01
H/S:VISHAY SIS412DN-T1-GE3/ 24 mohm/30mOhm@4.5Vgs/ 84.00412. 037
L/S:VISHAY SIS412DN-T1-GE3/ 24 mohm/30mOhm@4.5Vgs/ 84.00412. 037
GNDA_VCOR E
PR4705
PR4705
BOOT_NB
BOOT0
UGATE0
PHASE0
LGATE0
LGATE1
PHASE1
UGATE1
BOOT1
CPU_VDDN B_RUN_FB_H (10)
1 2
PR4712
PR4712
10R2F-L-GP
10R2F-L-GP
0R0402-PAD
0R0402-PAD
+5V_RUN
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
PC4712
PC4712
1 2
CPU_VDDN B_RUN_FB_L (10)
1 2
PR4716
PR4716
BOOT0
1 2
1R3J-L1-GP
1R3J-L1-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Indu
Isat =60Arms 68.R3610.20C
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01
H/S:VISHAY SiR462DP/ POWERPAK-8.2/810mOhm/ 4.5Vgs/ 84.00462.037
L/S:VISHAY SI7658ADP/ POWERPAK-2.3/ 2.8mOhm/ 4.5Vgs/ 84.07658.037
BOOT_NB B OOT_NB_R
UGATE0
PHASE0 ISP1
PR4724
PR4724
BOOT0_R
1 2
1R3J-L1-GP
1R3J-L1-GP
LGATE0
UGATE1
PHASE1
PR4746
PR4746
LGATE1
PC4735
PC4735
BOOT1_R BOO T1
SCD22U25V3KX- GP
SCD22U25V3KX- GP
ctor: 0.36UH PCMC104T-R36MN1R05J CYNTEC DCR 1.05(+5%~-5%)mohm
3
PR4708
PR4708
1 2
0R0603-PAD
0R0603-PAD
PC4719
PC4719
SCD22U25V3KX- GP
SCD22U25V3KX- GP
SIS406DN-T1-GE 3-GP
SIS406DN-T1-GE 3-GP
1 2
SIS406DN-T1-GE 3-GP
SIS406DN-T1-GE 3-GP
1 2
PU4711
PU4711
PU4709
PU4709
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
PU4710
PU4710
PU4708
PU4708
65MOS
65MOS
65MOS
65MOS
G S
UGATE_NB
PC4708
PC4708
1 2
SCD22U25V3KX- GP
SCD22U25V3KX- GP
LGATE_NB
678
DDD
DDD
65MOS
65MOS
G
G
4 5
678
DDD
DDD
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
65MOS
65MOS
G
G
4 5
G S
678
DDD
D
DDD
D
SSS
SSS
G
G
123
4 5
D
678
DDD
D
DDD
D
SSS
SSS
G
G
123
4 5
D
D
SSS
SSS
123
D
D
D
SSS
SSS
123
DDD
DDD
65MOS
65MOS
G
G
4 5
G S
DDD
DDD
65MOS
65MOS
G
G
4 5
G S
678
DDD
DDD
65MOS
65MOS
G
G
4 5
G S
678
DDD
DDD
65MOS
65MOS
G
G
4 5
678
678
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
SIS412DN-T1-GE3-GP
D
D
D
SSS
SSS
123
D
D
D
SSS
SSS
123
S G
G D
65MOS
G D
65MOS
4 5
G D
65MOS
G D
65MOS
4 5
D
D
D
PU4704
PU4704
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
SSS
SSS
123
D
D
D
PU4705
PU4705
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
SSS
SSS
123
PU4706
PU4706
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
PU4707
PU4707
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
678
DDD
DDD
678
DDD
DDD
+PWR_SR C
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
PU4702
PU4702
SSS
SSS
1117-7
123
PHASE_NB
PU4703
PU4703
SSS
SSS
123
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC4730
PC4730
PC4729
PC4729
1 2
1 2
PC4738
PC4738
1 2
1 2
PR4711
PR4711
DY
DY
2D2R5F-2-G P
2D2R5F-2-G P
PHASENB_RC
1 2
PC4711
PC4711
SC330P50V2KX-3GP
SC330P50V2KX-3GP
DY
DY
1 2
DY
DY
PHASE0_RC
1 2
DY
DY
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1 2
1 2
DY
DY
PHASE1_RC
1 2
DY
DY
PC4705
PC4705
1 2
PL4702
PL4702
1 2
IND-4D7UH- 88-GP
IND-4D7UH- 88-GP
0210-1
PR4725
PR4725
2D2R5F-2-GP
2D2R5F-2-GP
PC4721
PC4721
SC330P50V2KX-3GP
SC330P50V2KX-3GP
0210-1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PC4734
PC4734
PC4731
PC4731
1 2
PR4747
PR4747
2D2R5F-2-GP
2D2R5F-2-GP
PC4737
PC4737
SC330P50V2KX-3GP
SC330P50V2KX-3GP
0210-1
2
16KR2F-GP
16KR2F-GP
1 2
ISP0
+PWR_SR C
SE100U25VM-14GP
SE100U25VM-14GP
1 2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PR4722
PR4722
PR4731
PR4731
1 2
10R2F-L-GP
10R2F-L-GP
PTC4706
PTC4706
16KR2F-GP
16KR2F-GP
1 2
ISP1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC4713
PC4713
1 2
0114-1
SCD1U16V3KX- 3GP
SCD1U16V3KX- 3GP
DY
DY
0210-3
SE100U25VM-14GP
SE100U25VM-14GP
1 2
PR4748
PR4748
PR4750
PR4750
1 2
DY
DY
10R2F-L-GP
10R2F-L-GP
1 2
PTC4710
PTC4710
+VDDNB
Design Current: 2.8A
Peak current: 4A
4.4A<OCP<5.6A
+VDDNB
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
PC4709
PC4709
1 2
1 2
+PWR_SR C
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC4714
PC4714
PC4715
PC4715
1 2
1 2
1 2
PL4701
PL4701
COIL-D36UH- 3-GP
COIL-D36UH- 3-GP
0907
PR4728
PR4728
1 2
4K02R2F-GP
4K02R2F-GP
PC4720
PC4720
1 2
PR4732
PR4732
ISP0_R
1 2
NTC-10K-26- GP
NTC-10K-26- GP
0114-1
0114-1
PL4703
PL4703
1 2
COIL-D36UH- 3-GP
COIL-D36UH- 3-GP
0907
PR4749
PR4749
1 2
4K02R2F-GP
4K02R2F-GP
PC4736
PC4736
1 2
SCD1U16V3KX- 3GP
SCD1U16V3KX- 3GP
PR4751
PR4751
ISP1_R
1 2
NTC-10K-26- GP
NTC-10K-26- GP
0114-1
PTC4701
SE330U2VDM-L-GP
PTC4701
SE330U2VDM-L-GP
PC4710
PC4710
1 2
PC4717
PC4717
+VCC_CORE
Design Current: 36A
39.6A<OCP<54A
+VCC_COR E
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
PTC4704
PTC4704
PTC4703
PTC4703
PTC4705
PTC4705
1 2
1 2
1 2
PG4702
PG4702
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
DY
DY
ISN0
SE330U2VDM-L-GP
SE330U2VDM-L-GP
1 2
1 2
PG4703
PG4703
DY
DY
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
DY
DY
ISN1
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
VREG : +VCC_CORE&+VDDNB
VREG : +VCC_CORE&+VDDNB
VREG : +VCC_CORE&+VDDNB
Size Document Num ber Rev
Size Document Num ber Rev
Size D
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
+VCC_COR E
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
PTC4709
PTC4709
PTC4707
PTC4707
PTC4708
PTC4708
1 2
1 2
DY
DY
ocument Numb er Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
47 95 Thursday, March 04, 2010
47 95 Thursday, March 04, 2010
47 95 Thursday, March 04, 2010
A00
A00
A00
5
4
SSID = PWR.Plane.Regulator_+1.1V_RUN
1117-2
3
2
1
D D
0222-3
Remove
+5V_ALW
SC1U10V3KX-3GP
SC1U10V3KX-3GP
PC4801
PC4801
1 2
RT8209EGQW for +1.1V_RUN
PWM TYPE
*
10R3J-3-GP
10R3J-3-GP
1 2
PR4801
PR4801
*DEFAULT
300 ohm TPS51117
PRb PRa
4.7 ohm RT8209B 10 ohm
0 ohm
PRa
PC4802
SC1U10V3KX-3GP
PC4802
SC1U10V3KX-3GP
+5V_ALW
RB551V30-GP
RB551V30-GP
PD4801
PD4801
K A
PR4808 0R0402-P AD PR48 08 0 R0402-PAD
C C
IMVP_PW RGD (37,41,47,5 1)
1 2
PR4804 300KR2F-GP PR4804 300KR2F-GP
1 2
1 2
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
1 2
DY
DY
5V, 1.25mA
+1.1V_VO UT_V5FILT
+1.1V_VO UT_BST
+VDDC_E N
+1.1V_VO UT_TON
+1.1V_VO UT_TRIP
PC4808
PC4808
1 2
PR4803
PR4803
9K31R2F-GP
9K31R2F-GP
4
10
5
14
1
2
11
PRb
PR4806
PR4806
1 2
4D7R3J-L 1-GP
4D7R3J-L 1-GP
PU4801
PU4801
VDD
VDDP
FB
BOOT
EN/DEM
TON
CS
RT8209E GQW-GP
RT8209E GQW-GP
UGATE
LGATE
PHASE
VOUT
PGOOD
GND
PGND
NC#15
13
9
12
3
6
7
8
15
+1.1V_LL 1
+1.1V_DR VH
+1.1V_DR VL
+1.1V_LL +1.1V_VO UT_VFB
+1.1V_VO UT
VDDC_PW RGD
PC4811
PC4811
1 2
SCD1U25 V3KX-GP
SCD1U25 V3KX-GP
VDDC_PW RGD (37,41 )
0222-3
+PWR _SRC
678
PU4802
PU4802
65MOS
65MOS
4 5
DDD S
DDD S
678
DDD
DDD
G D
G D
SSG D
SSG D
DY
DY
SI7686DP-T1-GP
SI7686DP-T1-GP
123
4 5
123
0308-1
678
DDD
DDD
SIR164DP-T1-GE3-GP
SIR164DP-T1-GE3-GP
G D
G D
DY
DY
4 5
Close to VFB Pin (pin5)
678
DDD
DDD
PU4804
PU4804
SIR164DP-T1-GE3-GP
SIR164DP-T1-GE3-GP
SSS
SSS
G D
G D
65MOS
65MOS
123
123
4 5
SSS
SSS
SSS
SSS
PU4805
PU4805
SIR164DP-T1-GE3-GP
SIR164DP-T1-GE3-GP
PU4803
PU4803
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC4812
PC4812
1 2
1119-2
2D2R5F-2-GP
2D2R5F-2-GP
1 2
DY
DY
SC330P50V2KX-3GPDYPC4809
SC330P50V2KX-3GP
1 2
DY
0210-1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC4803
PC4803
1 2
0114-1
PL4801
PL4801
1 2
COIL-1D5UH -25-GP
COIL-1D5UH -25-GP
PR4802
PR4802
PC4809
+1.1V_VO UT
+1.1V_VO UT_VFB
R1
R2
SCD1U50V3KX-GP
SCD1U50V3KX-GP
PC4806
PC4806
PC4810
PC4810
1 2
1 2
Design Current = 7.4A
11.65A<OCP < 15.89A
+1.1V_RU N
SE330U2D5VM-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
18KR2F-GP
18KR2F-GP
PG4817
PG4817
1 2
1 2
PR4805
PR4805
1 2
PR4807
PR4807
38K3R2F -GP
38K3R2F -GP
DY
DY
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
1 2
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
PC4805
PC4805
1 2
SE330U2D5VM-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PC4804
PC4804
PTC4801
PTC4801
PC4807
PC4807
1 2
1 2
1 2
1 2
PTC4803
PTC4803
PTC4802
PTC4802
ST330U2VDM-3GP
ST330U2VDM-3GP
ST330U2VDM-3GP
ST330U2VDM-3GP
Vout=0.75V*(R1+R2)/R2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 1.5UH PCMC104T-1R5MN 33Arms CYNTEC/ 68.1R510.10J
O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L
B B
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR164DP/ POWERPAK-8/ 2.6mOhm/3.2mohm@4.5Vgs/ 84.00164.037
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
RT8209E_+1.1V_RUN
RT8209E_+1.1V_RUN
RT8209E_+1.1V_RUN
ocument Nu mber Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
48 95 Mon day, March 08, 2010
48 95 Mon day, March 08, 2010
48 95 Mon day, March 08, 2010
1
A00
A00
A00
5
SSID = PWR.Plane.Regulator_1p5v0p75v
1125-1
12KR2F-L -GP
12KR2F-L -GP
1 2
PR4902
PR4902
0622
1118-3
+1.5V_SU S
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
PC4906
PC4906
1 2
PC4902
PC4902
SC1KP50 V2KX-1GP
SC1KP50 V2KX-1GP
PM_SLP_ S5# (21 ,37)
PC4905
PC4905
DY
DY
1 2
PG4901
PG4901
1 2
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG4917
PG4917
1 2
GAP-CLOS E-PWR
GAP-CLOS E-PWR
On
Off(Hi-Z)
DDR
DDR2
1.5 V < VVDDQ < 3 V
D D
+3.3V_RU N
11/9
PR4916
PR4916
100KR2J -1-GP
100KR2J -1-GP
Refer to DJ1 PR8 606
RUNPW ROK (51,52,89,90 )
+5116_P WR_SRC
C C
TI: Non_ASM
RT: ASM
+5V_ALW
+1.5V_SU S
+0D75V_ DDR_P
1 2
Design Current = 0.7A
+0D75V_ DDR_P
1 2
1 2
1 2
B B
PC4914
PC4914
PC4913
PC4913
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
PC4915
PC4915
PC4916
PC4916
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
State S3 S5 VDDR VTTREF VTT
S0
Hi Hi
S3
S4/S5
Hi Lo
Lo Lo
VDDQSET VDDQ (V) VTTREF and VTT NOTE
GND
A A
V5IN
FB Resistors
2.5
1.8
Adjustable
5
1120-7
PR4906
PR4906
1 2
620KR2F -GP
620KR2F -GP
PR4909 1M1R2J-G P
PR4909 1M1R2J-G P
1 2
DY
DY
PR4910 0R0402-PAD PR 4910 0R0402-P AD
1 2
SC1KP50 V2KX-1GP
SC1KP50 V2KX-1GP
+0D75V_ DDR_P +0.7 5V_DDR_VTT
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
On
On
Off Off Off
On
On
VVDDQSNS/2
VVDDQSNS/2
VVDDQSNS/2
51116_V DD
0D75V_E N
1 2
4
13
12
11
10
23
7
1
4
24
2
1 2
PGOOD
TON
S5
S3
VLDOIN
NC#7
VTTGND
MODE
VTT
VTTSNS
25
1119-7
+5V_ALW
1 2
5V, 0.8mA
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
PC4901
PC4901
16
14
CS
VDD
GND
GND
RT8207G QW-GP
RT8207G QW-GP
3
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
TPS5111 6_UGT
TPS5111 6_VBST
SCD1U25 V3KX-GP
SCD1U25 V3KX-GP
TPS5111 6_LGT
PR4901
PR4901
5D1R3J-G P
5D1R3J-G P
15
PU4901
PU4901
VDDP
BOOT
UGATE
PHASE
LGATE
PGND
NC#17
VDDQ
DEM
VTTREF
5
PR4912
PR4912
1 2
0R0603-P AD
0R0603-P AD
1 2
1 2
PC4917
PC4917
+5V_ALW
1 2
22
21
20
19
18
17
8
9
FB
6
+V_DDR_ REF
PC4908
PC4908
PC4903
PC4903
SC1U10V3KX-3GP
SC1U10V3KX-3GP
TPS5111 6_VBST1
TPS5111 6_UGT
TPS5111 6_PHS
TPS5111 6_LGT
TPS5111 6_VDDQSNS
51116_V DDQSET
PR4908
PR4908
0R0603-P AD
0R0603-P AD
1 2
+5V_ALW
1 2
PC4907
PC4907
DY
DY
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
3
TPS5111 6_VBST
PR4911
PR4911
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
SI7686DP-T 1-GP
SI7686DP-T 1-GP
SIR164DP-T 1-GE3-GP
SIR164DP-T 1-GE3-GP
+5V_ALW
DY
DY
2 1
+5116_P WR_SRC
PU4902
PU4902
65MOS
65MOS
PU4903
PU4903
65MOS
65MOS
PD4901
PD4901
CH551H-3 0PT-GP
CH551H-3 0PT-GP
678
DDD S
DDD S
SSG D
SSG D
123
4 5
TPS5111 6_PHS
678
DDD
DDD
SSS
G D
SSS
G D
123
4 5
1 2
1 2
PR4913
PR4913
3D9R5J-G P
3D9R5J-G P
0225-3
TPS5111 6_PHS_SET
1 2
PC4920
PC4920
SC680P5 0V3JN-GP
SC680P5 0V3JN-GP
1125-1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 1.5UHPCMC104T-1R5MN DCR:3.8/4.2mohm Isat =33Arms Cyntec/ 68.1R510.10J
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR164DP/ POWERPAK-8/ 2.6mOhm/3.2mohm@4.5Vgs/ 84.00164.037
4
3
PC4909
PC4909
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1 2
COIL-1D5UH -25-GP
COIL-1D5UH -25-GP
0114-1
PM_SLP_ S3# (21,37,41,4 2,52,89)
PM_SLP_ S5# (21 ,37)
1.5V_RUN _EN (37,42 )
PC4922
PC4922
1 2
PL4901
PL4901
1 2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
TPS5111 6_VDDQSNS
30KR2F-G P
30KR2F-G P
51116_V DDQSET
30KR2F-G P
30KR2F-G P
2
PC4911
PC4911
PR4914
PR4914
PR4915
PR4915
2
1125-1
PR4903 2D2R2J-GP PR4903 2D2R2J-GP
PR4907 0R2J-2-GP
PR4907 0R2J-2-GP
PR4904 0R2J-2-GP
PR4904 0R2J-2-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PC4923
PC4923
1 2
1 2
PC4912
PC4912
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
1 2
PG4918
PG4918
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2
1 2
DY
DY
1 2
1
1 2
1 2
DY
DY
1 2
DY
DY
1116-6
+PWR _SRC
PG4903
PG4903
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG4905
PG4905
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG4907
PG4907
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG4909
PG4909
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG4911
PG4911
GAP-CLOS E-PWR
GAP-CLOS E-PWR
0D75V_E N
+5116_P WR_SRC
1 2
1 2
1 2
1 2
1 2
1 2
PC4904
PC4904
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
9/18
Design Current = 18.45A
28.99A<OCP< 34.3A
+1.5V_SU S
1 2
12
PC4918
PC4918
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
PC4921
PC4921
SC18P50 V2JN-1-GP
SC18P50 V2JN-1-GP
Close to VFB Pin (pin5)
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
1 2
PC4919
PC4919
PTC 4902
PTC4902
PTC 4901
PTC4901
SE220U2VDM-8GP
SE220U2VDM-8GP
SE220U2VDM-8GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
RT8207_+1.5V_SUS
RT8207_+1.5V_SUS
RT8207_+1.5V_SUS
ocument Nu mber Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
SE220U2VDM-8GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
49 95 Thu rsday, March 04, 2010
49 95 Thu rsday, March 04, 2010
49 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
SSID = PWR.Plane.Regulator_+1.1V_ALW
1117-2
3
2
1
D D
0106-1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
PR5004
PR5004
10KR2J-3 -GP
10KR2J-3 -GP
1 2
DY
3V_5V_P OK (37,46)
C C
PR5002
PR5002
2K2R2J-2 -GP
2K2R2J-2 -GP
DY
TP5001 TP5001
1.1V_RUN _PWRGD
1
Vout=0.8V*(R1+R2)/R2
RT9025 for +1.1V_ALW
+5V_ALW
PC5006
SC1U10V3KX-3GP
PC5006
SC1U10V3KX-3GP
1 2
+3.3V_AL W
PC5005
PC5005
1 2
9
1.2mA
VDD4NC#5
3
VIN
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
PC5004
PC5004
1 2
DY
DY
2
EN
1
PGOOD
PU5001
PU5001
RT9025-2 5PSP-GP
RT9025-2 5PSP-GP
Vo=0.8*(1+(R1/R2))
GND
VOUT
ADJ
GND
5
6
+1.1V_AL W_ADJ +1.1V_VOU T_EN
7
8
1 2
PR5001
PR5001
1K02R2F-1-GP
1K02R2F-1-GP
1 2
PR5003
PR5003
2K7R2F-G P
2K7R2F-G P
+1.1V_AL W_P
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC22U6D3V5MX-2GP
PC5001
PC5001
1 2
DY
DY
SC22U6D3V5MX-2GP
PC5003
1 2
DY
DY
PC5003
GAP-CLOS E-PWR
GAP-CLOS E-PWR
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PC5002
PC5002
1 2
PG5002
PG5002
1 2
PG5001
PG5001
1 2
+1.1V_AL W
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
RT9025_+1.1V_ALW
RT9025_+1.1V_ALW
RT9025_+1.1V_ALW
ocument Nu mber Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
50 95 Thu rsday, March 04, 2010
50 95 Thu rsday, March 04, 2010
50 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = PWR.Plane.Regulator_VDDR
D D
RT9025 for +VDDR
11/6
+5V_ALW
5V, 1.2mA
PC5101
SC1U10V3KX-3GP
PC5101
+1.5V_SU S
PC5106
SC10U6D3V5MX-3GP
PC5106
SC10U6D3V5MX-3GP
1 2
SC1U10V3KX-3GP
1 2
C C
RUNPW ROK (49,52,89,90 )
Vo=0.8*(1+(R1/R2))
1119-1
PR5108
PR5108
1 2
DY
DY
0R2J-2-GP
0R2J-2-GP
PD5101
VDDR_SE L (20,24)
B B
MEM_1V5 (22)
VDDR_SE L
MEM_1V5
VDDR_SEL
1
2
PD5101
3
BAT54AP T-GP
BAT54AP T-GP
+CPU_VDDR
IMVP_PW RGD (37,41,47 ,48)
1116-2
10KR2F-2 -GP
10KR2F-2 -GP
VDDR_SE L_R
PR5105
PR5105
PR5101
PR5101
+3.3V_RU N
1 2
1 2
2K2R2J-2 -GP
2K2R2J-2 -GP
1.05V H
VDDR_EN +VDDR_A DJ
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
PC5104
PC5104
1 2
DY
DY
Vout=0.8V*(R1+R2)/R2
PR5103
PR5103
10KR2F-2 -GP
10KR2F-2 -GP
1 2
VDDR_SE L_CNTL
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
DY
DY
VDD4NC#5
3
VIN
2
EN
1
PGOOD
PU5101
PU5101
RT9025-2 5PSP-GP
RT9025-2 5PSP-GP
12
DY
DY
PC5102
PC5102
1 2
9
5
GND
VOUT
PR5104
PR5104
ADJ
GND
100KR2J-1-GP
100KR2J-1-GP
6
7
8
PQ5101
PQ5101
2N7002A -7-GP
2N7002A -7-GP
0105-6
R1
1 2
PR5107
PR5107
5K62R2F -GP
5K62R2F -GP
R2
G
S D
1 2
PR5102
PR5102
1K05R2F -GP
1K05R2F -GP
1 2
PR5106
PR5106
8K2R2F-1 -GP
8K2R2F-1 -GP
1225-6
PC5105
SCD01U16V2KX-3GPDYPC5105
SCD01U16V2KX-3GP
1 2
DY
+VDDR_P
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC5107
PC5107
1 2
1 2
DY
DY
PC5103
PC5103
GAP-CLOS E-PWR
GAP-CLOS E-PWR
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG5101
PG5101
1 2
PG5102
PG5102
1 2
+CPU_VD DR
+1.5V_RUN +/- 5%
Design Current: 0.805A
Peak current 1.1 5A
0.9V L
10/2
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
RT9025 +VDDR
RT9025 +VDDR
RT9025 +VDDR
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
51 95 Thu rsday, March 04, 2010
51 95 Thu rsday, March 04, 2010
51 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = PWR.Plane.Regulator_1p8v
APL5930 for +1.8V_RUN
+3.3V_AL W +1 .8V_RUN_VIN
D D
C C
PG5201
PG5201
1 2
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG5202
PG5202
1 2
GAP-CLOS E-PWR
GAP-CLOS E-PWR
5
9
3
4
2
FB
SO-8-P
+1.8V_RU N_VIN +5V_ALW
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
PR5203
16K5R2F-2-GP
PR5203
16K5R2F-2-GP
1 2
PC520 3
PC5203
PC520 2
PC5202
1 2
DY
DY
Design Current =0.92A
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC5205
PC5205
PC5204
SC68P50V2JN-1GP
PC5204
SC68P50V2JN-1GP
1 2
1 2
+1.8V_RU N_P
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC5206
PC5206
1 2
DY
DY
+1.8V_RU N_P + 1.8V_RUN
PG5203
PG5203
1 2
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG5204
PG5204
1 2
GAP-CLOS E-PWR
GAP-CLOS E-PWR
R1
5912_1.8V_RUN_FB
R2
1 2
PR5204
PR5204
13K3R2F -L1-GP
13K3R2F -L1-GP
Vout=0.8V*(R1+R2)/R2
5V, 1.5mA
SC1U10V3KX-3GP
SC1U10V3KX-3GP
PC520 1
PC5201
1 2
6
PU5201
PU5201
RUNPW ROK (49,51,89,90 )
PM_SLP_ S3# (21,37,41 ,42,49,89)
1.8V_VGA _RUN_EN (37,9 0)
1 2
DY
DY
PR5202
PR5202
0R2J-2-GP
0R2J-2-GP
PR5201
PR5201
1 2
2K2R2J-2 -GP
2K2R2J-2 -GP
1D8V_RU N_EN
1 2
DY
DY
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
7
POK
8
EN
APL5930 KAI-TRG-GP
APL5930 KAI-TRG-GP
P C5207
PC5207
VIN#5
VIN#9
VCNTL
VOUT#3
VOUT#4
GND
1
SSID = PWR.Plane.Regulator_1p8v
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
APL5930_+1.8V_RUN
APL5930_+1.8V_RUN
APL5930_+1.8V_RUN
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
52 95 Thu rsday, March 04, 2010
52 95 Thu rsday, March 04, 2010
52 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = PWR.Plane.Regulator_0P9v
D D
C C
SSID = PWR.Plane.Regulator_2p5v
B B
RT9013-25PB for +2.5V_RUN
+3.3V_RU N +2.5V_RU N
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
PC5301
PC5301
1 2
1 2
A A
5
4
PR5301
PR5301
0R0402-P AD
0R0402-P AD
2D5V_RU N_EN
PC5302
PC5302
1 2
DY
DY
SC1U10V3KX-3GP
SC1U10V3KX-3GP
CHECK CURRENT IS ENOUGH OR NOT (CPU)
PU5301
PU5301
1
VIN
2
GND
EN3NC#4
RT9013-2 5PB-GP
RT9013-2 5PB-GP
3
VOUT
5
4
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
PC5303
PC5303
1 2
1 2
+2.5V_RUN +/- 5%
PC530 4
PC5304
Design Current: 175mA
Peak current 250 mA
11/6
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
VREG : +CPU_VDDR&+2.5V_RUN
VREG : +CPU_VDDR&+2.5V_RUN
VREG : +CPU_VDDR&+2.5V_RUN
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
53 95 Thu rsday, March 04, 2010
53 95 Thu rsday, March 04, 2010
53 95 Thu rsday, March 04, 2010
1
A00
A00
A00
SSID = VIDEO
LVDS CONNECTOR
10/1
LCD1
LCD1
48
41
42
43
44
45
46
47
49
IPEX-CONN4 0-2R-GP-U
IPEX-CONN4 0-2R-GP-U
GFX_PW R_SRC +LCDV DD
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
51
3.3V_LCD _RUN
LCD_BRIGH TNESS
BLON_OU T_C
LCD_CBL _DET#_C
LCD_TST _C
LCD_DET _G
+3.3V_CA MERA
1 2
1 2
C5401
C5401
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
LVDSB_T X2 (55)
LVDSB_T X2# (55)
LVDSB_T X1 (55)
LVDSB_T X1# (55)
LVDSB_T X0 (55)
LVDSB_T X0# (55)
LVDSB_T XC (55)
LVDSB_T XC# (55)
LVDSA_T XC (55)
LVDSA_T XC# (55)
LVDSA_T X2 (55)
LVDSA_T X2# (55)
LVDSA_T X1 (55)
LVDSA_T X1# (55)
LVDSA_T X0 (55)
LVDSA_T X0# (55)
LVDS_DA TA (55 )
LVDS_CL K (55)
LCD_BRIGH TNESS
C5402
C5402
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+3.3V_RU N
1 2
DY
DY
10KR2J-3 -GP
10KR2J-3 -GP
DY
DY
R5405
R5405
100KR2J -1-GP
100KR2J -1-GP
1 2
0105-7
R5408
R5408
100KR2J -1-GP
100KR2J -1-GP
1 2
1120-1
R5401
R5401
R5402
R5402
USB_CAM ERA#
USB_CAM ERA
100R2J-2 - GP
100R2J-2 -GP
1 2
0208-2
3.3V_LCD _RUN
10/1
BLON_OU T_C
LCD_CBL _DET#_C
LCD_TST _C
LCD_DET _G
LBKLT_C TL (55)
DIS
DIS
1 2
R5404 0 R2J-2-GP
R5404 0 R2J-2-GP
1 2
R5407 0 R2J-2-GP
R5407 0 R2J-2-GP
UMA
UMA
RN5401
RN5401
1
8
2
7
3
6
4 5
SRN100J -4-GP
SRN100J -4-GP
0222-1
R5409
R5409
1 2
0R0603-P AD
0R0603-P AD
R5411
R5411
1 2
0R0603-P AD
0R0603-P AD
9/22
SRN2K2J -1-GP
SRN2K2J -1-GP
LVDS_CL K
LVDS_DA TA
+3.3V_RU N_VGA
+3.3V_RU N
USB_PN1 1 (21)
USB_PP1 1 (21)
+3.3V_RU N
1
2 3
RN5402
RN5402
4
BLON_OU T (37)
LCD_CBL _DET# (3 7)
LCD_TST (3 7)
SSID = Inverter
GFX_PW R_SRC
1 2
C5407
C5406
SC1KP50 V2KX-1GP
SC1KP50 V2KX-1GP
C5406
C5407
SCD1U50 V3KX-GP
SCD1U50 V3KX-GP
1 2
SSID = VIDEO
INVERTER POWER
Change Poly-fuse
F5401
F5401
1 2
POLYSW -1D1A24V-1-GP
POLYSW -1D1A24V-1-GP
Main:69.50007.A41
Second:69.50007.A31
LCD POWER
+PWR _SRC
20.F1093.040
20.F1093.040
R5414
R5414
0R0603-P AD
0R0603-P AD
EC5405
EC5405
Camera Power
+3.3V_CA MERA +3.3V_RU N
1 2
1 2
C5403
C5403
SC10U6D 3V5MX-3GP
DY
DY
SC10U6D 3V5MX-3GP
1231-1
1 2
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
Close to LVDS connector
LVDSB_T XC#
LVDSB_T XC
LVDSA_T XC#
LVDSA_T XC
EC5406
EC5406
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
DY
DY
1 2
EC5407
EC5407
1 2
EC5408
EC5408
DY
DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
1 2
DY
DY
EC5409
EC5409
LCDVDD_ EN (55)
1 2
LCD_BRIGH TNESS
1 2
DY
DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
LCD_TST
1 2
1 2
EC5401
EC5401
DY
DY
DY
DY
SC33P50V2JN-3GP
SC33P50V2JN-3GP
For EMI request
E C5402
EC5402
SC33P50V2JN-3GP
SC33P50V2JN-3GP
BAT54C-U -GP
BAT54C-U -GP
LCD_TST _EN (37)
D5401
D5401
3
1231-1
R5412
R5412
ENVDD ENVDD _D
SCD1U10V2KX-5GP
0R0402-P AD
0R0402-P AD
SCD1U10V2KX-5GP
C5409
C5409
1 2
DY
DY
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
LCD/Inverter Connector
LCD/Inverter Connector
LCD/Inverter Connector
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
1 2
1 2
R5413
R5413
49K9R2F-L-GP
49K9R2F-L-GP
U5401
U5401
OUT3IN#4
2
GND
1
EN
G5285T1 1U-GP
G5285T1 1U-GP
4
5
IN#5
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
+3.3V_RU N +LCDVDD
1 2
C5405
C5405
SC1U10V3KX-3GP
SC1U10V3KX-3GP
A00
A00
54 95 Thu rsday, March 04, 2010
54 95 Thu rsday, March 04, 2010
54 95 Thu rsday, March 04, 2010
A00
5
4
3
2
1
SSID = VIDEO
9/18
RN5501
RN5501
VGA_TXAOUT2- (13)
VGA_TXAOUT2+ (13)
D D
C C
VGA_TXACLK- (13)
VGA_TXACLK+ (13)
GPU_LVDSA_TX2# (82)
GPU_LVDSA_TX2 (82)
GPU_LVDSA_TXC# (82)
GPU_LVDSA_TXC (82)
VGA_TXAOUT0- (13)
VGA_TXAOUT1- (13) LVDSA_TX1# (54)
VGA_TXAOUT1+ (13)
GPU_LVDSA_TX0# (82)
GPU_LVDSA_TX0 (82)
GPU_LVDSA_TX1# (82)
GPU_LVDSA_TX1 (82)
UMA
UMA
DIS
DIS
UMA
UMA
DIS
DIS
6
7
8
SRN0J-7-GP
SRN0J-7-GP
RN5503
RN5503
4 5
3
2
1
SRN0J-7-GP
SRN0J-7-GP
RN5505
RN5505
6
7
8
SRN0J-7-GP
SRN0J-7-GP
RN5506
RN5506
4 5
3
2
1
SRN0J-7-GP
SRN0J-7-GP
4 5
3
2
1
6
7
8
4 5
3
2
1
6
7
8
LVDSA_TX2# (54)
LVDSA_TX2 (54)
LVDSA_TXC# (54)
LVDSA_TXC (54)
LVDSA_TX0# (54)
LVDSA_TX0 (54) VGA_TXAOUT0+ (13)
LVDSA_TX1 (54)
VGA_TXBOUT1- (13)
VGA_TXBOUT1+ (13)
VGA_TXBOUT2- (13)
VGA_TXBOUT2+ (13) LVDSB_TX2 (54)
GPU_LVDSB_TX1# (82)
GPU_LVDSB_TX1 (82)
GPU_LVDSB_TX2# (82)
GPU_LVDSB_TX2 (82)
VGA_TXBCLK- (13) LVDSB_TXC# (54)
VGA_TXBCLK+ (13) LVDSB_TXC (54)
VGA_TXBOUT0- (13)
VGA_TXBOUT0+ (13) LVDSB_TX0 (54)
GPU_LVDSB_TXC# (82)
GPU_LVDSB_TXC (82)
GPU_LVDSB_TX0# (82)
GPU_LVDSB_TX0 (82)
UMA
UMA
DIS
DIS
UMA
UMA
DIS
DIS
RN5507
RN5507
6
7
8
SRN0J-7-GP
SRN0J-7-GP
RN5508
RN5508
4 5
3
2
1
SRN0J-7-GP
SRN0J-7-GP
RN5509
RN5509
6
7
8
SRN0J-7-GP
SRN0J-7-GP
RN5510
RN5510
4 5
3
2
1
SRN0J-7-GP
SRN0J-7-GP
4 5
3
2
1
6
7
8
4 5
3
2
1
6
7
8
LVDSB_TX1# (54)
LVDSB_TX1 (54)
LVDSB_TX2# (54)
LVDSB_TX0# (54)
10/1
RN5502
B B
NB_LCDPWR_EN (13)
NB_BL_PWM (13)
NB_BL_EN (13)
VGA_LCDVDD_EN (82)
VGA_LBKLT_CTL (82)
VGA_BLEN (82)
A A
5
RN5502
6
7
8
UMA
UMA
SRN0J-7-GP
SRN0J-7-GP
RN5504
RN5504
8
7
6
DIS
DIS
SRN0J-7-GP
SRN0J-7-GP
4 5
3
2
1
1
2
3
4 5
4
LCDVDD_EN (54)
LBKLT_CTL (54)
PANEL_BKEN (37)
3
10/1
RN5512
RN5512
LDDC_CLK (13)
LDDC_DATA (13) LVDS_DATA (54)
GPU_LVDS_CLK (82)
GPU_LVDS_DATA (82)
1
2 3
SRN0J-6-GP
SRN0J-6-GP
UMA
UMA
RN5511
RN5511
2 3
1
SRN0J-6-GP
SRN0J-6-GP
DIS
DIS
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
4
4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LVDS_Switch
LVDS_Switch
LVDS_Switch
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
LVDS_CLK (54)
55 95 Thursday, March 04, 2010
55 95 Thursday, March 04, 2010
55 95 Thursday, March 04, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
56 95 Thu rsday, March 04, 2010
56 95 Thu rsday, March 04, 2010
56 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
SSID = VIDEO
PCIE_NTX_ GRX_P[12..15] (12)
PCIE_NTX_ GRX_N[12..15] (12)
HDMI DISCRETE/ UMA Co-lay
D D
C C
B B
PCIE_NTX_ GRX_N13
PCIE_NTX_ GRX_P13
PCIE_NTX_ GRX_N12
PCIE_NTX_ GRX_P12
PCIE_NTX_ GRX_N15
PCIE_NTX_ GRX_P15
PCIE_NTX_ GRX_N14
PCIE_NTX_ GRX_P14
PCIE_NTX_ GRX_P12
PCIE_NTX_ GRX_N12
PCIE_NTX_ GRX_P13
PCIE_NTX_ GRX_N13
PCIE_NTX_ GRX_P14
PCIE_NTX_ GRX_N14
PCIE_NTX_ GRX_P15
PCIE_NTX_ GRX_N15
9/15
5V Tolerance
NB_DDC_ CLK0 (13)
NB_DDC_ DATA0 (13)
GPU_HDM I_CLK (8 2)
GPU_HDM I_DATA (82)
1
2 3
1
2 3
HDMI CONNECTOR
PCIE_N_H_ TX_GRX_P[12..15] (80)
PCIE_N_H_ TX_GRX_N[12..15] (80 )
RN5708
RN5714
RN5714
SRN0J-6-G P
SRN0J-6-G P
UMA
UMA
RN5713
RN5713
SRN0J-6-G P
SRN0J-6-G P
DIS
DIS
RN5708
6
7
UMA
UMA
8
SRN0J-7-G P
SRN0J-7-G P
RN5710
RN5710
6
7
UMA
UMA
8
SRN0J-7-G P
SRN0J-7-G P
RN5706
RN5706
6
7
DIS
DIS
8
SRN0J-7-G P
SRN0J-7-G P
RN5712
RN5712
6
7
DIS
DIS
8
SRN0J-7-G P
SRN0J-7-G P
10/5
RN5701
RN5701
SRN4K7J -8-GP
SRN4K7J -8-GP
4
4
NB_HDMI_T X0N
4 5
NB_HDMI_T X0P
3
NB_HDMI_T XCN
2
NB_HDMI_T XCP
1
NB_HDMI_T X2N
4 5
NB_HDMI_T X2P
3
NB_HDMI_T X1N
2
NB_HDMI_T X1P
1
PCIE_N_H_ TX_GRX_P12
4 5
PCIE_N_H_ TX_GRX_N12
3
PCIE_N_H_ TX_GRX_P13
2
PCIE_N_H_ TX_GRX_N13
1
PCIE_N_H_ TX_GRX_P14
4 5
PCIE_N_H_ TX_GRX_N14
3
PCIE_N_H_ TX_GRX_P15
2
PCIE_N_H_ TX_GRX_N15
1
+5V_RUN
4
1
2 3
DDC_DAT A_HDMI
DDC_CLK _HDMI
NB_HDMI_T XCN
NB_HDMI_T XCP
NB_HDMI_T X0N
NB_HDMI_T X0P
NB_HDMI_T X1N
NB_HDMI_T X1P
NB_HDMI_T X2N
NB_HDMI_T X2P
HDMI_PCH_ DATA0# (82)
HDMI_PCH_ DATA0 (82)
HDMI_PCH_ CLK# (82)
HDMI_PCH_ CLK (82)
HDMI_PCH_ DATA2# (82)
HDMI_PCH_ DATA2 (82)
HDMI_PCH_ DATA1# (82)
HDMI_PCH_ DATA1 (82)
6
7
8
6
7
8
C5703
C5703
C5704
C5704
C5709
C5709
C5702
C5702
C5707
C5707
C5708
C5708
C5705
C5705
C5706
C5706
9/23
RN5707
RN5707
UMA
UMA
SRN0J-7-G P
SRN0J-7-G P
RN5709
RN5709
UMA
UMA
SRN0J-7-G P
SRN0J-7-G P
1 2
DIS
DIS
1 2
DIS
DIS
1 2
DIS
DIS
1 2
DIS
DIS
1 2
DIS
DIS
1 2
DIS
DIS
1 2
DIS
DIS
1 2
DIS
DIS
4 5
3
2
1
4 5
3
2
1
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SC D1U10 V2KX-5GP
SC D1U10 V2KX-5GP
SC D1U10 V2KX-5GP
SC D1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SC D1U10 V2KX-5GP
SC D1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
11/12-3
HDMI_CN_C LK#
HDMI_CN_C LK
HDMI_CN_D ATA0#
HDMI_CN_D ATA0
HDMI_CN_D ATA1#
HDMI_CN_D ATA1
HDMI_CN_D ATA2#
HDMI_CN_D ATA2
HDMI_CN_D ATA0#
HDMI_CN_D ATA0
HDMI_CN_C LK#
HDMI_CN_C LK
HDMI_CN_D ATA2#
HDMI_CN_D ATA2
HDMI_CN_D ATA1#
HDMI_CN_D ATA1
10/1
HDMI CONN
10/1
HDMI1
HDMI1
SKT-HDMI19 P - 6 9-GP
SKT-HDMI19 P-69-GP
22.10296.211
22
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23
1 2
R5715 499R2F-2-GP R5715 499R2F-2-GP
+5V_RUN
HDMI_CN_D ATA2
HDMI_CN_D ATA2#
HDMI_CN_D ATA1
HDMI_CN_D ATA1#
HDMI_CN_D ATA0
HDMI_CN_D ATA0#
HDMI_CN_C LK
HDMI_CN_C LK#
DDC_CLK _HDMI
DDC_DAT A_HDMI
HPD_HD M I_CON
AFTP570 9 AFT P5709
1
1 2
1 2
R5717 499R2F-2-GP R5717 499R2F-2-GP
R5716 499R2F-2-GP R5716 499R2F-2-GP
1
1
1
1 2
R5718 499R2F-2-GP R5718 499R2F-2-GP
1
1
1
1
1
1
1
1
AFTP570 7 AFT P5707
AFTP570 6 AFT P5706
AFTP571 3 AFT P5713
1 2
R5719 499R2F-2-GP R5719 499R2F-2-GP
HDMI_PLL_ GND
AFTP570 3 AFT P5703
AFTP570 5 AFT P5705
A FTP570 4A FT P5704
AFTP570 1 AFT P5701
A FTP570 2A FT P5702
AFTP571 1 AFT P5711
A FTP571 0A FT P5710
AFTP570 8 AFT P5708
1 2
R5720 499R2F-2-GP R5720 499R2F-2-GP
+5V_RUN
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AFTP571 2 AFT P5712
1
C5701
C5701
1 2
HDMI_CN_C LK#
HDMI_CN_C LK
HDMI_CN_D ATA0#
HDMI_CN_D ATA0
HDMI_CN_D ATA1#
HDMI_CN_D ATA1
HDMI_CN_D ATA2#
HDMI_CN_D ATA2
1 2
1 2
R5721 499R2F-2-GP R5721 499R2F-2-GP
R5722 499R2F-2-GP R5722 499R2F-2-GP
R5724
R5724
0R0402-P AD
0R0402-P AD
1 2
HDMI_PLL_ GATE
9/22
+3.3V_RU N
Q5702
Q5702
PMBS390 4-1-GP
PMBS390 4-1-GP
A A
HDMI_HPD_ DET (13,82)
5
3
1
2
1 2
R5713
R5713
10KR2J-3 -GP
10KR2J-3 -GP
R5710
R5710
1 2
150KR2J -L1-GP
150KR2J -L1-GP
DY
DY
4
HPD_HDM I_CON HPD_HDM I_1
1 2
R5712
R5712
200KR2J -L1-GP
200KR2J -L1-GP
3
2
1 2
R5714
R5714
100KR2J -1-GP
100KR2J -1-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
G
HDMI Level Shifter/Connector
HDMI Level Shifter/Connector
HDMI Level Shifter/Connector
ocument Nu mber Rev
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Q5703
Q5703
2N7002A -7-GP
2N7002A -7-GP
S D
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
57 95 Thu rsday, March 04, 2010
57 95 Thu rsday, March 04, 2010
57 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = User.Interface
D D
C C
SSID = Thermal
Fan Connector
B B
3 1
*Layout* 15 mil
EMC2102 _FAN_TACH (39)
EMC2102 _FAN_DRIVE (39)
A A
5
4
EMC2102 _FAN_TACH
EMC2102 _FAN_DRIVE
SC10U10 V5ZY-1GP
SC10U10 V5ZY-1GP
C5801
C5801
AFTP580 1 AFT P5801
2 1
1 2
D5801
D5801
CH551H-3 0PT-GP
CH551H-3 0PT-GP
1
3
FAN1
FAN1
5
3
2
1
4
FOX-CON3 -6-GP-U
FOX-CON3 -6-GP-U
20.D0210.103
20.F1293.003
AFTP580 2 AFT P5802
AFTP580 3 AFT P5803
EMC2102 _FAN_TACH
1
EMC2102 _FAN_DRIVE
1
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ITP/Fan Connector
ITP/Fan Connector
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
ITP/Fan Connector
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
58 95 Thu rsday, March 04, 2010
58 95 Thu rsday, March 04, 2010
58 95 Thu rsday, March 04, 2010
1
A00
A00
A00
SSID = SATA
SATA HDD Connector
9/24
HDD1
HDD1
+3.3V_RU N
+5V_RUN
SATA_TX P0 (22)
SATA_TX N0 (22)
SATA_RX P0 (22 )
SATA_RX N0 (22)
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
1 2
C5906
C5905
C5905
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C5906
1118-2
1 2
C5904
C5904
SC10U6D3V 5MX-3GP
SC10U6D3V5MX-3GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
C5901
C5901
P1
V33
P2
V33
P3
V33
P7
V5
P8
V5
P9
V5
P13
V12_1
P14
V12_2
P15
V12_3
S2
A+
S3
A-
S6
B+
S5
B-
SKT-SATA 7P-15P-17-GP
SKT-SATA 7P-15P-17-GP
62.10065.C71
GND
GND
GND
GND
GND
GND
GND
GND
DAS/DSS
16
16
17
17
18
18
S1
S4
S7
P4
P5
P6
P10
P12
P11
9/24
ODD Connector
ODD1
ODD1
8
NP1
S1
S2
S3
S4
S5
S6
S7
P1
P2
P3
P4
P5
P6
NP2
SKT-SATA 7P+6P-42-GP
SKT-SATA 7P+6P-42-GP
62.10065.581
9
SATA_TX P1 (2 2)
SATA_TX N1 (22)
SATA_RX N1 (22)
SATA_RX P1 (22)
SC10U10 V5ZY-1GP
SC10U10 V5ZY-1GP
SATA_RX- and SATA_RX+ Trace
Length match within 20 mil
+5V_RUN
C5909
C5909
1 2
1231-2
1 2
C5910
C5910
SC10U10 V5ZY-1GP
SC10U10 V5ZY-1GP
DY
DY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
HDD/ODD
HDD/ODD
HDD/ODD
59 95 Thu rsday, March 04, 2010
59 95 Thu rsday, March 04, 2010
59 95 Thu rsday, March 04, 2010
A00
A00
A00
5
SSID = AUDIO
4
3
2
1
EC6008
EC6008
1 2
AFTP600 6 AFT P6006
LINE1
OUT
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1
AUD_AGN D
X01 0713
LINEOUT1
LINEOUT1
6
5
2
4
1
3
7
8
PHONE-JK 383-GP
PHONE-JK 383-GP
22.10133.K31
Speaker
D D
AUD_SPK _L- (30)
AUD_SPK _L+ (30)
AUD_SPK _R- (30 )
AUD_SPK _R+ (3 0)
1 2
EC6001
EC6001
DY
DY
DY
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
C C
1 2
1 2
EC6002
EC6002
DY
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1 2
EC6003
EC6003
EC6004
EC6004
DY
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
Connector
SC100P50V2JN-3GP
SC100P50V2JN-3GP
AFTP600 1 AFT P6001
AFTP600 5 AFT P6005
AFTP600 7 AFT P6007
AFTP600 9 AFT P6009
AUD_SPK _L-
1
AUD_SPK _L+
1
AUD_SPK _R-
1
AUD_SPK _R+
1
5
1
2
3
4
6
0303-1
Main 20.F0693.004
SEC. 20.F0693.004
SPK1
SPK1
FOX-CON4 -24-GP
FOX-CON4 -24-GP
1
AUD_HP1 _JD# (30)
AUD_HP1 _JACK_L2 (30)
AUD_HP1 _JACK_R2 (30)
AFTP600 2 AFT P6002
AFTP600 3 AFT P6003
AFTP600 4 AFT P6004
AFTP600 8 AFT P6008
SC1KP50 V2KX-1GP
SC1KP50 V2KX-1GP
AUD_HP1 _JD#
1
AUD_HP1 _JACK_L1
1
AUD_HP1 _JACK_R1
1
AUD_HP1 _JACK_L2
AUD_HP1 _JACK_R2
1 2
EC6005
EC6005
BLM18BD 601SN1D-GP
BLM18BD 601SN1D-GP
L6001
L6001
1 2
1 2
L6002
L6002
BLM18BD 601SN1D-GP
BLM18BD 601SN1D-GP
1 2
EC6006
EC6006
SC1KP50 V2KX-1GP
SC1KP50 V2KX-1GP
600ohm 100MHz
200mA 0.5ohm DC
AUD_HP1 _JD#
AUD_HP1 _JACK_L1
EC6007
EC6007
1 2
0107-2
AUD_HP1 _JACK_R1
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1117-1
MIC IN
AUD_VRE FOUT_B (30)
RN6001
RN6001
SRN4K7J -8-GP
SRN4K7J -8-GP
B B
AUD_EXT _MIC_L (30)
AUD_EXT _MIC_R (30)
A A
AUD_EXT _MIC_L
AUD_EXT _MIC_R
C6001 S C1U10V3KX-3GP C 6001 SC1U10V 3KX-3GP
C6002 S C1U10V3KX-3GP C 6002 SC1U10V 3KX-3GP
AFTP601 1 AFT P6011
AFTP601 2 AFT P6012
AFTP601 3 AFT P6013
1 2
1 2
MIC_IN_L_C
1
MIC_IN_R_C
1
EXT_MIC_J D#
1
1
2 3
4
1 2
MIC_IN_L_2
MIC_IN_R_2
EXT_MIC_J D# (30)
C6003
C6003
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
R6001
R6001
0R0603-P AD
0R0603-P AD
R6002
R6002
1 2
0R0603-P AD
0R0603-P AD
MICIN1
MICIN1
8
7
3
1 2
MIC_IN_L_C
MIC_IN_R_C
EC6010
EC6010
1 2
1 2
EC6011
EC6011
SC100P50V2JN-3GP
SC100P50V2JN-3GP
AUD_AGN D
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1117-1
1
4
2
5
6
PHONE-JK 383-GP
PHONE-JK 383-GP
22.1
AFTP601 0 AFT P6010
1
0133.K31
X01
0713
Internal
Microphone
INT_MIC_L_R (30)
EC6009
EC6009
SC1KP50 V2KX-1GP
SC1KP50 V2KX-1GP
MIC1 is in DIP
MIC1 is in DIP
MIC1
MIC1
1
MICROPHON E-40-GP-U1
MICROPHON E-40-GP-U1
1 2
2
23.42
143.001
1117-1
R6005
R6005
1 2
0R2J-2-GP
0R2J-2-GP
R6004
R6004
1 2
0R2J-2-GP
0R2J-2-GP
R6003
R6003
1 2
DY
R6006
R6006
R6009
R6009
R6008
R6008
R6010
R6010
DY
1 2
DY
DY
1 2
1 2
DY
DY
1 2
DY
DY
<Core Design>
<Core Design>
<Core Design>
AUD_AGN D
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
5
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
Audio Jack
Audio Jack
Audio Jack
1
A00
A00
60 95 Thu rsday, March 04, 2010
60 95 Thu rsday, March 04, 2010
60 95 Thu rsday, March 04, 2010
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
61 95 Thu rsday, March 04, 2010
61 95 Thu rsday, March 04, 2010
61 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
SSID = Flash.ROM
D D
SPI FLASH ROM (16M bits) for KBC
-6
1 2
+KBC_PW R
C6202
C6202
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C6203
C6203
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1231-2
EC_SPI_CL K (37)
EC_SPI_DO (37 )
+KBC_PW R
1 2
1118-2
DY
DY
EC_SPI_W P#
1 2
4
RN6201
RN6201
SRN100K J-6-GP
SRN100K J-6-GP
1
2 3
EC_SPI_CS #
EC_SPI_DI_R
EC_SPI_HO LD#
U6201
U6201
1
CS#
2
DO/IO1
3
WP#/IO2
4
GND
W25Q 16BVSSIG-GP
W25Q 16BVSSIG-GP
VCC
HOLD#/IO3
CLK
DI/IO0
SC4D7P5 0V2CN-1GP
SC4D7P5 0V2CN-1GP
PN:72.25Q16.001
8
EC_SPI_HO LD#
7
6
EC_SPI_DO _R
5
EC6202
EC6202
+KBC_PW R
12
DY
DY
R6201
R6201
100KR2J -1-GP
100KR2J -1-GP
C C
EC_SPI_CS # (37)
EC_SPI_DI (3 7)
EC_SPI_W P#_R (37)
EC6201
SC4D7P5 0V2CN-1GP
SC4D7P5 0V2CN-1GP
EC6201
1231-1
R6202 0R0402-P AD R6202 0R0402-PAD
1 2
R6203 0R0402-P AD R6203 0R0402-PAD
1 2
12
100KR2J -1-GP
DY
DY
100KR2J -1-GP
R6207
R6207
1215-2
B B
1 2
C6201
C6201
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
R6204 33R2J-2-GP R6 204 33R2 J-2-GP
1 2
EC6203
EC6203
SC22P50 V2JN-4GP
SC22P50 V2JN-4GP
1117
SSID = RBATT
+3.3V_RT C_LDO
D6201
+RTC_CE LL
0105-8
R6205
R6205
1 2
0R0402-P AD
0R0402-P AD
1 2
C6204
A A
C6204
SC1U10V 3KX-3GP
SC1U10V 3KX-3GP
RTC_PW R_L
D6201
BAT54C-U -GP
BAT54C-U -GP
1 2
3
1225-5
RTC_PW R
1 2
1KR2J-1-G P
1KR2J-1-G P
Width=20mils
AFTP620 2 AFT P6202
5
RTC Connector
+RTC_VC C
R6206
R6206
AFTP620 3 AFT P6203
+RTC_VC C
1
4
1
1
2
NP1
NP2
BAT-CON2 -1-GP-U
BAT-CON2 -1-GP-U
62.70001.011
RTC1
RTC1
PWR
GND
NP1
NP2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Flash/RTC
Flash/RTC
Flash/RTC
1
A00
A00
62 95 Thu rsday, March 04, 2010
62 95 Thu rsday, March 04, 2010
62 95 Thu rsday, March 04, 2010
A00
5
SSID = USB
IO Board USB Power
4
3
2
1
Close to I/O connector
D D
9/30
at least 80 mil
1 2
C6301
C6301
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C C
USB_PWR_EN# (37)
CRT Board USB Power
U6302
U6302
GND
VIN
VIN
EN#
rt 2A
VOUT#8
VOUT#7
VOUT#6
Suppo
9/30
at least 80 mil
B B
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
USB_PWR_EN# (37)
C6303
C6303
1
2
3
4
UP7534BRA8-15-GP
UP7534BRA8-15-GP
Support 2A
U6301
U6301
1
GND
VIN
VIN
EN#
VOUT#8
VOUT#7
VOUT#6
OC#
2
3
4
UP7534BRA8-15-GP
UP7534BRA8-15-GP
8
7
6
5
at least 80 mil
USB_OC#0_1 (21)
Close to CRT Board connector
+5V_USB2 +5V_ALW
at least 80 mil
USB_OC#2_3 (21)
1 2
DY
DY
1231-2
OC#
8
7
6
5
+5V_USB1 +5V_ALW
1 2
C6302
C6302
DY
DY
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1231-2
C6304
C6304
SC1U10V3KX-3GP
SC1U10V3KX-3GP
1118-2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
USB Power SW
USB Power SW
USB Power SW
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
63 95 Thursday, March 04, 2010
63 95 Thursday, March 04, 2010
63 95 Thursday, March 04, 2010
1
5
D D
4
3
2
1
(Blanking)
C C
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
5
A4
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
64 95 Thursday, March 04, 2010
64 95 Thursday, March 04, 2010
64 95 Thursday, March 04, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
65 95 Thu rsday, March 04, 2010
65 95 Thu rsday, March 04, 2010
65 95 Thu rsday, March 04, 2010
A00
A00
A00
5
SSID = User.Interface
4
3
2
1
Power LED(White)
E
C
E
C
+5V_ALW
1 2
EC6601
EC6601
DY
DY
SC220P5 0V2KX-3GP
SC220P5 0V2KX-3GP
+5V_RUN
SATA_LE D_R
+5V_ALW
WHITE_ LED_BAT
DY
DY
DY
DY
0111-2
1 2
R6601 1KR2J-1-G P R 6601 1KR2J -1-GP
1 2
R6603 470R2J-2 -GP R6603 4 70R2J-2-GP
1 2
R6609 1KR2J-1-G P
R6609 1KR2J-1-G P
0111-2
1 2
EC6604
EC6604
SC220P5 0V2KX-3GP
SC220P5 0V2KX-3GP
0111-2
1 2
EC6602
EC6602
SC220P5 0V2KX-3GP
SC220P5 0V2KX-3GP
DY
DY
1 2
1 2
POWE R_SW_LED _B
POWE R_SW_LED _C
R6604 1KR 2J-1-GP R 6604 1K R2J-1-GP
BAT_W HITE
R6602 1KR 2J-1-GP R 6602 1K R2J-1-GP
PWR_ LED_B LED_PW R
0208-1
SATA_LE D
PWR_ LED_B
SATA_LE D
BAT_W HITE
BAT_AMB ER
10/8
LEDBD1
LEDBD1
7
1
2
3
4
5
6
8
ACES - C O N 6-13-GP
ACES-CON 6-13-GP
20.K0320.006
Q6602
9/25
D D
SATA_LE D# (22)
PWRL ED# (37)
AMBER_L ED#_KBC (37)
WHITE_ LED#_KBC (3 7)
1 2
C6601 SCD1U10 V2KX-5GP C6601 SCD 1U10V2KX-5GP
1 2
C6602 SCD1U10 V2KX-5GP C6602 SCD 1U10V2KX-5GP
C C
10/1
RN6601
RN6601
1
2 3
SRN15KJ - 3 - G P
SRN15KJ -3-GP
RN6602
RN6602
1
2 3
SRN15KJ - 3 - G P
SRN15KJ -3-GP
AMBER_L ED#_KBC
WHITE_ LED#_KBC
1116-7
SATA_LE D#_C
4
PWRL ED#_C
AMBER_L ED_BAT#
4
WHITE_ LED_BAT#
1215-3
PWRL ED#_C
9/25
SATA_LE D#_C
9/25
WHITE_ LED_BAT#
Q6602
R2
R2
B
R1
R1
PDTA143 ET-GP
PDTA143 ET-GP
84.00143.M11
84.00143.M11
SATA HDD LED(White)
Q6601
Q6601
R2
R2
R1
R1
PDTA143 ET-GP
PDTA143 ET-GP
E
C
B
84.00143.M11
84.00143.M11
Battery LED1(White)
Q6603
Q6603
R2
R2
B
R1
R1
PDTA143 ET-GP
PDTA143 ET-GP
84.00143.M11
84.00143.M11
Battery LED2(Amber)
Q6604
9/25
AMBER_L ED_BAT#
B B
Q6604
R2
R2
R1
R1
PDTA143 ET-GP
PDTA143 ET-GP
E
C
B
84.00143.M11
84.00143.M11
+5V_ALW
DY
DY
0111-2
1 2
R6606 1KR2J-1-GP R6606 1KR2J -1-GP
1 2
EC6603
EC6603
SC220P5 0V2KX-3GP
SC220P5 0V2KX-3GP
BAT_AMB ER AMBER_L ED_BAT
Power button LED(White)
1216-1
KBC_PW RBTN# (37)
+5V_ALW
Q6605
9/25
PWR_ BTN_LED# (37)
A A
1 2
R6607 15KR2J-1 -GP R6607 15KR2J -1-GP
PWR_ BTN_LED#_C
Q6605
R2
R2
R1
R1
PDTA143 ET-GP
PDTA143 ET-GP
E
C
B
84.00143.M11
84.00143.M11
POWE R_SW_LED _R
0208-1
1 2
R6610 1KR2J-1-G P
R6610 1KR2J-1-G P
1 2
SC180P50V2JN-1GP
SC180P50V2JN-1GP
R6608 1KR2J-1-G P
R6608 1KR2J-1-G P
EC6605
EC6605
1 2
DY
DY
DY
DY
DY
DY
POWE R_SW_LED _C
POWE R_SW_LED _B
1 2
R6605 0R0402-P AD R 6605 0R0402 -PAD
0208-1
KBC_PW RBTN#_C
POWE R_SW_LED _C
POWE R_SW_LED _B
9/16
5
4
3
PWRB TN1
PWRB TN1
5
1
2
3
4
6
ACES-CON 4-10-GP-U
ACES-CON 4-10-GP-U
20.K0320.004
20.K0320.004
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
LED Bard/Power Button
LED Bard/Power Button
LED Bard/Power Button
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
66 95 Thu rsday, March 04, 2010
66 95 Thu rsday, March 04, 2010
66 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
67 95 Thu rsday, March 04, 2010
67 95 Thu rsday, March 04, 2010
67 95 Thu rsday, March 04, 2010
A00
A00
A00
5
4
3
2
1
SSID = Touch.Pad SSID = KBC
D D
C C
Internal KeyBoard Connector TouchPad Connector
0111-1
KB1
KB1
31
32
ACES-CON 30-8-GP
ACES-CON 30-8-GP
1
1
KROW 7
2
KROW 6
3
KROW 4
4
KROW 2
5
KROW 5
6
KROW 1
7
KROW 3
8
KROW 0
9
KCOL5
10
KCOL4
11
KCOL7
12
KCOL6
13
KCOL8
14
KCOL3
15
KCOL1
16
KCOL2
17
KCOL0
18
KCOL12
19
KCOL16
20
KCOL15
21
KCOL13
22
KCOL14
23
KCOL9
24
KCOL11
25
KCOL10
26
27
28
29
30
AFTP680 1 AFT P6801
1
AFTP680 2 AFT P6802
1
AFTP680 3 AFT P6803
1
AFTP680 4 AFT P6804
1
AFTP680 5 AFT P6805
1
AFTP680 6 AFT P6806
1
AFTP680 7 AFT P6807
1
AFTP680 8 AFT P6808
1
AFTP680 9 AFT P6809
1
AFTP681 0 AFT P6810
1
AFTP681 1 AFT P6811
1
AFTP681 2 AFT P6812
1
AFTP681 3 AFT P6813
1
AFTP681 4 AFT P6814
1
AFTP681 5 AFT P6815
1
AFTP681 6 AFT P6816
1
AFTP681 7 AFT P6817
1
AFTP681 8 AFT P6818
1
AFTP681 9 AFT P6819
1
AFTP682 1 AFT P6821
1
AFTP682 3 AFT P6823
1
AFTP682 2 AFT P6822
1
AFTP682 4 AFT P6824
1
AFTP682 5 AFT P6825
1
AFTP682 6 AFT P6826
1
AFTP682 7 AFT P6827
1
AFTP682 8 AFT P6828
KB_DET# (37)
KROW [0..7] (37)
KCOL[0..16 ] (37)
TPCLK (37)
TPDATA (37 )
SC33P50 V2JN-3GP
SC33P50 V2JN-3GP
10/7
RN6801
RN6801
SRN10KJ -5-GP
SRN10KJ -5-GP
C6802
C6802
+5V_RUN
1
2 3
4
1 2
1 2
AFTP682 9 AFT P6829
AFTP683 0 AFT P6830
AFTP683 1 AFT P6831
AFTP682 0 AFT P6820
C6803
C6803
SC33P50 V2JN-3GP
SC33P50 V2JN-3GP
+5V_RUN
1
+5V_RUN
1
TPCLK
1
TPDATA
1
1 2
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
C6801
C6801
10/2
TPAD1
TPAD1
6
4
3
2
1
5
ACES-CON 4-10-GP-U
ACES-CON 4-10-GP-U
20.K0320.004
20.K0326.004
20.K0524.030
20.K0461.030
B B
KB Backlight Connector
0208-2
L6801
F6801
F6801
1 2
DY
SC10U10V5KX-2GP
SC10U10V5KX-2GP
DY
FUSE-D5A 6V-2-GP
FUSE-D5A 6V-2-GP
5
1 2
C6804
C6804
DY
DY
A A
KB_BL_C TRL (37 )
KB_LED_ PWR
DY
DY
1 2
1 2
BLM18PG 181SN1D-GP
BLM18PG 181SN1D-GP
R6801
R6801
100KR2J -1-GP
100KR2J -1-GP
L6801
DY
DY
KB_BL_C TRL#
Q6801
Q6801
D
D
D
1
2
3 4
D
D
D
D
D
G
S
G
S
DY
DY
SI3456DDV -T1-GE 3 - G P
SI3456DDV -T1-GE3-GP
1 2
C6805
C6805
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
DY
DY
KB_LED_ BL_DET (3 7)
6
5
+5V_KB_ BL +5V_R UN
EC6802
SC10P50V2JN-4GPDYEC6802
SC10P50V2JN-4GP
1 2
DY
DY
0225-2
4
EC6801
SC10P50V2JN-4GPDYEC6801
SC10P50V2JN-4GP
1 2
20.K0320.004
20.K0320.004
KBLIT1
KBLIT1
5
1
2
3
4
DY
DY
6
ACES-CON 4-10-GP-U
ACES-CON 4-10-GP-U
+5V_KB_ BL
KB_LED_ BL_DET
KB_BL_C TRL#
1
AFTP683 5 AFT P6835
3
1
AFTP683 2 AFT P6832
1
AFTP683 3 AFT P6833
1
AFTP683 4 AFT P6834
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Key Board/Touch Pad
Key Board/Touch Pad
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Key Board/Touch Pad
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
68 95 Thu rsday, March 04, 2010
68 95 Thu rsday, March 04, 2010
68 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = Hall.Sensor
D D
9/29
AFTP6901 AFTP6901
AFTP6902 AFTP6902
+3.3V_ALW
1
LID_CLOSE#_1
1
+3.3V_ALW
9/29 11/9
C C
+3.3V_ALW
1 2
R6901
R6901
DY
DY
100KR2J-1-GP
100KR2J-1-GP
9/17
1231-1
LID_CLOSE# (37)
LID_CLOSE#
1 2
DY
DY
C6902
C6902
SCD047U16V2KX-1-GP
SCD047U16V2KX-1-GP
R6902 0R0402-PAD R6902 0R0402-PAD
1 2
LID_CLOSE#_1
74.06781.07B
B B
1 2
C6903
C6903
0208-3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HALLSW1
HALLSW1
1
VDD
3
OUTPUT
SOT23-2D8-213H56-COLAY-GP
SOT23-2D8-213H56-COLAY-GP
<Core Design>
<Core Design>
<Core Design>
GND
AFTP6903 AFTP6903
2
1
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
cument Number Rev
A4
A4
A4
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Do
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Hall Effect Sensor
Hall Effect Sensor
Hall Effect Sensor
69 95 Thursday, March 04, 2010
69 95 Thursday, March 04, 2010
69 95 Thursday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = Debug
D D
+3.3V_RUN
DB1
DB1
LPC_LAD0 (20,37)
LPC_LAD1 (20,37)
LPC_LAD2 (20,37)
LPC_LAD3 (20,37)
LPC_LFRAME# (20,37)
PLTRST#_LAN_WLAN (20,76,78)
PCLK_FWH (20,24)
C C
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
1
2
3
4
5
6
7
DY
DY
8
9
10
11
12
MLX-CON10-7-GP
MLX-CON10-7-GP
20.D0183.110
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
cument Number Rev
A4
A4
A4
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Do
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Dubug connector
Dubug connector
Dubug connector
70 95 Thursday, March 04, 2010
70 95 Thursday, March 04, 2010
70 95 Thursday, March 04, 2010
1
A00
A00
A00
5
D D
4
3
2
1
(Blanking)
C C
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
RESERVED
RESERVED
RESERVED
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
71 95 Thursday, March 04, 2010
71 95 Thursday, March 04, 2010
71 95 Thursday, March 04, 2010
1
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
RESERVED
RESERVED
RESERVED
1
72 95 Thu rsday, March 04, 2010
72 95 Thu rsday, March 04, 2010
72 95 Thu rsday, March 04, 2010
A00
A00
A00
5
SSID = User.Interface
4
3
2
1
D D
AFTP730 1 AFT P7301
AFTP730 2 AFT P7302
AFTP730 4 AFT P7304
AFTP730 5 AFT P7305
AFTP731 4 AFT P7314
USB_PP9 (21)
USB_PN9 (21)
BT_ACT (76)
BLUETOO TH_EN (37)
C C
WLAN _ACT (76)
Bluetooth Module conn.
BT1
BT1
15
BLUETOO TH_DET#
1
WLAN _ACT
BDC_ON
1
BLUETOO TH_EN
BT_LED
1
BLUETOO TH_GPIO3
1
BLUETOO TH_GPIO5
1
USB_PP9
USB_PN9
BT_ACT
BLUETOO TH_EN
WLAN _ACT
11
13
NP1
2
1
4
3
6
5
8
7
10
9
12
14
NP2
16
HRS-CONN 14D-GP-U
HRS-CONN 14D-GP-U
BT_ACT
USB_PP9
USB_PN9
1
AFTP731 3 AFT P7313
AFTP731 6 AFT P7316
AFTP731 7 AFT P7317
AFTP731 5 AFT P7315
AFTP731 8 AFT P7318
AFTP731 9 AFT P7319
AFTP732 0 AFT P7320
WLAN _ACT
1
BLUETOO TH_EN
1
BT_ACT
1
+3.3V_RU N
1
USB_PP9
1
USB_PN9
1
+3.3V_RU N
1 2
C7301
C7301
SC2D2U6 D3V3KX-GP
SC2D2U6 D3V3KX-GP
1118-2
1 2
DY
DY
R7303
R7303
100KR2J-1-GP
100KR2J-1-GP
B B
1 2
1 2
EC7302
EC7302
R7304
R7304
10KR2J-3-GP
10KR2J-3-GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
Bluetooth
Bluetooth
Bluetooth
1
73 95 Thu rsday, March 04, 2010
73 95 Thu rsday, March 04, 2010
73 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
C C
4
3
2
1
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
1
74 95 Thu rsday, March 04, 2010
74 95 Thu rsday, March 04, 2010
74 95 Thu rsday, March 04, 2010
A00
A00
A00
5
D D
4
3
2
1
(Blanking)
C C
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
5
A4
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
2
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
75 95 Thursday, March 04, 2010
75 95 Thursday, March 04, 2010
75 95 Thursday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = Int.Conn
10/9
IOBD1
IOBD1
D D
ESATA USB
USB PORT
WLAN USB
C C
WWAN PCIE
WWAN PCIE WWAN CLK
SMBUS
+DC_IN_SS
WWAN_RADIO_DIS# (37)
LAN PCIE
B B
LAN PCIE
USB_PP0 (21)
USB_PN0 (21)
USB_PP5 (21)
USB_PN5 (21)
USB_PN1 (21)
USB_PP1 (21)
USB_PP4 (21)
USB_PN4 (21)
E51_RXD (37)
E51_TXD (37)
PCIE_RXP2 (12)
PCIE_RXN2 (12)
PCIE_TXP2 (12)
PCIE_TXN2 (12)
SB_SMBDATA (18,19)
SB_SMBCLK (18,19)
WIFI_RF_EN (37)
WWAN_CLK_REQ# (7)
PSID_DISABLE# (37)
8103_GPO (37)
PCIE_RXP1 (12)
PCIE_RXN1 (12)
PCIE_TXP1 (12)
PCIE_TXN1 (12)
1216-2
85
86
2 1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
83
82
ACES-CONN80D-G P
ACES-CONN80D-GP
20.F1009.080
NP1
84
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
NP2
0208-2
SATA_TXN2 (22)
SATA_TXP2 (22)
SATA_RXN2 (22)
SATA_RXP2 (22)
PCIE_TXP0 (12)
PCIE_TXN0 (12)
PCIE_RXP0 (12)
PCIE_RXN0 (12)
CLK_PCIE_WLAN (7)
CLK_PCIE_WLAN# (7)
CLK_PCIE_LAN (7)
CLK_PCIE_LAN# (7)
CLK_PCIE_WWAN (7)
CLK_PCIE_WWAN# (7)
at least 80 mil
PM_LAN_ENABLE (37)
PLTRST#_LAN_WLAN (20,70,78)
WLAN_CLK_REQ# (7)
PCIE_WAKE# (21)
BT_ACT (73)
WLAN_ACT (73)
PSID_EC (37)
SATA(ESATA)
SATA(ESATA) WWAN USB
WLAN PCIE
WLAN PCIE
WLAN CLK
LAN CLK
+5V_USB1
+5V_ALW
+3.3V_RUN
+3.3V_ALW
+1.5V_RUN
<Core Design>
<Core Design>
<Core Design>
A A
0107-6
DY
DY
1 2
C7602 SC 10P50V2JN-4GP
C7602 SC 10P50V2JN-4GP
1 2
C7601 SC10P50V2JN-4GP
C7601 SC10P50V2JN-4GP
DY
DY
5
USB_PP5
USB_PN5
Title
Title
Title
IO Board Connector
IO Board Connector
Size Document Number Rev
Size Document Number Rev
Size Do
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
cument Number Rev
A4
A4
A4
2
IO Board Connector
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
76 95 Thursday, March 04, 2010
76 95 Thursday, March 04, 2010
76 95 Thursday, March 04, 2010
1
5
4
3
2
1
SSID = Int.Conn
10/1
11/12-5
L7703
L7703
L7702
L7702
L7701
L7701
1 2
1 2
1 2
C7703
C7703
1 2
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
BLM18BB 220SN-GP
C7707
C7707
DY
DY
SC8P250V2CC-GP
SC8P250V2CC-GP
BLM18BB 220SN-GP
BLM18BB 220SN-GP
BLM18BB 220SN-GP
BLM18BB 220SN-GP
BLM18BB 220SN-GP
1 2
0108-2
D D
RN7713
RN7713
SRN150F -1-GP
SRN150F -1-GP
1116-8
678
4 5
CRT_G CRT_GRE EN
CRT_B
1 2
C7706
C7706
DY
DY
SC8P250V2CC-GP
123
SC8P250V2CC-GP
1 2
C7705
C7705
DY
DY
SC8P250V2CC-GP
SC8P250V2CC-GP
C7702
C7702
CRT_RED CRT_R
CRT_GRE EN
CRT_BLU E
1 2
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
C7704
C7704
1 2
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
CRT Board Connector
CRTBD1
CRTBD1
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
ACES-CON 20-1-GP-U
ACES-CON 20-1-GP-U
20.F0772.020
20.F0772.020
at least 80 mil
CRT_RED
CRT_GRE EN
CRT_BLU E
CRT_HSYNC _CON
CRT_VSYNC _CON
CRT_DDC CLK_CON
CRT_DDC DATA_CON
USB_PN2 (21)
USB_PP2 (21)
USB_PN3 (21)
USB_PP3 (21)
Pin define modified
1117-3
+5V_USB 2
+5V_RUN
USB PORT
USB PORT
CRT RGB
CRT H/VSYNC
CRT SMBUS
0208-4
CRT_RED
CRT_GRE EN
CRT_BLU E
1
AFTP770 1 AFT P7701
1
AFTP770 2 AFT P7702
1
AFTP770 3 AFT P7703
SEC. 20.F1035.020
CRT RGB
C C
VGA_CRT _RED (82)
VGA_CRT _GREEN (82)
VGA_CRT _BLUE (82)
9/18
M_BLUE (13)
M_GREEN (1 3)
M_RED (13)
Close to CRT Board CONN
RN7701
RN7701
1
8
2
7
3
6
DIS
DIS
4 5
SRN0J-7-G P
SRN0J-7-G P
RN7702
RN7702
1
8
2
7
3
6
UMA
UMA
4 5
SRN0J-7-G P
SRN0J-7-G P
Filter design on CRT Board
CRT_R
CRT_G
CRT_B
CRT Hsync & Vsync level shift
3.3V Tolerance
VGA_CRT _HSYNC (80,82)
VGA_CRT _VSYNC (80,82 )
14
5 6
7
CRT DDCDATA & DDCCLK
4
1
2 3
+3.3V_RU N
9/29
U7702
U7702
5
6
DMN66D0 LDW-7-GP
DMN66D0 LDW-7-GP
VGA_HSYNC (13)
VGA_VSYNC (13)
3.3V Tolerance
14
3 4
2
1
CRT_DDC DATA_CON
CRT_DDC CLK_CON
9 8
7
B B
9/29
RN7712
RN7712
SRN2K2J -1-GP
SRN2K2J -1-GP
CRT_DDC DATA_CON_C
CRT_DDC CLK_CON_C
5V T
9/18
VGA_CRT _DDCCLK (82)
VGA_CRT _DDCDATA (82)
olerance
DDC_DAT A_CON (1 3)
DDC_CLK _CON (1 3)
RN7709
RN7709
SRN0J-6-G P
SRN0J-6-G P
1
2 3
UMA
UMA
RN7710
RN7710
SRN0J-6-G P
SRN0J-6-G P
1
2 3
DIS
DIS
4
4
5V Tolerance
Pull High 5V Design on CRT Board
Close to CRT Board CONN
+5V_RUN _CRT
1 2
14
1
U7701A
U7701A
CRT_HSYNC _OUT
CRT_VSYNC _OUT
13
U7701D
U7701D
NB_HSYNC_ OUT
TSAHCT1 25PW-GP
TSAHCT1 25PW-GP
NB_VSYNC_ OUT
4
U7701B
U7701B
TSAHCT1 25PW-GP
TSAHCT1 25PW-GP
+5V_RUN _CRT
12 11
10
U7701C
U7701C
TSAHCT1 25PW-GP
TSAHCT1 25PW-GP
2 3
TSAHCT1 25PW-GP
TSAHCT1 25PW-GP
7
14
7
C7701
C7701
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
SRN33J-5 -GP-U
SRN33J-5 -GP-U
9/15
0108-2
1120-2
RN7705
RN7705
4
DIS
DIS
RN7711
RN7711
4
UMA
UMA
SRN0J-6-G P
SRN0J-6-G P
+5V_RUN _CRT
1
2 3
2 3
1
D7701
D7701
2 1
CH551H-3 0PT-GP
CH551H-3 0PT-GP
CRT_HSYNC _CON
CRT_VSYNC _CON
+5V_RUN
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
ize D
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
S
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
CRT Board Connector
CRT Board Connector
CRT Board Connector
77 95 Thu rsday, March 04, 2010
77 95 Thu rsday, March 04, 2010
77 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
SSID = SDIO
D D
Card Reader connector
+3.3V_RUN
CARDBD1
CARDBD1
C C
1116-9
PLTRST#_LAN_WLAN (20,70,76)
USB_PN10 (21)
USB_PP10 (21)
1
2
3
4
5
6
MLX-CON6-21-GP
MLX-CON6-21-GP
7
8
20.F1035.006
B B
10/7
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CARD Reader CONN
CARD Reader CONN
CARD Reader CONN
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
5
Size Document Number Rev
Size Document Number Rev
Size Do
Date: Sheet of
Date: Sheet of
4
3
Date: Sheet of
cument Number Rev
A4
A4
A4
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
78 95 Thursday, March 04, 2010
78 95 Thursday, March 04, 2010
78 95 Thursday, March 04, 2010
1
5
H2
H1
H1
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
D D
1
H10
H10
HOLE335 R115-GP
HOLE335 R115-GP
1
DY
DY
H2
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
1
CPU Thermal module hole GPU Thermal module hole
HTML1
HTML1
HOLE197 R166-GP
HOLE197 R166-GP
1
DY
DY
H3
H3
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
1
HTML2
HTML2
HOLE197 R166-GP
HOLE197 R166-GP
1
DY
DY
H4
H4
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
HTML3
HTML3
HOLE197 R166-GP
HOLE197 R166-GP
1
DY
DY
4
H6
H6
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
1
1
H7
H7
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
1
HGPU1
HGPU1
STF237R 117H83-1-GP
STF237R 117H83-1-GP
1
3
H8
H8
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
1
0210-2
stand off
H9
H9
HTE95BE 95R29-R-5-GP
HTE95BE 95R29-R-5-GP
1
HBT1
HBT1
STF237R 117H123-GP
STF237R 117H123-GP
1
H5
H5
HOLE256 R111-GP
HOLE256 R111-GP
1
H11
H11
HOLE256 R111-GP
HOLE256 R111-GP
1
2
1
EMI Reserve
C C
+PWR _SRC +VGA_CO RE +3.3V_RU N
1 2
EC7901
EC7901
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1 2
1 2
EC7902
EC7902
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC7904
EC7904
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
1 2
EC7903
EC7903
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1 2
EC7905
EC7905
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
1 2
EC7906
EC7906
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1 2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1118-2
EC7907
EC7907
10/6
DY
DY
1 2
EC7910
EC7910
SCD1U25V2KX-GP
SCD1U25V2KX-GP
+5V_ALW
1 2
DY
DY
EC7911
EC7911
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY
DY
SPR1
DY
DY
SPR1
SPRING-58-GP
SPRING-58-GP
1
1 2
EC7912
EC7912
SCD1U25V2KX-GP
SCD1U25V2KX-GP
10/5
EMI Reserve
+PWR _SRC +3.3 V_RUN
B B
DY
DY
SC10P50V2JN-4GP
SC10P50V2JN-4GP
EC7924
EC7924
1 2
1118-2 RF Team Solution
1 2
C7909
C7909
SC56P50V2JN-2GP
SC56P50V2JN-2GP
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
DY
DY
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C7906
C7906
EC7916
EC7916
1 2
1117-4
EC7920
EC7920
C7905
C7905
DY
DY
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
1 2
1 2
DY
DY
SC10P50V2JN-4GP
SC10P50V2JN-4GP
+1.5V_RU N +3.3V_AL W +5V_RUN
1 2
SC56P50V2JN-2GP
SC56P50V2JN-2GP
EC7923
EC7923
C7904
C7904
DY
DY
SC10P50V2JN-4GP
SC10P50V2JN-4GP
+3.3V_RU N +5V_R UN + 5V_RUN +VCC_ CORE +5V_R UN +PWR_S RC +5V_ RUN +1.5V_RUN
EC7919
1 2
EC7917
EC7917
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
1 2
1 2
EC7922
EC7922
EC7915
EC7915
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
1 2
1 2
EC7919
EC7921
EC7921
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
1 2
1 2
EC7914
EC7914
EC7913
EC7913
DY
DY
SC10P50 V2JN-4GP
SC10P50 V2JN-4GP
1 2
EC7918
EC7918
0106-3 RF Team Solution 0108-1 EMC reserved
EC7927
EC7927
+1.5V_SU S
1 2
EC7926
EC7926
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
EC7925
EC7925
+PWR _SRC
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
C7922
C7922
1 2
C7902
C7902
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
C7917
C7917
SC56P50V2JN-2GP
SC56P50V2JN-2GP
+PWR _SRC
1 2
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
0224-1
A A
+15V_AL W
1 2
DY
DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
C7907
C7907
DY
DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1 2
C7915
C7915
DY
DY
SCD1U25V2KX-GP
SCD1U25V2KX-GP
5
1 2
C7911
C7911
+1.1V_RU N
1 2
C7910
C7910
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
C7908
C7908
SC56P50V2JN-2GP
SC56P50V2JN-2GP
+1.8V_RU N
1 2
SC56P50V2JN-2GP
SC56P50V2JN-2GP
C7919
C7919
+3.3V_RU N
1 2
SC56P50V2JN-2GP
SC56P50V2JN-2GP
C7920
C7920
4
+1.5V_SU S
1 2
C7921
C7921
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
+PWR _SRC +DC_IN_SS + SDC_IN
EC7930
EC7930
1 2
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
3
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
0225-5
EC7931
EC7931
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
EC7929
EC7929
1 2
DY
DY
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1 2
EC7932
EC7932
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
79 95 Thu rsday, March 04, 2010
79 95 Thu rsday, March 04, 2010
79 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
PCIE_N_H_ TX_GRX_P[12..15] (57)
PCIE_N_H_ TX_GRX_N[12..15] (57)
PCIE_NTX_ GRX_P[0..11] (12)
D D
C C
B B
PCIE_NTX_ GRX_N[0..11] (12)
CLK_PCIE_ VGA (7)
CLK_PCIE_ VGA# (7)
PCIE_NTX_ GRX_P0
PCIE_NTX_ GRX_N0
PCIE_NTX_ GRX_P1
PCIE_NTX_ GRX_N1
PCIE_NTX_ GRX_P2
PCIE_NTX_ GRX_N2
PCIE_NTX_ GRX_P3
PCIE_NTX_ GRX_N3
PCIE_NTX_ GRX_P4
PCIE_NTX_ GRX_N4
PCIE_NTX_ GRX_P5
PCIE_NTX_ GRX_N5
PCIE_NTX_ GRX_P6
PCIE_NTX_ GRX_N6
PCIE_NTX_ GRX_P7
PCIE_NTX_ GRX_N7
PCIE_NTX_ GRX_P8
PCIE_NTX_ GRX_N8
PCIE_NTX_ GRX_P9
PCIE_NTX_ GRX_N9
PCIE_NTX_ GRX_P10
PCIE_NTX_ GRX_N10
PCIE_NTX_ GRX_P11
PCIE_NTX_ GRX_N11
PCIE_N_H_ TX_GRX_P12
PCIE_N_H_ TX_GRX_N12
PCIE_N_H_ TX_GRX_P13
PCIE_N_H_ TX_GRX_N13
PCIE_N_H_ TX_GRX_P14
PCIE_N_H_ TX_GRX_N14
PCIE_N_H_ TX_GRX_P15
PCIE_N_H_ TX_GRX_N15
1204-3
DIS_Park/Mad
DIS_Park/Mad
1 2
R8018 10KR2F-2 -GP
R8018 10KR2F-2 -GP
0105-3
Remove
PWRG OOD PCIE_CALR N
VGA_RST #
VGA1A
VGA1A
AA38
PCIE_RX0P
Y37
PCIE_RX0N
Y35
PCIE_RX1P
W36
PCIE_RX1N
W38
PCIE_RX2P
V37
PCIE_RX2N
V35
PCIE_RX3P
U36
PCIE_RX3N
U38
PCIE_RX4P
T37
PCIE_RX4N
T35
PCIE_RX5P
R36
PCIE_RX5N
R38
PCIE_RX6P
P37
PCIE_RX6N
P35
PCIE_RX7P
N36
PCIE_RX7N
N38
PCIE_RX8P
M37
PCIE_RX8N
M35
PCIE_RX9P
L36
PCIE_RX9N
L38
PCIE_RX10P
K37
PCIE_RX10N
K35
PCIE_RX11P
J36
PCIE_RX11N
J38
PCIE_RX12P
H37
PCIE_RX12N
H35
PCIE_RX13P
G36
PCIE_RX13N
G38
PCIE_RX14P
F37
PCIE_RX14N
F35
PCIE_RX15P
E37
PCIE_RX15N
AB35
PCIE_REFCLKP
AA36
PCIE_REFCLKN
AJ21
NC#AJ21
AK21
NC#AK21
AH16
PWRGOOD
AA30
PERST#
MADISON-PRO -2-GP
MADISON-PRO -2-GP
CLOCK
CLOCK
10/8
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
4
1 OF 8
1 OF 8
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
CALIBRATION
CALIBRATION
PCIE_CALRP
PCIE_CALRN
DIS_GPU
DIS_GPU
PCIE_NRX_ GTX_P[0..15] (12 )
PCIE_NRX_ GTX_N[0..15] (12)
x01 change tolerant 20091117
PEG_C_R XP0
C8001 S CD1U10V2KX-5G P
C8001 S CD1U10V2KX-5G P
Y33
Y32
W33
W32
U33
U32
U30
U29
T33
T32
T30
T29
P33
P32
P30
P29
N33
N32
N30
N29
L33
L32
L30
L29
K33
K32
J33
J32
K30
K29
H33
H32
Y30
Y29
PEG_C_R XN0
PEG_C_R XP1
PEG_C_R XN1
PEG_C_R XP2
PEG_C_R XN2
PEG_C_R XP3
PEG_C_R XN3
PEG_C_R XP4
PEG_C_R XN4
PEG_C_R XP5
PEG_C_R XN5
PEG_C_R XP6
PEG_C_R XN6
PEG_C_R XP7
PEG_C_R XN7
PEG_C_R XP8
PEG_C_R XN8
PEG_C_R XP9
PEG_C_R XN9
PEG_C_R XP10
PEG_C_R XN10
PEG_C_R XP11
PEG_C_R XN11
PEG_C_R XP12
PEG_C_R XN12
PEG_C_R XP13
PEG_C_R XN13
PEG_C_R XP14
PEG_C_R XN14
PEG_C_R XP15
PEG_C_R XN15
PCIE_CALR P
1K27R2F -L-GP
1K27R2F -L-GP
1 2
DIS
DIS
C8002 S CD1U10V2KX-5G P
C8002 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8003 S CD1U10V2KX-5G P
C8003 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8004 S CD1U10V2KX-5G P
C8004 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8005 S CD1U10V2KX-5G P
C8005 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8006 S CD1U10V2KX-5G P
C8006 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8008 S CD1U10V2KX-5G P
C8008 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8007 S CD1U10V2KX-5G P
C8007 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8009 S CD1U10V2KX-5G P
C8009 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8010 S CD1U10V2KX-5G P
C8010 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8011 S CD1U10V2KX-5G P
C8011 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8012 S CD1U10V2KX-5G P
C8012 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8013 S CD1U10V2KX-5G P
C8013 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8014 S CD1U10V2KX-5G P
C8014 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8016 S CD1U10V2KX-5G P
C8016 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8015 S CD1U10V2KX-5G P
C8015 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8018 S CD1U10V2KX-5G P
C8018 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8017 S CD1U10V2KX-5G P
C8017 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8020 S CD1U10V2KX-5G P
C8020 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8019 S CD1U10V2KX-5G P
C8019 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8021 S CD1U10V2KX-5G P
C8021 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8022 S CD1U10V2KX-5G P
C8022 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8023 S CD1U10V2KX-5G P
C8023 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8024 S CD1U10V2KX-5G P
C8024 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8025 S CD1U10V2KX-5G P
C8025 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8026 S CD1U10V2KX-5G P
C8026 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8028 S CD1U10V2KX-5G P
C8028 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8027 S CD1U10V2KX-5G P
C8027 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8030 S CD1U10V2KX-5G P
C8030 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8029 S CD1U10V2KX-5G P
C8029 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8032 S CD1U10V2KX-5G P
C8032 S CD1U10V2KX-5G P
1 2
DIS
DIS
C8031 S CD1U10V2KX-5G P
C8031 S CD1U10V2KX-5G P
1 2
DIS
DIS
R8017
R8017
DIS
DIS
1 2
1 2
R8019 2 KR2F-3-GP
R8019 2 KR2F-3-GP
DIS
DIS
3
PCIE_NRX_ GTX_P0
PCIE_NRX_ GTX_N0
PCIE_NRX_ GTX_P1
PCIE_NRX_ GTX_N1
PCIE_NRX_ GTX_P2
PCIE_NRX_ GTX_N2
PCIE_NRX_ GTX_P3
PCIE_NRX_ GTX_N3
PCIE_NRX_ GTX_P4
PCIE_NRX_ GTX_N4
PCIE_NRX_ GTX_P5
PCIE_NRX_ GTX_N5
PCIE_NRX_ GTX_P6
PCIE_NRX_ GTX_N6
PCIE_NRX_ GTX_P7
PCIE_NRX_ GTX_N7
PCIE_NRX_ GTX_P8
PCIE_NRX_ GTX_N8
PCIE_NRX_ GTX_P9
PCIE_NRX_ GTX_N9
PCIE_NRX_ GTX_P10
PCIE_NRX_ GTX_N10
PCIE_NRX_ GTX_P11
PCIE_NRX_ GTX_N11
PCIE_NRX_ GTX_P12
PCIE_NRX_ GTX_N12
PCIE_NRX_ GTX_P13
PCIE_NRX_ GTX_N13
PCIE_NRX_ GTX_P14
PCIE_NRX_ GTX_N14
PCIE_NRX_ GTX_P15
PCIE_NRX_ GTX_N15
+1.0V_RUN_VGA
2
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
STRAPS
TX_PWRS_ENB
RESERVED
VGA_DIS
RESERVED
BIOS_ROM_EN
VIP_DEVICE_S TRAP_EN
RSVD
PIN
GPIO0
GPIO1 TX_DEEMPH_EN
GPIO2 BIF_GEN2_EN_A 0
GPIO5 GPIO5_AC_BATT
GPIO8 RESERVED
GPIO[13:11] ROMIDCFG[2:0]
GPIO21 RESERVED
GPIO_22_ROMCSB
V2SYNC
H2SYNC 0
GENERICC 0 RSVD
HSYNC X AUD[1]
DESCRIPTION O F DEFAULT SETT INGS
Transmitter Power Savings Enable
0: 50% Tx output swing 1 : Full Tx output swing
PCIE TRANSMITTER DE-EMPHASIS ENABLED
0:Tx de-emphasis disabled 1: Tx de-emphasis enabled
0:Advertises the PCIe device as 2.5 GT/s capable at power on.
1:Advertises the PCIe device as 5.0 GT/s capable at power on.
optional input allow the system to request a fast
power reduction by setting GPIO5 to low.
0:VGA Controller capacity enabled
1:The device won't be recog nized as the system's VGA con troller
BIOS_ROM_EN=1, Config[2:0] defines the ROM type
BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size
0:Disable external BIOS ROM device
VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is con nected on the VIP Host inte rface.
1:Enable external BIOS ROM device
RESERVED
RESERVED
AUD[1:0]:11-Audio for both DisplayPort and HDMI
VSYNC X AUD[0]
PIN STRAPS
DY
DY
R8001 3 KR2J-2-GP
R8001 3 KR2J-2-GP
TX_PW RS_ENB (82 )
TX_DEEM PH_EN (82)
BIF_GEN2_ EN_A (82)
GPIO8_ROMS O (82)
VGA_DIS (82)
CONFIG0 (8 2)
CONFIG1 (8 2)
CONFIG2 (8 2)
VGA_CRT _VSYNC (77,82 )
VGA_CRT _HSYNC (77,82)
VSYNC_DAC 2 (82)
HSYNC_DAC 2 (82)
BIOS_ROM_ EN (82 )
GPIO5_AC_ BATT (82)
GPIO21_BB _EN (82 )
1 2
DY
DY
R8002 3 KR2J-2-GP
R8002 3 KR2J-2-GP
1 2
DY
DY
R8003 1 0KR2J-3-GP
R8003 1 0KR2J-3-GP
1 2
DY
DY
R8004 1 0KR2J-3-GP
R8004 1 0KR2J-3-GP
1 2
DY
DY
R8005 1 0KR2J-3-GP
R8005 1 0KR2J-3-GP
1 2
DIS
DIS
R8006 1 0KR2J-3-GP
R8006 1 0KR2J-3-GP
1 2
DY
DY
R8007 1 0KR2J-3-GP
R8007 1 0KR2J-3-GP
1 2
DY
DY
R8008 1 0KR2J-3-GP
R8008 1 0KR2J-3-GP
1 2
RN8001
RN8001
1
2 3
DIS
DIS
DY
DY
R8012 1 0KR2J-3-GP
R8012 1 0KR2J-3-GP
1 2
DY
DY
R8013 1 0KR2J-3-GP
R8013 1 0KR2J-3-GP
1 2
DY
DY
R8014 1 0KR2J-3-GP
R8014 1 0KR2J-3-GP
1 2
DY
DY
R8015 1 0KR2J-3-GP
R8015 1 0KR2J-3-GP
1 2
DY
DY
R8016 1 0KR2J-3-GP
R8016 1 0KR2J-3-GP
1 2
1
RECOMMEN DED SETTINGS
0= DO NOT INS TALL RESISTOR
1 = INSTALL 3 K RESISTOR
X = DESIGN DEP ENDANT
NA = NOT AP PLICABLE
RECOMMEND
PLATFORM
SETTING
X
X
?
0
0 GPIO9
0 0 1
X X X
(256MB)
0
X
X
+3.3V_RUN_VGA
4
SRN10KJ -5-GP
SRN10KJ -5-GP
0105-3
1
1
0
0
0
0
0
0
0
0
0
1
1
A A
PLTRST# _NB_GPU (13,20,37 )
1 2
R8021 0R0402-P AD R 8021 0R0402 -PAD
5
C8033
C8033
SCD1U10 V2KX-5GP
SCD1U10 V2KX-5GP
1 2
DY
DY
10/7
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU_PCIE/STRAPPING(1/5)
GPU_PCIE/STRAPPING(1/5)
Size D
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
GPU_PCIE/STRAPPING(1/5)
ocument Nu mber Rev
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
80 95 Thu rsday, March 04, 2010
80 95 Thu rsday, March 04, 2010
80 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
VGA1C
MDA[0..31] ( 85) MDB[0..31] ( 87)
D D
MDA[32..63] (86)
C C
+1.5V_RUN
DIS_Mad
DIS_Mad
1 2
DIS_Park/Mad
DIS_Park/Mad
1 2
DIS_Mad
DIS_Mad
1 2
DIS
DIS
R8110
R8110
1 2
243R2F-2-GP
243R2F-2-GP
DIS_Mad
DIS_Mad
R8111
R8111
1 2
243R2F-2-GP
243R2F-2-GP
DIS_Mad
R8112
R8112
1 2
243R2F-2-GP
243R2F-2-GP
DIS_Mad
B B
MEM_CALRN0
R8104 243R2F-2-G P
R8104 243R2F-2-G P
MEM_CALRN1
R8106 243R2F-2-G P
R8106 243R2F-2-G P
MEM_CALRN2
R8107 243R2F-2-GP
R8107 243R2F-2-GP
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MVREFDA
MVREFSA
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
VGA1C
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
L18
L20
L27
N12
AG12
M12
M27
AH12
MADISON-PRO -2-GP
MADISON-PRO -2-GP
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
MVREFDA
MVREFSA
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
10/8 10/8
DDR2
DDR2
GDDR3/GDDR5
GDDR3/GDDR5
DDR3
DDR3
MEMORY INTERFACE A
MEMORY INTERFACE A
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7
DDBIA0_0/QSA_0#/WDQSA_0
DDBIA0_1/QSA_1#/WDQSA_1
DDBIA0_2/QSA_2#/WDQSA_2
DDBIA0_3/QSA_3#/WDQSA_3
DDBIA1_0/QSA_4#/WDQSA_4
DDBIA1_1/QSA_5#/WDQSA_5
DDBIA1_2/QSA_6#/WDQSA_6
DDBIA1_3/QSA_7#/WDQSA_7
1204-1
1 2
R8113
R8113
Ra Ra
100R2F-L1-GP- U
100R2F-L1-GP- U
DIS_MEMVREF_M96/M ad
DIS_MEMVREF_M96/M ad
1 2
1 2
DIS_M96/Mad
DIS_M96/Mad
R8117
R8117
DIS_M96/Mad
DIS_M96/Mad
100R2F-L1-GP- U
100R2F-L1-GP- U
Rb Rb Rb Rb
C8104
C8104
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
DDR3/GDDR3 Memory Stuff Option(Mad/Park)
GDDR3
GDDR5
1.5V
40.2R
100R
1.8V/1.5V
40.2R
100R
MVDDQ
Ra
A A
Rb
3 OF 8
3 OF 8
DDR2
DDR2
GDDR5/GDDR3
GDDR5/GDDR3
DDR3
DDR3
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
WCKA0_0/DQMA_0
WCKA0#_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0#_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1#_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1#_1/DQMA_7
GDDR5/DDR2/GDDR3
GDDR5/DDR2/GDDR3
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0#
CLKA1#
RASA0#
RASA1#
CASA0#
CASA1#
CSA0#_0
CSA0#_1
CSA1#_0
CSA1#_1
CKEA0
CKEA1
WEA0#
WEA1#
MAA0_8
MAA1_8
GDDR5
GDDR5
DIS_GPU
DIS_GPU
CLKA0
CLKA1
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7
A34
E30
E26
C20
C16
C12
J11
F8
J21
G19
H27
G27
J14
H14
K23
K19
K20
K17
K24
K27
M13
K16
K21
J20
K26
L15
H23
J19
MAA0 (85,86)
MAA1 (85,86)
MAA2 (85,86)
MAA3 (85,86)
MAA4 (85,86)
MAA5 (85,86)
MAA6 (85,86)
MAA7 (85,86)
MAA8 (85,86)
MAA9 (85,86)
MAA10 (85,86)
MAA11 (85,86)
MAA12 (85,86)
A_BA2 (85,86)
A_BA0 (85,86)
A_BA1 (85,86)
DQMA0 (85)
DQMA1 (85)
DQMA2 (85)
DQMA3 (85)
DQMA4 (86)
DQMA5 (86)
DQMA6 (86)
DQMA7 (86)
QSAP_0 (85)
QSAP_1 (85)
QSAP_2 (85)
QSAP_3 (85)
QSAP_4 (86)
QSAP_5 (86)
QSAP_6 (86)
QSAP_7 (86)
QSAN_0 (85 )
QSAN_1 (85 )
QSAN_2 (85 )
QSAN_3 (85 )
QSAN_4 (86 )
QSAN_5 (86 )
QSAN_6 (86 )
QSAN_7 (86 )
ODTA0 (85)
ODTA1 (86)
CLKA0 (85)
CLKA0# (85)
CLKA1 (86)
CLKA1# (86)
RASA0# (85)
RASA1# (86)
CASA0# (85)
CASA1# (86)
CSA0#_0 ( 85)
CSA1#_0 ( 86)
CKEA0 (85)
CKEA1 (86)
WEA0# (85)
WEA1# (86)
MAA13 (85,86)
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
1 2
R8114
R8114
100R2F-L1-GP- U
100R2F-L1-GP- U
DIS_MEMVREF_M96/M ad
DIS_MEMVREF_M96/M ad
1 2
1 2
DIS_M96/Mad
DIS_M96/Mad
R8118
R8118
DIS_M96/Mad
DIS_M96/Mad
100R2F-L1-GP- U
100R2F-L1-GP- U
C8105
C8105
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
x01 Change tolerant 20091117
1 2
R8115
R8115
100R2F-L1-GP- U
100R2F-L1-GP- U
Ra Ra
DIS_MEMVREF
DIS_MEMVREF
1 2
R8119
R8119
DIS
DIS
100R2F-L1-GP- U
100R2F-L1-GP- U
DDR3/GDDR3 Memory Stuff Option(M96/M92)
DDR3
1.5V
40.2R
100R
MVDDQ
Ra 40.2R
Rb
Reserved for JTAG
1KR2J-1-GP
1KR2J-1-GP
DIS_M96
DIS_M96
1215-4
1 2
DIS
DIS
C8106
C8106
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
GDDR3
1.8V
100R
MDB[32..63] (88)
+3.3V_RUN_VG A
DIS_Mad
DIS_Mad
R8122
R8122
DDR3
1.5V
100R
100R
R8121
R8121
10KR2J-3-GP
10KR2J-3-GP
1 2
1 2
RN8101
RN8101
SRN4K7J-8-G P
SRN4K7J-8-G P
+1.5V_RUN +1.5V_R UN +1.5V_RUN +1.5V_RUN
1 2
R8116
R8116
100R2F-L1-GP- U
100R2F-L1-GP- U
DIS_MEMVREF
DIS_MEMVREF
1 2
R8120
R8120
DIS
DIS
100R2F-L1-GP- U
100R2F-L1-GP- U
TEST_EN
1
2 3
DIS_M96
DIS_M96
4
MVREFSB MVREFDB MVREFSA MVREFDA
1 2
DIS
DIS
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MVREFDB
MVREFSB
CLKTESTA
CLKTESTB
C8107
C8107
VGA1D
VGA1D
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
Y12
AA12
AD28
AK10
AL10
MADISON-PRO -2-GP
MADISON-PRO -2-GP
DDR2
DDR2
GDDR3/GDDR5
GDDR3/GDDR5
DDR3
DDR3
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
MVREFDB
MVREFSB
TESTEN
CLKTESTA
CLKTESTB
4 OF 8
4 OF 8
DDR2
DDR2
GDDR5/GDDR3
GDDR5/GDDR3
DDR3
DDR3
P8
MAB0_0/MAB_0
T9
MAB0_1/MAB_1
P9
MAB0_2/MAB_2
N7
MAB0_3/MAB_3
N8
MAB0_4/MAB_4
N9
MAB0_5/MAB_5
U9
MAB0_6/MAB_6
U8
MAB0_7/MAB_7
Y9
MAB1_0/MAB_8
W9
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
WCKB0_0/DQMB_0
WCKB0#_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0#_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1#_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1#_1/DQMB_7
MEMORY INTERFACE B
MEMORY INTERFACE B
GDDR5/DDR2/GDDR3
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7
DDBIB0_0/QSB_0#/WDQSB_0
DDBIB0_1/QSB_1#/WDQSB_1
DDBIB0_2/QSB_2#/WDQSB_2
DDBIB0_3/QSB_3#/WDQSB_3
DDBIB1_0/QSB_4#/WDQSB_4
DDBIB1_1/QSB_5#/WDQSB_5
DDBIB1_2/QSB_6#/WDQSB_6
DDBIB1_3/QSB_7#/WDQSB_7
AC8
AC9
AA7
AA8
MAB1_5/BA2
Y8
MAB1_6/BA0
AA9
MAB1_7/BA1
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
T7
ADBIB0/ODTB0
W7
ADBIB1/ODTB1
L9
CLKB0
L8
CLKB0#
AD8
CLKB1
AD7
CLKB1#
T10
RASB0#
Y10
RASB1#
W10
CASB0#
AA10
CASB1#
P10
CSB0#_0
L10
CSB0#_1
AD10
CSB1#_0
AC10
CSB1#_1
U10
CKEB0
AA11
CKEB1
N10
WEB0#
AB11
WEB1#
T8
MAB0_8
W8
MAB1_8
DRAM_RST
AH11
DRAM_RST#
GDDR5
GDDR5
DIS_GPU
DIS_GPU
This basic topology should be used for DRAM_RST for
**
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
Designator
R_MEM_1
R_MEM_2
R_MEM_3
C_MEM
**
1 2
R8105
R8105
R_MEM_1
10KR2J-3-GP
10KR2J-3-GP
DIS_ V RAMRST
DIS_VRAMRST
MAB0 (87,88)
MAB1 (87,88)
MAB2 (87,88)
MAB3 (87,88)
MAB4 (87,88)
MAB5 (87,88)
MAB6 (87,88)
MAB7 (87,88)
MAB8 (87,88)
MAB9 (87,88)
MAB10 (87,88)
MAB11 (87,88)
MAB12 (87,88)
B_BA2 (87,88)
B_BA0 (87,88)
B_BA1 (87,88)
DQMB0 (87)
DQMB1 (87)
DQMB2 (87)
DQMB3 (87)
DQMB4 (88)
DQMB5 (88)
DQMB6 (88)
DQMB7 (88)
QSBP_0 (87)
QSBP_1 (87)
QSBP_2 (87)
QSBP_3 (87)
QSBP_4 (88)
QSBP_5 (88)
QSBP_6 (88)
QSBP_7 (88)
QSBN_0 (87 )
QSBN_1 (87 )
QSBN_2 (87 )
QSBN_3 (87 )
QSBN_4 (88 )
QSBN_5 (88 )
QSBN_6 (88 )
QSBN_7 (88 )
ODTB0 (87)
ODTB1 (88)
CLKB0 (87)
CLKB0# (87)
CLKB1 (88)
CLKB1# (88)
RASB0# (87)
RASB1# (88)
CASB0# (87)
CASB1# (88)
CSB0#_0 (87)
CSB1#_0 (88)
CKEB0 (87)
CKEB1 (88)
WEB0# (87)
WEB1# (88)
MAB13 (87,88)
R_MEM_2
1 2
DIS_VRAMRST
DIS_VRAMRST
R8103 0R2J-2-G P
R8103 0R2J-2-G P
** **
For Mannhatton
68pF
51R
DNI
10K
+1.5V_RUN
**
DY
DY
1 2
C_MEM
C8103
C8103
SC2200P50V2KX-2G P
SC2200P50V2KX-2G P
DIS_VRAMRST
DIS_VRAMRST
1 2
R_MEM_3
R8102
R8102
2K2R2J-2-GP
2K2R2J-2-GP
For M96-M2
1218-2
10K
0R/Short
DNI
2.2nF
MEM_RST (85,86,87,88)
X02-20091218
5
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Title
Title
Title
GPU_Memory(2/5)
GPU_Memory(2/5)
GPU_Memory(2/5)
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Berry
Berry
Berry
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O.C.
1
A00
A00
81 95 Thursday, March 04, 2010
81 95 Thursday, March 04, 2010
81 95 Thursday, March 04, 2010
A00
5
MEMORY ID Table
DVPDATA[0:3]
1000
0000
DVPDATA[0:3] Default:Pull down
D D
2N7002EDW -GP
2N7002EDW -GP
Q8203
Q8203
84.27002.F3F DIS
84.27002.F3F DIS
H_THERMT RIP# (10,2 1,37,39,42)
THERMTRIP_VG A_GATE (37 )
R8202 10KR2J-3-GP
R8202 10KR2J-3-GP
1 2
DIS
DIS
R8201 10KR2J-3-GP
R8201 10KR2J-3-GP
1 2
DIS
DIS
C C
+3.3V_RUN_VG A
R8205
R8205
DIS
DIS
10KR2J-3-GP
10KR2J-3-GP
1 2
JTAG_TMS_VGA
Madison Only
JTAG SIGNAL OPTION
Signal
N
ormal
mode
"1"(PU) TESTEN "1"(PU)
"0"(PD) "1"(PU) JTAG_TRST#
JTAG_TCK
CLK
JTAG_TMS
B B
+1.8V_RUN_VG A
+1.0V_RUN_VG A
A A
+1.8V_RUN_VG A
(1.8V@120mA DPLL_PVDD For M96)
L8201
L8201
( 1.8V@75mA DPLL_PVDD For Madison)
DIS
DIS
1 2
BLM18PG471SN1D- GP
BLM18PG471SN1D- GP
470ohm, 1A
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
L8207 BLM18PG471SN1D -GP
L8207 BLM18PG471SN1D -GP
1 2
C8205
C8205
DY
DY
(1.1V@150mA DPLL_VDDC For M96)
(1.0V@125mA DPLL_VDDC For Madison)
DIS
DIS
1 2
hm, 1A
470o
C8220
C8220
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
L8204
L8204
DIS
DIS
1 2
BLM15BD121SS1D- GP
BLM15BD121SS1D- GP
120ohm, 0.3A
C8223
C8223
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
Description
DDR3 Hynix-H5TQ1G63BFR-12C (80 0MHz)
Samsung-K4W1G1646E-HC12 (800M Hz)
DDR3
G
THERMTRIP_VG A
DIS
DIS
THERMTRIP_R
5
6
123 4
VGA_BLEN
JTAG_TRST #_VGA
1 2
DY
DY
10KR2J-3-GP
10KR2J-3-GP
R8208
R8208
DDC channel for LVDS
Straps
TX_PWRS _ENB (80)
TX_DEEMPH_EN (80)
BIF_GEN2_EN_A (80)
GPIO5_AC_BATT (80 )
GPIO8_ROMSO (80 )
VGA_DIS (80)
CONFIG0 (80)
CONFIG1 (80)
CONFIG2 (80)
GPIO21_BB_EN (80)
BIOS_ROM_EN (80)
CLK_VGA_27M_SS (7)
Debug
mode
"1"(PU)
"1"(PU) "1"(PU)
C8218
C8218
1 2
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
DY
DY
(1.8V@20mA TSVDD For M96)
(1.8V@5mA TSVDD For Madison)
1 2
DY
DY
5
1215-5
DPLL_PVDD
C8219
C8219
SCD1U 10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DIS
DIS
DPLL_VDDC
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8222
C8222
1 2
1 2
C8221
C8221
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
TSVDD
C8224
C8224
DIS
DIS
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
1 2
C8225
C8225
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
1 2
DIS
DIS
THERMTRIP_VG A# ( 37)
Q8202
Q8202
2N7002A-7-GP
2N7002A-7-GP
S D
GPU_LVDS_DA TA ( 55)
R8204
R8204
1 2
DIS
DIS
0R2J-2-GP
0R2J-2-GP
1 2
C8229 SCD1U1 0V2KX-5GP
C8229 SCD1U1 0V2KX-5GP
+1.8V_RUN_VG A
1 2
DIS
DIS
1 2
R8217
R8217
249R2F-GP
249R2F-GP
DIS
DIS
1215-5
CLK_VGA_27M_NSS (7)
DIS
DIS
1204-2
GPU_LVDS_CL K (55 )
PWRCN TL_0 (89)
PWRCN TL_1 (89)
DY
DY
R8216
R8216
499R2F-2-GP
499R2F-2-GP
DIS
DIS
R8221
R8221
1 2
0R2J-2-GP
0R2J-2-GP
MEM_ID Control
+1.8V_RUN_VG A
10/1
10/5
RN8201
RN8201
SRN4K7J-8-G P
SRN4K7J-8-G P
VGA_BLEN (55)
10/7
GPU_VREFG
C8217
C8217
SCD1U 10V2KX-5GP
SCD1U10V2KX-5GP
1 2
SCD1U10V2KX-5GPDYC8230
SCD1U10V2KX-5GP
XO_IN
+3.3V_RUN_VG A
TP8207 TPAD14-GP TP8207 TPAD14-GP
TP8208 TPAD14-GP TP8208 TPAD14-GP
TP8203
TP8203
TP8209
TP8209
TP8225 TPAD14-GP TP8225 TPAD14-GP
TP8202 TPAD14-GP TP8202 TPAD14-GP
TP8205 TPAD14-GP TP8205 TPAD14-GP
TP8206 TPAD14-GP TP8206 TPAD14-GP
TP8211 TPAD14-GP TP8211 TPAD14-GP
TP8218 TPAD14-GP TP8218 TPAD14-GP
TP8219 TPAD14-GP TP8219 TPAD14-GP
TP8212 TPAD14-GP TP8212 TPAD14-GP
TP8220 TPAD14-GP TP8220 TPAD14-GP
TP8221 TPAD14-GP TP8221 TPAD14-GP
4
VRAMDIS_Hynix
VRAMDIS_Hynix
R8207 10KR2J-3-GP
R8207 10KR2J-3-GP
1 2
1
TP8224 TPAD14-GP TP8224 TPA D14-GP
1
TP8222 TPAD14-GP TP8222 TPA D14-GP
1
TP8223 TPAD14-GP TP8223 TPA D14-GP
1
2 3
DIS
DIS
RN
RN
4
0R4P2R-PAD
0R4P2R-PAD
RN8202
RN8202
DIS
DIS
1
1
TPAD14-GP
TPAD14-GP
1
TPAD14-GP
TPAD14-GP
1
1
1
1
1
1
1
1
1
1
1
HDMI_HPD_DE T (13,57)
PLACE VREFG DIVIDER AND CAP
CLOSE TO ASIC
DPLL_VDDC
11/6
80D6R2F-L-G P
80D6R2F-L-G P
R8211
R8211
1 2
C8230
R8220
R8220
1 2
150R2F-1-GP
150R2F-1-GP
1 2
DY
R8210 0R2J-2 -GP
R8210 0R2J-2 -GP
DY
DY
VGA_THERMD A (39)
VGA_THERMD C (39)
TP8214 TPAD14-GP TP8214 TPA D14-GP
1
4
GPU_LVDS_CL K_C
12 34
GPU_LVDS_DA TA_C
GPIO6_VGA
VPIO14_VGA
GPIO16_SSIN
GPIO18_VGA
THERMTRIP_VG A
PEG_CLKREQ#
JTAG_TRST #_VGA
JTAG_TDI_VGA
JTAG_TCK_VG A
JTAG_TMS_VGA
JTAG_TDO_V GA
GENERICE_HP D4
DPLL_PVDD
DIS
DIS
DIS
DIS
1 2
DY
DY
TSVDD
MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
0107-5
GEN_A
GEN_B
GENERICC
GENERICD
GENERICF
GENERICG
1113-3
XTALIN
XTALOUT
XO_IN
1 2
C8226
C8226
SC470P50V2JN-G P
SC470P50V2JN-G P
FAN_PWM
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
AK26
AJ26
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
AK24
AH13
AM32
AN32
AN31
AV33
AU34
AW34
AW35
1204-2
AF29
AG29
AK32
AL31
AJ32
AJ33
C8227
C8227
XTALIN
1 2
DY
DY
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
1218-1
VGA1B
VGA1B
10/8
MUTI GFX
MUTI GFX
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
I2C
I2C
SCL
SDA
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCS#
GPIO_23_CLKREQ#
JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG
HPD1
VREFG
DPLL_PVDD
DPLL_PVSS
DPLL_VDDC
PLL/CLOCK
PLL/CLOCK
XTALIN
XTALOUT
XO_IN
XO_IN2
DPLUS
THERMAL
THERMAL
DMINUS
TS_FDO
TS_A
TSVDD
TSVSS
MADISON-PRO -2-GP
MADISON-PRO -2-GP
X8201
X8201
DY
DY
2 3
XTAL-27MHZ- 85-GP
XTAL-27MHZ- 85-GP
1 2
R8222 1MR2J-1-GP
R8222 1MR2J-1-GP
DY
DY
4 1
DPA
DPA
DPB
DPB
DPC
DPC
DPD
DPD
DAC1
DAC1
DAC2
DAC2
DDC/AUX
DDC/AUX
2 OF 8
2 OF 8
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N
TX4P_DPD1P
TX4M_DPD1N
TX5P_DPD0P
TX5M_DPD0N
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
COMP
H2SYNC
V2SYNC
VDD2DI
VSS2DI
A2VDD
A2VDDQ
A2VSSQ
R2SET
DDC1CLK
DDC1DATA
AUX1P
AUX1N
DDC2CLK
DDC2DATA
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
DDC6CLK
DDC6DATA
DDCCLK_AUX7P
DDCDATA_AUX7N
DIS_GPU
DIS_GPU
XTALOUT
1 2
DY
DY
3
AU24
AV23
AT25
AR24
AU26
AV25
AT27
AR26
AR30
AT29
AV31
AU30
AR32
AT31
AT33
AU32
AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16
AU20
AT19
AT21
AR20
AU22
AV21
AT23
AR22
AD39
R
AD37
R#
AE36
G
AD35
G#
AF37
B
AE38
B#
AC36
AC38
GPU_RSET
AB34
AD34
AE34
AC33
AC34
AC30
R2
AC31
R2#
AD30
G2
AD31
G2#
AF30
B2
AF31
B2#
AC32
C
AD32
Y
AF32
AD29
AC29
(1.8V@40mA VDD2DI For M96)
AG31
(1.8V@50mA VDD2DI For Madison)
AG32
AG33
AD33
AF33
R2SET
AA29
AM26
AN26
AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30
AL29
AM29
AN21
AM21
AJ30
AJ31
AK30
AK29
C8228
C8228
SC18P50V2JN-1- GP
SC18P50V2JN-1- GP
3
2
HDMI_PCH_CLK (57)
HDMI_PCH_CLK # (57)
HDMI_PCH_DA TA0 (57)
HDMI_PCH_DA TA0# (57)
HDMI_PCH_DA TA1 (57)
HDMI_PCH_DA TA1# (57)
HDMI_PCH_DA TA2 (57)
HDMI_PCH_DA TA2# (57)
JTAG_TCK_VG A
R8219
R8219
1 2
DY
DY
10KR2J-3-GP
10KR2J-3-GP
10/5
VGA_CRT_R ED (77)
VGA_CRT_GR EEN (77)
+3.3V tolerant
VGA_CRT_H SYNC (77,80)
VGA_CRT_VSYN C (77,8 0)
DIS
DIS
1 2
R8214 499R 2F-2-GP
R8214 499R 2F-2-GP
AVDD
VDD1DI
(3.3V@65mA A2VDD For M96)
(3.3V@130mA A2VDD For Madison)
DIS
DIS
1 2
715R2F-GP
715R2F-GP
R8218
R8218
VGA_CRT_D DCCLK (77)
VGA_CRT_D DCDATA ( 77)
GPU_HDMI_CLK (57)
GPU_HDMI_DAT A (57)
VGA_CRT_BLU E ( 77)
VGA_CRT_R ED
VGA_CRT_GR EEN
VGA_CRT_BLU E
HSYNC_DAC 2 (80)
VSYNC_DAC2 (80)
+1.8V_RUN_VG A
+3.3V_RUN_VG A
A2VDDQ
DDC channel for CRT
DDC channel for HDMI
RN8204
RN8204
1
2
DIS
DIS
3
4 5
SRN150F-1-G P
SRN150F-1-G P
10/1
8
7
6
DDC1/DDC2/DDC6 have 5V-tolerant
Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or
b) 27MHz (1.8V) oscillator connected to XTALIN or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
2
LVDS Interface
10/8
VGA1G
VGA1G
LVDS CONTROL
LVDS CONTROL
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
LVTMDP
LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
MADISON-PRO -2-GP
MADISON-PRO -2-GP
+1.8V_RUN_VG A
L8202
L8202
DIS
DIS
1 2
BLM15BD121SS1D- GP
BLM15BD121SS1D- GP
120ohm, 0.3A
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
(1.8V@45mA VDD1DI For M96)
L8203
L8203
(1.8V@45mA VDD1DI For Madison)
DIS
DIS
1 2
BLM15BD121SS1D- GP
BLM15BD121SS1D- GP
120ohm, 0.3A
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
DIS
DIS
1 2
R8203 0R3J-0 -U-GP
R8203 0R3J-0 -U-GP
7 OF 8
7 OF 8
AK27
VARY_BL
AJ27
DIGON
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
TXOUT_U3P
AG36
TXOUT_U3N
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
TXOUT_L3P
AP37
TXOUT_L3N
(1.8V@70mA AVDD For M96)
(1.8V@70mA AVDD For Madison)
C8201
C8201
C8202
C8202
(1.8V@20mA A2VDDQ For M96)
(1.8V@1.5mA A2VDDQ For Madison)
1 2
1 2
C8203
C8203
DIS
DIS
DIS
DIS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C8206
C8206
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8212
C8212
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
10/1
RN8203
RN8203
2 3
1
4
DIS
DIS
SRN10KJ-5-G P
SRN10KJ-5-G P
VGA_LBKLT_CTL (55)
VGA_LCDVDD _EN (55)
GPU_LVDSB_T XC (55)
GPU_LVDSB_T XC# (55)
GPU_LVDSB_T X0 (55)
GPU_LVDSB_T X0# (55)
GPU_LVDSB_T X1 (55)
GPU_LVDSB_T X1# (55)
GPU_LVDSB_T X2 (55)
GPU_LVDSB_T X2# (55)
GPU_LVDSA_T XC (55)
GPU_LVDSA_T XC# (55)
GPU_LVDSA_T X0 (55)
GPU_LVDSA_T X0# (55)
GPU_LVDSA_T X1 (55)
GPU_LVDSA_T X1# (55)
GPU_LVDSA_T X2 (55)
GPU_LVDSA_T X2# (55)
AVDD
1 2
C8204
C8204
DIS
DIS
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
VDD1DI
1 2
C8207
C8207
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
DIS
DIS
A2VDDQ
1 2
1 2
C8213
DY
DY
GPU_DP/LVDS/CRT/GPIO(3/5)
GPU_DP/LVDS/CRT/GPIO(3/5)
GPU_DP/LVDS/CRT/GPIO(3/5)
Berry
Berry
Berry
C8213
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
82 95 Thursday, March 04, 2010
82 95 Thursday, March 04, 2010
1
82 95 Thursday, March 04, 2010
A00
A00
A00
5
+1.5V_RUN
D D
+1.8V_RUN_VG A
L8301 BLM15BD121SS1D-GP
L8301 BLM15BD121SS1D-GP
120o
C C
L8302 BLM15BD121SS1D-GP
L8302 BLM15BD121SS1D-GP
120ohm, 0.3A
(For M96 SPV10 = VDDC)
(For M97, Broadway, Madison and Park SPV10 = 1.0V)
B B
1204-4
DIS_Mad
DIS_Mad
L8304 BLM15BD121SS1D-GP
L8304 BLM15BD121SS1D-GP
120ohm, 0.3A
DIS_Mad
DIS_Mad
1 2
L8305 BLM18PG4 71SN1D-GP
5
L8305 BLM18PG4 71SN1D-GP
470ohm, 1A
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
A A
For DDR3/GDDR5, MVDDQ = 1.5V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C8301
C8301
C8304
C8304
DIS
DIS
DIS
DIS
1 2
1 2
C8319
C8319
C8318
C8318
DY
DY
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8335
C8335
C8303
C8303
DIS
DIS
DIS
DIS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
(1.8V@136mA VDD_CT For M96)
DIS
DIS
1 2
hm, 0.3A
DIS
DIS
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
(1.8V@17mA VDD_CT For Madison)
+3.3V_RUN_VG A
1 2
C8374
C8374
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
DIS
DIS
1 2
C8376
C8376
DIS
DIS
(1.8V@50mA SPV18)
1 2
C8389
C8389
DIS_Mad
DIS_Mad
(1.8V@150mA MPV18)
1 2
C8392
C8392
DIS_Mad
DIS_Mad
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8305
C8305
DIS
DIS
1 2
C8320
C8320
DIS
DIS
SCD1U10V2KX-5GP
1 2
C8306
C8306
DIS
DIS
1 2
C8321
C8321
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
DIS
DIS
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
C8366
C8366
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
(1.8V@340mA VDDR4 For M96)
(1.8V@170mA VDDR4 For Madison)
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8375
C8375
DIS
DIS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8377
C8377
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8351
C8351
1 2
C8378
C8378
1 2
C8307
C8307
DIS
DIS
1 2
C8322
C8322
DIS
DIS
1 2
DIS
DIS
C8367
C8367
1204-5
+1.5V_RUN
PCIE_PVDD
+1.0V_RUN_VG A
+VGA_CORE
1204-5
M97, Broadway, Madison and Park only
M96 do not support core vsense feature
VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair
SPV18
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C8391
C8391
C8390
C8390
DIS_Mad
DIS_Mad
DI S_Mad
DIS_Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
MPV18
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C8393
C8393
C8396
C8396
DIS_Mad
DIS_Mad
D IS_Mad
DIS_Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4
(1.5V@2.9A VDDR1 For M96)
(1.5V@3.4A VDDR1 For Madison)
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8308
C8308
DIS
DIS
1 2
C8323
C8323
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
L8306 BLM15BD121SS1D-GP
L8306 BLM15BD121SS1D-GP
120ohm, 0.3A
BLM18PG471SN1D- GP
BLM18PG471SN1D- GP
BLM18PG471SN1D- GP
BLM18PG471SN1D- GP
SCD1U10V2KX-5GP
1 2
C8309
C8309
DIS
DIS
1 2
C8324
C8324
DY
DY
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8353
C8353
C8352
C8352
DIS
DIS
1 2
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8368
C8368
C8369
C8369
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DIS_M96
DIS_M96
1 2
(1.8V@68mA PCIE_PVDD For M96)
(1.8V@40mA PCIE_PVDD For Madison)
SPV10
L8303
L8303
1 2
DIS_Mad
DIS_Mad
L8307
L8307
1 2
DIS_M96
DIS_M96
1204-5
4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
C8310
C8310
DIS
DIS
1 2
C8325
C8325
VDDRH
DIS_M96
DIS_M96
1 2
C8311
C8311
C8312
C8312
DIS
DIS
DY
DY
1 2
1 2
C8327
C8327
C8326
C8326
DY
DY
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8355
C8355
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DIS_M96
DIS_M96
1 2
R8302 0R2 J-2-GP
R8302 0R2 J-2-GP
1 2
DIS_M96
DIS_M96
1 2
R8301 0R2 J-2-GP
R8301 0R2 J-2-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8380
C8380
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DIS_M96
DIS_M96
FB_GND
1 2
R8303 0R2 J-2-GP
R8303 0R2 J-2-GP
VDDC_CT
MPV18
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
0107-5
Removed
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8354
C8354
DIS
DIS
V@60mA VDDR3)
(3.3
C8397
C8397
(VDDC@136mA SPV10 For M96)
(1.0V@100mA SPV10 For Madison)
1 2
C8379
C8379
DIS
DIS
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
3
VGA1E
VGA1E
AC7
VDDR1
AD11
VDDR1
AF7
VDDR1
AG10
VDDR1
AJ7
VDDR1
AK8
VDDR1
AL9
VDDR1
G11
VDDR1
G14
VDDR1
G17
VDDR1
G20
VDDR1
G23
VDDR1
G26
VDDR1
G29
VDDR1
H10
VDDR1
J7
VDDR1
J9
VDDR1
K11
VDDR1
K13
VDDR1
K8
VDDR1
L12
VDDR1
L16
VDDR1
L21
VDDR1
L23
VDDR1
L26
VDDR1
L7
VDDR1
M11
VDDR1
N11
VDDR1
P7
VDDR1
R11
VDDR1
U11
VDDR1
U7
VDDR1
Y11
VDDR1
Y7
VDDR1
AF26
VDD_CT
AF27
VDD_CT
AG26
VDD_CT
AG27
VDD_CT
AF23
VDDR3
AF24
VDDR3
AG23
VDDR3
AG24
VDDR3
AF13
VDDR4
AF15
VDDR4
AG13
VDDR4
AG15
VDDR4
AD12
VDDR4
AF11
VDDR4
AF12
VDDR4
AG11
VDDR4
M20
NC_VDDRHA
VSSRHA
M21
NC_VSSRHA
V12
NC_VDDRHB
VSSRHB
U12
NC_VSSRHB
AB37
PCIE_PVDD
H7
MPV18
H8
MPV18
SPV18
AM10
SPV18
AN9
1 2
C8381
C8381
DIS
DIS
SPV10
AN10
SPVSS
AF28
FB_VDDC
AG28
FB_VDDCI
AH29
FB_GND
MADISON-PRO -2-GP
MADISON-PRO -2-GP
NOTE1:
Back Bias is not supported on M97, Broadway, Madison and Park
For the M96 Back Bias circuitry, refer to REF134
NOTE2:
FB_V
NOTE3:
M97 VDDC and VDDCI ball assignments are different from M96.
If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
NOTE4:
For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
10/8
MEM I/O
MEM I/O
LEVEL
LEVEL
TRANSLATION
TRANSLATION
I/O
I/O
PLL
PLL
VOLTAGE
VOLTAGE
SENESE
SENESE
DDC, FB_VDDCI and FB_GND are not support on M96
PCIE
PCIE
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
CORE
CORE
VDDC/BIF_VDDC
VDDC/BIF_VDDC
ISOLATED
ISOLATED
CORE I/O
CORE I/O
5 OF 8
5 OF 8
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
AA15
VDDC
AA17
VDDC
AA20
VDDC
AA22
VDDC
AA24
VDDC
AA27
VDDC
AB16
VDDC
AB18
VDDC
AB21
VDDC
AB23
VDDC
AB26
VDDC
AB28
VDDC
AC17
VDDC
AC20
VDDC
AC22
VDDC
AC24
POWER
POWER
VDDC
AC27
VDDC
AD18
VDDC
AD21
VDDC
AD23
VDDC
AD26
VDDC
AF17
VDDC
AF20
VDDC
AF22
VDDC
AG16
VDDC
AG18
VDDC
AG21
VDDC
AH22
VDDC
AH27
VDDC
AH28
VDDC
M26
VDDC
N24
VDDC
N27
R18
VDDC
R21
VDDC
R23
VDDC
R26
VDDC
T17
VDDC
T20
VDDC
T22
VDDC
T24
VDDC
T27
U16
VDDC
U18
VDDC
U21
VDDC
U23
VDDC
U26
VDDC
V17
VDDC
V20
VDDC
V22
VDDC
V24
VDDC
V27
VDDC
Y16
VDDC
Y18
VDDC
Y21
VDDC
Y23
VDDC
Y26
VDDC
Y28
VDDC
AA13
VDDCI
AB13
VDDCI
AC12
VDDCI
AC15
VDDCI
AD13
VDDCI
AD16
VDDCI
M15
VDDCI
M16
VDDCI
M18
VDDCI
M23
VDDCI
N13
VDDCI
N15
VDDCI
N17
VDDCI
N20
VDDCI
N22
VDDCI
R12
VDDCI
R13
VDDCI
R16
VDDCI
T12
VDDCI
T15
VDDCI
V15
VDDCI
Y13
VDDCI
3
(1.8V@210mA PCIE_VDDR For M96)
(1.8V@400mA PCIE_VDDR For Madion)
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8313
C8313
DY
DY
1 2
1 2
C8328
C8328
C8329
C8329
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8337
C8337
C8336
C8336
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8346
C8346
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8357
C8357
C8356
C8356
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8370
C8370
DIS
DIS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VDDC
1 2
1 2
C8315
C8315
C8314
C8314
DIS
DIS
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8347
C8347
DIS
DIS
1 2
C8330
C8330
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8338
C8338
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8358
C8358
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8371
C8371
DIS
DIS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
C8331
C8331
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(25A VDDC For M96)
(23.6A VDDC For Madison)
1 2
C8339
C8339
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8348
C8348
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8359
C8359
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
I and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8383
C8383
DIS
DIS
(Same as VDDC)
1 2
1 2
C8384
C8384
C8385
C8385
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
C8382
C8382
DIS
DIS
2
+1.8V_RUN_VG A
1 2
1 2
C8316
C8316
C8317
C8317
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
DIS
DIS
DIS
DIS
(1.1V@1.4A PCIE_VDDC For M96)
SC1U6D3V 2KX-GP
SC1U6D3V2KX-GP
(1.0V@1.1A PCIE_VDDC For Madison)
1 2
C8332
C8332
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8340
C8340
C8341
C8341
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8349
C8349
C8350
C8350
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
DIS
DIS
DIS
DIS
1 2
1 2
C8361
C8361
C8360
C8360
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8372
C8372
C8373
C8373
DIS
DIS
DIS
DIS
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
C8386
C8386
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8333
C8333
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8342
C8342
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8362
C8362
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8387
C8387
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
DIS
DIS
1 2
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
+1.0V_RUN_VG A
C8302
C8302
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8334
C8334
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
DIS
DIS
1 2
C8343
C8343
DIS
DIS
1 2
C8363
C8363
DIS
DIS
+VGA_CORE
1 2
C8388
C8388
SC10U6D3V5KX- 1GP
SC10U6D3V5KX- 1GP
DIS
DIS
1
+VGA_CORE
1 2
1 2
C8344
C8344
C8345
C8345
SC1U6D3V2KX- GP
SC1U6D3V2KX- GP
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
10/6
1 2
1 2
C8364
C8364
C8365
C8365
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPU_POWER(4/5)
GPU_POWER(4/5)
GPU_POWER(4/5)
Berry
Berry
Berry
1
Taipei Hsie n 221, Taiwan, R.O.C.
83 95 Thursday, March 04, 2010
83 95 Thursday, March 04, 2010
83 95 Thursday, March 04, 2010
A00
A00
A00
5
10/8
VGA1F
VGA1F
AB39
PCIE_VSS
E39
PCIE_VSS
F34
PCIE_VSS
F39
PCIE_VSS
G33
PCIE_VSS
G34
PCIE_VSS
H31
PCIE_VSS
H34
PCIE_VSS
H39
PCIE_VSS
J31
PCIE_VSS
J34
PCIE_VSS
K31
PCIE_VSS
K34
PCIE_VSS
K39
PCIE_VSS
D D
C C
B B
L31
PCIE_VSS
L34
PCIE_VSS
M34
PCIE_VSS
M39
PCIE_VSS
N31
PCIE_VSS
N34
PCIE_VSS
P31
PCIE_VSS
P34
PCIE_VSS
P39
PCIE_VSS
R34
PCIE_VSS
T31
PCIE_VSS
T34
PCIE_VSS
T39
PCIE_VSS
U31
PCIE_VSS
U34
PCIE_VSS
V34
PCIE_VSS
V39
PCIE_VSS
W31
PCIE_VSS
W34
PCIE_VSS
Y34
PCIE_VSS
Y39
PCIE_VSS
F15
GND
F17
GND
F19
GND
F21
GND
F23
GND
F25
GND
F27
GND
F29
GND
F31
GND
F33
GND
F7
GND
F9
GND
G2
GND
G6
GND
H9
GND
J2
GND
J27
GND
J6
GND
J8
GND
K14
GND
K7
GND
L11
GND
L17
GND
L2
GND
L22
GND
L24
GND
L6
GND
M17
GND
M22
GND
M24
GND
N16
GND
N18
GND
N2
GND
N21
GND
N23
GND
N26
GND
N6
GND
R15
GND
R17
GND
R2
GND
R20
GND
R22
GND
R24
GND
R27
GND
R6
GND
T11
GND
T13
GND
T16
GND
T18
GND
T21
GND
T23
GND
T26
GND
U15
GND
U17
GND
U2
GND
U20
GND
U22
GND
U24
GND
U27
GND
U6
GND
V11
GND
V16
GND
V18
GND
V21
GND
V23
GND
V26
GND
W2
GND
W6
GND
Y15
GND
Y17
GND
Y20
GND
Y22
GND
Y24
GND
Y27
GND
U13
GND
V13
GND
MADISON-PRO -2-GP
MADISON-PRO -2-GP
GND
GND
6 OF 8
6 OF 8
GND/PX_EN
VSS_MECH
VSS_MECH
VSS_MECH
DIS_GPU
DIS_GPU
A3
GND
A37
GND
AA16
GND
AA18
GND
AA2
GND
AA21
GND
AA23
GND
AA26
GND
AA28
GND
AA6
GND
AB12
GND
AB15
GND
AB17
GND
AB20
GND
AB22
GND
AB24
GND
AB27
GND
AC11
GND
AC13
GND
AC16
GND
AC18
GND
AC2
GND
AC21
GND
AC23
GND
AC26
GND
AC28
GND
AC6
GND
AD15
GND
AD17
GND
AD20
GND
AD22
GND
AD24
GND
AD27
GND
AD9
GND
AE2
GND
AE6
GND
AF10
GND
AF16
GND
AF18
GND
AF21
GND
AG17
GND
AG2
GND
AG20
GND
AG22
GND
AG6
GND
AG9
GND
AH21
GND
AJ10
GND
AJ11
GND
AJ2
GND
AJ28
GND
AJ6
GND
AK11
GND
AK31
GND
AK7
GND
AL11
GND
AL14
GND
AL17
GND
AL2
GND
AL20
GND
AL21
AL23
GND
AL26
GND
AL32
GND
AL6
GND
AL8
GND
AM11
GND
AM31
GND
AM9
GND
AN11
GND
AN2
GND
AN30
GND
AN6
GND
AN8
GND
AP11
GND
AP7
GND
AP9
GND
AR5
GND
B11
GND
B13
GND
B15
GND
B17
GND
B19
GND
B21
GND
B23
GND
B25
GND
B27
GND
B29
GND
B31
GND
B33
GND
B7
GND
B9
GND
C1
GND
C39
GND
E35
GND
E5
GND
F11
GND
F13
GND
VSS_MECH1
A39
VSS_MECH2
AW1
VSS_MECH3
AW39
+1.8V_RUN_VG A
BLM18PG471SN1D- GP
BLM18PG471SN1D- GP
470ohm, 1A
+1.0V_RUN_VG A
L8408 BLM15BD121SS1D-GP
L8408 BLM15BD121SS1D-GP
120oh
+1.8V_RUN_VG A
BLM18PG471SN1D- GP
BLM18PG471SN1D- GP
470ohm, 1A
+1.0V_RUN_VG A
L8407 BLM15BD121SS1D-GP
L8407 BLM15BD121SS1D-GP
120ohm, 0.3A
TP8401 TP AD14-GP TP8401 TPAD1 4-GP
1
TP8402 TP AD14-GP TP8402 TPAD1 4-GP
1
TP8403 TP AD14-GP TP8403 TPAD1 4-GP
1
4
VGA1H
DPD_VDD18
DPEF_CALR
DIS
DIS
1 2
AP20
AP21
AP13
AT13
AN17
AP16
AP17
AW14
AW16
AP22
AP23
AP14
AP15
AN19
AP18
AP19
AW20
AW22
AW18
AH34
AJ34
AL33
AM33
AN34
AP39
AR39
AU37
AF34
AG34
AK33
AK34
AF39
AH39
AK39
AL34
AM34
AM39
R8406
R8406
150R2F-1-GP
150R2F-1-GP
VGA1H
DPC_VDD18
DPC_VDD18
DPC_VDD10
DPC_VDD10
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPD_VDD18
DPD_VDD18
DPD_VDD10
DPD_VDD10
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPCD_CALR
DP E/F POWER
DP E/F POWER
DPE_VDD18
DPE_VDD18
DPE_VDD10
DPE_VDD10
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPF_VDD18
DPF_VDD18
DPF_VDD10
DPF_VDD10
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPEF_CALR
MADISON-PRO -2-GP
MADISON-PRO -2-GP
DPD_VDD18
1 2
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
DIS
DIS
SC1U6D3V 2KX-GP
SC1U6D3V2KX-GP
1 2
C8427
C8427
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(1.8V@130mA DPC_VDD18)
R8401
R8401
C8419
C8419
C8418
C8418
DIS
DIS
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
1 2
DPE_VDD10
1 2
C8424
C8424
C8425
C8425
DIS
DIS
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
C8428
C8428
DIS
DIS
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
1 2
DPF_VDD10
1 2
C8433
C8433
DIS
DIS
DIS
DIS
+1.0V_RUN_VG A
(1.1V@200mA DPC_VDD10 For M96)
(1.0V@110mA DPC_VDD10 For Madison)
+1.0V_RUN_VG A
(1.1V@200mA DPD_VDD10 For M96)
(1.0V@110mA DPD_VDD10 For Madison)
LVDS mode
(1.8V@200mA DPE_VDD18 For M96)
L8401
L8401
(1.8V@200mA DPE_VDD18 For Madison)
DIS
DIS
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
1 2
m, 0.3A
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
L8405
L8405
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
1 2
C8401
C8401
DIS
DIS
LVDS
mode
(1.1V@100mA DPE_VDD10 For M96)
(1.0V@120mA DPE_VDD10 For Madison)
DIS
DIS
1 2
C8404
C8404
DIS
DIS
LVDS mode
(1.8
V@200mA DPF_VDD18 For M96)
(1.8V@200mA DPF_VDD18 For Madison)
DIS
DIS
1 2
C8423
C8423
DIS
DIS
LVDS mode
(1.1V@100mA DPF_VDD10 For M96)
(1.0V@120mA DPF_VDD10 For Madison)
DIS
DIS
C8426
C8426
1 2
DIS
DIS
DIS
DIS
DPCD_CALR DPAB_CALR
1 2
150R2F-1-GP
150R2F-1-GP
DPE_VDD18
DPF_VDD18
1 2
C8434
C8434
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
10/8
3
DP A/B POWER DP C/D POWER
DP A/B POWER DP C/D POWER
DP PLL POWER
DP PLL POWER
8 OF 8
8 OF 8
DPA_VDD18
DPA_VDD18
DPA_VDD10
DPA_VDD10
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPB_VDD18
DPB_VDD18
DPB_VDD10
DPB_VDD10
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPAB_CALR
DPA_PVDD
DPA_PVSS
DPB_PVDD
DPB_PVSS
DPC_PVDD
DPC_PVSS
DPD_PVDD
DPD_PVSS
DPE_PVDD
DPE_PVSS
DPF_PVDD
DPF_PVSS
DIS_GPU
DIS_GPU
DPA_VDD18
AN24
AP24
DPA_VDD10
AP31
AP32
AN27
AP27
AP28
AW24
AW26
DPB_VDD18
AP25
AP26
(1.1V@200mA DPB_VDD10 For M96)
AN33
(1.0V@110mA DPB_VDD10 For Madison)
AP33
AN29
AP29
AP30
AW30
AW32
AW28
AU28
AV27
AV29
AR28
AU18
AV17
AV19
AR18
AM37
AN38
AL38
AM35
DPF_PVDD
DPF_PVSS
DPA_PVDD
R8404
R8404
1 2
150R2F-1-GP
150R2F-1-GP
DIS
DIS
(1.8V@20mA DPB_PVDD For M96)
(1.8V@20mA DPB_PVDD For Madison)
(1.8V@20mA DPC_PVDD For M96)
(1.8V@20mA DPC_PVDD For Madison)
(1.8V@20mA DPD_PVDD For M96)
(1.8V@20mA DPD_PVDD For Madison)
(1.8V@20mA DPE_PVDD For M96)
(1.8V@20mA DPE_PVDD For Madison)
DIS_Park/Mad
DIS_Park/Mad
1 2
R8407 0R2 J-2-GP
R8407 0R2 J-2-GP
DIS_Park/Mad
DIS_Park/Mad
1 2
R8408 0R2 J-2-GP
R8408 0R2 J-2-GP
1204-2
(1.1V@200mA DPA_VDD10 For M96)
(1.0V@110mA DPA_VDD10 For Madison)
1 2
C8402
C8402
DIS
DIS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8412
C8412
DIS
DIS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(1.8V@20mA DPF_PVDD)
1 2
C8429
C8429
DIS
DIS
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
1 2
DIS
DIS
(1.8V@20mA DPA_PVDD For M96)
(1.8V@20mA DPA_PVDD For Madison)
C8403
C8403
+1.0V_RUN_VG A
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8430
C8430
D IS
DIS
SC1U6D3V 2KX-GP
SC1U6D3V2KX-GP
DIS
DIS
1 2
C8413
C8413
DIS
DIS
C8405
C8405
SC10U6D3V5KX- 1GP
SC10U6D3V5KX- 1GP
1 2
DIS
DIS
DPE_PVDD
1 2
C8416
C8416
DIS
DIS
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
DIS
DIS
1 2
L8403 BLM15BD121SS1D-GP
L8403 BLM15BD121SS1D-GP
120ohm, 0.3A
+1.8V_RUN_VG A
1 2
L8404 BLM15BD121SS1D-GP
L8404 BLM15BD121SS1D-GP
DIS
DIS
120ohm, 0.3A
C8414
C8414
S C4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
DIS
DIS
1 2
L8406 BLM15BD121SS1D-GP
L8406 BLM15BD121SS1D-GP
120ohm, 0.3A
+1.0V_RUN_VG A
1204-4
DNI for M96/M92
L8402 BLM15BD121SS1D-GP
L8402 BLM15BD121SS1D-GP
120ohm, 0.3A
R8402 0R2 J-2-GP
R8402 0R2 J-2-GP
R8405 0R2 J-2-GP
R8405 0R2 J-2-GP
DIS_Mad
DIS_Mad
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
DIS_Mad
DIS_Mad
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
DIS_Mad
DIS_Mad
1 2
SC4D7U6D3V 3KX-GP
SC4D7U6D3V 3KX-GP
(1.8V@130mA DPA_VDD18)
1 2
C8406
C8406
DIS_Mad
DIS_Mad
(1.8V@130mA DPB_VDD18)
1 2
DY
DY
C8409
C8409
(1.8V@130mA DPD_VDD18)
1 2
DY
DY
C8415
C8415
1 2
D IS_Mad
DIS_Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8410
C8410
DIS_Mad
DIS_Mad
SC1U6D3V2K X-GP
SC1U6D3V2KX-GP
1 2
C8421
C8421
DIS_Mad
DIS_Mad
SC1U6D3V2K X-GP
SC1U6D3V2KX-GP
1
C8407
C8407
DIS_Mad
DIS_Mad
DPA_VDD18 +1.8V_RUN_VG A
1 2
C8408
C8408
DIS_Mad
DIS_Mad
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
DPB_VDD18
1 2
C8411
C8411
DIS_Mad
DIS_Mad
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
DPD_VDD18
C8422
C8422
SCD1U10V2KX- 5GP
SCD1U10V2KX- 5GP
1 2
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
Taipei Hsie n 221, Taiwan, R.O.C.
1
of
84 95 Thursday, March 04, 2010
84 95 Thursday, March 04, 2010
84 95 Thursday, March 04, 2010
5
Title
Title
Title
GPU_DPPWR/GND(5/5)
GPU_DPPWR/GND(5/5)
GPU_DPPWR/GND(5/5)
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A2
A2
A2
Berry A00
Berry A00
Berry A00
Date: Sheet
Date: Sheet of
4
3
2
Date: Sheet of
5
4
3
2
1
+1.5V_RU N +1.5V_RU N
1.5V, 350mA 1.5V, 350mA
1 2
C8508
C8508
C8507
D D
C C
C8507
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
20090902
CLKA0 (81)
CLKA0# (81)
56R2J-4-G P
56R2J-4-G P
SCD01U5 0V2KX-1GP
SCD01U5 0V2KX-1GP
B B
1 2
1 2
C8510
C8510
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
R8508
R8508
56R2J-4-G P
DIS_M96/Mad
DIS_M96/Mad
C8503
C8503
56R2J-4-G P
GPU_CLK A0_T
1 2
DIS_M96/Mad
DIS_M96/Mad
1 2
C8512
C8512
C8509
C8509
DI S_M96 / Mad
DI S_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
R8507
R8507
DIS_M96/Mad
DIS_M96/Mad
1 2
1 2
C8514
C8514
C8511
C8511
DI S_M96 / Mad
DI S_M96/Mad
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM1_V REF
VRAM2_V REF
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8502
C8502
1 2
DIS_M96/Mad
DIS_M96/Mad
DIS_M9 6/Mad
DIS_M96/Mad
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
DIS_M96/Mad
DIS_M96/Mad
R8503 243R2F-2-GP
R8503 243R2F-2-GP
MAA0 (81,8 6)
MAA1 (81,8 6)
MAA2 (81,8 6)
MAA3 (81,8 6)
MAA4 (81,8 6)
MAA5 (81,8 6)
MAA6 (81,8 6)
MAA7 (81,8 6)
MAA8 (81,8 6)
MAA9 (81,8 6)
MAA10 (81,8 6)
MAA11 (81,8 6)
MAA12 (81,8 6)
MAA13 (81,8 6)
A_BA0 (81,86)
A_BA1 (81,86)
A_BA2 (81,86)
CKEA0 (81)
DQMA2 (81) DQMA1 (81)
DQMA0 (81)
WEA0 # (81 )
CASA0# (81)
RASA0# (81)
1 2
1 2
C8513
C8513
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8505
C8505
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VRAM_ZQ 1 VRAM_ZQ 2
20090902
+1.5V_RU N
VRAM1
VRAM1
K8
K2
N1
R9
B2
D9
G7
R1
N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
H1
M8
L8
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3
J7
K7
K9
D3
E7
L3
K3
J3
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
1 2
R8510
R8510
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
1 2
R8511
R8511
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFDQ
VREFCA
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
BA0
BA1
BA2
CK
CK#
CKE
DMU
DML
WE#
CAS#
RAS#
DIS_Samsung_M96/Mad
DIS_Samsung_M96/Mad
VRAM1_V REF
DIS_M96/Mad
DIS_M96/Mad
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1 2
C8504
C8504
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
E3
MDA7
F7
MDA1
F2
MDA6
F8
MDA2
H3
MDA4
H8
MDA0
G2
MDA5
H7
MDA20 MDA8
D7
MDA19
C3
MDA23
C8
MDA18
C2
MDA22
A7
MDA16
A2
MDA21
B8
MDA17
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
QSAP_2 (81)
QSAN_2 (8 1)
QSAP_0 (81)
QSAN_0 (8 1)
ODTA0 (81)
CSA0#_0 (81)
MEM_RST (81,86,87 ,88)
MDA3 MDA29
MDA[0..31] (81)
1 2
C8525
C8525
C8524
C8524
DIS_M96 / Mad
DIS_M96/Mad
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8516
C8516
C8515
C8515
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8518
C8518
C8517
C8517
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM2_V REF
VRAM1_V REF
1 2
1 2
C8519
C8519
DI S_M96 / Mad
DI S_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8521
C8521
1 2
DIS_M96/Mad
DIS_M96/Mad
DY
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DIS_M96/Mad
DIS_M96/Mad
R8504 243R2F-2-GP
R8504 243R2F-2-GP
MAA0 (81,8 6)
MAA1 (81,8 6)
MAA2 (81,8 6)
MAA3 (81,8 6)
MAA4 (81,8 6)
MAA5 (81,8 6)
MAA6 (81,8 6)
MAA7 (81,8 6)
MAA8 (81,8 6)
MAA9 (81,8 6)
MAA10 (81,8 6)
MAA11 (81,8 6)
MAA12 (81,8 6)
MAA13 (81,8 6)
A_BA0 (81,86)
A_BA1 (81,86)
A_BA2 (81,86)
CLKA0 (81)
CLKA0# (81)
CKEA0 (81)
DQMA3 (81)
WEA0 # (81 )
CASA0# (81)
RASA0# (81)
C8520
C8520
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8522
C8522
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
20090902
+1.5V_RU N
1 2
R8513
R8513
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
VRAM2_V REF
1 2
R8512
R8512
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
DIS_M96/Mad
DIS_M96/Mad
K8
K2
N1
R9
B2
D9
G7
R1
N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
H1
M8
L8
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3
J7
K7
K9
D3
E7
L3
K3
J3
1 2
C8506
C8506
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
VRAM2
VRAM2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFDQ
VREFCA
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
BA0
BA1
BA2
CK
CK#
CKE
DMU
DML
WE#
CAS#
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DIS_Samsung_M96/Mad
DIS_Samsung_M96/Mad
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
MDA24
F7
MDA30
F2
MDA26
F8
MDA28
H3
MDA27
H8
MDA25
G2
MDA31
H7
D7
MDA14
C3
MDA9
C8
MDA10
C2
MDA15
A7
MDA12
A2
MDA13
B8
MDA11
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
QSAP_1 (81)
QSAN_1 (8 1)
QSAP_3 (81)
QSAN_3 (8 1)
ODTA0 (81)
CSA0#_0 (81)
MEM_RST (81,86,87 ,88)
MDA[0..31] (81)
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM1,2 (1/4)
GPU-VRAM1,2 (1/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPU-VRAM1,2 (1/4)
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
85 95 Thu rsday, March 04, 2010
85 95 Thu rsday, March 04, 2010
85 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
1.5V, 350mA 1.5V, 350mA
1 2
1 2
1 2
C8607
C8607
C8610
C8602
C8602
DIS_M96 / Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
D D
C C
SC1U6D3V2KX-GP
CLKA1 (81)
CLKA1# (81)
SCD01U5 0V2KX-1GP
SCD01U5 0V2KX-1GP
C8610
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R8607
R8607
56R2J-4-G P
56R2J-4-G P
DIS_M96/Mad
DIS_M96/Mad
C8603
C8603
1 2
C8612
C8612
C8609
C8609
DY
DY
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM3_V REF VRAM4_V REF
VRAM4_V REF VRAM3_V REF
1 2
R8608
R8608
56R2J-4-G P
56R2J-4-G P
DIS_M96/Mad
DIS_M96/Mad
GPU_CLK A1_T
1 2
DIS_M96/Mad
DIS_M96/Mad
1 2
1 2
C8611
C8611
C8614
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8614
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8606
C8606
1 2
DIS_M96/Mad
DIS_M96/Mad
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DIS_M96/Mad
DIS_M96/Mad
R8603 243R2F-2-GP
R8603 243R2F-2-GP
MAA0 (81,8 5)
MAA1 (81,8 5)
MAA2 (81,8 5)
MAA3 (81,8 5)
MAA4 (81,8 5)
MAA5 (81,8 5)
MAA6 (81,8 5)
MAA7 (81,8 5)
MAA8 (81,8 5)
MAA9 (81,8 5)
MAA10 (81,8 5)
MAA11 (81,8 5)
MAA12 (81,8 5)
MAA13 (81,8 5)
A_BA0 (81,85)
A_BA1 (81,85)
A_BA2 (81,85)
CKEA1 (81)
DQMA5 (81)
DQMA4 (81)
WEA1 # (81 )
CASA1# (81)
RASA1# (81)
1 2
1 2
C8613
C8613
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8608
C8608
1 2
DIS_M9 6/Mad
DIS_M96/Mad
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VRAM_ZQ 3 VRAM_ZQ 4
1 2
K8
K2
N1
R9
B2
D9
G7
R1
N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
H1
M8
L8
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3
J7
K7
K9
D3
E7
L3
K3
J3
4
VRAM3
VRAM3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFDQ
VREFCA
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
BA0
BA1
BA2
CK
CK#
CKE
DMU
DML
WE#
CAS#
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DQSU#
RESET#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSL
DQSL#
ODT
CS#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
3
MDA36
E3
MDA38
F7
MDA33
F2
MDA39
F8
MDA32
H3
MDA34
H8
MDA35
G2
MDA37
H7
MDA46
D7
MDA43
C3
MDA45
C8
MDA40
C2
MDA44
A7
MDA41
A2
MDA47
B8
MDA42
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
MDA[32..63 ] (81 )
QSAP_5 (81)
QSAN_5 (8 1)
QSAP_4 (81)
QSAN_4 (8 1)
ODTA1 (81)
CSA1#_0 (81)
MEM_RST (81,85,87 ,88)
1 2
C8621
C8621
C8618
C8618
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
CLKA1 (81)
CLKA1# (81)
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8622
C8622
C8623
C8623
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
1 2
C8625
C8625
DIS_M96 / Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8624
C8624
DIS_M96/Mad
DIS_M96/Mad
1 2
C8616
C8616
DIS_M96 / Mad
DIS_M96/Mad
DY
DY
DIS_M96/Mad
DIS_M96/Mad
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8617
C8617
1 2
DIS_M9 6/Mad
DIS_M96/Mad
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
DIS_M96/Mad
DIS_M96/Mad
R8604 243R2F-2-GP
R8604 243R2F-2-GP
MAA0 (81,8 5)
MAA1 (81,8 5)
MAA2 (81,8 5)
MAA3 (81,8 5)
MAA4 (81,8 5)
MAA5 (81,8 5)
MAA6 (81,8 5)
MAA7 (81,8 5)
MAA8 (81,8 5)
MAA9 (81,8 5)
MAA10 (81,8 5)
MAA11 (81,8 5)
MAA12 (81,8 5)
MAA13 (81,8 5)
A_BA0 (81,85)
A_BA1 (81,85)
A_BA2 (81,85)
CKEA1 (81)
DQMA6 (81)
DQMA7 (81)
WEA1 # (81 )
CASA1# (81)
RASA1# (81)
2
+1.5V_RU N +1.5V_RU N
1 2
C8615
C8615
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8619
C8619
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VRAM4
VRAM4
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MDA61
E3
MDA57
F7
MDA63
F2
MDA60
F8
MDA59
H3
MDA56
H8
MDA62
G2
MDA58
H7
MDA50
D7
MDA55
C3
MDA49
C8
MDA52
C2
MDA48
A7
MDA54
A2
MDA51
B8
MDA53
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
1
MDA[32..63 ] (81 )
QSAP_6 (81)
QSAN_6 (8 1)
QSAP_7 (81)
QSAN_7 (8 1)
ODTA1 (81)
CSA1#_0 (81)
MEM_RST (81,85,87 ,88)
DIS_Samsung_M96/Mad
B B
20090902
20090902
+1.5V_RU N
1 2
R8601
R8601
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
VRAM3_V REF
1 2
R8602
R8602
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
A A
5
1 2
DIS_M96/Mad
DIS_M96/Mad
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DIS_Samsung_M96/Mad
1 2
C8601
C8601
C8626
C8626
DIS_M96/Mad
DIS_M96/Mad
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1120-3
4
20090902
+1.5V_RU N
1 2
R8605
R8605
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
VRAM4_V REF
1 2
R8606
R8606
2K1R2F-G P
2K1R2F-G P
DIS_M96/Mad
DIS_M96/Mad
3
1 2
C8605
C8605
DIS_M96/Mad
DIS_M96/Mad
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
2
DIS_Samsung_M96/Mad
DIS_Samsung_M96/Mad
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM3,4 (2/4)
GPU-VRAM3,4 (2/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPU-VRAM3,4 (2/4)
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
86 95 Thu rsday, March 04, 2010
86 95 Thu rsday, March 04, 2010
86 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
1.5V, 350mA 1.5V, 350mA
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
DY
DY
1 2
C8710
C8710
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM5_V REF
VRAM6_V REF
C8709
C8709
1 2
C8702
C8702
C8707
C8707
DIS
DIS
SC1U6D3V2KX-GP
D D
C C
SC1U6D3V2KX-GP
20090902
CLKB0 (81)
CLKB0# (81)
SCD01U5 0V2KX-1GP
SCD01U5 0V2KX-1GP
B B
R8707
R8707
56R2J-4-G P
56R2J-4-G P
DIS
DIS
C8703
C8703
1 2
GPU_CLK B0_T
1 2
DIS
DIS
20090902
1 2
1 2
C8712
C8712
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R8708
R8708
56R2J-4-G P
56R2J-4-G P
DIS
DIS
+1.5V_RU N +1.5V_R UN
1 2
C8711
C8711
C8713
C8713
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8706
C8706
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
R8704 243R2F-2-GP
R8704 243R2F-2-GP
DIS
DIS
MAB0 (81,8 8)
MAB1 (81,8 8)
MAB2 (81,8 8)
MAB3 (81,8 8)
MAB4 (81,8 8)
MAB5 (81,8 8)
MAB6 (81,8 8)
MAB7 (81,8 8)
MAB8 (81,8 8)
MAB9 (81,8 8)
MAB10 (81,8 8)
MAB11 (81,8 8)
MAB12 (81,8 8)
MAB13 (81,8 8)
B_BA0 (81,88)
B_BA1 (81,88)
B_BA2 (81,88)
1 2
CKEB0 (81)
DQMB3 (81)
DQMB1 (81)
WEB0 # (81 )
CASB0# (81)
RASB0# (81)
1 2
R8701
R8701
2K1R2F-G P
2K1R2F-G P
DIS
DIS
1 2
R8702
R8702
2K1R2F-G P
2K1R2F-G P
DIS
DIS
1 2
1 2
C8714
C8714
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8708
C8708
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VRAM_ZQ 5 VRAM_ZQ 6
VRAM5_V REF VRAM6_VREF
DIS
DIS
DY
DY
1 2
C8701
C8701
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
K8
K2
N1
R9
B2
D9
G7
R1
N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
H1
M8
L8
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
M2
N8
M3
J7
K7
K9
D3
E7
L3
K3
J3
4
VRAM5
VRAM5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFDQ
VREFCA
ZQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
BA0
BA1
BA2
CK
CK#
CKE
DMU
DML
WE#
CAS#
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DIS_Samsung
DIS_Samsung
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
3
MDB14
MDB13
MDB12
MDB15
MDB11
MDB8
MDB9
MDB10
MDB26 MDB1
MDB27
MDB30
MDB24 MDB4
MDB31
MDB25 MDB7
MDB29
MDB28
MDB[0..31] (81)
1 2
C8715
C8715
C8717
C8717
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
QSBN_3 (8 1) QSBN_0 (81)
QSBP_1 (81)
QSBN_1 (8 1)
ODTB0 (81)
CSB0#_0 (81)
MEM_RST (81,85,86 ,88)
C8720
C8720
DY
DY
C8721
C8721
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM6_V REF
VRAM5_V REF
CLKB0 (81)
CLKB0# (81)
C8723
C8723
DY
DY
1 2
1 2
1 2
1 2
1 2
C8722
C8722
C8724
C8724
DIS
DIS
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8718
C8718
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
R8706 243R2F-2-GP
R8706 243R2F-2-GP
MAB0 (81,8 8)
MAB1 (81,8 8)
MAB2 (81,8 8)
MAB3 (81,8 8)
MAB4 (81,8 8)
MAB5 (81,8 8)
MAB6 (81,8 8)
MAB7 (81,8 8)
MAB8 (81,8 8)
MAB9 (81,8 8)
MAB10 (81,8 8)
MAB11 (81,8 8)
MAB12 (81,8 8)
MAB13 (81,8 8)
B_BA0 (81,88)
B_BA1 (81,88)
B_BA2 (81,88)
CKEB0 (81)
DQMB0 (81)
DQMB2 (81)
WEB0 # (81 )
CASB0# (81)
RASB0# (81)
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DIS
DIS
2
+1.5V_RU N +1.5V_RU N
1 2
1 2
C8725
C8725
DY
DY
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8719
C8719
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VRAM6
VRAM6
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DIS_Samsung
DIS_Samsung
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MDB16
E3
MDB18
F7
MDB20
F2
MDB19
F8
MDB22
H3
MDB17
H8
MDB23
G2
MDB21
H7
D7
MDB5
C3
MDB2
C8
C2
MDB3
A7
A2
MDB0
B8
MDB6
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
20090902
1 2
R8703
R8703
2K1R2F-G P
2K1R2F-G P
DIS
DIS
1 2
DIS
DIS
R8705
R8705
2K1R2F-G P
2K1R2F-G P
DIS
DIS
1 2
C8705
C8705
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
1
MDB[0..31] (81)
QSBP_0 (81) QSBP_3 (81)
QSBP_2 (81)
QSBN_2 (8 1)
ODTB0 (81)
CSB0#_0 (81)
MEM_RST (81,85,86 ,88)
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM5,6 (3/4)
GPU-VRAM5,6 (3/4)
GPU-VRAM5,6 (3/4)
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
87 95 Thu rsday, March 04, 2010
87 95 Thu rsday, March 04, 2010
87 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
VRAM7
1.5V, 350mA 1.5V, 350mA
1 2
1 2
1 2
1 2
1 2
C8809
C8809
C8808
C8808
C8802
C8802
DIS
DIS
DIS
D D
C C
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1 2
C8811
C8811
C8812
C8810
C8810
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM7_V REF VRAM8_V REF
VRAM8_V REF
C8812
DY
DY
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
20090902
CLKB1 (81)
CLKB1# (81)
SCD01U5 0V2KX-1GP
SCD01U5 0V2KX-1GP
B B
R8807
R8807
56R2J-4-G P
56R2J-4-G P
DIS
DIS
C8803
C8803
1 2
56R2J-4-G P
56R2J-4-G P
GPU_CLK B1_T
1 2
DIS
DIS
R8808
R8808
DIS
DIS
1 2
1 2
C8813
C8813
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8806
C8806
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
R8803 243R2F-2-GP
R8803 243R2F-2-GP
MAB0 (81,8 7)
MAB1 (81,8 7)
MAB2 (81,8 7)
MAB3 (81,8 7)
MAB4 (81,8 7)
MAB5 (81,8 7)
MAB6 (81,8 7)
MAB7 (81,8 7)
MAB8 (81,8 7)
MAB9 (81,8 7)
MAB10 (81,8 7)
MAB11 (81,8 7)
MAB12 (81,8 7)
MAB13 (81,8 7)
B_BA0 (81,87)
B_BA1 (81,87)
B_BA2 (81,87)
CKEB1 (81)
DQMB4 (81)
DQMB5 (81)
WEB1 # (81 )
CASB1# (81)
RASB1# (81)
1 2
C8814
C8814
DY
DY
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8807
C8807
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VRAM_ZQ 7 VRAM_ZQ8
DIS
DIS
VRAM7
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DIS_Samsung
DIS_Samsung
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MDB40
E3
MDB43
F7
MDB47
F2
MDB44
F8
MDB41
H3
MDB45
H8
MDB42
G2
MDB46
H7
MDB36
D7
MDB35
C3
MDB39
C8
MDB32
C2
MDB37
A7
MDB33
A2
MDB38
B8
MDB34
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
MDB[32..63 ] (81 )
QSBP_4 (81)
QSBN_4 (8 1)
QSBP_5 (81)
QSBN_5 (8 1)
ODTB1 (81)
CSB1#_0 (81)
MEM_RST (81,85,86 ,87)
1 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8821
C8821
DY
DY
1 2
C8822
C8822
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VRAM7_V REF
1 2
1 2
C8823
C8823
DIS
DIS
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8817
C8817
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
R8804 243R2F-2-GP
R8804 243R2F-2-GP
MAB0 (81,8 7)
MAB1 (81,8 7)
MAB2 (81,8 7)
MAB3 (81,8 7)
MAB4 (81,8 7)
MAB5 (81,8 7)
MAB6 (81,8 7)
MAB7 (81,8 7)
MAB8 (81,8 7)
MAB9 (81,8 7)
MAB10 (81,8 7)
MAB11 (81,8 7)
MAB12 (81,8 7)
MAB13 (81,8 7)
B_BA0 (81,87)
B_BA1 (81,87)
B_BA2 (81,87)
1 2
1 2
C8820
C8816
C8816
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
CLKB1 (81)
CLKB1# (81)
C8820
C8819
C8819
DY
DY
DIS
DIS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+1.5V_RU N +1.5V_RU N
1 2
1 2
C8825
C8825
C8824
C8824
DIS
DIS
DY
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8818
C8818
1 2
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DIS
DIS
CKEB1 (81)
DQMB7 (81)
DQMB6 (81)
WEB1 # (81 )
CASB1# (81)
RASB1# (81)
VRAM8
VRAM8
K8
VDD
K2
VDD
N1
VDD
R9
VDD
B2
VDD
D9
VDD
G7
VDD
R1
VDD
N9
VDD
A8
VDDQ
A1
VDDQ
C1
VDDQ
C9
VDDQ
D2
VDDQ
E9
VDDQ
F1
VDDQ
H9
VDDQ
H2
VDDQ
H1
VREFDQ
M8
VREFCA
L8
ZQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC#
T3
A13
M7
NC#M7
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK#
K9
CKE
D3
DMU
E7
DML
L3
WE#
K3
CAS#
J3
RAS#
K4W1 G1646E-HC12-GP
K4W1 G1646E-HC12-GP
DIS_Samsung
DIS_Samsung
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DQSU
DQSU#
DQSL
DQSL#
ODT
CS#
RESET#
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MDB53
E3
MDB51
F7
MDB55
F2
MDB49
F8
MDB54
H3
MDB48
H8
MDB52
G2
MDB50
H7
MDB61
D7
MDB62
C3
MDB58
C8
MDB59
C2
MDB63
A7
MDB56
A2
MDB57
B8
MDB60
A3
C7
B7
F3
G3
K1
L2
T2
T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
MDB[32..63 ] (81 )
QSBP_7 (81)
QSBN_7 (8 1)
QSBP_6 (81)
QSBN_6 (8 1)
ODTB1 (81)
CSB1#_0 (81)
MEM_RST (81,85,86 ,87)
20090902 20090902
+1.5V_RU N +1.5V_RU N
1 2
DIS
DIS
1 2
DIS
DIS
R8801
R8801
2K1R2F-G P
2K1R2F-G P
VRAM7_V REF VRAM8_V REF
1 2
C8801
DIS
DIS
C8801
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
R8802
R8802
2K1R2F-G P
2K1R2F-G P
1 2
DIS
DIS
1 2
DIS
DIS
R8805
R8805
2K1R2F-G P
2K1R2F-G P
R8806
R8806
2K1R2F-G P
2K1R2F-G P
DIS
DIS
1 2
C8804
C8804
SCD1U16 V2ZY-2GP
SCD1U16 V2ZY-2GP
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPU-VRAM7,8 (4/4)
GPU-VRAM7,8 (4/4)
GPU-VRAM7,8 (4/4)
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
88 95 Thu rsday, March 04, 2010
88 95 Thu rsday, March 04, 2010
88 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
SSID = Video.PWR.Regulator
D D
+5V_ALW
5V, 1.25mA
1 2
PC8908
PC8908
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
PR8903
PR8903
1 2
DIS
DIS
10R2F-L-G P
10R2F-L-G P
C C
RUNPW ROK (49,51,52,90 )
1 2
P C8918
PC8918
PC8904
PC8904
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1 2
DIS
DIS
SC1U10V2KX-1GP
SC1U10V2KX-1GP
PR8905 6K98R 2-GP
PR8905 6K98R 2-GP
0225-3
1 2
DIS
DIS
+GFX_CO RE_CS
+GFX_CO RE_EN_R
1120-8
PR8921 0R2J-2-GP
PR8921 0R2J-2-GP
1 2
DY
GFX_COR E_EN (37 )
PM_SLP_ S3# (21,37,41,4 2,49,52)
B B
DY
PR8920 10KR2J-3-GP
PR8920 10KR2J-3-GP
1 2
DIS
DIS
+GFX_CO RE_TON
DIS
DIS
PU8901
PU8901
16
TON
9
VDDP
2
VDD
4
PGOOD
10
CS
15
EM/DEM
17
GND
RT8208B GQW-GP
RT8208B GQW-GP
Change to RT8208B(Pin to Pin)
+GFX_CO RE_EN_R
1 2
PC8912
PC8912
SCD1U10 V2KX-4GP
SCD1U10 V2KX-4GP
DIS
DIS
11/9
4
3
RT8208AGQW for +VCC_GFX_CORE
+PWR _SRC
678
DDD S
DDD S
PU8902
PU8902
SI7686DP-T 1-GP
SI7686DP-T 1-GP
PU8903
PU8903
SSG D
SSG D
DIS_65MOS
DIS_65MOS
4 5
678
DDD
DDD
G
DIS_65MOS
G
DIS_65MOS
4 5
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
123
D
D
SSS
SSS
123
DIS
DIS
BOOT
UGATE
PHASE
LGATE
VOUT
PR8910
PR8910
1 2
DIS
DIS
249KR2F -GP
249KR2F -GP
+GFX_CO RE_BOOT + GFX_CORE_BOO T_C
13
+GFX_CO RE_UGATE
12
+GFX_CO RE_PHASE +GFX_CO RE_VDD
11
+GFX_CO RE_LGATE
8
7
G0
+GFX_CO RE_FB
3
FB
14
G1
PWRC NTL_1#
5
D1
PWRC NTL_0#
6
D0
+GFX_CO RE_VOUT
1
PR8902
PR8902
DIS
DIS
1R3J-L1-G P
1R3J-L1-G P
1 2
PWRC NTL_0 (82)
PWRC NTL_1 (82)
PC8906
PC8906
1 2
DIS
DIS
SCD1U25 V3KX-GP
SCD1U25 V3KX-GP
D I S
DIS
PU8904
PU8904
1 2
D I S
DIS
PC8914
PC8914
SC10U25V6KX-1GP
SC10U25V6KX-1GP
678
DDD
DDD
G
DIS_65MOS
G
DIS_65MOS
4 5
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
2
1117-6
DIS
DIS
1 2
1 2
PC8907
PC8907
PC8911
PC8911
DIS
DIS
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
Vout=0.75V*(R1+R2)/R2
Design Current = 21.94A
24.14A<OCP< 28.53A
1 2
1 2
D I S
DIS
PC8905
PC8903
PC8903
PC8905
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
0114-1
PL8901
PL8901
DIS
DIS
1 2
COIL-D56UH -2-GP
COIL-D56UH -2-GP
1 2
PR8906
PR8906
DY
DY
2D2R5F-2 -GP
D
D
SSS
SSS
123
2D2R5F-2 -GP
VGA_CORE_DIV
1 2
PC8910
PC8910
SC330P5 0V2KX-3GP
SC330P5 0V2KX-3GP
DY
DY
+GFX_CO RE_VOUT
PR8908
PR8908
10KR2F-2 -GP
10KR2F-2 -GP
DIS
DIS
DIS
DIS
1 2
PG8920
PG8920
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
DY
1 2
DY
PC8917 SC10P50V2JN-4GPDYPC8917 SC10P50V2JN-4GP
1
+VGA_CORE
1 2
1 2
PTC8901
PTC8901
SE330U2VDM-L-GP
SE330U2VDM-L-GP
1 2
1 2
PTC8902
PTC8902
PTC8903
PTC8903
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
DY
DY
DIS
DIS
DIS
DIS
PC8915
PC8915
1 2
PC8913 SC10P50V2JN-4GPDYPC8913 SC10P50V2JN-4GP
DIS
DIS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
0210-1
+GFX_CO RE_FB
DIS
DIS
1 2
PR8909
PR8909
150KR2F -L-GP
150KR2F -L-GP
PWRCNTL_0#
1 2
PR8911
PR8911
49K9R2F -L-GP
49K9R2F -L-GP
DIS
DIS
1 2
PR8912
PR8912
49K9R2F -L-GP
49K9R2F -L-GP
DIS_PowerPlay
DIS_PowerPlay
PWRCNTL_1#
M96 Power Table Park Power Table
PWRCNTL_0 +VCC_GFX_CORE
H
L
H
L 1.1V
PR8912=49.9KR
64.49925.6DL
A A
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037
5
4
PWRCNTL_1
H
H
L
L
0.9V
0.95V
1.05V
PWRCNTL_0 +VCC_GFX_CORE
H
L
H
L 1.12V
PWRCNTL_1
H
H
L
L
PR8912=49.9KR
64.44225.6DL
3
0.9V
0.95V
1.05V
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
RT8208B_+VCC_GFXCORE
RT8208B_+VCC_GFXCORE
RT8208B_+VCC_GFXCORE
ocument Nu mber Rev
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
89 95 Thu rsday, March 04, 2010
89 95 Thu rsday, March 04, 2010
89 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
APL5930 for +1.8V_RUN_VGA
+1.8V_RU N_VGA_P +1.8V_RUN_V GA
PG9002
PG9002
D D
+5V_ALW
DIS
DIS
C C
DIS
DIS
+3.3V_RU N +1 .8V_RUN_VGA_V IN
PG9001
PG9001
DIS
DIS
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG9004
PG9004
DIS
DIS
GAP-CLOS E-PWR
GAP-CLOS E-PWR
R9006
R9006
100KR2J -1-GP
100KR2J -1-GP
1 2
1.8V_DIS_GATE
5
6
123 4
1.8V_DIS
1.8V_VGA _RUN_EN
Vo=0.8*(1+(R1/R2))
PQ9001
PQ9001
2N7002E DW-GP
2N7002E DW-GP
84.27002.F3F
84.27002.F3F
DIS
DIS
1 2
R9005 10R2J-2-G P
R9005 10R2J-2-G P
1 2
1 2
1.8V_VGA _RUN_EN (37,5 2)
RUNPW ROK (49,51,52,89 )
1.8V_VGA _RUN_EN_C
1 2
PR9002
PR9002
0R0402-P AD
0R0402-P AD
+1.8V_RU N_VGA
Vout=0.8V*(R1+R2)/R2
5V, 1.5mA
PC9002
PC9002
SC1U10V 2KX-1GP
SC1U10V 2KX-1GP
1 2
PC9001
PC9001
DY
DY
APL5930 KAI-TRG-GP
APL5930 KAI-TRG-GP
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
APL5930KAI for +1.0V_RUN_VGA
+5V_RUN +1.8V_RUN_V GA_VIN
1 2
DIS
DIS
6
PU9001
PU9001
7
POK
8
EN
DIS
DIS
VIN#5
VIN#9
VCNTL
VOUT#3
VOUT#4
GND
1
5
9
3
4
2
FB
SO-8-P
Will be Change to +1.0V_RUN_VGA
5912_1.8V_DELAY_FB
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
16K5R2F-2-GP
16K5R2F-2-GP
DIS
DIS
1 2
PC9003
PC9003
DIS
DIS
1 2
PR9003
PR9003
1 2
PR9006
PR9006
13K3R2F -L1-GP
13K3R2F -L1-GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC68P50V2JN-1GP
SC68P50V2JN-1GP
DY
DY
DIS
DIS
1 2
PC9004
PC9004
PC9005
PC9005
1 2
1 2
DIS
DIS
GAP-CLOS E-PWR
GAP-CLOS E-PWR
PG9003
PG9003
1 2
DIS
DIS
GAP-CLOS E-PWR
GAP-CLOS E-PWR
Design Current =1.13A
+1.8V_RU N_VGA_P
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
PC9006
PC9006
1 2
DIS
DIS
DY
DY
1 2
PC9007
PC9007
+3.3V_RUN_VGA
+3.3V_RU N
3.3V_RUN _VGA_EN (3 7)
100KR2J -1-GP
100KR2J -1-GP
1 2
R9002
R9002
DIS_M96
DIS_M96
84.27002.F3F
84.27002.F3F
3.3V_ALW _1
2N7002E DW-GP
2N7002E DW-GP
DIS_Park/Mad
DIS_Park/Mad
1 2
R9001 0R2J-2-GP
R9001 0R2J-2-GP
Q9001
Q9001
D S
DIS_M96
DIS_M96
SI2301CDS -T1-GE3-GP
SI2301CDS -T1-GE3-GP
Id: 2A
G
Rds: 0.15ohm
5
6
Q9002
Q9002
DIS_M96
DIS_M96
123 4
3.3V_RUN _VGA_1
+3.3V_RU N_VGA
1 2
R9004
R9004
100R2J-2 -GP
100R2J-2 -GP
DIS_M96
DIS_M96
1208-1
6
VIN#5
VIN#9
VCNTL
VOUT#3
VOUT#4
GND
1
+1.5V_SU S
5
9
3
4
2
FB
SO-8-P
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
PC9009
PC9009
D IS
DIS
12KR2F-L-GP
12KR2F-L-GP
1 2
PR9009
PR9009
DIS
DIS
5930_1.0 VRUN_FB
1 2
PR9011
PR9011
32K4R2F -1-GP
32K4R2F -1-GP
DIS
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1 2
PC9010
PC9010
DY
DY
+1.0V_RUN_VGA
Design Current: 1.51A
+1.0V_RU N_VGA
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2
PC9012
PC9012
DIS
DIS
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
3
1 2
PC9013
PC9013
DIS
DIS
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PC9014
PC9014
1 2
DY
DY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size D
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
DISCRETE VGA POWER
DISCRETE VGA POWER
DISCRETE VGA POWER
ocument Nu mber Rev
Berry
Berry
Berry
Taipei Hsien 221, Taiwan, R.O.C.
90 95 Tuesd ay, March 09, 201 0
90 95 Tuesd ay, March 09, 201 0
90 95 Tuesd ay, March 09, 201 0
1
A00
A00
A00
5V, 1.5mA
PC9008
PC9008
SC1U10V 2KX-1GP
B B
+3.3V_AL W
R9007
R9007
100KR2J -1-GP
100KR2J -1-GP
DIS
DIS
1 2
1.0V_DIS_GATE
5
6
DIS
DIS
123 4
A A
1.0V_RUN _VGA_EN
5
1.0V_RUN _VGA_EN (37)
PQ9002
PQ9002
2N7002E DW-GP
2N7002E DW-GP
84.27002.F3F
84.27002.F3F
DIS
DIS
1.0V_DIS
1 2
R9010 10R2J-2-G P
R9010 10R2J-2-G P
+1.0V_RU N_VGA
RUNPW ROK (49,51,52,89 )
1 2
PR9007
PR9007
0R0402-P AD
0R0402-P AD
Vout=0.8V*(R1+R2)/R2
SC1U10V 2KX-1GP
1.0V_RUN _VGA_EN_C
1 2
PC9011
PC9011
DY
DY
SC4700P50V2KX-1GP
SC4700P50V2KX-1GP
4
+5V_ALW
1 2
DIS
DIS
PU9002
PU9002
7
POK
8
EN
DIS
DIS
APL5930 KAI-TRG-GP
APL5930 KAI-TRG-GP
5
4
3
2
1
POWER SEQUENCE
D D
C C
B B
A A
5
+PWR_SRC
+3.3V_RTC_LDO
VBAT(+RTC_CELL)
KBC_ROM_STRAPS
S5_ENABLE
+3.3V_ALW
+5V_ALW
WAKE#(PCIE_WAKE# )
RSMRST#(KBC_RSMR ST#)
S5_ROM_STRAPS
PWR_BTN#(PM_PWRB TN#)
PM_SLP_S3#/PM_SL P_S5#
+3.3V_RUN, +5V_R UN
+1.5V_SUS
+0.75V_DDR_VTT
+1.8V_RUN
+VGA_CORE
+2.5V_RUN
1.5V_RUN_EN, 1.0 V_RUN_VGA_EN
+1.5V_RUN, +1.0V _RUN_VGA
1.8V_VGA_RUN_EN
+1.8V_RUN_VGA
3.3V_RUN_VGA_EN
+3.3V_RUN_VGA
RUNPWROK
+CPU_VDDR
IMVP_VR_ON
+VCC_CORE, +VDDN B
IMVP_PWRGD
+1.1V_RUN
VDDC_PWRGD
SB_PWRGD
S0_ROM_STRAPS
NB_PWRGD
LDT_PG(CPU_LDT_P WRGD)
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
91 95 Thu rsday, March 04, 2010
91 95 Thu rsday, March 04, 2010
91 95 Thu rsday, March 04, 2010
1
A00
A00
A00
5
4
3
2
1
Change notes - Page 1
PAGE OWNER DATE VERSON Issue Description Modify List ITEM
11/6 X01
D D
11/9
11/10
11/11
11/12
C C
11/13
11/16
B B
11/17
A A
1 10 Add C1002 10uF, C1007, EC1001 0.1uF, C1008 10pF. Insure signal quality. EE
2 13 Change R1314 to 4.7K. Meet CRB. EE
3 51 Swap PU5101 pin3, pin4. Correct input voltage level. EE
4 82 Add R8210 0R.
Reserve GPU clock input source.
1 30 Change C3014 to 2.2uF. Reduce package size. EE
Change C6903 to 0.1uF. 2 69 Reduce package size.
3 49 Add PR4916 100KR.
To prevent leakage in S3 status. EE
18,19 1 ME Request by ME. Change DIMM socket Part Number.
37 2 EE To detect leakage current. Add R3754 100KR.
1 10 EE Modify R1028 pull-up to +1.5V_RUN. Solve leakage in S3 status.
1 20 EE Change C2011 to 18pF, C2012 to 15pF. Set accurate clock frequency.
2 37 EE Add C3717 10pF. Stable singal level.
3 Delete RN5711, RN5705. EE 57 Redundant parts.
4 13 EE Delete R1331, R1332, R1308.
Redundant parts.
5 77 EMC Add Pi-filter. Cure EMI.
1 20 Sourcer Change X2001 P/N. Request by Sourcer.
2 7 EE Change R713 to 47R. Fine tune damping.
3 82 EE Add R8211 80.6R, R8220 150R.
Set a voltage divider to 1.8V level swing.
4 21 EE Add R2133 1KR. For UMA VRAM vendor selection.
1 22 EE Delete RN2203 pin 4, pin 5 connection. Solve S5 leakage.
2 51 Change PR5105 pull-up to +3.3V_RUN. Prevent leakage. EE
3 21 Add C2103, C2104 0.1uF. For signal stability. EE
4 37 Add C3718 0.1uF. EE
5 41 Add C4101, C4102 0.1uF. EE
6 49 Add PC4923 0.1uF. EE
7 66 Add C6601, C6602 0.1uF. EE
For signal stability.
For signal stability.
For signal stability.
For signal stability.
8 77 Add RN7713 150R. Move impedance matching resistor from CRT/B to M/B. EMC
9 78 Change CARDBD1 pin 2 link to PLTRST#_LAN_WAN. Change card reader chip to RTS5159 to solve EMI. EMC
1 30 Add R3014, R3017, R3020 0R to link AGND and GND. Issue for pop noise when system boot. EE
2 42,48,50 Merge 1.1V power solution on main board. Save components. EE, Power
3 77 Modify CRTBD1 pin define. Relief EMI. EMC
4 79 Add some decoupled capacitors. Request by EMC. EMC
5 37 Change R3737 to 33R, stuff C3715 10pF.
6 62,89 Sutff EC6203 22pF, PC8911, PC8907 0.1uF. EMC
7 45,46,47 Stuff EC4502 0.1uF, PC4605, PC4609, PC4738 0.1uF.
5
4
Request by EMC. EMC
Request by EMC.
Request by EMC. EMC
3
EE
EE
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Change notes
Change notes
Change notes
1
A00
A00
92 95 Thursday, March 04 , 2010
92 95 Thursday, March 04 , 2010
92 95 Thursday, March 04 , 2010
A00
5
4
3
2
1
Change notes - Page 2
PAGE OWNER DATE VERSON Issue Description Modify List ITEM
11/17 X01
11/18
D D
11/19
11/20
C C
11/24
11/25
B B
11/29
X02 12/04
12/05
12/08 Implement co-layout Madison and M96.
12/15
A A
8 9 Delete R904. Remove redundant layout trace. EE
1 81 Swap R8105, C8103 location. Meet CRB. EE
2 79 Add some decoupled capacitor. By RF team request. RF
3 49 Change PR4903 to 620KR. Power
Change to common part.
1 All Synchronize with DJ schematic. Schematic standardlize. EE
Change P/N for PU4802, PU4803, PU4804, PU4805. 2 48 Rquest by Power team
3 All Review all capacitors tolerance.
Total review for deratig. EE
21 4 EE Reserve to fine tune signal quality. Add RN2105 0R.
21 5 EA Fine tuned value for signal. Change RN2101 to 4.7KR.
6 37 EA Add RN3705, R3755 0R. To isolate layout trace to DB1 connector.
7 49 EA Change PC4908 to 2.2uF. Changed by EA report.
1 54 EE Modify R5408 connection. To synchronize with DJ.
2 Add D7701. EE 57 To prevent leakage from RGB monitor.
3 86 EA Add C8626 0.1uF.
By EA report.
4 37 EE Add R3756 10KR, C3720 0.1uF. Synchronize with DJ.
5 37 EE Delete RN3705, R3755. For more layout space.
6 13 EE Delete TP1303, TP1304.
7 49 EE Delete PR4905.
For more layout space.
For more layout space.
8 89 EE Add PC8918 0.1uF. Stable signal quality.
1 46,49 Power Change PU4601, PU4901 Power components. Request by Power team.
1 46,47,49,89 Change power components. Request by Power team. Power
1 10 Change C1008 to 10pF. Fine tuned signal slew rate to meet specification. EE
2 30 Change R3007 to 2.2KR. EE
1 81 Set BOM mark R8104, R8106, R8107, R8110, R8111, R8112. EE
2 82,84 Add R8407, R8408 0R. EE
3 80 Add R8016 10KR. EE
4 83,84 Set BOM mark. EE
5 83 Add L8306, L8307, C8397, R8301, R8302, R8303. EE
By FAE suggestion.
Implement co-layout Madison and M96.
Implement co-layout Madison and M96.
Implement co-layout Madison and M96.
Implement co-layout Madison and M96.
Implement co-layout Madison and M96.
1 37 Change R3756, C3720 connection. Correct soft-start for EC power. EE
1 90 Set BOM mark. EE
1 15 Delete RN1501, Add G1501~G1504. Synchronize with DJ and supply sufficient power rail. EE
2 62 Add R6207 100KR. Insure SPI Write-Protect pin signal level. EE
3 66 Change C6602 net name.
4 81 Add R8122 1KR, RN8101 4.7KR. EE
5 82 Swap CLK_VGA_27M_NSS and CLK_VGA_27M_SS connection.
5
4
Correct signal name. EE
Meet M96 schematic check list.
Solve external RGB display tremble issue. EE
3
Power
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Change notes
Change notes
Change notes
1
A00
A00
93 95 Thursday, March 04 , 2010
93 95 Thursday, March 04 , 2010
93 95 Thursday, March 04 , 2010
A00
5
4
3
2
1
Change notes - Page 3
PAGE OWNER DATE VERSON Issue Description Modify List ITEM
12/16 X02
D D
12/17
12/18 1 82 Add R8222 1MR. Assure crystal resonant clock stable. EE
12/25
C C
B B
01/06 1 50 Add PR5004 10KR and empty PR5002. Avoid +1.1V_ALW leakage in South Bridge. EE
01/07 1 7 Add RN712,C722,C723 Reserve for SMBus signal quality tuning. EE
A A
01/08 1 79 Reserve EC7925,EC7926,EC7927. Reserve by EMC team. EMC
1 66 Change R6605 to 0R. Assure power button level set to low. EE
2 37,76 Add net "8103_GPO". Implement LAN DSM hardware function. EE
1 37 Add U3703. To solve SPI WP signal malfunction on EC. EE
2 81 Set VRAM reset circuit. Follow M96 reset circuit and reseve BOM option. EE
1 18 Change TC1801 to 330uF, 2V tolerance. Implement common part for 1.5V power rail. EE
2 46 Change PR4603 to 127KR. Set 5V current limitation. Power
3 46 Empty PR4618 and stuff PR4619. Set Ultra-sonic mode to keep +15V_ALW voltage level. Power
4 10 Set RN1006 PU to +1.5V_SUS. Follow AMD check list and cure +1.5V_RUN leakage. EE
5 62 Change R6206 to 1KR. According to Safety request, verified OK. Safety
6 51 Change PR5102 1KR, PR5106 8.2KR, PR5107 5.62KR. Set VDDR low voltage level to 0.9V. EE
1 10,37 Add Q1005, R1039, R1040. Request by AMD to set CPU into HTC mode in DOS. EE 12/29
2 47 Change PR4720 93.1KR, PR4721 24KR. Set power OCP value. Power
1 ALL Change some resistors as short-pad or resistor array. Save component counts. EE 12/31
2 ALL Change some capacitors with smaller value or empty. Save component counts. EE
1 15 01/04 Change R1507,R1508,R1509,R1510,R1511 to bead. Filter power noise. EMC
1 01/05 7 Combine R707,R721 as RN711. For more layout space. EE
2 81 Delete TP8101,TP8102. Remove useless test point for more layout space. EE
3 7,80 Delete R716,R8020, combine R8009,R8010 as RN8001. Redundant part. EE
4 37,39,41 R3747,R4104 short pad, delete R3722,R3904. Redundant part. EE
5 46 Change PR4620 as short pad. Redundant part. EE
6 51 Change PQ5101 with ESD protector. Change to common part. Power
7 54 Empty R5405 and Stuff R5408. Avoid LCD white panel. EE
8 62 Change R6205 to 0R. Already have one 1KR ahead. EE
2 13 Change R1342 to size 0603. Synchronous schematic w/DJ. EE
3 79 Add R7921 and R7922. Reserved RF team solution. RF
2 60 Change EC6007,EC6008 to 0.01uF. According FAE Request. IDT FAE
3 39 Add Q3904. According thermal team request. Thermal
4 21,18 Change location RN2105 to RN1801, add C1823,C1824. For SMBus signal quality fine tune. EE
5 39,82,83 Remove C3912,TP8301,TP8302,TP8213. Remove dummy part for more layout space. EE
6 76 Reserve C7601, C7602. Fine tune USB signal quality. EE
2 77 Change RN7711 to 0R, L7701,L7702,L7703 to bead 22R. According EMC measurement result. EMC
5
4
3
0108
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Berry AMD Discrete/UMA
Taipei Hsien 221, Taiwan, R.O.C.
Change notes
Change notes
Change notes
1
A00
A00
94 95 Thursday, March 04 , 2010
94 95 Thursday, March 04 , 2010
94 95 Thursday, March 04 , 2010
A00
5
4
3
2
1
Change notes - Page 4
PAGE OWNER DATE VERSON Issue Description Modify List ITEM
3 18,19 Add C1825,C1922. Reduce V_REF ripple by EA team result. EE 01/08 X02
4 37 Reserve C3721,C3722. Prevent signal cross talk. EE
D D
01/11
A00 02/08 1 66 Add for future LED brightness balance. Reserve R6609, R6610 1KR. EE
C C
02/10 1 Power Update Obsolete parts. Update obsolete parts due to policy. Power
02/22 1 54 Remove co-layout pad. As factory requst. EE
02/23 1 ALL Change to short pad. Change most of 0-ohm resistors to short pad. EE
B B
02/24 1 7,68,79 Reserve C724, C725, C6806, C6807, EC7928-EC7932. As EMC team request. EMC
02/25 1 13 Add TP1309. As factory requset to add. Factory
02/26 1 39,42 Empty R3906 and Change R4202 from 0R to 1KR. It is for solving T8 shutdown issue. EE
03/03 1 60 Change SPK1 part number. Request by ME. ME
03/05 1 20,24,37 Empty R2029,R2404,R3751. Saving unused components. EE
03/08 1 48 Stuff PU4803 and empty PU4804. Place the H/S and L/S MOS at the same surface. Power
A A
5 ALL Change capacitors value and add C3723. Ensure signal quality. EE
1 68 Change KB1 P/N. According ME request. ME
2 66 Change R6601,R6602,R6604,R6606 to 1KR, R6603 to 470R. Decrease LED brightness. EE
1 37 Add C3724, R3757. To set accurate current detection in EC. EE 01/12
2 10 Add R1041 0R. Add 0R for level shift off. EE
1 21,37 Add C3725, C2105. EE 01/13 Reserve for singal quality.
Request by Power Team. 1 Power Modify power team componets. 01/14 Power
2 7 Fine tuned damping resistor value. Change RN712 to 22R. EE
2 68 Add keyboard back light circuit, remove R5403. Add for keyboard with back light module. EE
3 69 Change HALLSW1 footprint for co-layout. Change for co-layout different kind of HALLSW1. EE
4 77 Add AFTP7701, AFTP7702, AFTP7703. Add AFTP test point for factory test. EE
2 79 Change HBT1 part number. Change HBT1 part number to match ME EMN file. ME
3 47 Add PTC4710. Add to solve board accoustic issue. EE
2 42 Add C4217, C4401, C4402. Ensure signal quality. EE
3 48 Delete Power Gap. Request by Power Team. Power
2 7,68 Rename EMC capacitor to EC704,EC705,EC6801,EC6802. Meet schematic standardization. EE
3 49,89 Change PR4913 to 3.9R, PR8905 to 6.98KR. PR4913 for snubber, PR8905 for OCP. Power
4 21 Change R2133 to 0R. Set GPIO input level from 0.5V to 0V. EE
5 79 Remove EC7928. Layout space limitation. EE
0308-1
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Change notes
Change notes
Change notes
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Berry
A3
Berry
A3
Berry
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
95 95 Mon day, March 08, 2010
95 95 Mon day, March 08, 2010
95 95 Mon day, March 08, 2010
A00
A00
A00