AMD Advanced Micro Devices AM29F010B-70PIB, AM29F010B-70PI, AM29F010B-70PEB, AM29F010B-70PE, AM29F010B-70PCB Datasheet
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FINAL
Publication# 16736 Rev: G Amendment/+2
Issue Date: March 1998
Am29F010
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
—5.0 V ± 10% for read, erase, and program
operations
— Simplifies system-level power requirements
■ High performance
— 45 ns maximum access time
■ Low power consumption
— 30 mA max active read current
— 50 mA max program/erase current
— <25 µA typical standby current
■ Flexible sector architecture
— Eight uniform sectors
— Any combination of sectors can be erased
— Supports full chip erase
■ Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
■ Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
■ Minimum 100,000 program/erase cycles
guaranteed
■ Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
2 Am29F010
GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 V olt-only Flash memory
organized as 131,072 bytes. The Am29F010 is offered
in 32-pin PLCC, TSOP, and PDIP packages. The bytewide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard
system 5.0 Volt V
CC
supply. A 12.0 volt VPP is not required for program or erase operations. The device can
also be programmed or erased in standard E PROM
programmers.
The standard device off ers acces s times of 45, 5 5, 70,
90, and 120 ns, allowing high- speed micropro ce ssor s
to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal stat e machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for t he programming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command seque nce. This in vokes the Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sec tor erase arc hitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection measures include a
low V
CC
detector automatically inhibits write operat ions
during power transitions. The hardware sector pro-
tection feature disables both program and erase operations in any combination of the sectors of memory,
and is implemented using standard EPROM programmers.
The system can place the device into the standby mode.
Power consumption is greatly reduced in t his mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
Am29F010 3
PRODUCT SELECTOR GUIDE
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F010
Speed Option
V
CC
= 5.0 V ± 5% -45 -55 (P)
V
CC
= 5.0 V ± 10% -55 (J, E, F) -70 -90 -120
Max Access Time (ns) 45 55 70 90 120
CE# Access (ns) 45 55 70 90 120
OE# Access (ns) 25 30 30 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
V
CC
V
SS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Data
Latch
Y-Gating
Cell Matrix
16736G-1
Address Latch
A0–A16
4 Am29F010
CONNECTION DIAGRAMS
16736G-2
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
V
SS
A8
A9
A11
OE#
A10
CE#
DQ7
V
CC
WE#
DQ6
NC
A14
A13
DQ5
DQ4
DQ3
NC
PDIP
DQ6
NC
DQ5
DQ4
DQ3
1
31 30
2
3
4
5
6
7
8
9
10
11
12
13
17
18
19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
VCCWE#
NC
DQ1
DQ2
V
SS
PLCC
16736G-3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard TSOP
16736G-4
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A
3
16736G-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A
3
Reverse TSOP
Am29F010 5
PIN CONFIGURATION
A0–A16 = 17 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
V
CC
= +5.0 Volt Single Power Supply
(See Product Selector Guide for speed
options and voltage supply tolerances)
V
SS
= Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
17
8
DQ0–DQ7
A0–A16
CE#
OE#
WE#
16736G-6
6 Am29F010
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DE SCR IP TIO N
Am29F010
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Am29F010 -70 E C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
(Contact an AMD representative for more information.)
TEMPERATURE RANGE
C = Commercial (0
°C to +70°C)
I=Industrial (–40
°C to +85°C)
E = Extended (–55
°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded
Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
B
Valid Combinations
AM29F010-45
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
AM29F010-55
V
CC
= 5.0 V ± 5%
PC5, PI5, PE5
AM29F010-55
VCC = 5.0 V ± 10%
JC, JI, JE, EC, EI, EE, FC, FI, FE
AM29F010-70
AM29F010-90
AM29F010-120
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Am29F010 7
DEVICE BUS OPERATIONS
This section describes the re quirements and us e of the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any ad dressable memory locatio n.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F010 Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D
OUT
= Data Out
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
IH
.
The internal state machine is set for reading array
data upon device power-up , or after a hardware reset. This ensures that no spurious alteration of the
memory content occu rs during the power trans ition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to VIH.
An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for the wr ite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Operation CE# OE# WE#
Addresses
(Note 1) DQ0–DQ7
Read L L H A
IN
D
OUT
Write L H L A
IN
D
IN
Standby VCC ± 0.5 V X X X High-Z
Output Disable L H H X High-Z
Hardware Reset X X X X High-Z
Temporary Sector Unprotect X X X A
IN
D
IN
8 Am29F010
Program and Erase Operation Status
During an erase or program operation, t he system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specificat ions apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet for t iming
diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mo de. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is held at V
CC
± 0.5 V. (Note that this is a more
restricted voltage range than V
IH
.) The device enters
the TTL standby mode when CE# is held at V
IH
. The
device requires the standard access time (t
CE
) before
it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Table 2. Am29F010 Sector Addresses Table
Autoselect Mode
The autoselect mode provides manu facturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding progra mming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V
ID
. See
“Command Definitions” for details on using the autoselect mode.
Sector A16 A15 A14 Address Range
SA0 0 0 0 00000h-03FFFh
SA1 0 0 1 04000h-07FFFh
SA2 0 1 0 08000h-0BFFFh
SA3 0 1 1 0C000h-0FFFFh
SA4 1 0 0 10000h-13FFFh
SA5 1 0 1 14000h-17FFFh
SA6 1 1 0 18000h-1BFFFh
SA7 1 1 1 1C000h-1FFFFh
Am29F010 9
Table 3. Am29F010 Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20495. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact a n
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to t he Comma nd Definitions table). In addition, the following hardware data
protection measures prevent accidental era sure or pro-
gramming, which might otherwise be caused by spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When VCC is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
Description CE# OE# WE#
A16
to
A14
A13
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
ID
XLXLL 01h
Device ID: Am29F010 L L H X X V
ID
XLXLH 20h
Sector Protection Verification L L H SA X V
ID
XLXHL
01h
(protected)
00h
(unprotected)
10 Am29F010
COMMAND DEFINITIONS
Writing specific address and data command s or sequences into the command register initiates device operations. The Command Defini tions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is a utomatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Em bedded Program or Embedded Erase algorithm.
The system
must
issue the reset command to re-enable the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device r esets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be w ritten between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be w ritten between the sequence cycles in a program command sequ ence before programming begins. This resets the device to
reading array data. Once programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be w ritten between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset command
must
be written to return to reading array data.
If DQ5 goes high during a program or erase operat ion,
writing the reset command returns the device to reading array data.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alt ernative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at add re ss X X00h or r et ri eves the man ufacturer code. A read cycle at address XX 01h returns
the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that
sector is protecte d, or 0 0h if i t is u np rotec ted . Refe r to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is
not
required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the programmed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the p rogram operation by usin g
DQ7or DQ6. See “Write Operation Stat us” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indic ate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
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