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查询Am29F010B供应商
Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 V ± 10% f or read, er ase, and program o perations
— Simplifies system-level power requirements
■ Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
■ High performance
— 45 ns maximum access time
■ Low power consumption
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
■ Flexible sector arc hitecture
— Eight 16 Kb yte sectors
— Any combination of sector s can be er ased
— Supports full chip erase
■ Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/ unprotection can be
implemented using standard PROM
programming equipment
■ Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
■ Erase Suspend/Resume
— Supports reading data from a sector not
being erased
■ Minimum 1 million erase cyc les guara nteed per
sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22336 Rev: C Amendment/0
Issue Date: November 28, 2000
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GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010B
is offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The devi c e i s d e si g n e d t o b e p r o g r a m m e d in-system with the
standard system 5.0 Volt V
required for program or erase opera tion s. The device can
also be programmed or erased i n standard EPROM
programmers.
This device is manufactured using AMD’ s 0.32 µm process technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wai t states . To eliminate bus contention the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an interna l state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This inv okes the Embed ded Pro-
gram algorithm—an internal algorithm that
supply. A 12.0 v o lt VPP is not
CC
automatically times the program puls e wid ths a nd
veri fies proper cell margin.
Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase
algorithm—an in ternal algorithm that auto matically
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection m easures include a
low V
detector automatically inhibits write operations
CC
during power transitions . T he hard ware sector protection feature disables both progr am and erase operations
in any combination of the sectors of memory, and is implemented using standard EPROM programmers.
The system can place the devic e into the standb y mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electri cally erases all bits
within a sector s imultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
2 Am29F010B
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TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29F010B Device Bus Operations .................................9
Requirements for Reading Array Data ........................ .............9
Writing Commands/Command Sequences ......... ................... ..9
Program and Erase Operation Status .................................... 10
Standby Mode .................... ............................. ................ .......10
Output Disable Mode ..............................................................10
Table 2. Am29F010B Sector Addresses Table ...............................10
Autoselect Mode .....................................................................10
Table 3. Am29F010B Autoselect Codes (High Voltage Method) . ...11
Sector Protection/Unprotection ............................................... 11
Hardware Data Protection ......................................................11
Low VCC Write Inhibit ......................................................................11
Write Pulse “Glitch” Protection ........................................................11
Logical Inhibit ................................. ....... ....... .... ..... ....... ......... ....... ...11
Power-Up Write Inhibit ....................................................................11
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data ................................................................12
Reset Command .................................... ............................. ....12
Autoselect Command Sequence ..................................... .......12
Byte Program Command Sequence .......................................12
Figure 1. Program Operation ..........................................................13
Chip Erase Command Sequence ...........................................13
Sector Erase Command Sequence ........................................13
Erase Suspend/Erase Resume Commands .................. .........14
Figure 2. Erase Operation ...............................................................14
Command Definitions .............................................................15
Table 4. Am29F010B Command Definitions ...................................15
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 16
DQ7: Dat a# Po ll i n g ... .. .. ........................... .............. .............. ...16
Figure 3. Data# Polling Algorithm ...................................................16
DQ6: Toggle Bit I ....................................................................16
Reading Toggle Bit DQ6 .........................................................17
Figure 4. Toggle Bit Algorithm .........................................................17
DQ5: Exceeded Timing Limits ................................................17
DQ3: Sector Erase Timer .......................................................18
Table 5. Write Operation Status .....................................................18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 19
Figure 5. Maximum Negative Overshoot Waveform ........... ..... .... ..19
Figure 6. Maximum Posi tive Overshoot Waveform ........................19
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Test Setup ....................................................................... 22
Table 6. Test Specifications ...........................................................22
Key to Switching Waveforms . . . . . . . . . . . . . . . 22
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Read Operatio n s Ti mi n g s .................. ............................. 23
Erase and Program Operations ......................................................... 24
Figure 9. Program Operation Timings ............................................ 2 5
Figure 10. Chip/Sector Erase Operation Timings .......................... 25
Figure 11. Data# Polling Timings (During Embedded Algorithms) . 26
Figure 12. Toggle Bit Timings (During Embedded Algorithms) ...... 26
Erase and Program Operations ......................................................... 27
Alternate CE# Controlled Writes .................................................... 27
Figure 13. Alternate CE# Controlled Write Operation Timings ...... 2 8
Erase and Programming Performance . . . . . . . 28
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 29
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
PLCC and PDI P P in Capacitance . . . . . . . . . . . . 29
Data Retenti on . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 30
PD 032—32-Pin Plastic DIP ...................................................30
PL 032—32-Pin Plastic Leaded Chip Carrier .........................31
TS 032—32-Pin Standard Thin Small Outline Package .........32
TSR 032—32-Pin Standard Thin Small Outline Package ..... ..33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision A (August 12, 1999) .................................................34
Revision A+1 (September 22, 1999) .................................... ..34
Revision A+2 (September 27, 1999) .................................... ..34
Revision B (November 12, 1999) ............................................34
Revision C (November 28, 2000) ........................................... 34
Am29F010B 3
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PRODUCT SELECTOR GUIDE
Family Part Number Am29F010B
= 5.0 V ± 5% -45
V
Speed Option
Max Access Time (ns) 45 55 70 90 120
CE# Access (ns) 45 55 70 90 120
OE# Access (ns) 25 30 30 35 50
CC
= 5.0 V ± 10% -55 -70 -90 -120
V
CC
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
DQ0
–
DQ7
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
WE#
CE#
OE#
A0–A16
State
Control
Command
Register
VCC Detector
PGM Voltage
Generator
Timer
Chip Enable
Output Enable
STB
Logic
Address Latch
Y-Decoder
X-Decoder
STB
Data
Latch
Y-Gating
Cell Matrix
4 Am29F010B
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CONNECTION DIAGRAMS
A7
A6
A5
A4
A3
A2
A1
A0
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PDIP
NC
A16
A15
A12
DQ0
DQ1
DQ2
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
14
A12
4
15
DQ1
A15
3
DQ2
A16
1
2
PLCC
17
SS
V
NC
32
18
DQ3
VCCWE#
31 30
19 2016
DQ5
DQ4
NC
29
28
27
26
25
24
23
22
21
DQ6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
Am29F010B 5
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CONNECTION DIAGRAMS
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A
1
2
3
4
5
6
7
8
Standard TSOP
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Reverse TSOP
10
11
12
13
14
15
16
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A
3
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
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PIN CONFIGURATION
A0–A16 = 17 Addresses
LOGIC SYMBOL
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
V
CC
= +5.0 Volt Single Power Supply
(See Product Selector Guide f o r speed
options and voltage supply tolerances)
V
SS
= Device Ground
NC = Pin Not Connected Internally
17
A0–A16
CE#
OE#
WE#
8
DQ0–DQ7
Am29F010B 7
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ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F010B 70 E C
TEMPERATURE RANGE
C = Commercial (
I = Industrial (–40°C to +85°C)
E = Extended (–55
PACKAGE TYPE
P = 32-Pin Plastic PDIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
0°C to +70°C)
°C to +125°C)
Valid Combinations VCC Voltage
Am29F010B-45
Am29F010B-55
Am29F010B-70
Am29F010B-90
Am29F010B-120
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
5.0 V ± 5%
5.0 V ± 10%
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
8 Am29F010B
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DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory
location. The register is composed of latches th at store
the commands, along with the address and data infor-
of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.
mation needed to execute the command. The contents
Table 1. Am29F010B Device Bus Operations
Addresses
Operation CE# OE# WE#
Read L L H A
Write L H L A
Standby VCC ± 0.5 V X X X High-Z
Output Disable L H H X High-Z
Hardware Reset X X X X High-Z
Legend:
L = Logic Low = V
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D
IL
(Note 1) DQ0–DQ7
IN
IN
D
D
= Data Out
OUT
OUT
IN
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates arra y data to the output pins . WE# should
remain at V
.
IH
The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address input s produc e valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specification for
reading array data.
. CE# is the power
IL
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
An erase operation can erase one sect or, multiple sectors, or the entire device. The Sector Addre ss Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the
entire chip.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
, and OE# to VIH.
IL
in the DC Characteristics table represents the ac-
Am29F010B 9
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Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet f or t iming
diagrams.
CC
The device enters the CMOS standby mode when the
CE# pin is held at V
0.5 V. (Note that this is a more
±
CC
restricted voltage ran ge than V
the TTL standby mode when CE# is held at V
device requires the standard ac cess time (t
is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
Standby Mode
When the system is not reading or writing to the device ,
in the DC Characteristics tables represents the
I
CC3
standby current specification.
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
Table 2. Am29F010B Sector Addresses Table
Sector A16 A15 A14 Address Range
SA0 0 0 0 00000h-03FFFh
SA1 0 0 1 04000h-07FFFh
.) The device enters
IH
IH
) before it
CE
. The
SA2 0 1 0 08000h-0BFFFh
SA3 0 1 1 0C000h-0FFFFh
SA4 1 0 0 10000h-13FFFh
SA5 1 0 1 14000h-17FFFh
SA6 1 1 0 18000h-1BFFFh
SA7 1 1 1 1C000h-1FFFFh
Note: All sectors are 16 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
on address pin A9. Address p ins A6,
ID
A1, and A0 must be as shown in Autoselect Codes
(High V oltage Method) table. I n addition, when verifying
sector protection, the sector address must appear on
the appropriate highest order address bits . Ref er to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that
are don’t care. When all necessary bits have been set
as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V
“Command Definitions” for details on using the autoselect mode.
. See
ID
10 Am29F010B
Page 11
Table 3. Am29F010B Autoselect Codes (High Voltage Method)
Description CE# OE# WE#
A16
to
A14
A13
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
Device ID: Am29F010B L L H X X V
Sector Protection Verification L L H SA X V
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sect or. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
) on address pin A9 and the
ID
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representative to obtain a cop y of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
ID
ID
ID
gramming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
Write Inhibit
CC
is less than V
CC
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent unintentional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
, CE# = VIH or WE# = VIH. To initiate a write cycle,
V
IL
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
protection measures pre vent accidental eras ure or pro-
XLXLL 01h
XLXLH 20h
01h
XLXHL
, the device does not ac-
LKO
. The system must provide the
LKO
is greater than V
CC
and OE# = VIH during power up , the
IL
(protected)
00h
(unprotected)
power-up and
CC
.
LKO
CC
CC
Am29F010B 11
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COMMAND DEFINITIONS
Writing specific addre ss and data commands or sequences into the command register initiates device
operations. The Command Definitions tab le defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Embedded Erase algorithm.
must
The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the
timing diagram.
issue the reset command to re-en-
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data. Once programming begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data.
must
Autoselect Command Sequence
The autoselect c ommand sequenc e allows the host
system to access the manufacturer and de vic es codes ,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is in tended for PROM programmers and requires V
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
on address bit A9.
ID
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
not
gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and v erify the programmed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7or DQ6. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored.
Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indic ate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
required to provide further
12 Am29F010B
Page 13
START
Write Program
Command Sequence
Data Poll
Embedded
Program
algorithm
in progress
Increment Address
Note: See the appropriate Command Definitions table for
program command sequence.
No
from System
Verify Data?
Yes
Last Address?
Yes
Programming
Completed
No
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
not
algorithm. The device does
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and ve rifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored.
The system can determine the status of the erase op-
eration by using DQ7 or DQ6. See “Write Operation
Status” for information on these status bits. When the
require the system to
Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no
longer latched.
Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for p arameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command . The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
not
The device does
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector erase commands can be assumed to be less than
50 µs, the system need not monitor DQ3. Any com-
mand during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the s ector
erase timer has timed out. (See the “DQ3 : Sector Erase
Timer” section.) The tim e-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, all other
commands are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6. Refer
to “Write Operation Status” for information on these
status bits.
require the system to preprogram
Am29F010B 13
Page 14
Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section f or par amet ers , and to
the Sector Erase Operations Ti ming diagr am for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the s yst em to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from any sector not selected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Normal read and write
timings and command definitions apply . Reading at any
address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7 to
determine if a sector is actively erasing or is er ase-suspended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is complete, the system can once again read arra y data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information.
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
START
Write Erase
Command Sequence
Data Poll
from System
No
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Data = FFh?
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
14 Am29F010B
Figure 2. Erase Operation
Page 15
Command Definitions
Table 4. Am29F010B Command Definitions
Bus Cycles (Notes 2-3)
Command
Sequence
(Note 1)
Read (Note 4) 1 RA RD
Reset (Note 5) 1 XXXX F0
Reset (Note 6) 3 555 AA 2AA 55 555 F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Autoselect
(Note 7)
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
Device ID 4 555 AA 2AA 55 555 90 X01 20
Sector Protect Verify
(Note 8)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Cycles
4 555 AA 2AA 55 555 90
(SA)
X02
00
01
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command
bus cycles are write operations.
4. No unlock or command cycles required when reading array
data.
5. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).
6. The device accepts the three-cycle reset command
sequence for backward compatibility.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16–A14 uniquely select any sector.
7. The fourth cycle of the autoselect command sequence is a
read operation.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
9. The system may read in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Am29F010B 15
Page 16
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ3, DQ5, DQ6, and DQ7.
Table 5 and the following subsections describe the
functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
completed. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase command sequence.
During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. When the Embedded Program
algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provi de the program address to read valid status information on DQ7.
If a program address falls within a pro tected sector,
Data# Polling on DQ7 is active for approximately 2 µs,
then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase algorithm is complete, Data# Polling produces a “1 ” on
DQ7. This is analogous to the complement/true datum
output described for the Embedded Progr am algorithm:
the erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
No
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
Yes
After an erase command sequence is written, if all s ectors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the
following
may change asynchronously with DQ0–DQ6 while
read cycles. This is because DQ7
2. DQ7 should be rechecked even if DQ5 = “1” because
Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
16 Am29F010B
No
FAIL
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
DQ7 may change simultaneously with DQ5.
PASS
Figure 3. Data# Polling Algorithm
Page 17
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whethe r an Embedded
Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all s ectors selected for eras ing are protected , DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
If a program address falls within a pro tected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
No
START
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
= Toggle?
Yes
DQ5 = 1?
Yes
(Note 1)
No
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 f or the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timin g diagram.
Reading Toggle Bit DQ6
Refer to Figure 4 for the following discussion. Whe never the system initially begins readin g toggle bit
status, it must read DQ7–DQ0 at least t wice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or era se operation. The system can
read array data on DQ7–DQ 0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to readin g
array data.
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
(Notes
1, 2)
No
Program/Erase
Operation Complete
Figure 4. Toggle Bit Algorithm
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successi ve read cycles , determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this cas e, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4).
Am29F010B 17
Page 18
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously programmed to “0.” Only an era se operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase comm and sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 µs.
See also the “Sector Erase Command Sequence”
section.
After the sector erase command sequenc e is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands are ignored until the
erase operation is complete. If DQ3 is “0”, the device
will accept additional sector erase commands. To ensure the command has been accepted, the system
software should check the status of DQ3 prior to and
following each subsequent sector erase com mand. If
DQ3 is high on the second status check, the last command might not have been accepted. Table 5 shows
the outputs for DQ3.
Table 5. Write Operation Status
DQ7
Operation
Standard
Mode
Erase
Suspend
Mode
Notes:
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Embedded Program Algorithm DQ7# Toggle 0 N/A
Embedded Erase Algorithm 0 Toggle 0 1
Reading within Erase Suspended Sector 1 No toggle 0 N/A
Reading within Non-Erase Suspended Sector Data Data Data Data
(Note 1) DQ6
DQ5
(Note 2) DQ3
18 Am29F010B
Page 19
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
(Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
V
CC
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.0 V
All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pin is – 0.5 V. Dur ing
voltage transitions, inputs may overshoot V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is V
age transitions, inp ut and I/O pins may overs hoot to V
+ 2.0 V for periods up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 pins may overshoot V
for periods of up to 20 ns. See Figure 5. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 14.0
V for periods up to 20 ns.
3. No more tha n one output short ed at a time. Durat ion of
the short circuit should not be greater than one second.
Stresses above thos e listed under “Ab solute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute m axi mum ratin g co ndi tions for
extended periods may affect device reliability.
+ 0.5 V. During volt-
CC
to –2.0 V
SS
to –2.0 V
SS
CC
+0.8 V
–0.5 V
–2.0 V
V
CC
+2.0 V
V
CC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 5. Maximum Negative
Overshoot Waveform
20 ns
20 ns
20 ns
Figure 6. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Case Temperatur e (T
Industrial (I) Devices
Case Temperatur e (T
Extended (E) Devices
Case Temperatur e (T
Supply Voltages
V
CC
for ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V
V
CC
for ±10% devices . . . . . . . . . .+4.50 V to +5.50 V
V
CC
Operating rang es define those limits between which the
functionality of the device is guaranteed.
) . . . . . . . . . . . . . 0°C to +70°C
A
) . . . . . . . . . . . –40°C to +85°C
A
) . . . . . . . . . . –55°C to +125°C
A
Am29F010B 19
Page 20
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
V
I
I
LIT
I
I
CC1
I
CC2
I
CC3
V
V
V
V
V
LKO
LI
LO
IH
ID
OL
OH
Input Load Current VIN = V
A9 Input Load Current V
Output Leakage Curren t V
V
Active Read Current
CC
(Notes 1, 2)
V
Active Write Current
CC
(Notes 2, 3, 4)
V
Standby Current CE# and OE# = V
CC
Input Low Voltage –0.5 0.8 V
IL
CC
OUT
CE# = V
CE# =
Input High Voltage 2.0 V
Voltage for A utoselect and Sector
Protect
V
CC
Output Low Voltage IOL = 12 mA, V
Output High Voltage IOH = –2.5 mA, V
Low VCC Lock-out Voltage 3.2 4.2 V
to VCC, V
SS
= V
Max, A9 = 12.5 V 50 µA
CC
= V
SS
OE# = V
IL,
OE# = V
VIL,
CC
to VCC, V
IH
IH
IH
= 5.0 V 10.5 12.5 V
= V
CC
CC
= V
CC
Notes:
1. The I
2. Maximum I
3. I
current listed is typically less than 2 mA/MHz, with OE# at VIH.
CC
specifications are tested with VCC=VCCmax.
CC
active while Embedded Program or Embedded Erase Algorithm is in progress.
CC
4. Not 100% tested.
= V
CC
= V
Max
CC
Max
CC
1.0 µA
±
1.0 µA
±
12 30 mA
30 40 mA
0.4 1.0 mA
+ 0.5 V
CC
Min 0.45 V
Min 2.4 V
CC
20 Am29F010B
Page 21
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
I
I
I
V
V
V
I
I
LIT
I
LO
CC1
CC2
CC3
V
V
V
V
OH1
OH2
LKO
Input Load Current VIN = V
LI
A9 Input Load Current V
Output Leakage Current V
V
Active Current (Notes 1, 2) CE# = V
CC
V
Active Current
CC
(Notes 2, 3, 4)
V
Standby Current (Note 5) CE# = V
CC
Input Low Voltage –0.5 0.8 V
IL
Input High Voltage 0.7 x V
IH
Voltage for Autoselect and
ID
Sector Protect
Output Low Voltage IOL = 12 mA, V
OL
Output High Voltage
CC
OUT
CE# = V
V
CC
I
OH
IOH = –100 µA, V
Low V
Lock-out Voltage 3.2 4.2 V
CC
to VCC, V
SS
= V
Max, A9 = 12.5 V 50 µA
CC
= V
to VCC, V
SS
OE# = V
IL,
OE# = V
IL,
0.5 V,
±
CC
= V
CC
CC
IH
IH
OE# = V
= 5.25 V 10.5 12.5 V
= V
CC
CC
= –2.5 mA, V
CC
CC
= V
= V
Notes:
1. The I
2. Maximum I
3. I
current listed is typically less than 2 mA/MHz, with OE# at VIH.
CC
specifications are tested with VCC=VCCmax.
CC
active while Embedded Program or Embedded Erase Algorithm is in progress.
CC
4. Not 100% tested.
5. I
= 20 µA max at extended temperatures (> +85°C).
CC3
= V
CC
CC
Max
Max
1.0 µA
±
1.0 µA
±
12 30 mA
30 40 mA
IH
CC
15µA
V
+ 0.3 V
CC
Min 0.45 V
Min 0.85 V
CC
Min VCC – 0.4 V
CC
CC
V
Am29F010B 21
Page 22
TEST CONDITIONS
5.0 V
Table 6. Test Specifications
Test Condition -45 All others Unit
Device
Under
Test
C
L
Note: Diodes are IN3064 or equivalent
6.2 k
Ω
Figure 7. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
2.7 k
Ω
Output Load 1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels
Output timing measurement
reference levels
Steady
Changing from H to L
Changing from L to H
L
30 100 pF
1.5 0.8 V
1.5 2.0 V
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
22 Am29F010B
Page 23
AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbol
Speed Options
Parameter Description Test Setup
t
AVAVtRC
t
AVQVtACC
t
ELQVtCE
t
GLQVtOE
t
EHQZtDF
t
GHQZtDF
t
OEH
Read Cycle Time (Note 1) Min 45 55 70 90 120 ns
Address to Output Delay
Chip Enable to Output Delay OE# = V
Output Enable to Output Delay Max 25 30 30 35 50 ns
Chip Enable to Output High Z
(Note 1)
Output Enable to Output High Z
(Note 1)
Output Enable Hold Time
(Note 1)
Output Hold Time From
t
AXQXtOH
Addresses CE# or
OE#,
Whichever Occurs First
Notes:
1. Not 100% tested.
2. See Figure 7 and Table 6 for test specifications.
UnitJEDEC Std -45 -55 -70 -90 -120
CE# = V
OE# = V
IL
IL
IL
Max 45 55 70 90 120 ns
Max 45 55 70 90 120 ns
Max 10 15 20 20 30 ns
Max 10 15 20 20 30 ns
Read Min 0 ns
Toggle and Data
Polling
Min 10 ns
Min 0 ns
Addresses
CE#
OE#
WE#
Outputs
t
RC
Addresses Stable
t
ACC
t
OE
t
OEH
t
CE
HIGH Z
Output Valid
Figure 8. Read Operations Timings
t
DF
t
OH
HIGH Z
Am29F010B 23
Page 24
AC CHARACTERISTICS
Erase and Program Operations
Parameter Symbol
t
AVAV
t
AVWL
t
WLAX
t
DVWH
t
WHDX
t
GHWL
t
ELWL
t
WHEH
t
WLWH
t
WHWL
t
WHWH1
t
WHWH2
t
WC
t
AS
t
AH
t
DS
t
DH
t
OES
t
GHWL
t
CS
t
CH
t
WP
t
WPH
t
WHWH1
t
WHWH2
t
VCS
Speed Options
Parameter Description
UnitJEDEC Std -45 -55 -70 -90 -120
Write Cycle Time (Note 1) Min 45 55 70 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 35 45 45 45 50 ns
Data Setup Time Min 20 20 30 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recover Time Before Write
(OE# High to WE# Low)
Min 0 ns
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 25 30 35 45 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs
Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
VCC Set Up Time (Note 1) Min 50 µs
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more informaiton.
24 Am29F010B
Page 25
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
t
WC
Addresses
CE#
555h
t
CH
OE#
t
WP
WE#
t
CS
t
DS
t
DH
Data
V
CC
t
VCS
A0h
Note: PA = program address, PD = program data, D
Figure 9. Program Operation Tim ings
Read Status Data (last two cycles)
t
AS
PA PA
t
AH
t
t
WPH
PD
is the true data at the program address.
OUT
PA
WHWH1
Status
D
OUT
Erase Command Sequence (last two cycles) Read Status Data
t
AS
555h for chip erase
VA
t
AH
VA
Addresses
t
WC
2AAh SA
CE#
t
t
WP
t
DS
55h
CH
t
WPH
t
DH
30h
10 for Chip Erase
t
WHWH2
In
Progress
Complete
OE#
WE#
Data
V
CC
t
VCS
t
CS
Note: SA = sector address (for Sector Erase), VA = Valid Address f or r eading s tatus data (see “Write Operation Status”).
Figure 10. Chip/Sector Erase Operation Timings
Am29F010B 25
Page 26
AC CHARACTERISTICS
Addresses
t
ACC
CE#
t
CH
OE#
t
OEH
WE#
DQ7
t
RC
VA
t
CE
t
OE
t
DF
t
OH
Complement
VA VA
Complement
True
Valid Data
High Z
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 11. Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
CE#
OE#
WE#
DQ6
t
CH
t
OEH
High Z
t
ACC
t
CE
VA
t
VA VA
OE
t
DF
t
OH
Valid Status
(first read) (second read) (stops toggling)
VA
Valid DataValid StatusValid Status
Note: V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 12. Toggle Bit Timings (During Embedded Algorithms)
26 Am29F010B
Page 27
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Parameter Symbol
Parameter Description
t
AVAV
t
AVEL
t
ELAX
t
DVEH
t
EHDX
t
GHEL
t
WLEL
t
EHWH
t
ELEH
t
EHEL
t
WHWH1
t
WHWH2
t
WC
t
AS
t
AH
t
DS
t
DH
t
OES
t
GHEL
t
WS
t
WH
t
CP
t
CPH
t
WHWH1
t
WHWH2
Write Cycle Time (Note 1) Min 45 55 70 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 35 45 45 45 50 ns
Data Setup Time Min 20 20 30 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time (Note 1) Min 0 ns
Read Recover Time Before Write Min 0 ns
WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 25 30 35 45 50 ns
CE# Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs
Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Speed Options
UnitJEDEC Standard -45 -55 -70 -90 -120
Am29F010B 27
Page 28
AC CHARACTERISTICS
PA for program
SA for sector erase
555 for chip erase
t
AS
t
AH
Data# Polling
PA
Addresses
555 for program
2AA for erase
t
WC
t
WH
WE#
t
GHEL
OE#
t
WHWH1 or 2
DQ7# D
OUT
CE#
Data
t
WS
t
CP
t
CPH
t
DS
t
DH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D
2. Figure indicates the last two bus cycles of the command sequence.
Figure 13. Alternate CE# Controlled Write Operation Timings
= Array Data.
OUT
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Chip/Sector Erase Time 1.0 15 sec
Byte Programming Time 7 300 µs
Chip Programming Time (Note 3) 0.9 6.25 sec
Excludes 00h programming prior to
erasure (Note 4)
Excludes system-level overhead
(Note 5)
Notes:
°
1. Typical program and erase times assume the following conditions: 25
C, 5.0 V VCC, 1 million cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V
= 4.5 V (4.75 V for -45), 100,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles.
CommentsTyp (Note 1) Max (Note 2) Unit
28 Am29F010B
Page 29
LATCHUP CHARACTERISTIC
Parameter Description Min Max
Input Voltage with respect to V
Current –100 mA +100 mA
V
CC
on I/O pins –1.0 V VCC + 1.0 V
SS
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
C
C
OUT
C
IN2
Input Capacitance VIN = 0 6 7.5 pF
IN
Output Capacitance V
= 0 8.5 12 pF
OUT
Control Pin Capacitance VIN = 0 7.5 9 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
= 25°C, f = 1.0 MHz.
A
PLCC AND PDIP PIN CAPACITANCE
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
C
C
OUT
C
IN2
Input Capacitance VIN = 0 4 6 pF
IN
Output Capacitance V
= 0 8 12 pF
OUT
Control Pin Capacitance VPP = 0 8 12 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
= 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time
C
°
150
125°C
10 Years
20 Years
Am29F010B 29
Page 30
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic DIP
Dwg rev AD; 10/99
30 Am29F010B
Page 31
PHYSICAL DIMENSIONS* (continued)
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
Am29F010B 31
Page 32
PHYSICAL DIMENSIONS* (continued)
TS 032—32-Pin Standard Thin Small Outline Package
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
32 Am29F010B
Page 33
PHYSICAL DIMENSIONS* (continued)
TSR 032—32-Pin Standard Thin Small Outline Package
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
Am29F010B 33
Page 34
REVISION SUMMARY
Revision A (August 12, 1999)
Initial release. The Am29F010B replaces the
Am29F010A data sheet (22181B+1).
Revision A+1 (September 22, 1999)
Device Bus Operations
Sector Protection/Unprotection:
tion number for the programming supplement.
Corrected the publica-
Revision A+2 (September 27, 1999)
Erase and Programming Performance table
In Notes 1 and 6, corrected the erase cycle endurance
to 1 million cycles.
Revision B (November 12, 1999)
AC Characteristics—Figure 9. Program Operations
Timing and Figure 10. Chip/Sector Erase
Operations
Deleted t
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
and changed OE# waveform to start at
GHWL
Revision C (November 28, 2000)
Global
Added table of contents. Removed Preliminary status
from document.
Ordering Information
Deleted burn-in option.
Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
34 Am29F010B
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