AMD Am29F010B Service Manual
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Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 V ± 10% f or read, er ase, and program o perations
— Simplifies system-level power requirements
■ Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
■ High performance
— 45 ns maximum access time
■ Low power consumption
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
■ Flexible sector arc hitecture
— Eight 16 Kb yte sectors
— Any combination of sector s can be er ased
— Supports full chip erase
■ Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/ unprotection can be
implemented using standard PROM
programming equipment
■ Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
■ Erase Suspend/Resume
— Supports reading data from a sector not
being erased
■ Minimum 1 million erase cyc les guara nteed per
sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22336 Rev: C Amendment/0
Issue Date: November 28, 2000
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010B
is offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The devi c e i s d e si g n e d t o b e p r o g r a m m e d in-system with the
standard system 5.0 Volt V
required for program or erase opera tion s. The device can
also be programmed or erased i n standard EPROM
programmers.
This device is manufactured using AMD’ s 0.32 µm process technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wai t states . To eliminate bus contention the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an interna l state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This inv okes the Embed ded Pro-
gram algorithm—an internal algorithm that
supply. A 12.0 v o lt VPP is not
CC
automatically times the program puls e wid ths a nd
veri fies proper cell margin.
Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase
algorithm—an in ternal algorithm that auto matically
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection m easures include a
low V
detector automatically inhibits write operations
CC
during power transitions . T he hard ware sector protection feature disables both progr am and erase operations
in any combination of the sectors of memory, and is implemented using standard EPROM programmers.
The system can place the devic e into the standb y mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electri cally erases all bits
within a sector s imultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
2 Am29F010B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29F010B Device Bus Operations .................................9
Requirements for Reading Array Data ........................ .............9
Writing Commands/Command Sequences ......... ................... ..9
Program and Erase Operation Status .................................... 10
Standby Mode .................... ............................. ................ .......10
Output Disable Mode ..............................................................10
Table 2. Am29F010B Sector Addresses Table ...............................10
Autoselect Mode .....................................................................10
Table 3. Am29F010B Autoselect Codes (High Voltage Method) . ...11
Sector Protection/Unprotection ............................................... 11
Hardware Data Protection ......................................................11
Low VCC Write Inhibit ......................................................................11
Write Pulse “Glitch” Protection ........................................................11
Logical Inhibit ................................. ....... ....... .... ..... ....... ......... ....... ...11
Power-Up Write Inhibit ....................................................................11
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data ................................................................12
Reset Command .................................... ............................. ....12
Autoselect Command Sequence ..................................... .......12
Byte Program Command Sequence .......................................12
Figure 1. Program Operation ..........................................................13
Chip Erase Command Sequence ...........................................13
Sector Erase Command Sequence ........................................13
Erase Suspend/Erase Resume Commands .................. .........14
Figure 2. Erase Operation ...............................................................14
Command Definitions .............................................................15
Table 4. Am29F010B Command Definitions ...................................15
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 16
DQ7: Dat a# Po ll i n g ... .. .. ........................... .............. .............. ...16
Figure 3. Data# Polling Algorithm ...................................................16
DQ6: Toggle Bit I ....................................................................16
Reading Toggle Bit DQ6 .........................................................17
Figure 4. Toggle Bit Algorithm .........................................................17
DQ5: Exceeded Timing Limits ................................................17
DQ3: Sector Erase Timer .......................................................18
Table 5. Write Operation Status .....................................................18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 19
Figure 5. Maximum Negative Overshoot Waveform ........... ..... .... ..19
Figure 6. Maximum Posi tive Overshoot Waveform ........................19
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Test Setup ....................................................................... 22
Table 6. Test Specifications ...........................................................22
Key to Switching Waveforms . . . . . . . . . . . . . . . 22
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Read Operatio n s Ti mi n g s .................. ............................. 23
Erase and Program Operations ......................................................... 24
Figure 9. Program Operation Timings ............................................ 2 5
Figure 10. Chip/Sector Erase Operation Timings .......................... 25
Figure 11. Data# Polling Timings (During Embedded Algorithms) . 26
Figure 12. Toggle Bit Timings (During Embedded Algorithms) ...... 26
Erase and Program Operations ......................................................... 27
Alternate CE# Controlled Writes .................................................... 27
Figure 13. Alternate CE# Controlled Write Operation Timings ...... 2 8
Erase and Programming Performance . . . . . . . 28
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 29
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
PLCC and PDI P P in Capacitance . . . . . . . . . . . . 29
Data Retenti on . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 30
PD 032—32-Pin Plastic DIP ...................................................30
PL 032—32-Pin Plastic Leaded Chip Carrier .........................31
TS 032—32-Pin Standard Thin Small Outline Package .........32
TSR 032—32-Pin Standard Thin Small Outline Package ..... ..33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision A (August 12, 1999) .................................................34
Revision A+1 (September 22, 1999) .................................... ..34
Revision A+2 (September 27, 1999) .................................... ..34
Revision B (November 12, 1999) ............................................34
Revision C (November 28, 2000) ........................................... 34
Am29F010B 3
PRODUCT SELECTOR GUIDE
Family Part Number Am29F010B
= 5.0 V ± 5% -45
V
Speed Option
Max Access Time (ns) 45 55 70 90 120
CE# Access (ns) 45 55 70 90 120
OE# Access (ns) 25 30 30 35 50
CC
= 5.0 V ± 10% -55 -70 -90 -120
V
CC
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
DQ0
–
DQ7
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
WE#
CE#
OE#
A0–A16
State
Control
Command
Register
VCC Detector
PGM Voltage
Generator
Timer
Chip Enable
Output Enable
STB
Logic
Address Latch
Y-Decoder
X-Decoder
STB
Data
Latch
Y-Gating
Cell Matrix
4 Am29F010B
CONNECTION DIAGRAMS
A7
A6
A5
A4
A3
A2
A1
A0
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PDIP
NC
A16
A15
A12
DQ0
DQ1
DQ2
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
14
A12
4
15
DQ1
A15
3
DQ2
A16
1
2
PLCC
17
SS
V
NC
32
18
DQ3
VCCWE#
31 30
19 2016
DQ5
DQ4
NC
29
28
27
26
25
24
23
22
21
DQ6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
Am29F010B 5
CONNECTION DIAGRAMS
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A
1
2
3
4
5
6
7
8
Standard TSOP
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Reverse TSOP
10
11
12
13
14
15
16
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A
3
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
6 Am29F010B
PIN CONFIGURATION
A0–A16 = 17 Addresses
LOGIC SYMBOL
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
V
CC
= +5.0 Volt Single Power Supply
(See Product Selector Guide f o r speed
options and voltage supply tolerances)
V
SS
= Device Ground
NC = Pin Not Connected Internally
17
A0–A16
CE#
OE#
WE#
8
DQ0–DQ7
Am29F010B 7
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F010B 70 E C
TEMPERATURE RANGE
C = Commercial (
I = Industrial (–40°C to +85°C)
E = Extended (–55
PACKAGE TYPE
P = 32-Pin Plastic PDIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
0°C to +70°C)
°C to +125°C)
Valid Combinations VCC Voltage
Am29F010B-45
Am29F010B-55
Am29F010B-70
Am29F010B-90
Am29F010B-120
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
5.0 V ± 5%
5.0 V ± 10%
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
8 Am29F010B
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory
location. The register is composed of latches th at store
the commands, along with the address and data infor-
of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.
mation needed to execute the command. The contents
Table 1. Am29F010B Device Bus Operations
Addresses
Operation CE# OE# WE#
Read L L H A
Write L H L A
Standby VCC ± 0.5 V X X X High-Z
Output Disable L H H X High-Z
Hardware Reset X X X X High-Z
Legend:
L = Logic Low = V
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D
IL
(Note 1) DQ0–DQ7
IN
IN
D
D
= Data Out
OUT
OUT
IN
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates arra y data to the output pins . WE# should
remain at V
.
IH
The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address input s produc e valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specification for
reading array data.
. CE# is the power
IL
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
An erase operation can erase one sect or, multiple sectors, or the entire device. The Sector Addre ss Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the
entire chip.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
, and OE# to VIH.
IL
in the DC Characteristics table represents the ac-
Am29F010B 9
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet f or t iming
diagrams.
CC
The device enters the CMOS standby mode when the
CE# pin is held at V
0.5 V. (Note that this is a more
±
CC
restricted voltage ran ge than V
the TTL standby mode when CE# is held at V
device requires the standard ac cess time (t
is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
Standby Mode
When the system is not reading or writing to the device ,
in the DC Characteristics tables represents the
I
CC3
standby current specification.
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
Table 2. Am29F010B Sector Addresses Table
Sector A16 A15 A14 Address Range
SA0 0 0 0 00000h-03FFFh
SA1 0 0 1 04000h-07FFFh
.) The device enters
IH
IH
) before it
CE
. The
SA2 0 1 0 08000h-0BFFFh
SA3 0 1 1 0C000h-0FFFFh
SA4 1 0 0 10000h-13FFFh
SA5 1 0 1 14000h-17FFFh
SA6 1 1 0 18000h-1BFFFh
SA7 1 1 1 1C000h-1FFFFh
Note: All sectors are 16 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
on address pin A9. Address p ins A6,
ID
A1, and A0 must be as shown in Autoselect Codes
(High V oltage Method) table. I n addition, when verifying
sector protection, the sector address must appear on
the appropriate highest order address bits . Ref er to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that
are don’t care. When all necessary bits have been set
as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V
“Command Definitions” for details on using the autoselect mode.
. See
ID
10 Am29F010B
Table 3. Am29F010B Autoselect Codes (High Voltage Method)
Description CE# OE# WE#
A16
to
A14
A13
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
Device ID: Am29F010B L L H X X V
Sector Protection Verification L L H SA X V
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sect or. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
) on address pin A9 and the
ID
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representative to obtain a cop y of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
ID
ID
ID
gramming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
Write Inhibit
CC
is less than V
CC
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent unintentional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
, CE# = VIH or WE# = VIH. To initiate a write cycle,
V
IL
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
protection measures pre vent accidental eras ure or pro-
XLXLL 01h
XLXLH 20h
01h
XLXHL
, the device does not ac-
LKO
. The system must provide the
LKO
is greater than V
CC
and OE# = VIH during power up , the
IL
(protected)
00h
(unprotected)
power-up and
CC
.
LKO
CC
CC
Am29F010B 11
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