Please note that in this databook, references to "DVI" and "HDMI" refer to the capa bility of the TMDS interface, multiplexed on the PCI-E external graphics interface, to enable
DVI or HDMI through passive enabling circuitries. Any statement in this databook on any DVI or HDMI-related functionality must be understood in that context.
Advanced Micro Devices, Inc., will not provide any indemnity, pay any royalty, nor provide any license/sublicense to any:
(a) Intellectual property rights relating to any of the following: (i) Macrovision for its Analog Protection System ("APS") technologies; (ii) Advanced Television Systems
Committee (ATSC) standard and related technologies; or (iii) the High Definition Multimedia Interface (HDMI) standard and related technologies; or
(b) Audio and/or video codecs or any industry standard technology (e.g., technology or specifications promulgated by any standards development organization, consortium,
trade association, special interest group or like entity).
This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,5 49; and 7,050,698 and other intellectual property rights. The use of Macrovision's copy protection
technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by
Macrovision. Reverse engineering or disassembly is prohibited.
This device may only be sold or distributed to: (i) a Macrovision Authorized Buyer, (ii) a customer (PMA Customer) who has executed a Proprietary Materials Agreement
(PMA) with Macrovision that is still in effect, (iii) a contract manufacturer approved by Macrovision to purchase this device on behalf of a Macrovision Authorized Buyer or
a PMA Customer, or (iv) a distributor who has executed a Macrovision-specified distribution agreement with ATI.
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, and combinations thereof, ATI, ATI logo, ATI Radeon, ATI Avivo, PowerPlay, PowerShift, PowerXpress, ATI HyperMemory,
3Dc, Cool'n'Quiet, AMD OverDrive, and AMD PowerNow! are trademarks of Advanced Micro Devices, Inc.
DisplayPort is a trademark of VESA.
HDMI, the HDMI Logo and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
2
C is a trademark of Philips.
I
Linux is a registered trademark of Linus Torvalds.
Macrovision is a registered trademark of Macrovision Corporation in the United States and/or other countries.
Microsoft, Windows, Windows Vista, DirectDraw, and DirectX are registered trademarks of Microsoft Corporation.
OpenGL is a registered trademark of SGI.
PCI Express is a registered trademark of PCI-SIG.
WinBench is a registered trademark of Ziff Davis, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect
to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except as set forth in AMD's Standard
Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the
implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications
intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or
environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
1.2.5A-Link Express II Interface..................................................................................................................................1-4
1.2.62D Acceleration Features .....................................................................................................................................1-4
1.2.73D Acceleration Features .....................................................................................................................................1-4
1.2.8Motion Video Acceleration Features....................................................................................................................1-5
1.2.9Multiple Display Features ....................................................................................................................................1-5
1.2.13Integrated HD Audio Controller and Codec.........................................................................................................1-8
1.2.15Power Management Features ...............................................................................................................................1-8
1.2.17Test Capability Features .......................................................................................................................................1-9
1.2.18Additional Features ..............................................................................................................................................1-9
1.5 Graphics Device ID and Graphics Engine Clock Speed...................................................................................................1-10
1.6 Conventions and Notations ...............................................................................................................................................1-10
1.6.6Acronyms and Abbreviations .............................................................................................................................1-11
2.4.1LVDS Data Mapping............................................................................................................................................2-7
2.7 DVI-I Support .................................................................................................................................................................. 2-18
3.5.11 x 16 or 2 x 8 Lane Interface for External Graphics .......................................................................................... 3-6
3.5.2A-Link Express II Interface for Southbridge....................................................................................................... 3-6
3.5.36 x 1 Lane Interface for General Purpose External Devices .............................................................................. 3-6
3.11 Power Management Pins................................................................................................................................................3-11
3.13 Power Pins...................................................................................................................................................................... 3-12
5.1.1Maximum and Minimum Ratings........................................................................................................................ 5-1
5.3 Package Information ...........................................................................................................................................................5-9
5.3.3Board Solder Reflow Process Recommendations ..............................................................................................5-11
5.3.3.1Stencil Opening Size for Solder Paste Pads on PCB 11
5.3.3.2Reflow Profile 11
Chapter 6: Power Management and ACPI
6.1 ACPI Power Management Implementation ........................................................................................................................6-1
6.2 Power Management for the Graphics Controller ................................................................................................................6-2
6.2.1PCI Function Power States...................................................................................................................................6-2
6.2.2PCI Power Management Interface........................................................................................................................6-2
6.2.3Capabilities List Data Structure in PCI Configuration Space ..............................................................................6-2
6.2.7PMC - Power Management Capabilities (Offset = 2) ..........................................................................................6-6
Chapter 7: Testability
7.1 Test Capability Features......................................................................................................................................................7-1
7.2 Test Interface.......................................................................................................................................................................7-1
7.3 XOR Test ............................................................................................................................................................................7-1
7.3.1Description of a Generic XOR Tree.....................................................................................................................7-1
7.3.2Description of the RS780E XOR Tree .................................................................................................................7-2
7.3.3XOR Tree Activation ...........................................................................................................................................7-2
7.3.4XOR Tree for the RS780E ...................................................................................................................................7-2
7.4.1Description of a Generic VOH/VOL Tree ...........................................................................................................7-4
7.4.2VOH/VOL Tree Activation..................................................................................................................................7-5
A.1 RS780E Pin List Sorted by Ball Reference........................................................................................................................1-2
A.2 RS780E Pin List Sorted by Pin Name................................................................................................................................1-7
Figure 1-1: Possible Configurations for the x16 PCI-E Graphics Interface .................................................................................. 1-3
Figure 2-5: LVTM Interface of the RS780E ................................................................................................................................. 2-6
Figure 2-8: Data Transmission Ordering for the TMDS Interfaces ............................................................................................. 2-13
Figure 2-9: Pins for Analog Output on the DVI-I Connector ...................................................................................................... 2-18
Figure 3-1: RS780E Pin Assignment Top View (Left) .................................................................................................................. 3-2
Figure 3-2: RS780E Pin Assignment Top View (Right) ................................................................................................................ 3-3
Figure 4-1: RS780E Power Rail Power-up Sequence .................................................................................................................... 4-4
Figure 4-2.: LCD Panel Power Up/Down Timing ......................................................................................................................... 4-5
Figure 5-1: DC Characteristics of the TMDS Interfaces ................................................................................................................ 5-5
Figure 5-2: DC Characteristics of the LVDS Interface .................................................................................................................. 5-6
Figure 6-1: Linked List for Capabilities ......................................................................................................................................... 6-5
Figure 7-1: Example of a Generic XOR Tree ................................................................................................................................7-2
Figure 7-2: Sample of a Generic VOH/VOL Tree ......................................................................................................................... 7-5
Table 1-1: Possible Configurations for the PCI-E General Purpose Links .....................................................................................1-3
Table 1-2: Graphics Device ID and Graphics Engine Clock Speed .............................................................................................1-10
Table 1-3: Pin Type Codes ............................................................................................................................................................1-10
Table 1-4: Acronyms and Abbreviations ......................................................................................................................................1-11
Table 2-4: DDR3 Memory Row and Column Addressing ..............................................................................................................2-5
Table 2-5: LVDS 18-bit TFT Single Pixel per Clock (Single Channel) Signal Mapping ..............................................................2-8
Table 2-6: LVDS 18-bit TFT Dual Pixel per Clock (Dual Channel) Signal Mapping ...................................................................2-9
Table 2-7: LVDS 24-bit TFT Single Pixel per Clock (Single Channel) Signal Mapping ............................................................2-11
Table 2-8: LVDS 24-bit TFT Dual Pixel per Clock (Dual Channel) Signal Mapping .................................................................2-12
Table 2-9: Single Link Signal Mapping for DVI/HDMI™ .........................................................................................................2-14
Table 2-10: Dual-Link Signal Mapping for DVI ..........................................................................................................................2-15
Table 2-11: Support for HDMI™ Packet Type .............................................................................................................................2-16
Table 3-3: 1 x 16 or 2 x 8 Lane PCI Express® Interface for External Graphics ............................................................................3-6
Table 3-4: 1 x 4 Lane A-Link Express II Interface for Southbridge ...............................................................................................3-6
Table 3-5: 6 x 1 Lane PCI Express® Interface for General Purpose External Devices ..................................................................3-6
Table 3-15: Power Pins .................................................................................................................................................................3-12
Table 3-17: Strap Definitions for the RS780E ..............................................................................................................................3-15
Table 4-1: Timing Requirements for HyperTransport Reference Clock (100MHz) Output by the Clock Generator ....................4-1
Table 4-3: Timing Requirements for REF_CLKP Used as OSCIN (14.3181818MHz) .................................................................4-2
Table 4-4: Timing Requirements for the LVTM Interface in LVDS Mode ...................................................................................4-3
Table 4-5: RS780E Power Rail Power-up Sequence ......................................................................................................................4-4
Table 4-6: LCD Power Up/Down Timing .......................................................................................................................................4-5
Table 5-1: Maximum and Minimum Ratings ..................................................................................................................................5-1
Table 5-2: DC Characteristics for 3.3V TTL Signals .....................................................................................................................5-2
Table 5-3: DC Characteristics for DDC Signals (DDC Mode) .......................................................................................................5-2
Table 5-4: DC Characteristics for AUX Signals (AUX Mode) ......................................................................................................5-2
Table 5-5: DC Characteristics for POWERGOOD .........................................................................................................................5-3
Table 5-6: DC Characteristics for HyperTransport™ and PCI-E Differential Clock (HT_REFCLK, GFX_REFCLK,
Table 5-7: DC Characteristics for REFCLK_P Input for OSCIN (14.3181818MHz) ....................................................................5-3
Table 5-8: DC Characteristics for the Memory Interface when Supporting DDR2 ........................................................................5-3
Table 5-9: DC Characteristics for the Memory Interface when Supporting DDR3 ........................................................................5-4
Table 5-10: DC Characteristics for the LVTM Interface in TMDS Mode .....................................................................................5-4
Table 5-11: DC Characteristics for the TMDS Interface Multiplexed on the PCI-E Gfx Lanes ....................................................5-5
Table 5-12: Electrical Requirements for the LVTM Interface in LVDS Mode ..............................................................................5-6
Table 5-13: Electrical Specifications for the DisplayPort™ Interface ...........................................................................................5-7
Table 6-1: ACPI States Supported by the RS780E .........................................................................................................................6-1
Table 6-2: ACPI Signal Definitions ................................................................................................................................................6-1
Table 6-3: Standard PCI Configuration Space Header Type 0 .......................................................................................................6-2
Table 6-4: PCI Status Register ........................................................................................................................................................6-3
Table 6-9: Next Item Pointer (NEXT_ITEM_PTR) .......................................................................................................................6-5
Table 6-10: Power Management Capabilities – PMC .....................................................................................................................6-6
Table 7-1: Pins on the Test Interface ..............................................................................................................................................7-1
Table 7-2: Example of an XOR Tree ..............................................................................................................................................7-2
Table 7-3: RS780E XOR Tree ........................................................................................................................................................7-3
Table 7-4: Truth Table for the VOH/VOL Tree Outputs ................................................................................................................7-5
Table 7-5: RS780E VOH/VOL Tree ...............................................................................................................................................7-7
The AMD 780E (referred to in this document by its codenmae “RS780E”) is an eighth generation Integrated Graphics
Processor (IGP) that integrates a DirectX
single chip. It supports AMD Athlon™ single-core and AMD Athlon X2 dual-core processors, AMD Sempron™
processors, and AMD Turion™ 64 X2 dual-core mobile technology. The RS780E integrates an ATI M72-based graphics
engine, dual display, an LVDS interface, internal or external TMDS, DisplayPort™ capability, and Northbridge
functionality in a single BGA package. This high level of integration and scalability enables manufacturers to offer
enthusiast level capabilities and performance while minimizing board space and system cost.
Robust and Flexible Core Logic Features
The RS780E combines graphics and system logic functions in a single chip using a 21mm body BGA package, reducing
overall solution area. For optimal system and graphics performance, the RS780E supports a high speed HyperTransport™
interface to the AMD processor, running at a data rate of up to 4.4GT/s and supporting both HT 1.0 and HT 3.0 protocols.
The RS780E is ideally suited for 64-bit operating systems, and supports platform configurations with greater than 4GB of
system memory. The rich PCI Express
Express external graphics controllers and up to six other PCI Express peripherals (up to seven when using only 8 lanes for
external graphics, or up to eight when not using external graphics), all supporting the PCI Express 2.0 standard with data
rates of up to 5.0GT/s. These capabilities are complemented by the advanced I/O features of AMD’s SB710 Southbridge.
Best for Windows Vista
The RS780E delivers an unmatched Windows Vista® experience. It harnesses the increased bandwidth of HyperTransport
3.0 to a DirectX 10 graphics core, which provides the 3D rendering power needed to generate the Windows Vista desktop
even under the most demanding circumstances. The ATI M72-based graphics core employs a unified shader architecture
to deliver optimal 3D performance across the whole spectrum of 3D applications. This future-proof core ensures
compatibility with both current and upcoming 3D applications, and meets Windows Vista Premium Logo requirements
through 2008 and beyond.
®
®
10 compliant Shader Model 4.0 graphics core and a system controller in a
®
expansion capabilities of RS780E include support for one x16 or two x8 PCI
Leading Multimedia Capabilities
The RS780E incorporates AMD’s Unified Video Decoder (UVD) technology, which provides dedicated hardware decode
of the H.264, VC-1, and MPEG-2 video formats used in HD DVD and for Blu-ray disks. The RS780E also incorporates
the innovative ATI Avivo™* display architecture, providing users with visual quality which is second to none. Advanced
scaling and color correction capabilities, along with increased precision through the entire display pipeline, ensure an
optimal image on CRT monitors, LCD panels, and any other display device. Dual DisplayPort output capability provides
the ability to interface to the next generation of digital display devices. That is complemented by two integrated TMDS
interfaces, configurable to enable DVI/HDMI™ and support HDCP, allowing compatibility with even the most modern
high definition televisions without the additional cost of external components.
*Note: ATI Avivo™ is a technology platform that includes a broad set of capabilities offered by certain ATI Radeon™
products. Full enablement of some ATI Avivo™ capabilities may require complementary products.
Low Power Consumption and Industry Leading Power Management
The RS780E is manufactured using the power efficient nm technology, and it supports a whole range of industry
standards and new proprietary power management features. In addition to comprehensive support for the ACPI
specification, the exclusive ATI PowerPlay™ technology (enhanced with new adaptive frame buffer compression and ATI
PowerShift™ features) minimizes the RS780E's power consumption by adjusting graphics core performance and core
voltage to the task and usage environment. System power can be further reduced through the dedicated local frame buffer
interface supported by the RS780E. The integrated UVD dramatically reduces CPU loading and hence overall power
consumption during HD video playback.
The graphics driver for the RS780E is fully compatible with all other Radeon class graphics controllers from AMD. A
single driver can support multiple graphics configurations across AMD’s product lines, including the Radeon family and
the AMD chipset family. In addition, this driver compatibility allows the RS780E to benefit immediately from AMD's
software optimization and from the advanced Windows
Radeon family drivers.
1.2RS780E Features
1.2.1 CPU HyperTransport™ Interface
•
Supports 16-bit up/down HyperTransport (HT) 3.0 interface up to 4.4GT/s.
•Supports 200, 400, 600, 800, and 1000MHz HT1 frequencies.
•Supports 1.8, 2.0, and 2.2 GHz HT3 frequencies.
•Supports AMD Athlon single-core and AMD Athlon X2 dual-core processors, AMD Sempron processors, and AMD
Turion 64 X2 dual-core mobile technology.
•Supports power saving features as specified in section 8.6.1 of the HyperTransport I/O Link Specification Rev 3.00a,
including:
•Dynamic link configuration
•Dynamic link disconnection
RS780E Features
®
XP, Windows Vista®, and Linux® support available in the
•Dynamic link width
•Dynamic link frequency
•Disconnected link refresh (HT3 only)
•Inactive link refresh (HT3 only)
•Supports LDTSTOP interface and CPU link frequency throttling and stutter mode.
1.2.2 Memory Interface
•
Supports an optional dedicated local frame buffer (side-port) of up to 128MB through a 16-bit interface. Note,
however, that the memory interface is optimized for a 64MB local frame buffer.
•New highly flexible memory architecture allows asymmetric side-port and shared system memory frame buffer sizes.
Supported configurations include UMA only and UMA+side-port (interleave mode).
•New dynamic memory allocation scheme improves performance and reduces power simultaneously.
•Support for DDR2 memories up to DDR2-800, with a maximum memory clock speed of 400MHz. Memory clock is
independent of any other clock source and can therefore be set to any frequency equal to or less than 400MHz
(DDR2-800), allowing the use of lower speed side-port memories.
•Support for DDR3 memories up to DDR3-800, with a maximum memory clock speed of 400MHz (up to
DDR3-1200, with a maximum memory clock speed of 600MHz, when the core voltage is fixed at 1.1V). Memory
clock is independent of any other clock source and can therefore be set to any frequency equal to or less than the
maximum limit, allowing the use of lower speed side-port memories.
•Support one memory device of x16 width (see section 2.2.1.1, “Supported DDR2 Components,” on page 2-4.and
section 2.2.2.1, “Supported DDR3 Components,” on page 2-5, for details).
•Asynchronous HyperTransport and memory controller interface speeds.
•Supports DDR SDRAM self refresh mechanism.
•Supports dynamic CKE and ODT for power conservation.
* Note: Includes dedicated and shared memory. The amount of HyperMemory available is determined by various factors.
For details, please consult your AMD CSS representative.
1.2.4 PCI Express® Interface
Supports PCI-E Gen2 (version 2.0).
•
•Optimized peer-to-peer and general purpose link performance.
•Highly flexible PCI Express implementation to suit a variety of platform needs.
•A dual-port, x16 graphics interface, configurable to any one of the modes illustrated in Figure 1-1:
•Supports programmable lane reversal for the graphics link to ease motherboard layout when the end device does not
•Supports two independent displays over the PCI-E interface for external graphics (see Figure 1-1,“Possible
Configurations for the x16 PCI-E Graphics Interface,” on page 1-3 for details).
•Supports 4, 2, or 1-lane transmission.
•Supports both the 2.7Gbps and 1.62Gbps link symbol rates.
•Supports the Auxiliary Channel (AUX CH).
•Supports a maximum resolution of 2560x1600 @60Hz with 4 lanes.
1.2.13 Integrated HD Audio Controller and Codec
•
Integrated HD Audio codec supports linear PCM and AC3 (5.1) audio formats for HDMI output.
•Separate logical chip function.
•Can encrypt data onto one associated HDMI output.
•Uses Microsoft UAA driver.
•Internally connected to the integrated HDMI, or HDMI-enabled interface, hence no external cable required.
•Support for basic audio (32, 44.1 or 48 KHz stereo) and AC3 or DTS at the same sample rates.
RS780E Features
1.2.14 Clock Generation
Support for an external clock chip to generate side-port memory, PCI-E, and A-Link Express II clocks.
•
1.2.15 Power Management Features
•
Single chip solution in 55nm, 1.1V CMOS technology.
•Supports ACPI 2.0 for S0, S3, S4, and S5 states.
•Full IAPC (Instantly Available PC) power management support.
•Static and dynamic power management support (APM as well as ACPI) with full VESA DPM and Energy Star
compliance.
•The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture—
On, Standby, Suspend, and Off. Each power state can be achieved by software control bits.
•Hardware controlled intelligent clock gating enables clocks only to active functional blocks, and is completely
transparent to software.
•Dynamic self-refresh for the side-port memory.
•Support for Cool'n'Quiet™ via FID/VID change.
•Support for AMD PowerNow!™.
•Clocks to every major functional block are controlled by a unique dynamic clock switching technique that is
completely transparent to the software. By turning off the clock to the block that is idle or not used at that point, the
power consumption is significantly reduced during normal operation.
•Supports PowerExpress™ and PowerPlay™ (enhanced with the PowerShift™ feature).
•Supports dynamic lane reduction for the PCI-E graphics interface when coupled with an AMD-based graphics
device, adjusting lane width according to required bandwidth.
1.2.16 PC Design Guide Compliance
The RS780E complies with all relevant Windows Logo Program (WLP) requirements from Microsoft for WHQL
certification.
*Note: AMD’s product warranty does not cover damages caused by overclocking, even when overclocking is enabled via
the AMD OverDrive utility.
1.4Branding Diagram
Branding Diagram
Figure 1-3 RS780E ASIC A13 Production Branding
1.5Graphics Device ID and Graphics Engine Clock Speed
Table 1-2 Graphics Device ID and Graphics Engine Clock Speed
Variant
RS780E0x9615200500
Graphics
Device ID
Graphics Engine Clock Speed (MHz)
Min.Max.
1.6Conventions and Notations
The following conventions are used throughout this manual.
1.6.1Pin Names
Pins are identified by their pin names or ball references. Multiplexed pins sometimes assume alternate “functional names”
when they perform their alternate functions, and these “functional names” are given in Chapter 3, “Pin Descriptions and
Strap Options.”
All active-low signals are identified by the suffix ‘#’ in their names (e.g., MEM_RAS#).
1.6.2Pin Types
The pins are assigned different codes according to their operational characteristics. These codes are listed in Table 1-3.
OtherPin types not included in any of the categories above
1.6.3Numeric Representation
Hexadecimal numbers are appended with “h” (Intel assembly-style notation) whenever there is a risk of ambiguity. Other
numbers are in decimal.
Pins of identical functions but different running integers (e.g., “GFX_TX7P, GFX_TX6P,... GFX_TX0P”) are referred to
collectively by specifying their integers in square brackets and with colons (i.e., “GFX_TX[7:0]P”). A similar short-hand
notation is used to indicate bit occupation in a register. For example, NB_COMMAND[15:10] refers to the bit positions
10 through 15 of the NB_COMMAND register.
1.6.4 Register Field
A field of a register is referred to by the format of [Register Name].[Register.Field]. For example,
“NB_MC_CNTL.DISABLE_BYPASS” is the “DISABLE_BYPASS” field of the register “NB_MC_CNTL.”
1.6.5 Hyperlinks
Phrases or sentences in blue italicfont are hyperlinks to other parts of the manual. Users of the PDF version of this manual
can click on the links to go directly to the referenced sections, tables, or figures.
1.6.6Acronyms and Abbreviations
The following is a list of the acronyms and abbreviations used in this manual.
Table 1-4 Acronyms and Abbreviations
AcronymFull Expression
ACPIAdvanced Configuration and Power Interface
A-Link-E IIA-Link Express II interface between the IGP and the Southbridge.
BGABall Grid Array
BIOS
BISTBuilt In Self Test.
BLTBlit
bppbits per pixel
CECConsumer Electronic Control
CPISCommon Panel Interface Specification
CRTCathode Ray Tube
CSPChip Scale Package
DACDigital to Analog Converter
DBIDynamic Bus Inversion
DDC
DDRDouble Data Rate
Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a
system or expansion card.
Display Data Channel. A VESA standard for communicating between a computer system and
attached display devices.
HyperTransport I/O Link Specification from the HyperTransport Consortium. Figure 2-2, “Host Interface Block
Diagram,” illustrates the basic blocks of the host bus interface of the RS780E.
Figure 2-2 Host Interface Block Diagram
The HyperTransport (HT) Interface, formerly known as the LDT (Lightning Data Transport) interface, is a high speed,
packet-based link implemented on two unidirectional buses. It is a point-to-point interface where data can flow both
upstream and downstream at the same time. The commands, addresses, and data travel in packets on the HyperTransport
link. Lengths of packets are in multiples of four bytes. The HT link consists of three parts: the physical layer (PHY), the
data link layer, and the protocol/transaction layer. The PHY is the physical interface between the RS780E and the CPU.
The data link layer includes the initialization and configuration sequences, periodic redundancy checks,
connect/disconnect sequences, and information packet flow controls. The protocol layer is responsible for maintaining
strict ordering rules defined by the HT protocol.
The RS780E HyperTransport bus interface consists of eighteen unidirectional differential data/control pairs and two
differential clock pairs in each of the upstream and downstream direction. On power up, the HT link is 8-bit wide and runs
at a default speed of 400MT/s. After negotiation, carried out by the HW and SW together, the link width can be brought
up to 16-bit and the interface can run up to 4.4GT/s. The interface is illustrated in Figure 2-3, “RS780E Host Bus
Interface Signals.” The signal name and direction for each signal is shown with respect to the processor. Note that the
signal names may be different from those used in the pin listing of the RS780E. Detailed descriptions of the signals are
given in section 3.3, “CPU HyperTransport™ Interface‚’ on page 3-5.
In order to significantly decrease system power and increase graphics performance, the RS780E provides an optional
side-port memory interface for dedicated frame buffer memory, to be used exclusively for the integrated graphics core.
The side-port memory interface can significantly reduce system power by allowing the CPU to stay in its lowest power
state during periods of inactivity. Screen refreshes are fetched from the side-port memory, and there is no need to "wake
up" the CPU to fetch screen refresh data.
The RS780E memory controller is unique and highly optimized. It operates in 16-bit mode at very high speed (up to
DDR2-800 and DDR3-800, and up to DDR3-1200 when the core voltage is fixed at 1.1V), and has a programmable
interleaved mode that significantly increases the memory bandwidth and reduces data latency to the integrated graphics
core. The additional bandwidth provided to the internal graphics core will also aid the RS780E in reaching and exceeding
Microsoft's Windows Vista
2.2.1 DDR2 Memory Interface
Figure 2-4, “RS780E Side-Port Memory Interface,” on page 2-4 illustrates the side-port memory interface of the
RS780E.
The RS780E memory controller supports up to 128MB of dedicated side-port frame buffer DDR2 memory. It controls a
single rank of DDR2 devices in 16-bit memory configuration. It supports device sizes of 256, 512, and 1024 Mbits, and a
device width of x16. Because the memory controller supplies only one chip select signal, only devices with one chip
select are supported. A wide range of DDR2 timing parameters, configurations, and loadings are programmable via the
RS780E memory controller configuration registers
The memory controller supports DDR2 SDRAM chips in several configurations. These chips are organized in banks,
rows (or pages), and columns. The supported DDR2 components have four or eight banks. Table 2-1 lists the supported
memory components.
Table 2-1 Supported DDR2 Components
DDR2 SDRAM
ConfigMbitsCS Mode Bank Bits Row BitsCol Bits
16Mbx162564213932
32Mbx16512102131064
64Mbx1610241131310128
Mbytes
2.2.1.2 Row and Column Addressing
Table 2-2 shows how the physical address P (after taking out the bank bit) is used to provide the row and column
The RS780E memory controller supports up to 128MB of dedicated side-port frame buffer DDR3 memory. It supports a
single rank of DDR3 device in 16-bit memory configuration. It supports device sizes of 512 and 1024 Mbits, and a device
width of x16. A wide range of DDR3 timing parameters, configurations, and loadings are programmable via the RS780E
memory controller configuration registers.
2.2.2.1 Supported DDR3 Components
The memory controller supports DDR3 SDRAM chips in several configurations. These chips are organized in banks,
rows (or pages), and columns. Table 2-3 lists the supported memory components.
Address
64Mbx16 devices
128Mbx16 devices
Table 2-3 Supported DDR3 Components
DDR3 SDRAM
ConfigMbitsCS Mode Bank Bits Row BitsCol Bits
32Mbx1651293121064
64Mbx1610241131310128
Mbytes
2.2.2.2 Row and Column Addressing
Table 2-4 shows how the physical address P (after taking out the bank bit) is used to provide the row and column
LVDS lower data channel 1
LVDS lower data channel 2
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
LVDS upper data channel 3
TXOUT_U3N/P
LVDS upper data channel 1
TXOUT_U0N/P
TXOUT_U1N/P
TXOUT_U2N/P
TXCLK_LN/P
TXOUT_L0N/P
TXCLK_UN/P
TXOUT_L1N/P
TXOUT_L2N/P
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
TMDS data channel 0
TMDS data channel 2
NC
TMDS data channel 4
TMDS clock channel
TMDS data channel 5
NC
GPIO3
GPIO2
GPIO4
TMDS data channel 3
TXOUT_U3N/P
TMDS data channel 1
TXOUT_L3N/P
LVDS lower data channel 3
TXOUT_L3N/P
NC
LVTM Interface in LVDS Mode
LVTM Interface in TMDS Mode
The RS780E’s LVTM (LVDS/TMDS) interface supports either an LVDS or a TMDS output. A custom video BIOS from
AMD will configure the LVTM interface to drive out either LVDS or a TMDS signals as desired.
A custom video BIOS and proper signal routing from the LVTM interface to a connector are the only requirements for the
RS780E to support either an LVDS or a TMDS output on the LVTM interface. No other register programming is needed
for selecting one option over the other, and customers should not attempt to configure the LVTM port by programming
the RS780E’s registers directly. Figure 2-5, “LVTM Interface of the RS780E,” compares the functions of the pins in
LVDS and TMDS mode. Operations in the LVDS and TMDS mode are explained in section 2.4, “LVDS‚’ on page 2-7,
and section 2.5, “DVI/HDMI™‚’ on page 2-13, respectively.
LVTM (LVDS/TMDS) Interface
Notice that the RS780E can also provide a TMDS output via its TMDS interface that is multiplexed with its PCI Express
graphics link. As a result, the RS780E can provide two digital display outputs using its two on-chip integrated TMDS
transmitters—one through the LVTM interface, and the other through the TMDS interface multiplexed with the PCI-E
graphics interface.
The RS780E’s LVTM interface can operate as a dual-channel 18-/24-bit LVDS interface. Notice that for designs
implementing only a single LVDS channel, the LOWER channel of the interface should be used.
2.4.1 LVDS Data Mapping
Figure 2-6 shows the transmission ordering of the LVDS signals for 18-bit transmission on the lower and the upper data
channels. The signal mappings for single and dual channel transmission are shown in Table 2-5 and Table 2-6
respectively.
Figure 2-7 shows the transmission ordering of the LVDS signals for 24-bit transmission on the lower and the upper data
channels. The signal mappings for single and dual channel transmission are shown in Table 2-9 and Table 2-10
respectively.
Figure 2-6 Single/Dual Channel 18-bit LVDS Data Transmission Ordering
Table 2-8 LVDS 24-bit TFT Dual Pixel per Clock (Dual Channel) Signal Mapping
TX Signal24-bit TX Signal24-bit
LP1C1Ro0UP1C1Re0
LP1C2Ro1UP1C2Re1
LP1C3Ro2UP1C3Re2
LP1C4Ro3UP1C4Re3
LP1C5Ro4UP1C5Re4
LP1C6Ro5UP1C6Re5
LP1C7Go0UP1C7Ge0
LP2C1Go1UP2C1Ge1
LP2C2Go2UP2C2Ge2
LP2C3Go3UP2C3Ge3
LP2C4Go4UP2C4Ge4
LP2C5Go5UP2C5Ge5
LP2C6Bo0UP2C6Be0
LP2C7Bo1UP2C7Be1
LP3C1Bo2UP3C1Be2
LP3C2Bo3UP3C2Be3
LP3C3Bo4UP3C3Be4
LP3C4Bo5UP3C4Be5
LP3C5HSYNCUP3C5(from the register)
LP3C6VSYNCUP3C6(from the register)
LP3C7ENABLEUP3C7(from the register)
LP4C1Ro6UP4C1Re6
LP4C2Ro7UP4C2Re7
LP4C3Go6UP4C3Ge6
LP4C4Go7UP4C4Ge7
LP4C5Bo6UP4C5Be6
LP4C6Bo7UP4C6Be7
LP4C7ReservedUP4C7Reserved
LVDS
Note: Signal names with letter 'o' mean 'odd' pixel or the first pixel on the panel, and signal names with letter 'e' mean
'even' pixel or the second pixel on the panel.
2.4.2 LVDS Spread Spectrum
The RS780E has an internal LVDS spread spectrum controller capable of generating a frequency modulated profile for
the LVDS signals. The amount of spread (center spread of up to +/-2.5% and down spread of up to 5%) and the
modulation frequency (in the range of 20-50kHz) are programmable through the LVDS registers.
Depending upon encoded Green channelpixeldataDepending upon state of PLL_SYNC and CTL1
Depending upon state of CTL2 and CTL3
TR1TR0TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9
Depending upon encoded Red channel pixel data
TB0 TB1 TB2 TB3 TB4 TB5 TB6 TB7 TB8 TB9
Depending upon encoded Blue channel pixel data
Various control and audio (for HDMI only) signals
Various control and audio (for HDMI only) signals
Various control and audio (for HDMI™ only) signals
Encoded Red Channel Pixel Data
Encoded Green Channel Pixel Data
Encoded Blue Channel Pixel Data
2.5DVI/HDMI™
2.5.1 DVI/HDMI™ Data Transmission Order and Signal Mapping
The RS780E contains two dual-link TMDS interfaces, multiplexed on the PCI Express® graphics lanes (see section 3.9,
“TMDS Interface Multiplexed on the PCI Express® Graphics Lanes‚’ on page 3-10
section 3.8, “LVTM Interface in TMDS Mode‚’ on page 3-9), which support clock frequencies of up to 162 MHz on each
link.
Figure 2-8 shows the transmission ordering of the signals on the interfaces.
) and on the LVTM interface (see
Figure 2-8 Data Transmission Ordering for the TMDS Interfaces
For dual-link mode, which is for DVI only, the same transmission order applies to data channels on the second link, with
the first link transmitting data for even pixels and the second link for odd pixels. See
The signal mapping for the transmission is shown in
Table 2-9 (single link) and Table 2-10 (dual-link DVI) below.
0x810x01AVIYesInserted on line selected by software.
0x820x02
0x830x03AudioYes
0x840x04MPEG SourceNo—
* Note: These packet types are supported using generic packet types. A maximum of two of them can be supported simultaneously.
Packet Type
Audio Clock
Regeneration
ID
Source Product
Descriptor
Supported
or Not
YesInserted by hardware as required.—
Yes *——
SourceComment
Sent when required to meet
maximum time between data island
specification.
Audio samples come from HD audio DMA.
Channel status from HD audio and video
registers.
Inserted in horizontal blank whenever audio
FIFO contains data.
Sending and contents controlled by video
driver.
For colorimetry, repetition count,
video format, picture formatting.
Inserted on line selected by software.
Contents from registers written by video
and HD audio drivers.
For channel counts, sampling
frequency, etc.
According to the CEA-861
specification, MPEG Source
InfoFrames should not be used.
Notes:
1 - Tested over the operating temperature range at nominal supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing
out of the RSET resistor).
2 - Tested over the operating temperature range at reduced supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing
out of the Rset resistor).
3 - Full scale error from the value predicted by the design equations.
4 - About the mid-point of the distribution of the three DACs measured at full scale deflection.
5 - Linearity measured from the best fit line through the DAC characteristics. Monotonicity guaranteed.
6 - Load = 37.5 + 20 pF with Iref = -1.50 mA (Iref is the current flowing out of the Rset resistor).
7 - Measured from the end of the overshoot to the point where the amplitude of the video ringing is down to +/-5% of the final steady state
value.
8 - This parameter is sampled, not 100% tested.
9 - Monotonicity is guaranteed.
The RS780E has the capability of driving both digital and analog outputs simultaneously to a DVI-I connector. This is
accomplished by routing the RED, GREEN, BLUE, DACHSYNC, DACVSYNC, and AVSSN signals from the
RS780E’s CRT output (see
C4(HS), C5(GND), and Pin 8 (VS) signals (see
For the DVI output portion of the DVI-I connector, AMD recommends using the RS780E’s LVTM interface to provide
the DVI output and routing these digital signals (see
appropriate inputs on the DVI-I connector. The video BIOS must be configured so that the RS780E drives out DVI
signals from its LVTM interface. Display modes supported include desktop resolutions such as 800x600, 1024x768,
1152x864, 1280x1024, and 1600x1200 at 16bpp or 32bpp, with 60Hz or 75Hz screen refresh rate.
DVI-I Support
section 3.7, “CRT Interface‚’ on page 3-7) to the DVI-I connector’s C1(R), C2(G), C3(B),
Figure 2-9, “Pins for Analog Output on the DVI-I Connector,” below).
Figure 2-9 Pins for Analog Output on the DVI-I Connector
section 2.3, “LVTM (LVDS/TMDS) Interface‚’ on page 2-6) to the
2.8Clock Generation
The RS780E provides support for an external clock chip to generate side-port memory, PCI-E, and A-Link II clocks. For
information on the supported external clock chips, please consult your AMD CSS representative.
This chapter gives the pin descriptions and the strap options for the RS780E. To jump to a topic of interest, use the
following list of hyperlinked cross references:
“Pin Assignment Top View” on page 3-2
“Interface Block Diagram” on page 3-4
“CPU HyperTransport™ Interface” on page 3-5
“Side-port Memory Interface” on page 3-5
“PCI Express® Interfaces” on page 3-6:
“1 x 16 or 2 x 8 Lane Interface for External Graphics” on page 3-6
“A-Link Express II Interface for Southbridge” on page 3-6
“6 x 1 Lane Interface for General Purpose External Devices” on page 3-6
“Miscellaneous PCI Express® Signals” on page 3-6
“Clock Interface” on page 3-7
“CRT Interface” on page 3-7
“LVTM Interface” on page 3-8
“TMDS Interface Multiplexed on the PCI Express® Graphics Lanes” on page 3-10
HT_RXCALNOtherVDDHTRXVSSReceiver Calibration Resistor to VDD_HT power rail.
HT_RXCALPOtherVDDHTRXVSSReceiver Calibration Resistor to Ground
HT_TXCALPOtherVDDHTTXVSSTransmitter Calibration Resistor to HTTX_CALN
HT_TXCALNOtherVDDHTTXVSSTransmitter Calibration Resistor to HTTX_CALP
IVDDHTRXVSSReceiver Command, Address, and Data Differential Pairs
IVDDHTRXVSS
IVDDHTRXVSS
OVDDHTTXVSSTransmitter Command, Address, and Data Differential Pairs
OVDDHTTXVSS
OVDDHTTXVSS
Power
Domain
3.4Side-port Memory Interface
Table 3-2 Side-Port Memory Interface
Ground
Domain
Functional Description
Receiver Clock Signal Differential Pairs. Forwarded clock signal. Each byte of
RXCAD uses a different clock signal. Data is transferred on each clock edge.
Receiver Control Differential Pairs. For distinguishing control packets from
data packets.
Transmitter Clock Signal Differential Pairs. Each byte of TXCAD uses a
different clock signal. Data is transferred on each clock edge.
Transmitter Control Differential Pairs. Forwarded clock signal. For
distinguishing control packets from data packets.
MEM_DQ[15:0]I/OVDD_MEMVSSNoneMemory Data Bus. Supports SSTL2 and SSTL3.
MEM_DM[1:0]I/OVDD_MEMVSSNoneData masks for each byte during memory write cycles
MEM_DQS[1:0]PI/OVDD_MEMVSSNone
MEM_DQS[1:0]NI/OVDD_MEMVSSNoneDo not connect.
MEM_COMPP,
MEM_COMPN
MEM_VREFOther–VSSNone
OtherVDD_MEMVSSNone
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
Memory Address Bus. Provides the multiplexed row and column
addresses to the memory.
Memory Data Strobes. These are bi-directional data strobes for
latching read/write data.
Memory interface compensation pins for N and P channel
devices. Connect through resistors to VDD_MEM and ground
respectively (refer to the reference schematics for the proper
resistor values).
Reference voltage. It supplies the threshold value for
distinguishing between “1” and “0” on a memory signal. Typical
value is 0.5*VDD_MEM.
Clock Differential Pair for external graphics. Input from the external
clock generator, as a reference clock for external graphics.
Clock Differential Pair for Southbridge and general purpose PCI-E
devices. Input from the external clock generator, as a reference clock
for A-Link II and general purpose PCI-E.
Clock Differential Pair for general purpose PCI-E devices. Not used.
Can be left unconnected, or connected to the external clock generator
for maintaining system compatibility with the RX780 or RD780.
Reference clock input for the RS780E. REFCLK_P is a single-ended,
14.31818MHz input from the external clock generator; input swing
should be 1.1V. Connect REFCLK_N to VREF (0.55V) on the
motherboard.
Functional Description
Display Horizontal Sync
Display Vertical Sync
DAC internal reference to set full scale DAC current through 1%
resistor to AVSSQ
2
I
C™ data for display (to video monitor). The signal is 5V-tolerant.
2
I
C clock for display (to video monitor). The signal is 5V-tolerant.
Digital panel backlight brightness control. Active high. It controls
backlight on/off or acts as PWM output to adjust brightness.
If LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_EN = 0, the pin
controls backlight on/off. Otherwise, it is the PWM output to adjust
the brightness.
LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_LEVEL can be used
to control the backlight level (256 steps) by means of pulse width
modulation. The duty cycle of the backlight signal can be set
through the LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_LEVEL
bits. For example, setting these bits to a value of 32 will set the
on-time to 32/256*(1/REF) and the off-time to
(256-32)/256*(1/REF), where REF is the XTALIN frequency and is
typically 14.318MHz or 100MHz.
Note that the PWM frequency is set by
LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_RES and
LVTMA_PWRSEQ_REF_DIV.LVTMA_BL_MOD_REF_DIV. The
PWM frequency =
REF/((BL_MOD_REF_DIV+1)*(BL_MOD_RES+1)).
For more information, refer to the RS780 Register Reference Guide, order# 43451.
In CPIS mode, LVDS_BLON is VARY_BL as defined in CPIS.
PWM mode should be enabled. LVDS_EN_BL should be
connected to ENA_BL, which turns the backlight AC inverter
on/off.
Control Panel Digital Power On/Off. Active high.
Enables Backlight for CPIS compliant LCD panels. Active high.
Controlled by the hardware power up/down sequencer. For more
details, refer to
Figure 4-2, “LCD Panel Power Up/Down
Timing,” on page 4- 5.
3.8.2 LVTM Interface in TMDS Mode
Table 3-10 LVTM Interface in TMDS Mode
Pin Name
TXOUT_L0NTX0MOVDDLT18VSSLTNoneTMDS data channel 0 (-)
TXOUT_L0PTX0POVDDLT18VSSLTNoneTMDS data channel 0 (+)
TXOUT_L1NTX1MOVDDLT18VSSLTNoneTMDS data channel 1 (-)
TXOUT_L1PTX1POVDDLT18VSSLTNoneTMDS data channel 1 (+)
TXOUT_L2NTX2MOVDDLT18VSSLTNoneTMDS data channel 2 (-)
TXOUT_L2PTX2POVDDLT18VSSLTNoneTMDS data channel 2 (+)
TXOUT_L3NTX3MOVDDLT18VSSLTNone
TXOUT_L3PTX3POVDDLT18VSSLTNone
TXOUT_U0NTX4MOVDDLT18VSSLTNone
TXOUT_U0PTX4POVDDLT18VSSLTNone
TMDS
Functional
Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
TMDS data channel 3 (-). The channel is only used
in DVI dual-link mode and is not used for HDMI™
support.
TMDS data channel 3 (+). The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
TMDS data channel 4 (-). The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
TMDS data channel 4 (+) The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
TMDS data channel 5 (-). The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
TMDS data channel 5 (+). The channel is only used
in DVI dual-link mode and is not used for HDMI
support.
3.9TMDS Interface Multiplexed on the PCI Express® Graphics Lanes
The RS780E supports a dual-link TMDS interface, enabling DVI/HDMI™, which is multiplexed on the PCI-E external
graphics lanes.
HDMI is enabled only through the single-link mode.
Graphics Interface,”
shows the multiplexing relationships between the PCI-E external graphics signals and the TMDS
signals.
Table 3-11 TMDS Interface Multiplexed on the PCI Express® Graphics Interface
Table 3-11, “TMDS Interface Multiplexed on the PCI Express®
Pin Name
GFX_TX0PA5TX2P - 1st Link Red+
GFX_TX0NB5TX2M - 1st Link Red-
GFX_TX1PA4TX1P - 1st Link Green+
GFX_TX1NB4TX1M - 1st Link Green-
GFX_TX2PC3TX0P - 1st Link Blue+
GFX_TX2NB2TX0M- 1st Link Blue -
GFX_TX3PD1TXCP - Clock+
GFX_TX3ND2TXCM - Clock-
GFX_TX4PE2TX5P- 2nd Link Red+
GFX_TX4NE1TX5M - 2nd Link Red-
GFX_TX5PF4TX4P- 2nd Link Green+
GFX_TX5NF3TX4M - 2nd Link Green-
GFX_TX6PF1TX3P - 2nd Link Blue+
GFX_TX6NF2TX3M - 2nd Link Blue-
Ball
Reference
3.10DisplayPort™ Interface
The RS780E supports a maximum two DisplayPort™ channels through signals multiplexed on the PCI-E graphics
interface. Different implementations are possible, depending on the system configuration.
possibility, which uses the lower eight lanes of the interface for two DisplayPort outputs. For more explanations, please
refer to
Table 3-12 DisplayPort™ Interface Multiplexed on the PCI Express® Graphics Interface
Pin Name
GFX_TX0P,
GFX_TX0N
GFX_TX1P,
GFX_TX1N
GFX_TX2P,
GFX_TX2N
GFX_TX3P,
GFX_TX3N
DDC_CLK0/AUX0P,
DDC_DATA0/AUX0N
GFX_TX4P,
GFX_TX4N
GFX_TX5P,
GFX_TX5N
GFX_TX6P,
GFX_TX6N
GFX_TX7P,
GFX_TX7N
DDC_CLK1/AUX1P,
DDC_DATA1/AUX1N
AUX_CALC8Calibration for auxiliary pads.
Ball
Reference
A5/B5Main Link Channel Pair 0 on the first DisplayPort™ connector
A4/B4Main Link Channel Pair 1 on the first DisplayPort connector
C3/B2Main Link Channel Pair 2 on the first DisplayPort connector
D1/D2Main Link Channel Pair 3 on the first DisplayPort connector
A8/B8Auxiliary Channel Pair 0 on the first DisplayPort connector
E2/E1Main Link Channel Pair 0 on the second DisplayPort connector
F4/F3Main Link Channel Pair 1 on the second DisplayPort connector
F1/F2Main Link Channel Pair 2 on the second DisplayPort connector
H4/H3Main Link Channel Pair 3 on the second DisplayPort connector
B7/A7Auxiliary Channel Pair 1 on the second DisplayPort connector
DisplayPort™ Function
3.11 Power Management Pins
Table 3-13 Power Management Pins
Pin NameType
ALLOW_LDTSTOP I/ODVDD33VSSAllow LDTSTOP. The signal is used for controlling LDTSTOP assertions. When
SYSRESET#IVDD33VSSGlobal Hardware Reset. This signal comes from the Southbridge.
SUS_STAT#IVDD33VSS
POWERGOOD IVDD18VSSInput from the motherboard signifying that the power to the RS780E is up and
Power
Domain
Ground
Domain
Functional Description
running in CLMC mode it is an input from the CPU (LDTREQ#) or SB; when
running in legacy C3 and GSM modes, it is an output to the SB
1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted
Note: 1.8V signalling can be used on the signal.
Suspend Status. SUS_STAT# from the Southbridge is connected to the pin to gate
the sideport memory I/Os while power is ramping up and the POWERGOOD
signal to the RS780E is still low.
ready. Signal High means all power planes are valid. It is not observed internally
until it has been high for more than six consecutive REFCLK cycles. The rising
edge of this signal is deglitched.
NC––––No connect. These pins should be left unconnected to anything.
STRP_DATAI/OVDD33VSS
TESTMODEIVDD33VSS–
THERMALDIODE_P,
THERMALDIODE_N
TMDS_HPDI/OVDD33VSS
VDDLT33Other–––
A-O–––
Power
Domain
Ground
Domain
Integrated
Termination
50k
programmable:
PU/PD/non
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
50k
programmable:
PU/PD/none
Functional Description
Calibration for auxiliary pads.
DDC Clock 0 for displays, or AUX0P of the auxiliary pair for the
DisplayPort™ connected onto lane 0 to 3 of the PCI-E external
graphics interface. Can also be used as a GPIO.
DDC Data Channel 0 for displays, or AUX0N of the auxiliary pair for
the DisplayPort connected onto lane 0 to 3 on the PCI-E external
graphics interface. Can also be used as a GPIO.
DDC Clock 1 for displays, or AUX1P of the auxiliary pair for the
DisplayPort connected onto lane 4 to 7 of the PCI-E external
graphics interface. Can also be used as a GPIO.
DDC Data Channel 1 for displays, or AUX1N of the auxiliary pair for
the DisplayPort connected onto lane 4 to 7 on the PCI-E external
graphics interface. Can also be used as a GPIO.
Hot plug detect for DisplayPort. Can also be used as GPIO.
2
I
C™ interface clock signal.It can also be used as GPIO. The signal
is 5V-tolerant.
2
I
C interface data signal. It can also be used as GPIO. The signal
is 5V-tolerant.
2
I
C interface data signal for external EEPROM based strap loading.
Can also be used as GPIO, or as output to the voltage regulator for
pulse-width modulation of RS780E’s core voltage.
When High, puts the RS780E in test mode and disables the
RS780E from operating normally.
Diode connections to external SMBus microcontroller for
monitoring IC thermal characteristics.
TMDS Hot Plug Detect. It monitors the hot-plug line for panel
detection. It is a 3.3V CMOS compatible input. When not used for
hot plug detection, it can also be used as output to the voltage
regulator for pulse-width modulation of various voltages on the
motherboard.
These balls are only for maintaining pin-compatibility with the
RS740-series IGPs AMD chipsets. They can either be connected to
a 3.3V rail or left unconnected on RS780E systems.
3.13Power Pins
Table 3-15 Power Pins
Pin NameVoltage
AVDD3.3V2E12, F12Dedicated power for the DAC. Effort should be made at the board
level to provide as clean a power as possible to this pin to avoid
noise injection, which can affect display quality. Adequate
decoupling should be provided between this pin and AVSS.
Ground Pins
Table 3-15 Power Pins (Continued)
Pin NameVoltage
AVDDQ1.8V1H15DAC Bandgap Reference Voltage
IOPLLVDD1.1V1AE241.1V power for memory I/O PLLs
IOPLLVDD181.8V1AE231.8V power for memory I/O PLLs
PLLVDD1.V1A121.1V Power for system PLLs
PLLVDD181.8V1D141.8V power for system PLLs
VDD_MEM1.5/1.8V6AA11, AB10, AC10, AD10,
VDD18_MEM1.8V2AD11, AE111.8V power for side-port memory interface
VDDA18HTPLL1.8V1H17I/O power for HyperTransport PLL
VDDA18PCIE1.8V15AA9, AB9, AD9, AE9, H9,
VDDA18PCIEPLL1.8V2D7, E71.8V I/O power for PCI-E PLLs
VDDC1.0-1.1V22J11, J14, J16, K12, K15,
VDD181.8V2F9, G91.8V I/O transform power
VDD333.3V2H11, H123.3V I/O power
VDDHT1.1V7J17, K16, L16, M16, P16,
VDDHTRX1.1V7A23, B23, D22, E21, F20,
VDDHTTX1.2V13AA21, AB22, AC23, AD24,
VDDLT181.8V2A15, B151.8V I/O power for the interface
VDDLTP181.8V1A13Power for PLL macro.
VDDPCIE1.1V17A6, B6, C6, D6, E6, F6, G7,
Total Power Pin Count107
Pin
Count
Ball ReferencePin Description
Isolated power for side-port memory interface.
AE10, Y11
1.8V I/O power for PCI-E graphics, SB, and GPP interfaces
J10, K10, L10, M10, P10,
R10, T10, U10, W9, Y9
3G17, F18, F19Grounds for the DAC. These pins must be connected directly to
made at the board level to provide as clean a ground as possible
to this pin to avoid noise injection, which can affect display quality.
Adequate decoupling should be provided between this pin and
AVDD.
The RS780E provides strapping options to define specific operating parameters. The strap values are latched into internal
registers after the assertion of the POWERGOOD signal to the RS780E.
shows the definitions of all the strap functions. These straps are set by one of the following four methods:
•Attaching pull-up resistors to specific strap pins listed in Table 3-17 to set their values to “1”.
•Attaching pull-down resistors to specific strap pins listed in Table 3-17 to set their values to “0”.
•Downloading the strap values from an I
representative for details).
•Setting through an external debug port, if implemented (contact your AMD CSS representative for details).
All of the straps listed in
through resistors. To select “0”, the strap pins must be pulled down to VSS through resistors. During reset, the strap pins
are undriven, allowing the external pull-up or pull-down to pull a pin to “0” or “1.” The values on the strap pins are then
latched into the device and used as operational parameters. However, for debug purposes, those latched values may be
overridden through an external debug strap port or by a bit-stream downloaded from a serial EEPROM.
Table 3-17, “Strap Definitions for the RS780E,”
2
C™ serial EEPROM (for debug purpose only; contact your AMD CSS
Table 3-17 are defined active low. To select “1”, the strap pins must be pulled up to VDD33
SIDE_PORT_EN#DAC_HSYNCIndicates if memory side-port is available or not.
LOAD_EEPROM_STRAPS# SUS_STAT#Selects loading of strap values from EEPROM.
Note: On the RS780E, the widths of the A-Link Express II interface and the general purpose PCI-E links are configured through the
programmable strap GPPSB_LINK_CONFIG, which is programmed through RS780E’s registers. See the RS780 ASIC Family Register
Reference Guide, order# 43451, and the RS780 ASIC Family Register Programming Requirements, order# 43291, for details.SR5580
Register Reference Guide [forthcoming] and the SR5580 Register Programming Requirements [forthcoming] for details.
DAC_VSYNCEnables debug bus access through memory I/O pads and GPIOs.
0: Enable
1: Disable
(See debug bus specification documents for more details.)
0: Available
1: Not available.
2
0: I
C™ master can load strap values from EEPROM if connected, or use default
values if EEPROM is not connected. Please refer to RS780E's reference schematics
for system level implementation details.
Table 4-1 Timing Requirements for HyperTransport Reference Clock (100MHz) Output by the Clock Generator
SymbolParameterMinimumMaximumUnitNote
V
CROSS
FFrequency99.9100MHz2
ppmLong Term Accuracy-300+300Ppm3
S
FALL
S
RISE
T
jc max
T
j-accumulated
V
D(PK-PK)
V
D
V
D
DCDuty Cycle4555%11
Notes:
More details are available in AMD HyperTransport 3.0 Reference Clock Specification and AMD Family 10h Processor Reference Clock
Parameters, order # 34864.
1 Single-ended measurement at crossing point. Value is maximum-minimum over all time. DC value of common mode is not important
due to blocking cap.
2 Minimum frequency is a consequence of 0.5% down spread spectrum.
3 Measured with spread spectrum turned off.
4 Only simulated at the receive die pad. This parameter is intended to give guidance for simulation. It cannot be tested on a tester but
is guaranteed by design.
5 Differential measurement through the range of ±100mV, differential signal must remain monotonic and within slew rate specification
when crossing through this region.
6 T
7 Accumulated T
8 V
9 V
V
10 The difference in magnitude of two adjacent V
signal.
11 Defined as t
is the maximum difference of t
jc max
D(PK-PK)
is the amplitude of the ring-back differential measurement, guaranteed by design that the ring-back will not cross 0V VD.
D(min)
is the largest amplitude allowed.
D(max)
Change in Crossing point voltage over all edges-140mV1
Output falling edge slew rate-10-0.5V/ns4, 5
Output rising edge slew rate0.510V/ns4, 5
Jitter, cycle to cycle-150ps6
Accumulated jitter over a 10 s period-11ns7
Peak to Peak Differential Voltage4002400mV8
Differential Voltage2001200mV9
Change in V
over a 10s time period, measured with JIT2 TIE at 50ps interval.
jc
is the overall magnitude of the differential signal.
HIGH/tCYCLE
cycle to cycle-7575mV10
DDC
between any two adjacent cycles.
CYCLE
measurements. V
DDC
.
DDC
Chapter 4
Timing Specifications
is the stable post overshoot and ring-back part of the
1. Measured from -150mV to + 150mV from VREF, which is 0.55V.
2. Measured at VREF, which is 0.55V.
3. Measured with spread spectrum disabled.
REFCLK Long Term Jitter Requirement (1s after
scope trigger)
–500ps
4.5Side-port Memory Timing for DDR2 Mode
The RS780E’s side-port memory DDR2 interface complies with all the timing requirements given in the JESD79-2B
specification. Please refer to the JEDEC standard for any timing details.
4.5.1Read Cycle DQ/DQS Delay
During a memory read cycle, there is a DLL inside the RS780E that can delay each DQS signal with respect to its byte of
the DQ valid window. This delay ensures adequate setup and hold time to capture the memory data. This DLL delay is
programmable through the following registers:
The fraction of strobe delay, in terms of a memory clock period is (24+MCA_DLL_ADJ_DQSR) / 240. For example: if
MCA_DLL_ADJ_DQSR_1 = 36, then DQS1 is delayed by 0.25 x memory_clock_period. So, if the memory clock period
is 5ns, then DQS1 is delayed internally by 1.25ns with respect to DQ[15:8].
Similar to a read cycle, during memory write cycle there is a DLL inside the RS780E that can delay each DQS signal with
respect to its byte of the DQ valid window. This delay ensures adequate setup and hold time for DQ and DQS to the
memory. This DLL delay is programmable by the following registers in the same manner as with the read cycle:
Again, the fraction of strobe delay, in terms of a memory clock period is (24+MCA_DLL_ADJ_DQSR) / 240. For
example: if MCA_DLL_ADJ_DQ_B0 = 96, then DQS0 is delayed by 0.5 x memory_clock_period. So, if the memory
clock period is 5ns, then DQS0 is delayed internally by 2.5ns with respect to DQ[7:0].
Depending on the board layout of DQS and DQ signals, it may be necessary to have different delays for each DQS signal.
Layouts of the DQS and DQ signals should follow the rules given in the AMD
Design Guide,
order# 42336.
4.6LVDS Timing
Table 4-4 Timing Requirements for the LVTM Interface in LVDS Mode
ParameterMinTy pMaxUnitNotes
Differential Clock Period11.7–40ns1
Differential Clock Frequency25–85MHz
Frequency of the LVDS PLL VOC175–595MHz
Differential Clock Cycle-to-Cycle Jitter––420ps1
Transmitter PLL Reset Time
Transmitter PLL Lock Time
Differential Low-to-High Transition Time
Differential High-to-Low Transition Time
Data Channel to Channel Skew–100–ps
Notes:1 Time intervals measured at 50% LTPVDD18 threshold point.
2 Minimum time to keep LVDS_PLL_RESET asserted.
3 Measured after LVDS_PLL_RESET is de-asserted.
is the bit-time, which is 1/7 of the differential clock period
AVDDDI1.711.81.89VDedicated digital power for the DAC
AVDDQ1.711.81.89VDAC Bandgap Reference Voltage
IOPLLVDD1.0451.11.155V1.1V power for memory I/O PLLs
IOPLLVDD181.711.81.89V1.8V power for memory I/O PLLs
PLLVDD1.0451.11.155V1.1V power for system PLLs
PLLVDD181.711.81.89V1.8V power for system PLLs
VDD_MEM1.425/1.711.5/1.8V1.575/1.89VIsolated power for side-port memory
VDD18_MEM1.711.81.89V1.8V power for side-port memory
VDDA18HTPLL1.711.81.89VI/O power for HyperTransport PLL
VDDA18PCIE1.711.81.89V1.8V I/O power for PCI-E graphics,
VDDA18PCIEPLL1.711.81.89V1.8V I/O power for PCI-E PLLs
VDDC0.951.0-1.11.155VCore power
VDD181.711.81.89V1.8V I/O transform power
VDD333.1353.33.465V3.3V I/O power
VDDHT1.0451.11.155VI/O power for HyperTransport interface
VDDHTRX
VDDHTTX
VDDLT181.711.81.89V1.8V I/O power for the LVTM interface
VDDLTP181.711.81.89VPower for LVTM PLL macro
VDDPCIE1.0451.11.155VMain I/O power for PCI-E graphics,
Note: Numbers in this table are to be qualified.
1.045
1.141.21.26V
1.1
1.155V
Chapter 5
interface
interface
SB, and GPP interfaces
Note: Variable core voltage is not
supported on platforms that support
either (a) PCI-E Gen2, or (b)
DDR3-1200 side-port frame buffer
memory, as these features require a
fixed core voltage of 1.1V.
Table 5-13 Electrical Specifications for the DisplayPort™ Interface
SymbolParameterMin TypMaxUnitNotes
UI
HIGH_RATE
UI
LOW_RATE
V
TX-DIFFp_p
V
TX-PREMMP-RATIO
Unit Interval for DP High Bit Rate (2.7
Gbps/lane)
Unit Interval for DP Reduced Bit Rate (1.62
Gbps/lane)
Differential Peak-to-Peak Output Voltage Level 0.34-0.92V-
Pre-emphasis Level0-7.2dB-
5.2RS780E Thermal Characteristics
This section describes some key thermal parameters of the RS780E. For a detailed discussion on these parameters
and other thermal design descriptions including package level thermal data and analysis, please consult the Thermal
Design and Analysis Guidelines
5.2.1RS780E Thermal Limits
Table 5-14 RS780E Thermal Limits
ParameterMinimumNominalMaximumUnitNote
Operating Case Temperature0—95
Absolute Rated Junction
Temperature
Storage Temperature-40—60
Ambient Temperature0—45
Thermal Design Power—13—W4
Notes:
1 - The maximum operating case temperature is the die geometric top-center temperature measured via a thermocouple based on the
methodology given in the document Thermal Design and Analysis Guidelines for the RS780 Product Family, order# 44638 (Chapter 12).
This is the temperature at which the functionality of the chip is qualified.
2 - The maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing
damage to the ASIC. This temperature can be measured via the integrated thermal diode described in the next section.
3 - The ambient temperature is defined as the temperature of the local intake air to the thermal management device. The maximum
ambient temperature is dependent on the heat sink's local ambient conditions as well as the chassis' external ambient, and the value
given here is based on AMD’s reference heat sink solution for the RS780E. Refer to Chapter 6 in the Thermal Design and Analysis Guidelines for the RS780 Product Family, order# 44638, for heatsink and thermal design guidelines. Refer to Chapter 7 of the above
mentioned document for details of ambient conditions.
4 - Thermal Design Power (TDP) is defined as the highest power dissipated while running currently available worst case applications at
nominal voltages. Since the core power of modern ASICs using 65nm and smaller process technology can vary significantly, parts
specifically screened for higher core power were used for TDP measurement. The TDP is intended only as a design reference, and
The RS780E has an on-die thermal diode, with its positive and negative terminals connected to the THERMALDIODE_P
and THERMALDIODE_N pins respectively. Combined with a thermal sensor circuit, the diode temperature, and hence
the ASIC temperature, can be derived from a differential voltage reading (
below:
where:
V = Difference of two base-to-emitter voltage readings, one using current = I and the other using current = N x I
N
= Ratio of the two thermal diode currents (=10 when using an ADI thermal sensor, e.g. ADM 1020, 1030)
= Ideality factor of the diode
K = Boltzman’s Constant
T = Temperature in Kelvin
q = Electron charge
RS780E Thermal Characteristics
V). The equation relating T to V is given
The series resistance of the thermal diode (RT) must be taken into account as it introduces an error in the reading
o
(for every 1.0, approximately 0.8
induced, plus any other known fixed error. Measured values of diode ideality factor and series resistance for the
R
T
diode circuit are defined in the Thermal Design and Analysis Guidelines
C is added to the reading). The sensor circuit should be calibrated to offset the
To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling
device, follow the recommendations below:
•It is recommended that the maximum load that is evenly applied across the contact area between the thermal
management device and the die does not exceed 6 lbf. Note that a total load of 4-6 lbf is adequate to secure the
thermal management device and achieve the lowest thermal contact resistance with a temperature drop across
the thermal interface material of no more than 3°C. Also, the surface flatness of the metal spreader should be
0.001 inch/1 inch.
•Pre-test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and
the pressure applying around the ASIC package will not exceed 600 micron strain under any circumstances.
•Ensure that any distortion (bow or twist) of the board after SMT and cooling device assembly is within industry
1:1 ratio to pad, or
400µm max for the nine
corner balls’ openings
1:1 ratio to pad, or
400µm max for the eight
corner balls’ openings
1:1 ratio to pad, or
400µm max for the nine
corner balls’ openings
1:1 ratio to pad, or
400µm max for the nine
corner balls’ openings
1:1 ratio to pad,
with special
requirement for
corner balls
guidelines (IPC/EIA J-STD-001). For measurement method, refer to the industry approved technique described
in the manual IPC-TM-650, section 2.4.22.
5.3.3Board Solder Reflow Process Recommendations
5.3.3.1Stencil Opening Size for Solder Paste Pads on PCB
It is recommended that the stencil aperture for solder paste be kept at the same size as the land pads'. However, for
the nine (or eight) pads at each corner of the ASIC package, the size of the openings should not exceed 400µm (see
Figure 5-3 below). This recommendation is based on AMD’s sample land pattern design for the RS780E, which is
available from your AMD CSS representative.
5.3.3.2Reflow Profile
A reference reflow profile is given below. Please note the following when using RoHS/lead-free solder (SAC105/305/405
Tin-Silver-Cu):
•The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT
process. Modifications to the reference reflow profile may be required in order to accommodate the requirements of
the other components in the application.
•An oven with 10 heating zones or above is recommended.
Figure 5-3 Recommended Stencil Opening Sizes for Solder Paste Pads on PCB
•To ensure that the reflow profile meets the target specification on both sides of the board, a different profile and oven
recipe for the first and second reflow may be required.
This chapter describes the support for ACPI power management provided by the RS780E. The RS780E Northbridge
supports ACPI
required for meeting the power management specifications of PC2001, OnNow, and the Windows Logo Program and
Device Requirements version 2.1.
supported by the RS780E.
management scheme of the RS780E.
Table 6-1 ACPI States Supported by the RS780E
Graphics States:
D0Full on, display active.
D1Display Off. RS780E power on. Configuration registers, state, and main memory contents retained.
D3 HotSimilar to D1, with additional power saving and the graphics PLLs shut off.
D3 ColdRS780E power off.
Processor States:
S0/C0: Working StateWorking State. The processor is executing instructions.
S0/C1: HaltCPU Halt state. No instructions are executed. This state has the lowest latency on resume and contributes
S0/C2: Stop Grant
Caches Snoopable
S0/C3/C1e: Stop Grant
Caches Snoopable
System States:
S3: Standby
Suspend to RAM
S4: Hibernate
Suspend to Disk
S5: Soft OffSystem is off. OS re-boots when the system transitions to the working state.
G3: Mechanical OffOccurs when system power (AC or battery) is not present or is unable to keep the system in one of the
Revision 2.0. The hardware, system BIOS, video BIOS, and drivers of the RS780E have all the logic
Table 6-1, “ACPI States Supported by the RS780E,” describes the ACPI states
Table 6-2, “ACPI Signal Definitions,” describes the signals used in the ACPI power
ACPI StateDescription
minimum power savings.
Stop Grant or Cache Snoopable CPU state. This state offers more power savings but has a higher latency
on resume than the C1 state.
Processor is put into Stop Grant state. Caches are still snoopable. The HyperTransport link may be
disconnected and put into a low power state. System memory may be put into self-refresh.
System is off but context is saved to RAM. OEM support of this state is optional. System memory is put
into self-refresh.
System is off but context is saved to disk. When the system transitions to the working state, the OS is
resumed without a system re-boot.
other states.
Chapter 6
Power Management and ACPI
Note: Also supported are additional processor power states that are not part of the ACPI specification, e.g. C1E (C1
Enhanced) and C3 pop-up. Please refer to the
Programming Requirements,
Table 6-2 ACPI Signal Definitions
Signal NameDescriptionSource
ALLOW_LDTSTOPOutput to the Southbridge to allow LDTSTOP# assertion.Northbridge
LDTSTOP#HyperTransport™ Technology Stop: Enables and disables links during
SB710 Databook, order# 45215, and the RS780 ASIC Family Register
order# 43291, for more information.
Southbridge
6.2Power Management for the Graphics Controller
The RS780E supports power management for the embedded graphics device as specified by the PCI Bus Power
Management Interface Specification version 1.0, according to which the integrated graphics core of the RS780E qualifies
as a device embedding a single function in the power management system.
6.2.1PCI Function Power States
There are up to four power states defined for each PCI function associated with each PCI device in the system. These
power states are D0, D1, D2 and D3. D0 (on) consumes the most power while D3 (off) consumes the least. D1 and D2
enable levels of power savings in between those of D0 and D3. The concepts of these power states are universal for all
functions in the system. When transitioned to a given power management state, the intended functional behavior is
dependent upon the type (or class) of the function.
6.2.2PCI Power Management Interface
The four basic power management operations are:
•Capabilities Reporting
•Power Status Reporting
•Setting Power State
•System Wakeup
All four of these capabilities are required for each power management function with the exception of wakeup event
generation.
Power Management for the Graphics Controller
This section describes the format of the registers in the PCI Configuration Space that are used by these power
management operations. The Status and Capabilities Pointer (CAP_PTR) fields have been highlighted to indicate where
the PCI Power Management features appear in the standard Configuration Space Header.
Table 6-3 Standard PCI Configuration Space Header Type 0
R e g i s t e r F i e l d s ( 3 2 B i t s )
MSBLSB
Device IDVendor ID00h (LSB)
Status (with Bit 4 set to 1)Command04h
Class CodeRevision ID08h
BISTHeader TypeLatency TimerCache Line Size0Ch
Base Address Registers10h
CardBus CIS Pointer28h
Subsystem IDSubsystem Vendor ID2Ch
Expansion ROM Base Address30h
ReservedCAP_PTR34h
Reserved38h
Max_LatMin_GntInterrupt PinInterrupt Line3Ch
Offset
14h
18h
1Ch
20h
24h
6.2.3Capabilities List Data Structure in PCI Configuration Space
The Capabilities bit in the PCI Status register (offset = 06h) indicates whether or not the subject function implements a
linked list of extended capabilities. Specifically, if bit 4 is set, the CAP_PTR register is implemented to give offset to the
first item in the Capabilities link list.
15:05----Refer to PCI Local Bus Specification, Revision 2.2
041bRead OnlyThis bit indicates whether this function implements a list of extended capabilities
03:000hRead OnlyReserved
Read/
Write
Description
such as PCI power management. When set, this bit indicates the presence of
Capabilities. A value of 0 implies that this function does not implement
Capabilities.
The location of the Capabilities Pointer (CAP_PTR) depends on the PCI header type. See PCI Specification Revision 2.2
for specification of CAP_PTR offsets.
Table 6-5 Capabilities Pointer (CAP_PTR)
BitsDefault Value
07:0050hRead OnlyThe CAP_PTR provides an offset in the PCI Configuration Space of the
Read/
Write
Description
function to access the location of the first item in the Capabilities linked list. The
CAP_PTR offset is DWORD aligned, so that the two least significant bits are
always zeros.
The graphics core implements extended capabilities of the AGP and Power Management. It needs to provide the
standardized register interface. The first entry in the chain of descriptors has to be the PMI descriptor, as this functionality
will be supported even if the RS780E operates as a PCI device. The Capabilities Identifier for Power Management is 01h.
6.2.4Register Block Definition
This section describes the PCI Power Management Interface registers. These registers are implemented inside the Host
Interface (HI) as part of the configuration space of the device (RS780E).
Table 6-6 Power Management Register Block
Register FieldsOffset
Capability Identifiers (CAP_ID)00h
Next Item Pointer (NEXT_ITEM_PTR)01h
Power Management Capabilities (PMC)02h
Power Management Control/Status Register (PMCSR)04h
Reserved06h
The first 16 bits (Capabilities ID [offset = 0] and Next Item Pointer [offset = 1]) are used for the linked list infrastructure.
The next 32 bits (PMC [offset = 2] and PMCSR registers [offset = 4]) are required for compliance with this specification.
As with all PCI configuration registers, these registers may be accessed as bytes, 16-bit words, or 32-bit DWORDs. All of
the write operations to the reserved registers must be treated as no-ops. This implies that the access must be completed
normally on the bus and the data should be discarded. Read accesses to the reserved or the unimplemented registers must
be completed normally and a data value of 0000h should be returned.
Table 6-7 Power Management Control/Status Register (PMCSR)
Field
Name
Power State 1:000This field describes the power state of the graphics core.
Power State 15:20These Read Only bits will return the clock status of each clock tree, generated inside the clock
Bits
Default
(Reset)
StatesFunction
00 = D0Normal operation, no power savings enabled
01 = D1Sleeping state 1:
10 = D2Sleeping state 2
11 = D3Everything, except Host Interface, is turned off.
block.
The offset for each register is listed as an offset from the beginning of the linked list item that is determined either from
the CAP_PTR (if Power Management is the first item in the list) or the NEXT_ITEM_PTR of the previous item in the list.
6.2.5Capability Identifier: CAP_ID (Offset = 0)
The Capability Identifier, when read by system software as 01h, indicates that the data structure currently being pointed to
is the PCI Power Management data structure. Each function of a PCI device may have only one item in its capability list
with CAP_ID set to 01h.
Description
Display is off
Host access to DRAM is allowed
Display is off.
All engines are off.
Graphics core does not respond to host accesses to the frame buffer.
Table 6-8 Capability Identifier (CAP_ID)
BitsDefault Value
07:0001hRead OnlyThis field, when set to 01h, identifies the linked list item as being the PCI Power
Read/
Write
Description
Management registers
Figure 6-1, ‘Linked List for Capabilities,” shows the implementation of the capabilities list. The CAP_PTRgives the
location of the first item in the list. PCI Power Management registers have been stated as example in this list (although the
capabilities can be in any order).
•The first byte of each entry is required to be the ID of that capability. The PCI Power Management capability has an
ID of 01h.
•The next byte is a pointer giving an absolute offset in the functions PCI Configuration Space to the next item in the
list and must be DWORD aligned.
•If there are no more entries in the list, the NEXT_ITEM_PTRmust be set to 0 to indicate an end of the linked list.
Each capability can then have registers following the NEXT_ITEM_PTR.
The definition of these registers (including layout, size, and bit definitions) is specific to each capability. The PCI Power
Management Register Block is defined in
Figure 6-1, ‘Linked List for Capabilities,” below.
The Next Item Pointer register describes the location of the next item in the capability list of the function. The value given
is an offset in the PCI Configuration Space of that function. This register must be set to 00h if the function does not
implement any other capabilities defined by the PCI Specifications for inclusion in the capabilities list, or if power
management is the last item in the list.
Table 6-9 Next Item Pointer (NEXT_ITEM_PTR)
Bits
07:0080hRead Only This field provides an offset in the PCI Configuration Space of the function pointing to the location
Default
Value
Read/
Write
Description
of next item in the capability list of the function. For Power Management of the RS780E, this
pointer is set to 80h and it points to the next capability pointer of the MSI structure.
6.2.7PMC - Power Management Capabilities (Offset = 2)
The Power Management Capabilities register is a 16-bit Read Only register that provides information on the capabilities
of the function related to power management. The information in this register is generally static and is known at design
time.
Table 6-10 Power Management Capabilities – PMC
Power Management for the Graphics Controller
BitsDefault Value
15:1100111bRead OnlyThis 5-bit field indicates the power states in which the function may assert PME#. A value of
10001bRead OnlyRS780E supports D2.
09001bRead OnlyRS780E supports D1.
08:06000bRead OnlyReserved
051bRead OnlyThe Device Specific Initialization bit indicates whether special initialization of this function is
040bRead OnlyReserved
030bRead OnlyReserved
02:00001bRead OnlyA value of 001b indicates that this function complies with Revision 1.0 of the PCI Power
Read/
Write
Description
0b for any bit indicates that the function is not capable of asserting the PME# signal while in
that power state.
bit(11) XXXX1b - PME# can be asserted from D0.
bit(12) XXX1Xb - PME# can be asserted from D1.
bit(13) XX1XXb - PME# can be asserted from D2.
bit(14) X0XXXb - PME# cannot be asserted from D3hot.
bit(15) 0XXXXb - PME# cannot be asserted from D3cold.
required (beyond the standard PCI configuration header) before the generic class device
driver is able to use it. The RS780E requires device specific initialization after Reset; this field
must therefore return a value 1 to the system.
The RS780E has integrated test modes and capabilities. These test features cover both the ASIC and board level testing.
The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part. The board level
tests modes can be used for motherboard manufacturing and debug purposes. The following are the test modes of the
RS780E:
•Full scan implementation on the digital core logic that provides about 99% fault coverage through ATPG (Automatic
Test Pattern Generation Vectors).
•Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
•Improved access to the analog modules and PLLs in the RS780E to allow full evaluation and characterization of these
modules.
•A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) to allow board level testing of
neighboring devices.
•An XOR TREE test mode on all the digital I/O’s to allow for proper soldering verification at the board level.
•A VOH/VOL test mode on all digital I/O’s to allow for proper verification of output high and output low voltages at
the board level.
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
Chapter 7
Testability
7.2Test Interface
Table 7-1 Pins on the Test Interface
Pin NameBall numberTypeDescription
TESTMODED13IIEEE 1149.1 test port reset
DDC_DATA0/AUX0NB8ITMS: Test Mode Select (IEEE 1149.1 test mode select)
I2C_DATAA9ITDI: Test Mode Data In (IEEE 1149.1 data in)
I2C_CLKB9ITCLK: Test Mode Clock (IEEE 1149.1 clock)
TMDS_HPDD9OTDO: Test Mode Data Out (IEEE 1149.1 data out)
POWERGOODA10II/O Reset
7.3XOR Test
7.3.1Description of a Generic XOR Tree
An example of a generic XOR tree is shown in the Figure 7-1.
Pin A is assigned to the output direction, and pins 1 through 6 are assigned to the input direction. It can be seen that after
all pins 1 to 6 are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin A.
The following is the truth table for the XOR tree shown in
The RS780E chip enters the XOR tree test mode by means of the JTAG. First, the 8-bit instruction register of the JTAG is
loaded with the XOR instruction (“00001000”). This instruction assigns the input direction to all the pins except pin TDO,
which is assigned the output direction to serve as the output of the XOR tree. After loading, the JTAG is taken to the
Run-Test state for completion of the XOR tree initialization.
A
10MHz clock frequency for the Test Mode Clock (I2C_CLK) is recommended for the XOR TREE test mode. A pair of
differential clock at 10MHz should also be supplied to HT_REFCLKP/N to enable I/Os for testing.
Figure 7-1 The XOR start signal is assumed to be logic 1.
7.3.4XOR Tree for the RS780E
The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the
TDO Pin. Refer to
tree will cause the output to toggle.
There is no specific connection order to the signals on the tree. When the XOR tree is activated, any pin on the XOR tree
must be either pulled down or pulled up to the I/O voltage of the pin. Only pins that are
floating.
When differential signal pairs are listed as single entries on the XOR tree, opposite input values should be applied to the
two signals in each pair (e.g., for entry no. 1 on the tree, when “1” is applied to HT_RXCAD0P, “0” should be applied to
HT_RXCAD0N).
The VOH/VOL logic gives signal output on I/O’s when test patterns are applied through the TEST_ODD and
TEST_EVEN inputs. Sample of a generic VOH/VOL tree is shown in
5. Load JTAG instruction register with the instruction 0110 0011.
6. Load JTAG instruction register with the instruction 0010 0111.
7. Set POWERGOOD to 1.
8. Load JTAG instruction register with the instruction 1001 1001.
9. Run test by loading JTAG data register with data 0000 0000 0000 00xy, where bit x is the input value for
TEST_ODD and bit y that for TEST_EVEN (see Table 7-4 above).
10. To end test, load JTAG instruction register with the instruction 0101 1101.
7.4.3VOH/VOL Pin List
Table 7-5 shows the RS780E VOH/VOL tree. There is no specific order for connection. Under the Control column, an
“ODD” or “EVEN” indicates that the logical output of the pin is same as the “TEST_ODD” or “TEST_EVEN” input
respectively.
When a differential pair appear in the table as a single entry, the output of the positive (“P”) pin is indicated in the Control
column (see last paragraph for explanations), and the output of the negative pin (“N”) will be of the opposite value. For
example, for entry no. 1 on the tree, when TEST_EVEN is 1, HT_TXCAD0P will give a value of 1 and HT_TXCAD0N
will give a value of 0.