®
Enhanced
Configuration Devices
(EPC4, EPC8 & EPC16)
April 2002, ver. 2.0 Data Sheet
Features
Preliminary
Information
■ Enhanced configurati o n de v ices include EPC4, EPC8, and EPC16
devices
■ 4-, 8-, and 16-Mbit Flash mem ory devices that co nfigure Stratix
APEX
TM
II, APEX 20K, MercuryTM, ACEXTM1K, and FLEX® 10K
TM
,
devices
– Compression increases effective configuration density of these
devices up to 7, 15, or 30 Mbits
■ Available in the 100-pin plastic quad flat pack (PQFP) package and
the 88-pin Ultra FineLine BGA
■ Standard Flash die and a controller die combined into one package
■ V
■ Supports true N-bit (N = 1, 2, 4, and 8) programmable logic device
CCINT
and V
are both 3.3 V
CCIO
TM
package
(PLD) concurrent configuration mode
– Configures multiple PLDs in parallel
– Supports an 8-bit parallel data output on every DCLK cycle
■ Pin-selectable 2-ms or 100-ms power-on reset (POR) time
■ Programmable clock speed with three clock modes for faster
configuration time
– Internal oscillator defau lts to 10 MHz
– Programmable internal oscilla tor for higher frequencies of 33 , 50,
and 66 MHz
– External clock source with frequencies up to 133 MHz
■ EPC16 configuration device allows PLD or processor to access
unused Flash memory locations via external flash interface
■ Flash memory can hold up to eight pages of configuration files,
enabling systems to reconfigure PLDs with different configuration
files
■ Flash block/sector protection capability (EPC16 configuration
devices only)
■ Compliant with IEEE Std. 1532 in-system programmability (ISP)
specification
■ Supports ISP via Jam
TM
Standard Test and Programming Lang uag e
(STAPL)
■ Supports Joint Test Action Group (JT AG) bou nd ary scan
■ nINIT_CONF pin allows private JTAG instruction to initiate PLD
configuration
■ Programmable configuration done error detection capability
■ Internal program mab le we ak pull- ups on nCS and OE pins, Flash
address, and control lines, and bus hold on data line
■ Standby mode with reduced power consumption
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Altera Corporation 1
DS-ECD-2.0
Enhanced Configuration Devices Data Sheet Preliminary Information
1 A future version of th is data sheet wil l include more infor mation
on Stratix device support.
Architecture Description
Figure 1. Enhanced Configurat ion Device Block Di agram
Enhanced Configuration Device
The Alter a® enhanced configuration devices sup port a sing le-de vice
solution for very high-den sity PLDs w hile decre asing confi guration time.
The core of an enhanced configuration device is divided into two major
blocks, the controller and the Flash memory. The Flash memory can be
used for APEX II, APEX 20K, Mercury, ACEX, and FLEX 10K device
configuration, and its unuse d locations can be used as memory storage for
the PLD or processor.
1 All references to the direct Flash interface in this document are
for EPC16 configuration devices only. For information on using
Flash memory interface in the EPC4 or EPC8 configuration
devices, please conta ct Alte ra Applications.
Figure1 shows a block diagram of the enhanced configuration device’s
core blocks, their connection to the PLD, and their interface with the
JTAG/ISP interface.
JTAG/ISP Interface
Flash
2 Altera Corporation
Controller
PLD
Preliminary Informa tion Enhanced Configurati on D evi ces Data Sheet
(1)
Enhanced Configuration Device Controller Unit
The controller unit of the enhanced configuration device has a 3.3-V core
and an I/O interfa ce. The con troller is a s ynchronous s ystem that i ncludes
the following:
■ Power-on reset circuitry (POR)
■ Internal oscillator (IOSC)
■ Clock divider unit (CDU)
■ Decompression engin e
■ PLD configuration unit (PCU)
■ JTAG interface unit (JIU)
Figure 2 shows a block diagram of the enhanced configuration device
controller unit.
Figure 2. Enhanced Configuration Device Controller Unit Block Diagram
Page Mode Select TDI, TDO, TMS , TCK
EXCLK
Enhanced Configuration
Device
A[20:0]
OE#
WE#
CE#
WP#
Controller
3
4
JIU
Flash
Memory
DQ[15:0]
RP#
RD/BY#
16
16
POR Unit
POR POR Counter
Flash
Reset
PLD Reset
PORSEL
16
Decompression
Engine
Flash Data Out Bus
Flash Data In Bus
16
[15:8]
[7:0]
DCLK
Pause
Note to Figure 2:
(1) EXCLK should be connected to VCC or GND if it is not being used.
8
CDU
DCLK
SYSCLK
1
7
nINIT_CONF
IOSC
Oscillator
INTOSC
PCU
DATA[7:0]
Divide
by N
Divide
by M
nCS
OE
nCONFIG
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PLD
DCLK
DATA[7:0]
CONF_DONE
nSTATUS
Altera Corporation 3
Enhanced Configuration Devices Data Sheet Preliminary Information
Power-On Reset Unit
The POR circuit kee ps t he system in reset unt il th e power supply voltage
levels have stabilized. T he enhanced configura tion device has tw o options
for the POR time: the user can either keep the POR time at the 100-ms
default value or reduce the POR time through the selectable input pin to
2 ms for applications that require fast power-up. The
controls the POR reduction time from 100 ms to 2 ms. See Table 7 on
page 28 for more information.
The POR unit manages the controller’s reset scheme. When the POR
counter expires, the POR unit releases the
OE pin. The POR time can be
further extended from an external source by driv i ng the
1 Do not execute JTAG or ISP instructions until POR is complete.
The enhanced configuration device reset can be divided into three
categories:
PORSEL input pin
OE pin low.
■ The POR reset starts at initial power-up reset during V
drops an ytime after V
V
CC
■ The PLD initiates re-configuration by driving nSTATUS low, which
has stabilized.
CC
ramp or if
CC
occurs if the PL D dete cts a cyclic re dund anc y che ck (C RC ) er r or or if
nCONFIG input pin is asserted in the PLD.
the
■ The controller detects an e rro r an d asserts the OE to initiate re-
configuration of APEX II, APEX 20K, Mercury, ACEX 1K, and
FLEX 10K devices when the auto restar t upon error option is enab led
in software.
Internal Oscillator
Frequencies for the internal oscillator (IOSC) of the enhanced
configuration device, which supports four modes of internal clock
frequencies, are shown in Table 1. The user can program the oscillator,
which is controlled by option bits through the software.
Table 1. Internal Oscillator Frequencies
Mode Min (MHz) Typ (MHz) Max (MHz)
A 6.4 8.0 10.0
B 21.0 26.5 33.0
C 32.0 40.0 50.0
D 42.0 53.0 66.0
4 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evi ces Data Sheet
Clock Divider Unit
The CDU generates SYSCLK and DCLK for the controller by dividin g t he
internal oscillator clock (INTOSC) or external clock (EXCLK). The CDU’s
clock division architecture has two di vid ers. The fir st divider (N) divides
down the selected reference clock to generate
(M) divides down
DCLK to generate SYSCLK. Each divider contains a 1 to
16 integer divider. Both a 1.5 divider an d a 2.5 divid er are also
implemented in the first divider (N), but the second divide r (M) ca n only
divide integers. As a default from powe r-up, the INTOSC is in mode A, the
first divider is set to divide by one to generate the
divider is set to divide by two to generate the
The default duty cycle for all clock divisions other than non-integer
divisions is 50% (for the non-integer dividers, the duty cycle will not be
50%). For integer divisions, the CDU allows the duty cycle of
SYSCLK to be programmable by setting appropriate option bits through
the software. The
frequency of the PLD, but the
DCLK frequency is limited by the maximum DCLK
SYSCLK frequency is limited by the
maximum Flash performance (about 10 MHz). Therefore,
SYSCLK might run at different frequencies. See Figure 3 for details on the
CDU.
DCLK. The second divider
DCLK, and the second
SYSCLK (see Figure 3).
DCLK and
DCLK and
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The maximum DCLK frequency for each PLD family is specified in
Application Note 116 (Configuring SRAM-Based LUT Devices).
Figure 3. Clock Divi der Unit
CDU
INTOSC
DCLK
Divide
SYSCLK
Altera Corporation 5
EXCLK
Divide
by N
by M
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Enhanced Configuration Devices Data Sheet Preliminary Information
Decompression Engine
Enhanced configuration devices support decompression. Configuration
TM
data is compressed by the Quartus
II software and stored in the
enhanced configuration d evice. Durin g configuration, t he decompress ion
engine inside the enhanced configuration device will decompress or
expand data. This feature increases the effective configuration density of
the enhanced config uration device up to 7, 15, or 30 Mb its in EPC 4, EPC8,
and EPC16, resp e ctivel y .
The enhanced configurat ion device also supports a parallel data bus to the
PLD to reduce config ur a tion tim e . Ho we ver , in some cases, the PL D data
transfer is limited by the Flash data transfer rate. With parallel
programming mode in the PL D (w he n N = 8 and the
DCLK frequency is
66 MHz), the data output bandwidth to the PLD is faster than the data
input bandwidth reading from the Flash. Because configuration time
depends on the ratio of data bits read and the bandwidth used, the
compression will improve configura tion time. The decompres sion engine
decompresses the configuration data before sending it to the PLD
configuration unit (PCU) for PLD configuration.
PLD Configuration Unit
The function of the PCU is to transmit decompressed data to the PLD,
depending on the configuration mode. The enhanced configuration
device supports four concurrent configuration modes, with N = 1, 2, 4, or
8. Depending on the data width, the PCU shifts the data to transmit
appropriate data to the valid data pins. Unused data pins drive low.
In addition to transmitting data to the PLD, the PCU is responsible for
delaying the
DCLK to the PLD whenever there is insufficient
decompressed data, i.e., when waiting for the decompression engine to
decompress data. This technique is called “Pausing
The PCU manages the
error occurs when
CONF_DONE error detection logic. A CONF_DONE
nCS is not de-asserted within a certain numb er of clock
cycles after the last data bit is transmitted to the PLD. When a
DCLK.”
CONF_DONE
error is detected, the PCU asserts signals to the POR unit, which asserts
OE pin to start re-configuring the PLD. This is done only when the
the
auto-restart configuration upon frame e rror option i s enabled in softw are.
6 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evi ces Data Sheet
JTAG Interface Unit
The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in en ha nced
configuration devices to facilitate the testing of its interconnection and
functionality. Enhance d c onfiguration devi ces also s upport t he ISP mode .
The enhanced configuration device’s ISP is compliant with the IEEE Std.
1532 draft 2.0 specification. In addition to programming, erasing, and
verifying the Flash, enha nced configuration devi ces (EPC16 configuration
devices) also support block/sector protection through IEEE Std. 1532compliant instruct ions.
The JTAG interface unit (JIU) communicates directly with the Flash
memory (see Figure 4). The JIU operates at the maximum JTAG
frequency of 10 MHz.
Figure 4. JTAG/ISP Interface
JTAG/ISP Interface
Controller
TCK
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Flash
Memory
JIU
Before the J T AG/ISP interface pr ograms the Fl ash memory, a JTAG
instruction (PENDCFG) asserts the PLD’s nCONFIG pin (connected to
nINIT_CONF pi n), which will termina te any access to Flas h. When the ISP
mode starts, the JIU takes over the Flash memory. If the ISP mode starts
during PLD configuration, the configuration terminates immediately.
Altera Corporation 7
Enhanced Configuration Devices Data Sheet Preliminary Information
Flash Memory
The Flash memory in EPC4, EPC8, and EPC16 devices is 4, 8, or 16 Mbits,
respectively, with the boot block at the bottom. The Flash memory is
divided into three types of blocks: the boot block, parameter block, and
main block. Each block has protection capability and can be erased
individually. The enhanced configuration device can also program and
erase the Flash lock bits through the JTA G inte rf ace . T he lock bi ts p rot ec t
Flash again st an in adver tent er ase; a b lock cannot be er ased wh en the lo ck
bit is set.
Boot Block
The boot block, which is 8K words on the EPC16 configurati on device, c an
replace a dedicated boot PROM for a microproces sor (as found in
Excalibur
data, but not configuration data. The boot block features hardwarecontrollable write protection to protect the crucial microprocessor boot
code from accidental modification using a combination of RP# and WP#
pins and a block lock bit. Each block contains a lock bit that disables a
program or an erase operation on the block.
To use the bottom boot block in the Flash memory, WP# should be
connected to VCC. If WP# is connected to GND, the bottom boot block is
locked so it cannot be programmed or erased. WP# only exists in the
bottom boot blocks; the other blocks are not affected.
TM
embedded processo r solutions). It can also store other syst em
1 When using the Quartus II software versions 2.0, WP# should be
connected to VCC whe n programming with a Programm er
Object File (.pof), otherwise, the Quartus II software
cannot successfully program the device. Jam
TM
(.jam) and Jam
Byte-Code (.jbc) files can be us ed to su ccessfu lly prog ram EPC4,
EPC8, and EPC16 devices when WP# is floating.
Parameter Block
The parameter block is used for storing small, frequently updated
parameters. In EPC16 d evices, there are six p arameter blocks of 4K words.
Parameter block protection is controlled by using a combination of RP#
and block loc k bi ts.
Main Block
The main block fills the remainder of the Flash memory and contains
configuration and user memory space. In EPC16 configuration devices,
there are 31 blocks of 32K words. Similar to the parameter block, the
protection of the ma in block is controlle d using a combination of RP# and
block lock bits.
8 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evi ces Data Sheet
Memory Map
The EPC16 configuration devic e me mo ry map can be divided into two
main sections: controller memory space and user memory space.
The controller memory space consis ts of the controlle r’s option bits and a
maximum of eight pages of configuration data. The memory space starts
with address 08000h (after 32K words of boot/parameter blocks) and
continues up ward. 512 b its reside from addres s 08000h to 00801fh, and
they are reserved for option bits.
Figure 5 shows the 16-Mbit Flash memory map for EPC16 devices.
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Altera Corporation 9
Enhanced Configuration Devices Data Sheet Preliminary Information
B
r
r
Figure 5. Flash Memory in EPC16 Configuration Device (Bottom Boot)
FFFFFh
Empty locations that can
be used by PLD/processo
Main Block
08020h
0801Fh
08000h
oot/Parameter Block
Not Used
Page 7
Page 0
Option Bits
Reserved Bottom
Boot/Parameter
Not used by PLD/processo
Page mode section
Controller's 512 option bits
Bottom 32K words are
reserved for processor
00000h
10 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evi ces Data Sheet
In EPC16 conf iguration d evices, the b oot block s and the p arameter blocks
are located at the bottom of the 32K-word blocks. Due to the lock bit
flexibility available with 4K blocks and the
blocks, the user may want to use the bottom 32K-word block (boot and
parameter blocks) for PLD or processor memory space. Altera
recommends using the bottom 3 2K-word blocks (boot/parameter blocks).
However, if the PLD or pr ocessor will b oot from the top 32 K-word blocks,
the user should re-map the address to the bottom block by using glue
logic. In systems that do not use PLD or processor memory space, the
system user can use the bottom 32K-word blocks for configuration data
memory space.
WP# feature in the two 4K boot
Page Mode Selection
The Page Mode Selection feature allows the enhanced configuration
device to store up to eight different designs per PLD. The user chooses
which design will configure the PLD at configuration. The Page Mode
Selection will enable designers to switch the functionality of a PLD (or
PLDs) by switching PGM [ ] pins.
1 Each page mo de can h ave up to 8- bit conc urrent conf iguration of
devices.
Three input pins (PGM[2:0]) select one of eight pages of the
configuration files that configure the PL Ds. Page 0 is defined as the default
page (see Figu re 5 on page 10). Connect these pins on the board to select
the user-specified page in the Quartus II software when generating the
EPC4, EPC8, or EPC16 POF file. PGM2 is the most significant bit (MSB).
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Operating Modes
The operating mod es define th e e nha nced con f igura tion devi ce’ s proce ss
flow of data an d contro l signal s. The data proce ss fl ow expl ains how data
is transf er red between blocks during read and write cycles. The control
process flow expla ins h ow con tr ol signa ls ha nd sh ak e bet ween the blocks
to facilitate data transfer. The main modes are normal mode and
programming mode.
Normal Mode
The Normal mode controls the PLD configuration process using
compressed da ta in the Flash memor y. Th e proces s inv olves rea ding da ta
from the Flash memory, data decompression, and sending data to the
PLD.
Altera Corporation 11
Enhanced Configuration Devices Data Sheet Preliminary Information
Upon power-up, th e POR unit ge nerates all the reset signals . The POR unit
resets all enh anced configura tion dev ice’s c ontrol units using the 10-MHz
default internal clock as the main clock source. After the POR counter
expires, the POR unit d e-asse rts
be extended. Upon start of the configuration process, the device samples
PGM[] select pins to determine which page of the configuration files
the
in Flash memory should be used for PLD configuration. The CDU will
switch the int erna l clock to the n ew c lock s et tings according to t he op tion
bit setting. Th e device start s to read the Flash configuration da ta. When
goes hig h, the PCU starts the
When the last configuration data bits have been read from the Flash
memory, the page counter expires and the PCU stops reading from the
Flash memory. If no error is detected on CONF_DONE, DCLK will continue
toggling until
cycle. If
OE and start a new PLD reconfiguration.
assert
nCS goes high, indicating a successful PLD configuration
CONF_DONE error detection detec ts an error, the POR unit will
OE. By holding OE low, the POR time can
DCLK and configures the PLD.
OE
Device Configuration
f
After the PLD configuration process is complete, PCU stops
keep the Flash memory in an idle state, the device enables pull-ups, pulldowns, and/or bus-keepers to the Flash interface pins.
DCLK. To
Programming Mod e
During ISP mode, the JTAG interface accesses the Flash memory. The
controller processes the ISP instructions to access the Flash memory
through the JIU. After receiving an ISP instruction, the JIU decodes the
instruction and performs the necessary Flash bus cycle. At the end of the
programming mode, the JIU interfaces with the PLD to initiate a PLD
reconfiguration cycle. When the JTAG interface takes the bus-mastership,
it starts to reconfigure the PLD. During PLD configuration, the JTAG
interface should not be used, as using it may interfere with the PLD
configuration. After the re-configuration cycle is successfully completed,
the PLD asserts
DATA[7:0] remains in the last logic state.
and
The control signals from the enhanced configuration device (DATA[],
DCLK, nCS, nINIT_CONF, and OE) interface directly with the APEX II,
APEX 20K, Mercury, ACEX, or FLEX 10K devices’ control signals.
For more information on parallel configuration, refer to Application
Note 116 (Configuring SRAM-Based LUT Devices).
CONF_DONE high. Upon this assertion, DCLK drives low,
12 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
The DCLK pin, whic h is drive n from th e enha nced conf igura tion devic e to
the PLD, acts as t he confi guration cy cle refer ence cloc k. It func tions a s the
configuration data “write-enable” strobe signal. The OE pin is an open-
drain pin and is driven low when POR is not complete. A bu ilt-in 2-ms or
100-ms counter holds the release of
permit voltage level stabilization . After POR expires, the POR time can be
extended externally by driving
enhanced configuration device resets the address counters.
The nCS pin of the enhanced configuration device is connected to the
CONF_DONE pin of the PLD. The nCS pin check s for a successful PLD
configuration a fter t he last c onfigur ation d ata has b een tra nsmitte d to the
PLD. The P LD alwa ys driv es the nCS low when th e
the nCS and
The enhanced configuration device allows the user to initiate
configuration of APEX II, APEX 20K, Mercury, ACEX, or FLEX 10K
devices via th e
LUT-based PLDs. A JTAG ins tr uct ion c aus es the e nha nc ed con figura tion
device to drive nINIT_CONF low, which , in turn, pu lls nCONFIG low. The
enhanced configuration device then drives nINIT_CONF high to start
configuration. When the JTAG state machine exits this stage,
nINIT_CONF releases the nCONFIG, and the PLD configuration is
initiated.
OE pins have a programmable weak int ernal pull -up res istor.
nINIT_CONF pin, which can be tied to the nCONFIG pin of
OE during the initial power-up to
OE low. When OE is driven low, the
OE is pulled low. Both
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Serial Configuration Mode
APEX II, APEX 20K, Mercury, ACEX, and FLEX 10K devices can be
configured through the enhanced configuration device in the serial
programming mode. In this mode, the enhanced configuration device
sends a se rial bi t-stream of conf igurati on data to its DATA0 pin, which is
routed to the DATA0 input pin on LUT-based PLDs.
Figure 6 shows APEX II, APEX 20K, Mercury, ACEX, or FLEX 10K devices
configured with an enhanced configuration device in the serial
programming mode.
Altera Corporation 13
Enhanced Configuration Devices Data Sheet Preliminary Information
)
Figure 6. Seria l Co nf i gu r at i on Mode
Enhanced Configuration
V
CC
TMI
WE#C
RP#C
DCLK
DATA0
OE
nCS
nINIT_CONF
V
CC
WP#
PORSEL
PGM[2..0]
TMO
GND
Device
(9)
(9)
(1)
VCCW
WE#F
RP#F
A[20..0]
RY/BY#
(6)
DQ[15..0]
EXCLK
CE#
OE#
V
CC
(4)
(8)
(7)
Optional External
Clock Source
PLD or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
(2
GND
MSEL0
MSEL1
PLD
DCLK
DATA0
(5)
nSTATUS
CONF_DONE
nCONFIG
nCE
V
CC
(3) (3)
GND
V
CC
Notes to Figure 6:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to the controller unit. The only pins that need external
connection are WP#, WE#, and RP#, whi ch are shown in Figure 13 on page 29. If Flash is being used as an external
memory source (in EPC16 configuration devices), then the Flash pins should be connected. For more information,
consult the LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
(2) For Flash in t erface in EPC 4 a n d EPC8 configuration devices, plea se contact Alt era Applications.
(3) The OE, nCS, and nINIT_CONF pins on enh anced config urat ion dev ices h ave in ternal pull -up res isto rs. The inter nal
pull-up resistor on the nINIT_CONF pin is always active. However, on OE and nCS pins, the user has the option of
turning these resistors on or off through the software. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE p ull-up s on config urat ion
device option when generating programming files. If external pull-up resistors are used, they should be 1 kΩ (except
APEX 20KE devices require 10 kΩ).
(4) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
(5) nSTATUS should not have an external pull-up resistor for ACEX or FLEX devices. Instead, the programmable
internal resistor on OE should be used.
(6) nINIT_CONF has an internal pull-up resistor that is always active. If nINIT_CONF is not available or not used,
nCONFIG must be pulled to V
an external pull-up should not be used. For more information, refer to Application Note 116 (Configuring SRAM-Based
LUT Devi c es).
either directly or through a 1-k Ω resistor. When configuring an APEX 20KE device,
CC
(7) The Flash interface exists only in E PC 16 c on fig u ra tion devices and is a tri-state interface. Th e sig na ls disp la ye d as
dotted lines should not be d r iv en when the F la sh interface is not availa ble. For Flash int erface avai lability, refer to
Table 2 on page 15.
(8) EXCLK is an input on ly. In the Quar tu s II software, t he us er can select EXCLK or internal oscillator as the cloc k
source. For pin connections, refer to Table 7 on page 28.
(9) For pin connections, refer to Table 7 on page 28.
14 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
In the enhanced configuration device, the Flash memory stores the
configuration data, and the controller transfers the configuration data
through the
DATA0 pin to LUT-based PLDs. DATA0, DCLK, nCS,
nINIT_CONF, and OE pins interfa ce the enhanced configurati on device to
the PLD.
External Flash Memory Interface
In EPC16 configuration devices, the unuse d memory porti on of the main
block (i.e., memory that was not used for the configuration file) can be
used by an ext ernal sourc e such as a micr oproce ssor or PLD. This exter nal
source uses the unused Flash memory to store application codes. The
address, data, and control ports of the F lash memory are internally
connected to the e nhanced config uration device controller and to external
device pins. An external source can drive these external device pins to
access the Flash memory when the interface to Flash is available, (i.e.,
when the controller is not accessing Flash memory).
When the controller accesses Flash memory while configuring a PLD or
programming an enhanced configurat ion devic e, the process or must tristate the Flash interface pins to avoid contention. When the controller is
not accessing Flash memory, the interface pins tri-state and allow the
processor or PLD to access the Flash memory.
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Flash memory access is available after successful configuration of the
PLD, as indicated in Table 2, which lists the s ignals tha t ind icate when the
Flash memory is available.
Table 2.Enhanced Configuration Devices Interface Signals (Part 1 of 2)
nINIT_CONF/
nCONFIG
0 X X Not available PLD or enhanced configuration device
1 0 0 Not available PLD or enhanced configuration device
110 (DCLK active) Not available C onfiguration is in process when DCLK
Altera Corporation 15
OE/
nSTATUS
nCS/
CONF_DONE
External Flas h
Interface
PLD State
is in power-on reset (POR) mode , or
nCONFIG is asserted by external
source (PLD or processor), or priv at e
JTAG initiates configuration
instruction.
is in POR mode or has failed
configuration.
is toggling.
Enhanced Configuration Devices Data Sheet Preliminary Information
Table 2.Enhanced Configuration Devices Interface Signals (Part 2 of 2)
nINIT_CONF/
nCONFIG
110 (DCLK
1 1 1 Available PLD is configured.
OE/
nSTATUS
nCS/
CONF_DONE
inactive)
External Flash
Interface
Available Enhan ce d con fig urat ion device is
blank when CONF-DONE is low and
DCLK is not toggling.
When using an external source (processor or PLD) to access Flash
memory, the following considerations should be made:
■ User cannot force the enhanced configuration device’s controller to
relinquish Flash ac cess to the e xternal source (processor or PLD). The
external source (processor or PLD) must wait until configuration is
complete, or when CONF_DONE goes h i gh, befor e accessing the Fla sh
memory.
■ If the Auto_Restart configuration option is enabled and corrupted
programming data is in the Flash memory, enhanced configuration
devices will continuousl y try to co nfigur e the PLD. I n such ca ses, th e
external source (processor or PLD) cannot access the Flash memory
until a valid programming file is downloaded to the enhanced
configuration device.
■ The external source (processor or PLD) can cause the configuration
process to restart by releasing control of the interface and then
toggling nCONFIG.
Multiple Device Configuration in Serial Mode
PLD State
The enhanced configuration device supports parallel configuration of
multiple devices in serial configuration mode (see Figure7). The
enhanced configuration device can simultan eou sly output 1, 2, 4, or 8
parallel DATA outputs to multip le LUT-b a se d PLDs. The user selects the
configuration modes via the software.
16 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Figure 7. Concurrent Configuration of Multiple Devices in Serial Mode (Different Data with N = 8)
GND
GND
GND
MSEL1
MSEL0
MSEL1
MSEL0
MSEL1
MSEL0
PLD0
nSTATUS
CONF_DONE
nCONFIG
PLD1
DATA0
nSTATUS
CONF_DONE
nCONFIG
PLD7
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA0
nCE
DCLK
nCE
DCLK
nCE
V
(5)
GND
(5)
GND
V
CC
CC
(3)
(3)
Enhanced Configuration
V
CC
Device
TMI
WE#C
RP#C
DCLK
DATA0
DATA1
DATA[2..6]
OE
nCS
nINIT_CONF
DATA 7
(9)
PORSEL
(9)
PGM[2..0]
TMO
GND
(1)
VCCW
WE#F
RP#F
A[20..0]
RY/BY#
DQ[15..0]
(6)
EXCLK
CE#
OE#
WP#
(8)
V
CC
(4)
(7)
V
CC
External PLD
or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
Optional External
Clock Source
(2)
13
Tools
(5)
GND
Notes to Figure 7:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to controller unit. The only pins that need external connection
are WP#, WE#, and RP#, which are shown in Figure 13 on page 29. If Flash is being used as an external mem or y
source (in EPC16 conf iguratio n devices), t hen the Fla sh pins shou ld be connecte d. For more inf ormation, c onsult t he
LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
(2) For Flash interface in EPC4 and E P C8 c on fig u r at ion d evices, please contact Altera A p pli cat ions.
(3) The OE, nCS, and nINIT_CONF pins on enhanced configurat ion devices ha ve internal pull-up re sistors. The interna l
pull-up resistor on the nINIT_CONF pin is always active. However, on OE and nCS pins, the user has the option of
turning these resistors on or off through the software. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration
device option when generating programming files. If external pull-up resistors are used, they should be 1 kΩ (except
APEX 20KE devices r equi r e 10 kΩ).
(4) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
Altera Corporation 17
Enhanced Configuration Devices Data Sheet Preliminary Information
(5) nSTATUS should not have an external pull-up resistor for ACEX or FLEX devices. Instead, the programmable
internal resistor on OE should be used.
(6) nINIT_CONF has an in t ernal pull- up resistor wh ic h is always ac t iv e. If nINIT_CONF is not available or not used,
an external pull-up should not be used. When configuring an APEX 20KE device, an external pull-up should not be
used. For more information, refer to ApplicationNote 116 (Configuring SRAM-Based LUT Devices).
(7) The Flash interface exists only in E PC 16 c on fig u ra tion devices and is a tri-state interface. Th e sig na ls disp la ye d as
dotted lines should not be d r iv en when the F la sh interface is not availa ble. For Flash int erface avai lability, refer to
Table 2 on page 15.
(8) EXCLK is an input only. In the Quartus II software, the user can select t he EXCLK or the internal oscillator as the clock
source. For pin connections, refer to Table 7 on page 28.
(9) For pin connections, refer to Table 7 on page 28.
Table3 summarizes the passive serial configuration modes in the
enhanced configuration device.
Table 3. Enhanced Configuration Devices in Passive Serial Mode
Mode Name Mode
Used Outputs Unused Outputs
(1)
Passive serial mode 1 DATA0 DATA[7..1] drive out
Multi-device passive seria l
mode
Multi-device passive seria l
mode
Multi-device passive seria l
mode
Note to Table 3:
(1) The m o de category give s the num be r o f valid DATA outputs at each configuration
mode.
2 DATA[1..0] DATA[7..2] drive out
4 DATA[3..0] DATA[7..4] drive out
8 DATA[7..0] –
Figure8 shows parallel configuration of multiple devices in pa ssive serial
mode with the same DATA.
18 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Figure 8. Concurrent Configuration of Multiple Devices in Serial Mode (Same Data with N = 1)
GND
GND
GND
MSEL1
MSEL0
MSEL1
MSEL0
MSEL1
MSEL0
PLD0
nSTATUS
CONF_DONE
nCONFIG
PLD1
nSTATUS
CONF_DONE
nCONFIG
PLD7
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA0
nCE
DCLK
DATA0
nCE
DCLK
DATA0
nCE
V
V
CC
CC
(3)
(5)
GND
(5)
GND
(3)
EPC16 Configuration
V
CC
TMI
WE#C
RP#C
DCLK
DATA0
OE
nCS
nINIT_CONF
V
CC
WP#
PORSEL
PGM[2..0]
TMO
GND
Device
(9)
(9)
(1)
VCCW
WE#F
A[20..0]
RY/BY#
(6)
DQ[15..0]
EXCLK
RP#F
CE#
OE#
(8)
V
CC
(4)
PLD or Processor
(7)
Optional External
Clock Source
(2)
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
13
Tools
(5)
GND
Notes to Figure 8:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to controller unit. The only pins that need external connection
are WP#, WE#, and RP#, which are shown in Figure 13 on page 29. If Flash is being used as an external mem or y
source (in external EPC16 configuration devices), then the Flash pins should be connected. For more information,
consult the LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
(2) For Flash interface in EPC4 and E P C8 c on fig u r at ion d evices, please contact Altera A p pli cat ions.
(3) The OE, nCS, and nINIT_CONF pins on enhanced configurat ion devices ha ve internal pull-up re sistors. The interna l
pull-up resistor on the nINIT_CONF pin is always active. However, on OE and nCS pins, the user has the option of
turning these resistors on or off through the software. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration
device option when generating programming files. If external pull-up resistors are used, they should be 1 kΩ (except
APEX 20KE devices r equi r e 10 kΩ).
(4) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
Altera Corporation 19
Enhanced Configuration Devices Data Sheet Preliminary Information
)
(5) nSTATUS should not have an external pull-up resistor for ACEX or FLEX devices. Instead, the programmable
internal resistor on OE should be used.
(6) nINIT_CONF has an internal pull-up resistor that is always active. If nINIT_CONF is not available or not used,
nCONFIG must be pulled to V
an external pull-up should not be used. For more information, refer to Application Note 116 (Configuring SRAM-Based
either directly or through a 1-k Ω resistor. When configuring an APEX 20KE device,
CC
LUT Devi c es).
(7) The Flash interface exists only in E PC 16 c on fig u ra tion devices and is a tri-state interface. Th e sig na ls disp la ye d as
dotted lines should not be d r iv en when the F la sh interface is not availa ble. For Flash int erface avai lability, refer to
Table 2 on page 15.
(8) EXCLK is an input only. In the Quartus II software, the user can select t he EXCLK or the internal oscillator as the clock
source. For pin connections, refer to Table 7 on page 28.
(9) For pin connections, refer to Table 7 on page 28.
Fast Passive Parallel Configuration Mode
APEX II devices can be configured through enhanced configuration
devices in the FPP configuration mode. In this mode, the enhanced
configuration devi ce sen ds a byte of data to the DATA[7..0] pins, which
route to the DATA[7..0] input pins in the APEX II device. APEX II
devices receive byte-wide configuration data per each clock cycle.
Figure9 shows the enhanced configuration device FPP configura tion
mode.
Figure 9. FPP Configuration Mode
Enhanced Configuration
V
CC
TMI
WE#C
RP#C
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF
V
CC
WP#
PORSEL
PGM[2..0]
TMO
GND
Device
(8)
(1)
A[20..0]
RY/BY#
(5)
DQ[15..0]
(8)
EXCLK
VCCW
WE#F
RP#F
CE#
OE#
V
CC
(4)
(7)
(6)
Optional External
Clock Source
PLD or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
(2
GND
V
CC
APEX II Device
MSEL0
MSEL1
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
nCE
V
CC
(3) (3)
GND
V
CC
20 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Notes to Figure 9:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to the controller unit. The only pins that need external
connection are WP#, WE#, an d RP#, which are shown in Figure 13 on page 29. If Flash is being used as an external
memory source (in EPC16 configuration devices), then the Flash pins should be connected. For more information,
consult the LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
(2) For Flash interface in EPC4 and E P C8 c on fig u r at ion d evices, please contact Altera A p pli cat ions.
(3) The OE, nCS, and nINIT_CONF pins on enhanced configurat ion devices ha ve internal pull-up re sistors. The interna l
pull-up resistor on the nINIT_CONF pin is always active. However, on OE and nCS pins, the user has the option of
turning these resistors on or off through the software. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration
device option when generating pro gram min g files. If external pull-up resistors are used , they should be 1 kΩ.
(4) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
(5) nINIT_CONF has an internal pull-up resistor that is always active. If nINIT_CONF is not available or not used,
nCONFIG must be pulled to V
Application Note 116 (Configuring SRAM-Based LUT Devices).
(6) The Flash interface exists only in EPC16 configuration devices and is a tri -state in ter face. The signals displayed as
dotted lines should not be driven when the Flash interface is not available. For Flash interface availability, refer to
Table 2 on page 15.
(7) EXCLK is an input only. In the Quartus II software, the user can select EXCLK or internal osci lla to r as the c lock
source. For pin connections, refer to Table 7 on page 28.
(8) For pin connecti o ns , refe r t o Table 7 on page 28.
either directly or throu gh a 1-kΩ resistor. For more information, refer to
CC
Figure 10 shows a diagram of multi ple AP EX II device configur ation wit h
an enhanced configur ation d e vice in pa ralle l prog ramming mode. In this
mode, multiple APEX II devices are cascaded together. After the first
APEX II device complet es configuration , its nCEO pin activates the second
APEX II device’s nCE pin. This pin activation prompts the second device
to start configuration. (See Figure 10.)
13
Tools
Because CONF_DONE pins are tied together, all devices initialize and
simultaneously enter user mode. If the enhanced configuration device
detects an error, the configuration stops for the whole chain because
nSTATUS pins are tied together.
Altera Corporation 21
Enhanced Configuration Devices Data Sheet Preliminary Information
Figure 10. FPP Configuration of Multiple Devices in a Chain
Enhanced
Configuration
GND
V
CC
MSEL0
MSEL1
APEX II Device N
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
V
CC
nCEO
MSEL0
MSEL1
APEX II Device 1
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
VCCV
(3) (3)
V
CC
V
CC
Device
TMI
WE#C
RP#C
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF
WP#
PORSEL
(8)
PGM[2..0]
TMO
CC
GND
(1)
VCCW
A[20..0]
RY/BY#
(5)
DQ[15..0]
(8)
EXCLK
WE#F
RP#F
CE#
OE#
V
CC
(4)
(7)
Notes to Figure 10:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to the controller unit. The only pins that need external
connection are WP#, WE#, and RP#, whi ch are shown in Figure 13 on page 29. If Flash is being used as an external
memory source (in EPC16 configuration devices), then the Flash pins should be connected. For more information,
consult the LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
(2) For Flash in t erface in EPC 4 a n d EPC8 configuration devices, plea se contact Alt era Applications.
(3) The OE, nCS, and nINIT_CONF pins on enh anced config urat ion dev ices h ave in ternal pull -up res isto rs. The inter nal
pull-up resistor on the nINIT_CONF pin is always active. However, on OE and nCS pins, the user has the option of
turning these resistors on or off through the software. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE p ull-up s on config urat ion
device option when generating programming files. If external pull-up resistors are used, they should be 1 kΩ (except
APEX 20KE devices require 10 kΩ).
(4) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
(5) nINIT_CONF has an internal pull-up resistor that is always active. If nINIT_CONF is not available or not used,
nCONFIG must be pulled to V
Application Note 116 (Configuring SRAM-Based LUT Devices).
either directly or through a 1-kΩ resistor. For more information, refer to
CC
(6) The Flash interface exists only in E PC 16 c on fig u ra tion devices and is a tri-state interface. Th e sig na ls disp la ye d as
dotted lines should not be d r iv en when the F la sh interface is not availa ble. For Flash int erface avai lability, refer to
Table 2 on page 15.
(7) EXCLK is an input on ly. In the Quar tu s II software, t he us er can select EXCLK or internal oscillator as the cloc k
source. For pin connections, refer to Table 7 on page 28.
(8) For pin connections, refer to Table 7 on page 28.
(6)
Optional External
Clock Source
External PLD
or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
(2)
Serial Configuration of Multiple Devices in a Chain
Because enhanced configuration devices contain a significant amount of
Flash memory, the user does not need to cascade multiple enhanced
configuration devices to configure large devices.
22 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
2)
G
An enhanced con fig ur ati o n de vice ca n configure a chain of PLDs tha t a re
cascaded together. Figure 11 shows the enhanced configuration device
configuring a chain of multiple PLDs in serial mode.
Figure 11. Serial Configuration of Multiple Devices in a Chain
Enhanced
ND
MSEL0
MSEL1
PLDN
DCLK
DATA0
(5)
nSTATUS
CONF_DONE
nCONFIG
nCE
PLD0
DCLK
DATA0
(5)
nSTATUS
CONF_DONE
nCONFIG
nCEO
MSEL0
MSEL1
GND GND
nCE
VCCV
(3) (3)
Configuration
V
CC
V
CC
Device (1)
TMI
WE#C
RP#C
DCLK
DATA0
OE
nCS
nINIT_CONF
WP#
PORSEL (9)
PGM[2..0] (9)
TMO
CC
VCCW
WE#F
RP#F
A[20..0] (4)
RY/BY#
CE#
(6)
OE#
DQ[15..0]
EXCLK (8)
V
CC
(7)
Optional External
Clock Source
External PLD
or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
(
13
GND
Tools
Notes to Figure 11:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to controller unit. The only pins that need external connection
are WP#, WE#, and RP#, which are shown in Figure 13 on page 29. If Flash is being used as an external memor y
source (in external EPC16 configuration devices), then the Flash pins should be connected. For more information,
consult the LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
(2) For Flash interface in EPC4 and E P C8 c on fig u r at ion d evices, please contact Altera A p pli cat ions.
(3) The OE, nCS, and nINIT_CONF pins on enhanced configurat ion devices ha ve internal pull-up re sistors. The interna l
pull-up resistor on the nINIT_CONF pin is always active. However, on OE and nCS pins, the user has the option of
turning these resistors on or off through the software. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration
device option when generating pro gram min g files. If external pull-up resistors are used , they should be 1 kΩ.
(4) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should
be left floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
(5) nSTATUS should not have an external pull-up resistor for ACEX or FLEX devices. Instead, the programmable
internal resistor on OE should be used.
(6) nINIT_CONF has an internal pull-up resistor that is always active. If nINIT_CONF is not available or not used,
nCONFIG must be pulled to V
an external pull-up sh ould not be us ed. For more in formation, ref er to Application Note 116 (Configuring SRAM-Based
LUT Devices).
either directly or through a 1-kΩ resistor. When configuring an APEX 20KE device,
CC
(7) The Flash interface exists only in EPC16 configuration devices and is a tri -state in ter face. The signals displayed as
dotted lines should not be driven when the Flash interface is not available. For Flash interface availability, refer to
Table 2 on page 15.
(8) EXCLK is an input only. In the Quartus II software, the user can select the EXCLK or the int ern al os cil lat or as th e clo ck
source.For pin connections, refer to Table 7 on page 28.
(9) For pin connections, refer to Table 7 on page 28.
Altera Corporation 23
Enhanced Configuration Devices Data Sheet Preliminary Information
Figure 12 shows the timing waveform for the enhanced configuration
device scheme.
Figure 12. Enhanced Configuration Device Scheme Timing Waveform Note (1)
nINIT_CONF or
VCC/nCONFIG
OE/nSTATUS
t
LOE
nCS/CONF_DONE
DCLK
DATA
User I/O
INIT_DONE
Driven High
t
t
OE
CE
bit/byte
Tri-State
bit/byte
1
t
t
LC
HC
bit/byte
2
n
Tri-State
User Mode
(2)
(3)
Notes to Figure 12:
(1) For timing information, refer to the Table 4 on page 25.
(2) The configuration device will drive
DATA low after configur a t ion.
(3) APEX II and APEX 20K devices enter user mode 40 clock cycles after CONF_DONE goes high. Mercury devices enter
user mode 136 clock cycles after CONF_DONE goes high. ACEX 1K, FLEX 10K, and FLE X 6000 devices enter user
mode 10 clock cycles after CONF_DONE goes high.
24 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Table 4 defines the enhanced configuration device timing parameters
when using enhanced configuration devices at 3.3 V.
Table 4.Enhanced Configuration Device Configuration Parameters (PLD Interface)
Symbol Parameter Condition Min Typ Max Unit
f
DCLK
t
DCLK
t
HC
t
LC
t
CE
t
OE
t
OH
DCLK frequency 40% duty cycle 66.7 MHz
DCLK period 15 ns
DCLK duty cycle high time 40% duty cycle 6 ns
DCLK duty cycle low time 40% duty cycle 6 ns
OE to first DCLK delay 40 µs
OE to first DATA available 40 µs
DCLK rising edge to DATA
(1) (3)
(3)
change
(2) OE assert to DCLK disable
t
CF
277 ns
delay
(2) OE assert to DATA disable
t
DF
277 ns
delay
(3) DCLK rising edge to OE 60 ns
t
RE
t
LOE
OE assert time to assure
60 ns
reset
f
ECLK
t
ECLK
t
ECLKH
EXCLK input frequency 40% duty cycle 133 MHz
EXCLK input period 7.5 ns
EXCLK input duty cycle high
40% duty cycle 3.375 ns
time
t
ECLKL
EXCLK input duty cycle low
40% duty cycle 3.375 ns
time
t
ECLKR
t
ECLKF
(4) POR t ime 2 ms 1 2 3 ms
t
POR
EXCLK input rise time 133 MHz 3 ns
EXCLK input fall time 133 MHz 3 ns
100 ms 50 100 120 ms
ns
13
Tools
Notes to Table 4:
(1) To calculate tOH, use the following eq u at ion : tOH = 0.5(DCLK period) - 2.5 ns.
(2) This parameter is used in cyclic redundancy check (CRC) error detection by CPLD.
(3) This parameter is used for CONF_DONE error detection by the enhanced configuration device.
(4) The VCC ramp time should be less tha n 1 m s for 2-ms P OR, an d it shou ld b e les s than 100 ms for 100-ms POR.
Altera Corporation 25
Enhanced Configuration Devices Data Sheet Preliminary Information
Power Sequencing
Altera recommends that you power-up the PLD before the enhanced
configuration device’s POR expires. The pin-selectable POR time feature
is useful for ensuring this power-up sequence. The enhanced
configuration device has two POR settings, 2 ms and 100 ms. For more
margin, the 100-ms setting can be selected to allow the PLD to power-up
before configuration is attempted.
Enhanced Configurat ion Dev ice P in- Out s
Tables5 through 7 describe pin definit ions for the enh anced configur ation
device. These tables include PLD interface pins, Flash interface pins, JTAG
interface pins, and other pins.
Table 5. PLD Interface Pins with Respect to Controller
Pin Name Pin Type Description
DATA[7..0] Output This is the PLD configurati on out put dat a bus . DATA changes on
each rising edge of DCLK.
DCLK Output The DCLK pin is always an output. The enhanced configuration
device drives the DCLK signal to the PL D as th e con fig urat ion
clock.
nCS Input The nCS pin is an input to the enhanced configuration devic e and
is used to input the PLD’s CONF_DONE signal for error detection
after the last configuration data is transmitted to the PLD. The PLD
will always drive nCS low when OE is asserted. This pin contains a
programmable internal weak pull-up.
nINIT_CONF Output The nINIT_CONF pin can be connected to the nCONFIG pin on
LUT-based PLDs to initiat e c onf iguration for the enhanced
configuration device v ia a priv at e JTAG instruction. This pin
contains a programmable internal weak pull-up.
OE Open-Drain I/O This pin is driven low when POR is not complete. A user-selectable
2-ms or 100-ms counter holds off the release of OE during initial
power up to permit voltage leve ls to stabilize. POR time can be
extended externall y by driv ing OE low . After t he enhanced
configuration device c ont roller releases OE, it waits for OE to go
high before starting the PLD co nfi gurat ion process. This pin
contains a programmable internal weak pull-up.
26 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Table 6. Flash Interface Pins Note (1)
Pin Name Pin Type Description
A[20:0] (2) Input These pins are the address input to the Flash memory for read and
write operations. The addresses are internally latched during a write
cycle.
DQ[15:0] Input/Output These pins are a Data bus that interface with the Flash memory and
the controller. The controller or an external source drives DQ[15:0]
during the Flash command and the data write bus cycles. During the
data read cycle, Flash memory driv es the DQ[15:0] to the
controller.
(3) Input When asserted, it activates th e Fla sh memory . Wh en it is high, it
CE#
deselects the device and reduc es pow er c ons um pt ion to standby
levels.
(3), (4) Input When asserted, it resets the Flas h me m ory . W hen high, it enables
RP#
normal operation. When low, it inhibits write operation in the Flash
memory, which provides da ta pro te ction during power transitions.
(3) Input The controller asserts this pin during Flash read cycles. When
OE#
asserted, it enables the driver s of Fla sh ou tpu t pin s.
(3), (5) Input The controller asserts WE# during Flash write cycle. When asserted,
WE#
it controls writes to the Flash memory. In the Flash memory,
addresses and data are latched on the rising edge of the WE# pulse.
(3), (5) Input This pin is usually tied to VCC or ground on the board. The controller
WP#
does not drive this pin because it could c aus e c ont ent ion.
VCCW Supply Bloc k eras e, full chip erase, word write, or lock bit configur atio n
power supply.
RY/BY#
Notes to Table 6:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
(2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices are
(3) The # symbol means active low. RP#F and WE#F are pins o n t he Fl as h die. RP#C and WE#C are pins on the cont rolle r
(4) These pins can be driven to 12 V during Flash testing. Because the controller cannot tolerate the 12-V level,
(5) WP# should be connected to VCC on the board when using the Quartus II softwar e ver sions 1.0 and 1.1.
(3) Output Flash asserts this pin when a write or erase operation is complete.
This is a Flash only pin.
unconnected because they are internally connected to controller unit. The only pins that need external connection
are WP#, WE#, and RP#, which are shown in Figure 13 on page 29. If Flash is being used as an external memor y
source (in EPC16 conf iguratio n devices), t hen the Fla sh pins shou ld be connecte d. For more inf ormation, c onsult t he
LHF16J06 Data Sheet on the Altera web site (http://www.altera.com).
floating. These pins should not be connected to any signal, i.e., they are no-connect pins.
die. WE#C and WE#F should be connected together on the PCB. RP#F and RP#C should also be connected together
on the PCB.
connection on these pins from the controller to the Flash will not be bonded internally in the package and they will
be available as two separate pins. The user is required to connect the two pins at the board level (for example, on
the PCB, connect the WE# pin from controller to WE# pin from the Flash memory, as sho wn in Fi gure13 on page 29).
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Altera Corporation 27
Enhanced Configuration Devices Data Sheet Preliminary Information
Table 7.JTAG Interface Pins and Other Pins with Respect to Controller
Pin Name Pin Type Descripti on
TDI Input This is a JTAG data input pin. Connect this pin to VCC if the
JTAG circuitry is not used.
TDO Output This is a JTAG data outp ut pin. Do not co nnec t this pin if the
JTAG circuitry is not used.
TCK Input This is a JTAG clock pin. Connect this pin to ground if the JTAG
circui try is not u sed.
TMS Input This is a JTAG mode select pin. Connect this pin to VCC if the
JTAG circuitry is not used.
PGM[2..0] Input These th ree input pins select one of the eight pages of the
configuration files to configure the PLD. Connect these pins on
the board to select the page spec ifie d by the des igner in the
Quartus II software when generating the enhanced
configuration device POF file. PGM [ 2] is the MS B.
EXCLK Input During Normal mode, the EXCLK pin operat es as the ex te rnal
clock source.
PORSEL Input This pin selects a 2-m s or 100 -m s PO R counter delay during
power up. When PORSEL is Low, POR time is 100 ms. When
PORSEL is High, POR time is 2 ms.
TMO Input Test mode pin selects different test modes. In operating mode,
this pin should be connected to GND
TMI Input Test mode pin selects different test modes. In operating mode,
this pin should be connected to VCC
Package
The EPC16 configuration device is available in both the 88-pin Ultra
FineLine BGA package and the 100-pin PQFP package. The Ultra
FineLine BGA package, wh ich is based on 0.8-mm pit ch, maximi zes board
space efficiency. A board can be laid out for this package using only one
PCB layer. The EPC8 and EPC4 devices are available in the 100-pin PQFP
package.
Figure 13 shows the PCB ro uting for the 88-p in Ultra FineLine BGA
package. The Gerber file for this layout is on the Altera web site at
http://www.altera.com.
28 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Figure 13. PCB Routing for 88-Pin Ultra FineLine BGA Package Notes (1), (4)
DQ14
DQ4
VCC
DQ2
DQ0
DCLK
DQ5
VCC
DQ3
DQ1
DATA7 NC
DATA6DATA5DQ7
DATA4
DATA3
DATA2
DATA1
DATA0GNDVCCA1A2A3
NCGNDTM0OE#GNDCE#
NC
OE
VCC
NC
VCC
WE# C
(2)
TCK
TDI
TDO
TMS
nCS
GND
A20
A16
WE# F
(2)
GND
WP#
(3)
NC
A18
EXCLK
A11
A8
RY/BY#
RP# F
(2)
VCCW
NC
A17
A5
A15
A10
nINIT
CONF
TM1
A19
PGM2
A7
A4
A14
A9
PGM1
VCC
DQ11
PORSEL
A6
A0
A13
DQ15
PGM0
DQ13
DQ12
RP# C
VCC DQ10
DQ9
A12 GND
DQ6
(2)
DQ8
Notes to Figure 13:
(1) If the direct Flash interface is not used in an enhanced configuration device, then the Flash pins should be left
unconnected because they are internally connected to controller unit. The only pins that need external connection
are WP#, WE#, and RP#. If Flash is being used as an external memory source (in EPC16 configuration devices), then
the Flash pins should be connected. For more information, consult the LHF16J06 Data Sheet on the Altera web site
(http://www.altera.com).
(2) RP#F and WE#F are pins on the Flash die. RP#C and WE#C are pins on the control le r die. WE#C an d WE#F should be
connected together on the PCB. RP#F and RP#C should also be connected together on the PCB.
(3) WP# should be connected to 3.3 V to be able to program the bottom boot block, which is required when
programming the device from the Quartus II software.
(4) For pin connections, refer to the Altera web site at http://www.altera.com.
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Altera Corporation 29
Enhanced Configuration Devices Data Sheet Preliminary Information
0
m
1.0 2.0
mm
Package Layout Recomm endation
Enhanced configu ratio n de vices in 100-pin PQF P pack ages h ave d iffere nt
package dime nsion th an other 100-pi n PQFP de vices. Figure14 shows the
100-pin PQFP PCB footprint specifications for enhanced configuration
devices. These footprint dimensions are based on vendor-supplied
package outline diagrams.
Figure 14. Enhanced Configuration Device PCB Footprint Specifications for 100-Pin PQFP Packages
Notes (1), (2), (3)
0.65-mm pad pitch
.325 mm
19.3 m
25.3 mm
2.4 mm
0.5 1.5
0.410 mm
30 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Notes to Figure 14:
(1) Used 0.5-mm increase for front and back of nominal foot length
(2) Used 0.3-mm increase to maximum foot width.
(3) Diagram s a r e based on ven d o r - s upplied drawings.
ISP Programming & Configuration File Support
The Quartus II developme nt software pr ovides programming su pport for
the enhanced configuration device and automatically generates the
programming files for the EPC4, EPC8, and EPC16 configuration devices.
In a multi-device project, the software can combine the programming files
for multiple APEX II, APEX 20K, Mercury, ACEX, or FLEX 10K devices
into one EPC4, EPC8, or EPC16 confi gu ration device.
Enhanced configuration devices can be programmed in-system through
its industry-standard 4-pin JTAG interface. ISP in the enhanced
configuration devic e provid es ease in prot otyping a nd updat ing APEX I I,
APEX 20K, Mercury, ACEX, or FLEX device functionality. Enhanced
configuration devices can also be programmed by third-party Flash
programmers.
After programming an enhanced configura tion device in-syst em, LUTbased PLD configuration can be initiated by including the enhanced
configuration device’s JTAG INIT_CONF instruction. See Table8.
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Altera Corporation 31
Enhanced Configuration Devices Data Sheet Preliminary Information
The ISP circuitry in the enhanced configuration device is compliant with
the IEEE Std. 1532 specifi catio n. The IEEE Std. 1532 is a standard th at
allows con c urrent ISP b e tween devic e s from multi ple vendors.
Table 8.Enhanced Configuration Device JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows a snapshot of the state of the enhanced configuration device pins to
be captured and examin ed during normal device operation and permits an
initial data pattern output at the dev ic e pins .
EXTEST Allows the external circuitry and board-level interconnections to be tested by
forcing a test pattern at the outp ut pins and ca ptu ring res ult s at the input
pins.
BYPASS Places the 1-bit bypass register between t he TDI and the TDO pins, which
allow the BST data to pass synchronously through a selected device to
adjacent devices during normal device operation.
IDCODE
USERCODE Selects the USERCOD E regis t er and places it between TDI and TDO,
INIT_CONF This function initiates the PLD re-configuration process by tying
PENDCFG This functio n a sserts nINIT_CONF before accessing th e Fla sh mem ory , if
(1) Selects the device IDCOD E register and places it between TDI and TDO,
allowing the device IDCOD E t o be se rially sh ifted out to TDO. The device
IDCODE for the enhanced configuration device is shown below:
0100A0DDh
allowing the USERCOD E to be ser ially shi ft ed out th e TDO. The 32-bit
USERCODE is a programmable user-defined pattern.
nINIT_CONF to the PLD(s) nCONFIG pin(s). After this instruction is
updated, the nINIT_CONF is released and starts the PLD co nf iguration.
the external PLD/proc es so r is connec t ed t o the Flash. This avoids a Flash
bus contention when bot h JTAG/ISP and external PLD/proc es s or w ant to
access the Flash. Before JTAG/ISP can access the Flash, the external
PLD/processor needs to be reset by asserting nINIT_CONF, which puts the
external PLD/proces s or in a “res et ” state and w ait s for the de-as s ert ion of
the INIT_CONF.
Note to Table 8:
(1) For enhanced configuration devices, instruction register length is 10 and boundary scan length is 174.
32 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Tes ting
The enhanced configuration device provides JTAG BST circuitry that
complies with the IEEE Std. 1149.1- 19 90 specification. JTAG boundaryscan testing can be performed before or after configuration, b ut not during
configuration. Table 9 shows the timing parameters and values for the
enhanced configuration device.
Table 9. JTAG Timing Parameters & Values
Symbol Parameter Min Max Unit
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
TCK clock period 100 ns
TCK clock high time 50 ns
TCK clock low time 50 ns
JTAG port setup time 20 ns
JTAG po rt hold t ime 45 ns
JTAG port clock output 25 ns
JTAG port high impedance to
valid output
JTAG port valid output to
high impedance
Capture register setup time 20 ns
Capture register hold time 45 ns
Update register clock to
output
Update register high-
impedance to valid output
Update register valid outpu t
to high impedance
25 ns
25 ns
25 ns
25 ns
25 ns
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Altera Corporation 33
Enhanced Configuration Devices Data Sheet Preliminary Information
Operating Conditions
Tables 10 through 15 provide inform a tion on a bs olut e maximum ratin gs,
recommended operating conditions, DC operating conditions, supply
current values, capacitance, and configuration parameters for the
enhanced configuration device.
Table 10.Enhanced Configuration Device Absolute Maximum Rating
Symbol Parameter Condition Min Max Unit
V
V
I
I
P
T
T
T
CC
I
MAX
OUT
D
STG
AMB
J
Supply voltage With respect to
–0.5 4.6 V
ground
DC input voltage With respect to
–0.5 3.6 V
ground
DC VCC or ground current 100 mA
DC output current, per pin –25 25 mA
Power dissipation 360 mW
Storage temperature No bias –65 150 ° C
Ambient temperature Under bias –65 135 ° C
Junction temperature Under bias 135 ° C
Table 11.Enhanced Configuration Device Recommended Operating Conditions
Symbol Parameter Condition Min Max Unit
V
CC
V
I
V
O
T
A
T
R
T
F
Supplies voltage for 3.3-V
3.0 3.6 V
operation
Input voltage With respect to
–0.3 VCC + 0.3 V
ground
Output voltage 0 V
Operating temperature For commercial
070° C
CC
use
For industrial use –40 85 ° C
Input rise time 20 ns
Input fall time 20 ns
V
34 Altera Corporation
Preliminary Informa tion Enhanced Configurati on D evices Data Sheet
Table 12. Enhanced Configuration Device DC Operating Conditions
Symbol Parameter Condition Min Typ Max Unit
V
CC
V
IH
V
IL
V
OH
Supplies voltage to core 3.0 3.3 3.6 V
High-level input voltage 2.0 VCC + 0.3 V
Low-level input voltage 0.8 V
3.3-V mode high-level TTL
I
= –4 mA 2.4 V
OH
output voltage
3.3-V mode high-level CMOS
= –0.1 mA V
I
OH
– 0.2 V
CC
output voltage
V
OL
Low-level output voltage TTL I
Low-level output voltag e
= –4 mA DC 0.45 V
OL
= –0.1 mA DC 0.2 V
I
OL
CMOS
I
I
I
OZ
R
CONF
Input leakage current V
Tri-state output off-state
current
Configuration pins Internal pull up
= V
or ground –10 10 µA
I
CC
V
= V
or
O
CC
–10 10 µA
ground
6kΩ
(OE, nCS, nINIT,
CONF)
Table 13. Enhanced Configuration Device ICC Supply Current Values
Symbol Parameter Condition Min Typ Max Unit
I
I
CC0
CC1
VCC supply current
(standby)
VCC supply current (during
configuration)
50 100 µA
50 100 mA
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Table 14.Enhanced Configuration Device Capacitance
Symbol Parameter Condition Min Max Unit
C
IN
C
OUT
Altera Corporation 35
Input pin capacitance 10 pF
Output pin capacitance 10 pF
e
s
a
ir
g
Enhanced Configurati on D evi ces D ata Sh eet Preliminar y Info r mati on
Table 15.Enhanced Configuration Device Configuration Parameters (Flash Interface)
Symbol Parameter Condition Min Typ Max Unit
f
SCLK
t
SCLK
t
SCLKH
t
SCLKL
t
AVQV(F)
t
GLQV(F)
t
WLWH(F)
t
WHR0(F)
Device
Pin-Outs
SYSCLK frequency – 10 MHz
SYSCLK period 100 – ns
SYSCLK duty cycle high time 50 ns
SYSCLK duty cycle low time 50 ns
Flash address to data
–85ns
DQ[15:0] delay
Flash OE# to data DQ[15:0]
–40ns
delay
Flash WE# pulse width 50 – ns
Flash WE# high to SR7 ready – 100 ns
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
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stylized Altera logo, specific device designations, and all other words and logos that are identified a
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or use of any inf ormation, product, or servi c e described herein except as exp ressly agree d
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36 Altera Corporation
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