101 Innovation Drive
San Jose, CA 95134
www.altera.com
RLDRAM II Controller
MegaCore Function User Guide
MegaCore Version: 9.1
Document Date: November 2009
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
UG-RLDRAM-8.1
ii MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide
Contents
Chapter 1. About This MegaCore Function
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–1
Features ................................................................................................................................................... 1–2
General Description ............................................................................................................................... 1–2
OpenCore Plus Evaluation .............................................................................................................. 1–4
Performance and Resource Utilization ............................................................................................... 1–4
Chapter 2. Functional Description
Block Description ................................................................................................................................... 2–1
Control Logic .................................................................................................................................... 2–2
Datapath ............................................................................................................................................ 2–3
OpenCore Plus Time-Out Behavior ............................................................................................. 2–12
Device-Level Configuration ............................................................................................................... 2–12
PLL Configuration ......................................................................................................................... 2–12
Example Design .............................................................................................................................. 2–14
Constraints ...................................................................................................................................... 2–16
Interfaces ............................................................................................................................................... 2–16
Initialization .................................................................................................................................... 2–16
Writes ............................................................................................................................................... 2–17
Reads ................................................................................................................................................ 2–19
Refreshes .......................................................................................................................................... 2–21
Signals ................................................................................................................................................... 2–22
Parameters ............................................................................................................................................ 2–28
Memory ............................................................................................................................................ 2–29
Timing .............................................................................................................................................. 2–31
Project Settings ................................................................................................................................ 2–32
MegaCore Verification ........................................................................................................................ 2–33
Simulation Environment ............................................................................................................... 2–33
Hardware Testing ........................................................................................................................... 2–33
Chapter 3. Getting Started
Design Flow ............................................................................................................................................ 3–1
RLDRAM II Controller Walkthrough ................................................................................................. 3–2
Create a New Quartus II Project .................................................................................................... 3–3
Launch IP Toolbench ....................................................................................................................... 3–4
Step 1: Parameterize ......................................................................................................................... 3–5
Step 2: Constraints ............................................................................................................................ 3–7
Step 3: Set Up Simulation ................................................................................................................ 3–8
Step 4: Generate ................................................................................................................................ 3–8
Simulate the Example Design ............................................................................................................ 3–11
Altera Corporation MegaCore Version 9.1 iii
Contents
Simulate with IP Functional Simulation Models ....................................................................... 3–11
Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 3–12
Edit the PLL .......................................................................................................................................... 3–13
Compile the Example Design ............................................................................................................ 3–14
Program a Device ................................................................................................................................ 3–15
Implement Your Design ..................................................................................................................... 3–15
Set Up Licensing .................................................................................................................................. 3–15
Additional Information
Revision History ......................................................................................................................................... i
How to Contact Altera ............................................................................................................................... i
Typographic Conventions ....................................................................................................................... ii
iv MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide
1. About This MegaCore Function
Release Information
f For more information about this release, refer to the MegaCore IP Library
Device Family Support
Table 1–1 provides information about this release of the Altera®
RLDRAM II Controller MegaCore® function.
Table 1–1. Release Information
Item Description
Ver si on 9. 1
Release Date November 2009
Ordering Code IP-RLDRAMII
Product ID 00AC
Vendor ID 6AF7
Release Notes and Errata.
Altera verifies that the current version of the Quartus® II software
compiles the previous version of each MegaCore function. The MegaCore
IP Library Release Notes and Errata report any exceptions to this
verification. Altera does not verify compilation with MegaCore function
versions older than one release.
MegaCore functions provide either full or preliminary support for target
Altera device families:
■ Full support means the MegaCore function meets all functional and
timing requirements for the device family and may be used in
production designs
■ Preliminary support means the MegaCore function meets all
functional requirements, but may still be undergoing timing analysis
for the device family; it may be used in production designs with
caution.
Altera Corporation MegaCore Version 9.1 1–1
November 2009
Features
Table 1–2 shows the level of support offered by the RLDRAM II
Controller MegaCore function to each Altera device family.
Table 1–2. Device Family Support
Device Family Support
®
HardCopy
Stratix
Stratix
Other device families No support
II
®
II
II GX Full
Preliminary
Full
Features
General Description
■ Common I/O (CIO) and separate I/O (SIO) device support
■ Memory burst length 2, 4, and 8-beat support
■ Nonmultiplexed addressing
■ Datapath generation
■ Data strobe signal (DQS) and non-DQS capture modes
■ Automatic constraint generation
■ Easy-to-use IP Toolbench interface
■ IP functional simulation models for use in Altera-supported VHDL
and Verilog HDL simulators
■ Support for OpenCore Plus evaluation
The RLDRAM II controller MegaCore function handles the complex
aspects of using RLDRAM II—initializing the memory devices and
translating read and write requests from the local interface into all the
necessary RLDRAM II command signals.
The RLDRAM II controller is optimized for Altera Stratix II devices and
has preliminary support for Stratix II GX and HardCopy II devices. The
advanced features available in these devices allow you to interface
directly to RLDRAM II devices.
Figure 1–1 on page 1–3 shows a system-level diagram including the
example design that the RLDRAM II Controller MegaCore function
creates for you.
1–2 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Figure 1–1. RLDRAM II Controller System-Level Diagram
Example Design
Local
Pass
or Fail
Example
Driver
Interface
Control Logic
(Encrypted)
About This MegaCore Function
Clock
Note to Figure 1–1:
(1) Non-DQS mode only.
System
PLL
DLL
Fedback
Clock
PLL (
1
Datapath
(Clear Text)
)
RLDRAM II Controller
RLDRAM II
Interface
RLDRAM II
IP Toolbench generates the following items:
■ A testbench, which instantiates the example design
■ A synthesizable example design which instantiates the following
modules:
● RLDRAM II controller:
• Encrypted control logic, which takes transaction requests
from the local interface and issues writes, reads, and
refreshes to the memory interface
• A clear-text datapath
● Example driver—generates write, read and refresh requests and
outputs a pass_fail signal to indicate that the tests are
passing or failing
● System phase-locked loop (PLL)—generates the RLDRAM II
controller clocks
● Delay locked loop (DLL)—instantiated in DQS mode and
generates the DQS delay control signal for the dedicated DQS
delay circuitry
Altera Corporation MegaCore Version 9.1 1–3
November 2009 RLDRAM II Controller MegaCore Function User Guide
Performance and Resource Utilization
● Optional fedback clock PLL—instantiated in non-DQS mode and
OpenCore Plus Evaluation
With Altera’s free OpenCore Plus evaluation feature, you can perform
the following actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function
or AMPPSM megafunction) within your system
■ Verify the functionality of your design, as well as evaluate its size
and speed quickly and easily
■ Generate time-limited device programming files for designs that
include MegaCore functions
■ Program a device and verify your design in hardware
You only need to obtain a license for the megafunction when you are
completely satisfied with its functionality and performance, and want to
take your design to production.
f For more information on OpenCore Plus hardware evaluation using the
RLDRAM II controller, refer to “OpenCore Plus Time-Out Behavior” on
page 2–12 and AN 320: OpenCore Plus Evaluation of Megafunctions.
generates a capture clock for the datapath read capture and logic
path
Performance
Table 1–3 shows typical expected performance for the RLDRAM II
Controller MegaCore function, with the Quartus II software.
and Resource
Utilization
1–4 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Table 1–3. Performance
Device Capture Mode
Stratix II
(EP2S60F1020C3)
Stratix II GX
(EP2SGX30CF780C3)
f
(MHz)
MAX
Non-DQS 200
DQS 300
Non-DQS 200
DQS 300
About This MegaCore Function
Stratix II and Stratix II GX devices support RLDRAM at up to 300 MHz.
Table 1–4 shows the clock frequency support for Stratix II and Stratix GX
device families, with the Quartus II software.
Table 1–4. RLDRAM II Maximum Clock Frequency Support in Stratix II &
Stratix GX Devices
Speed Grade Frequency (MHz)
–3 300
–4 250
–5 200
Table 1–5 shows typical sizes in combinational adaptive look-up tables
(ALUTs) and logic registers for the RLDRAM II controller.
Table 1–5. Typical Size Note (1)
Device Memory Width (Bits)
Stratix II and
Stratix II GX
Notes to Ta b l e 1– 5 :
(1) These sizes are a guide only and vary with different choices of parameters.
9 127 169
18 130 209
36 151 287
72 185 444
Combinational
ALUTs
Logic
Registers
Altera Corporation MegaCore Version 9.1 1–5
November 2009 RLDRAM II Controller MegaCore Function User Guide
Performance and Resource Utilization
1–6 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
2. Functional Description
Control Logic
(Encrypted)
RLDRAM II Controller
clk
write_clk
addr_cmd_clk
non_dqs_
capture_clk (
Note 3
)
reset_clk_n
reset_addr_cmd_clk_n
reset_read_clk_n[]
capture_clk[] (
Note 4)
dqs_delay_ctrl[] (
Note 4)
local_addr[]
local_bank_addr[]
local_dm[]
local_read_req
local_refresh_req
local_wdata[]
local_write_req
local_init_done
local_rdata[]
local_rdata_valid[]
local_wdata_req
Datapath
rldramii_dq[]
rldramii_q[]
rldramii_qk[]
rldramii_qvld[]
rldramii_a_0[]
rldramii_ba_0[]
rldramii_clk[]
rldramii_clk_n[]
rldramii_cs_n_0
rldramii_d[]
rldramii_dm[]
rldramii_ref_n_0
rldramii_we_n_0
Block Description
Figure 2–1. RLDRAM II Controller Block Diagram Note (1) , (2)
Notes to Figure 2–1:
(1) You can edit the rldramii_ prefix in IP Toolbench.
(2) The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and
(3) Non-DQS mode only.
(4) DQS mode only.
Altera Corporation MegaCore Version 9.1 2–1
November 2009
<signal>_1 are present.
Figure 2–1 shows the RLDRAM II Controller MegaCore function block
diagram.
Block Description
The RLDRAM II controller comprises the following two blocks:
■ Control logic (encrypted)
■ Datapath (clear text)
The control logic performs the following actions:
■ Generates initialization sequence using the RLDRAM II initialization
values set in IP Toolbench
■ Generates write, read, or refresh accesses when requested at the local
interface
■ Generates datapath control signals that ensure that the write data is
output on the memory rldramii_dq[] (CIO devices) or
rldramii_d[] (SIO devices) bus during the correct clock cycles
The datapath performs the following actions:
■ Interfaces to common I/O (CIO) or separate I/O (SIO) RLDRAM II
devices
■ Generates RLDRAM II clocks
■ Places RLDRAM II commands onto the memory command bus using
one of the following system PLL clocks on either the rising or falling
edge:
● System clock
● Wri t e c l ock
● Dedicated clock
■ Places write data onto the rldramii_dq[] or rldramii_d[] bus
during the correct clock cycles
■ Captures the read data using dedicated data strobe signal (DQS)
delay circuitry during DQS mode or an external capture clock in nonDQS mode
Control Logic
The control logic is responsible for controlling transactions at the memory
interface. The control logic accepts read, write, and refresh requests and
executes them immediately as RLDRAM II transactions.
In addition to reads, writes, and refreshes the control logic is also
responsible for controlling initialization of the RLDRAM II devices.
f For more information on reads, writes, refreshes, and initialization, see
“Interfaces” on page 2–16.
2–2 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Table 2–1. Control Signals
Functional Description
Table 2–1 shows the RLDRAM II control signals generated by the control
logic for each operation.
Operation Acronym
Idle NOP High Don’t care Don’t care Don’t care Don’t care
Mode
Register
Set
Read READ Low High High Address Bank address
Write WRITE Low Low High Address Bank address
Auto
Refresh
MRS Low Low Low See your
AREF Low High Low Don’t care Bank address
rldramii
_cs_n_0
rldramii
_we_n_0
rldramii
_ref_n_0
rldramii
_a_0[20:0]
RLDRAM data
sheet
rldramii
_ba_0[2:0]
Don’t care
Datapath
Figure 2–2 on page 2–4 shows the datapath block diagram.
Altera Corporation MegaCore Version 9.1 2–3
November 2009 RLDRAM II Controller MegaCore Function User Guide
Block Description
Optional
Pipeline
Registers
Datapath
rldramii_clk[]
Address &
Command
Output
Registers
Optional
Pipeline
Registers
Write
Data
Logic
Optional
Pipeline
Registers
Read
Data
Logic
Memory
Clock
Generator
rldramii_clk_n[]
Optional
Pipeline
Registers
QVLD
Group
DM
Group
DQS Group
control_dm[]
control_doing_wr
control_wdata[]
control_wdata_valid
control_a[]
control_ba[]
control_cs_n
control_ref_n
control_we_n
control_rdata[]
capture_clk[]
non_dqs_capture_clk
dqs_delay_ctrl[]
control_qvld[]
rldramii_dq[]
rldramii_d[]
rldramii_q[]
rldramii_qk[]
rldramii_qvld[]
rldramii_dm[]
rldramii_a_0[]
rldramii_ba_0[]
rldramii_cs_n_0
rldramii_ref_n_0
rldramii_we_n_0
Figure 2–2. Datapath Block Diagram Note (1)
Note to Figure 2–2:
(1) The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and
2–4 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
<signal>_1 are present.
The datapath performs the following functions:
■ Interfaces to CIO or SIO RLDRAM II devices
■ Outputs write data to the RLDRAM II interface
■ Captures RLDRAM II read data and data valid (QVLD) signals with:
● In DQS mode, a delayed rldramii_qk[] generated by the
● In non-DQS mode, an external capture clock
dedicated DQS delay circuitry
Functional Description
■ Generates the RLDRAM II clocks
■ Generates addresses and commands on:
● System, dedicated, or write clock
● Rising or falling edge
■ Inserts pipeline registers in address and command and write data
path
■ Inserts pipeline registers in read data and QVLD path
The datapath provides the interface between the read and write data
busses of the datapath interface and the double-clocked, bidirectional
data bus of the memory interface. The datapath data busses are twice the
width of the memory data bus, because the memory interface transfers
data on both the rising and falling edges of the clock.
IP Toolbench generates a clear-text VHDL or Verilog HDL datapath,
which matches your custom variation. If you are designing your own
controller, Altera recommends that you use this module as your
datapath.
Figure 2–3 shows the write control signals timing relationship when
writing to the datapath.
Figure 2–3. Datapath Write Control Signal Timing
clk
control_doing_wr
control_wdata_valid
control_wdata[]
control_dm[]
01 23 45 6767
1111
Memory Clock Generator
The memory clock generator generates memory clocks. There can be up
to four memory clocks and they are generated with an altddio_out
megafunction.
Address & Command Output Registers
The address and command output registers can have the following
options:
■ System, write, or dedicated clock clocking for the output registers.
■ Rising or falling edge clocking
Altera Corporation MegaCore Version 9.1 2–5
November 2009 RLDRAM II Controller MegaCore Function User Guide
Block Description
Pipeline Registers
IP Toolbench can insert pipeline registers into the datapath to help meet
timing at higher frequencies. IP Toolbench offers the following pipeline
options:
■ Insert address and command and write data pipeline registers. The
pipeline depth is the same for the write-data path and the address
and command path. The write data and address and command
pipeline registers are clocked off the system clock.
■ Insert read data and QVLD pipeline registers. The pipeline depth is
the same for the read-data path and the QVLD path. The read data
and QVLD pipeline registers are clocked off the clock that captures
the read data—the delayed rldramii_qk[] signal in DQS mode;
the external capture clock in non-DQS mode.
DQS Group
The datapath instantiates one or more DQS groups, which generates
write data, rldramii_dq[] (CIO devices), or rldramii_d[] (SIO
devices) and captures read data rldramii_dq[] (CIO devices), or
rldramii_q[] (SIO devices). The IP Toolbench DQ per DQS (CIO
devices) or Q per DQS (SIO devices) parameter determines the DQS
group width. For example, if DQ per DQS is 9 bits, the
control_wdata[] and control_rdata[] signals are 18-bits wide. To
build larger widths, the datapath instantiates multiple DQS group
modules to increase the data-bus width in increments of DQ per DQS (or
Q per DQS) bits.
1 The datapath generates the DM output, rldramii_dm[], in the
DM group module. It generates the DM output in the same way
as the write data.
1 The datapath captures the QVLD input, rldramii_qvld[], in
the QVLD group module. The rldramii_qvld[] signal is
captured in the same way that the DQS group module captures
the read data. In DQS mode, the delayed rldramii_qk[]
captures rldramii_qvld[]; in non-DQS mode, the external
clock captures rldramii_qvld[].
Figure 2–4 on page 2–7 shows the Stratix II series and HardCopy II
devices DQS group block diagram (DQS mode, CIO devices).
2–6 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Figure 2–4. DQS Group Block Diagram—DQS Mode, CIO Devices Note (1), (2), (3)
control_doing_wr
D
QQ
dq_oe
Functional Description
control_wdata
control_wdata_valid
control_rdata
capture_clk
2W
2W
W
Note 4
W
D
Q
EN
DQ
EN
W
W
write_clk
dq_capture_clk
DDQ
DQ
QD
QDQD
0
DQ
1
DQS
DQS Delay
Notes to Figure 2–4:
(1) This figure shows the logic for one DQ output only.
(2) All clocks are clk, unless marked otherwise.
(3) Bus width W is dependent on the DQ per DQS parameter.
(4) Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the DQ pin.
This inversion is automatic if you use an altdq megafunction for the DQ pins.
Figure 2–5 on page 2–8 shows the Stratix II series and HardCopy II
devices DQS group block diagram (DQS mode, SIO devices).
Altera Corporation MegaCore Version 9.1 2–7
November 2009 RLDRAM II Controller MegaCore Function User Guide
Block Description
Figure 2–5. DQS Group Block Diagram—DQS Mode, SIO Devices Note (1), (2), (3)
control_doing_wr
D
QQ
dq_oe
control_wdata
control_wdata_valid
control_rdata
capture_clk
2W
2W
W
Note 4
W
D
Q
EN
DQ
EN
W
W
write_clk
dq_capture_clk
DDQ
DQ
QD
QDQD
0
D
1
Q
DQS
DQS Delay
Notes to Figure 2–4:
(1) This figure shows the logic for one Q output and one D input only.
(2) All clocks are clk, unless marked otherwise.
(3) Bus width W is dependent on the Q per DQS parameter.
(4) Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the Q pin.
This inversion is automatic if you use an altdq megafunction for the Q pins.
Datapath Example
Figure 2–6 shows an example datapath. The example RLDRAM II
controller and memory configuration has the following parameters:
■ DQS mode
■ Two 18-bit CIO RLDRAM II devices. Each RLDRAM II device has
two rldramii_qk[] data strobes, each associated with 9-bits of
data
■ 36-bit RLDRAM II interface, which requires a 72-bit datapath
interface
2–8 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Figure 2–6. Example Datapath
Datapath
Optional
Pipeline
Registers
RLDRAM II
Device 1
RLDRAM II
Device 0
Read
Data
Logic
Optional
Pipeline
Registers
QVLD
Group 1
DQS Group 3
control_rdata[35:18]
control_qvld[1]
capture_clk[1]
rldramii_dq[35:27]
rldramii_qk[3]
Optional
Pipeline
Registers
Read
Data
Logic
DQS Group 2
control_rdata[71:54]
rldramii_dq[26:18]
rldramii_qk[2]
rldramii_qvld[1]
Optional
Pipeline
Registers
Read
Data
Logic
Optional
Pipeline
Registers
QVLD
Group 0
DQS Group 1
control_rdata[17:0]
control_qvld[0]
rldramii_dq[17:9]
rldramii_qk[1]
Optional
Pipeline
Registers
Read
Data
Logic
DQS Group 0
control_rdata[53:36]
rldramii_dq[8:0]
rldramii_qk[0]
rldramii_qvld[0]
capture_clk[0]
Functional Description
Figure 2–6 shows the following points, which are applicable for all
interface configurations:
■ Each DQS rldramii_dq[] byte group is captured by the delayed
version of its associated rldramii_qk[] data strobe:
Altera Corporation MegaCore Version 9.1 2–9
November 2009 RLDRAM II Controller MegaCore Function User Guide
Loading...