Altera Remote Update IP Core User Manual
2015.04.07
Device Control
Module
Development
Location
Device Configuration
Network
Data
Data
Data
Configuration
devices
(Serial flash)
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Altera Remote Update IP Core User Guide
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The Altera Remote Update IP core implements a remote system update using dedicated remote system
upgrade circuitry available in supported devices.
Remote system update helps you deliver feature enhancements and bug fixes without recalling your
product, and reduces time-to-market and extends product life. The Altera Remote Update IP core
downloads a new configuration image from a remote location, stores the image in a configuration device,
and upgrades the configuration circuitry to start a reconfiguration cycle.
The dedicated circuitry performs error detection during and after the configuration process. When the
dedicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe,
default factory configuration image and then provides error status information.
The following figure shows a functional diagram for a typical remote system update process.
Figure 1: Typical Remote System Update Process
Note:
Related Information
• Configuration Center
• ALTREMOTE_UPDATE Knowledge Base
Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license.The OpenCore® feature allows evaluation of any Altera® IP core in simulation and
compilation in the Quartus® II software. Some Altera IP cores, such as MegaCore® functions, require that
you purchase a separate license for production use. The OpenCore Plus feature allows you to evaluate IP
that requires purchase of an additional license. Use these features to evaluate the IP core until you are
satisfied with the functionality and performance. After you purchase a license, visit the Self Service
Licensing Center to obtain a license number for any Altera product.
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Altera recommends you to use 20–MHz f
for all devices.
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acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
2
Customizing and Generating IP Cores
Figure 2: IP Core Installation Path
Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
Customizing and Generating IP Cores
You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and
parameter editor allow you to quickly select and configure IP core ports, features, and output files.
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IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note:
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your
project. You can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families.
• Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP, to access
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
partner IP information on the Altera website.
installation folder, and view links to documentation.
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Search and filter IP for your target device
Double-click to customize, right-click for
detailed information
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Figure 3: Quartus II IP Catalog
Using the Parameter Editor
3
Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes
exclusive system interconnect, video and image processing, and other system-level IP that are not
available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer
to Creating a System with Qsys in the Quartus II Handbook.
Using the Parameter Editor
The parameter editor helps you to configure IP core ports, parameters, and output file generation options.
• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values
for specific applications.
• View port and parameter descriptions, and links to documentation.
• Generate testbench systems or example designs (where provided).
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View IP port
and parameter
details
Apply preset parameters for
specific applications
Specify your IP variation name
and target device
Legacy parameter
editors
4
Specifying IP Core Parameters and Options
Figure 4: IP Parameter Editors
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Specifying IP Core Parameters and Options
The parameter editor GUI allows you to quickly configure a custom IP variation. Use the following steps
to specify IP core options and parameters in the Quartus II software.Refer to Specifying IP Core
Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy
parameter editor.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
• Optionally select preset parameter values if provided for your IP core. Presets specify initial
parameter values for specific applications.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
4. Click Generate HDL, the Generation dialog box appears.
5. Specify output file generation options, and then click Generate. The IP variation files generate
according to your specifications.
6. To generate a simulation testbench, click Generate > Generate Testbench System.
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View IP port
and parameter
details
Apply preset parameters for
specific applications
Specify your IP variation name
and target device
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Upgrading IP Cores
7. To generate an HDL instantiation template that you can copy and paste into your text editor, click
Generate > HDL Example.
8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If
you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in
Project to add the file.
9. After generating and instantiating your IP variation, make appropriate pin assignments to connect
ports.
Figure 5: IP Parameter Editor
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Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require upgrade before
you can compile the IP variation in the current version of the Quartus II software. Most Altera IP cores
support automatic upgrade.
Note:
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Upgrading IP cores for Arria 10 and later devices appends a unique identifier to the original IP
core entity name(s), while leaving the IP instance name(s) in tact. There is no requirement to
update these entity references in any supporting Quartus II file, such as the Quartus II Settings File
(.qsf), Synopsys Design Constraints File (.sdc), or SignalTap File (.stp). The Quartus II software
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6
Upgrading IP Cores
reads only the instance name and ignores entity names in paths that specify both entity and
instance names. The upgrade process preserves the original IP variation file (.v, .sv, or .vhd) as
<my_variant>_BAK.v, .sv, .vhd in the project directory.
Table 1: IP Core Upgrade Status
IP Core Status Corrective Action
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Required Upgrade IP
Components
You must upgrade the IP variation before compiling in the current version of
the Quartus II software. Refer to the Description for details about IP core
version differences.
Optional Upgrade IP
Components
Upgrade is optional for this IP variation in the current version of the Quartus
II software. You can upgrade this IP variation to take advantage of the latest
development of this IP core. Alternatively you can retain previous IP core
characteristics by declining to upgrade. Refer to the Description for details
about IP core version differences.
Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of the
Quartus II software due to IP core end of life or incompatibility with the
current version of the Quartus II software. You are prompted to replace the
obsolete IP core with a current equivalent IP core from the IP Catalog. Refer to
the Description for details about IP core version differences and links to
Release Notes.
1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP
core variation. The Upgrade IP Components dialog automatically displays the status of IP cores in
your project, along with instructions for upgrading each core. Click Project > Upgrade IP
Components to access this dialog box manually.
2. To upgrade one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade
option is turned on for the IP core(s), and then click Perform Automatic Upgrade. The Status and
Version columns update when upgrade is complete. Example designs provided with any Altera IP core
regenerate automatically whenever you upgrade an IP core.
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Runs “Auto Upgrade” on all supported outdated cores
Opens editor for manual IP upgrade
“Auto Upgrade”
supported
Upgrade required
Upgrade
optional
Upgrade details
“Auto Upgrade”
successful
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Figure 6: Upgrading IP Cores
Upgrading IP Cores
7
Altera Remote Update IP Core User Guide
3. To manually upgrade an individual IP core that does not support automatic upgrade, select the IP core
and then click Upgrade in Editor. The parameter editor opens, allowing you to adjust parameters and
regenerate the latest version of the IP core.
You upgrade IP cores at the command line as long as the IP core supports auto upgrade. IP cores that
do not support automatic upgrade do not support command line upgrade.
• To upgrade a single IP core that supports auto-upgrade, type the following command:
quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip>.<hdl>
<qii_project>
Example:
quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx
• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the following
command:
quartus_sh –ip_upgrade –variation_files “<my_ip_filepath/my_ip1>.<hdl>;
<my_ip_filepath/my_ip2>.<hdl>” <qii_project>
Example:
quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v" hps_testx
Note:
IP cores older than Quartus II software version 12.0 do not support upgrade. Altera verifies that
the current version of the Quartus II software compiles the previous version of each IP core.
The Altera IP Release Notes reports any verification exceptions for Altera IP cores. Altera does
not verify compilation for IP cores older than the previous two releases.
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Post-fit timing
simulation netlist
Post-fit timing
simulation (3)
Post-fit functional
simulation netlist
Post-fit functional
simulation
Analysis & Synthesis
Fitter
(place-and-route)
TimeQuest Timing Analyzer
Device Programmer
Quartus II
Design Flow
Gate-Level Simulation
Post-synthesis
functional
simulation
Post-synthesis functional
simulation netlist
(Optional) Post-fit
timing simulation
RTL Simulation
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
EDA
Netlist
Writer
8
Simulating Altera IP Cores in other EDA Tools
Related Information
Altera IP Release Notes
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
Figure 7: Simulation in Quartus II Design Flow
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Note: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current
version of the Quartus II software. Altera IP supports a variety of simulation models, including
simulation-specific IP functional simulation models and encrypted RTL models, and plain text
RTL models. These are all cycle-accurate models. The models support fast functional simulation of
your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores,
only the plain text RTL model is generated, and you can simulate that model. Use the simulation
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After POR or
nCONFIG Assertion
Read Start Address
from Flash
Load Application
Number POF
After POR or
nCONFIG Assertion
Load Factory POF
Enter Factory
User Mode
Enter Application
User Mode
Reconfiguration
or Start Address = 0
Reconfiguration
or Start Address = 0
Reconfiguration &
Start Address > 0 and not 32
Error Count > 3
Watchdog
Timeout
Error Count <= 3
No Error
Factory Configuration Application Configuration
Reconfiguration &
Start Address = 32
Reconfiguration &
Start Address = 32
Reconfiguration &
Start Address > 0
and not 32
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models only for simulation and not for synthesis or any other purposes. Using these models for
synthesis creates a nonfunctional design.
Related Information
Simulating Altera Designs
Arria 10 Devices
This section covers the remote system configuration modes, components, parameter, ports, and
parameter settings for Arria® 10 devices.
Remote System Configuration Mode
Arria 10 devices support remote configuration mode only.
Remote configuration supports “Direct to application” and “Application to Application” update. Remote
configuration only supports 4-bytes address scheme so there is no support for devices with densities
smaller than 128Mbit.
Figure 8: Transitions Between Factory and Application Configurations in Remote Update Mode
Arria 10 Devices
9
When used with low-voltage quad-serial configuration (EPCQ-L) devices, the remote update mode allows
a configuration space to start at any flash sector boundary, allowing a maximum of 512 pages in the
EPCQ-L256 device and 1024 pages in the EPCQ-L512 device, in which the minimum size of each page is
512Kbits. Additionally, the remote update mode features a user watchdog timer that can detect functional
errors in an application configuration.
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Remote System Configuration Components
Remote System Configuration Components
Table 2: Remote System Configuration Components in Arria 10 Devices
Components Details
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Page mode feature
Factory configuration
Application configuration
Watchdog timer
The dedicated 32-bit start address register PGM[31..0] holds the start address.
Factory configuration can be set as the default configuration setup depends on
the address pointer set.
The factory configuration loads into the device upon power-up.
If a system encounters an error while loading application configuration data
or if the device reconfigures due to nCONFIG assertion, the device loads the
factory configuration. The remote system configuration register determines
the reason for factory configuration. Based on this information, the factory
configuration determines which application configuration to load.
Application configuration can be the default configuration setup depends on
the address pointer set.
The application configuration loads into the device upon power-up.
The application configuration is the configuration data from a remote source
and the data is stored in different locations or pages of the memory storage
device, excluding the factory page.
A watchdog timer is a circuit that determines the functionality of another
mechanism. The watchdog timer functions like a time delay relay that remains
in the reset state while an application runs properly.
Remote update sub-block
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Arria 10 devices are equipped with a built-in watchdog timer for remote
system configuration to prevent a faulty application configuration from
indefinitely stalling the device.
The timer is a 29-bit counter, but you use only the upper 12 bits to set the
value for the watchdog timer.
The timer begins counting after the device goes into user mode. If the applica‐
tion configuration does not reset the user watchdog timer before time expires,
the dedicated circuitry reconfigures the device with the factory configuration
and resets the user watchdog timer.
To ensure the application configuration is valid, you must continuously reset
the watchdog reset_time within a specific duration during user mode
operation.
The remote update sub-block manages the remote configuration feature. A
remote configuration state machine controls this sub-block. This sub-block
generates the control signals required to control the various configuration
registers.
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Components Details
Parameter Settings
11
Remote configuration
registers
The remote configuration registers keep track of page addresses and the cause
of configuration errors. You can control both the update and shift registers.
The status and control registers are controlled by internal logic, but are read
via the shift register. The control register is 38-bit wide.
For details about configuration registers, refer to the Configuration, Design
Security, and Remote System Upgrades chapter in the respective device
handbook.
Parameter Settings
Table 3: Altera Remote Update IP Core Parameters for Arria 10 Devices
GUI Name Legal Value in GUI Description
Which operation mode
will you be using?
Which configuration
device will you be using?
Add support for writing
configuration parameters
REMOTE Specifies the configuration mode of the ALTERA
REMOTE UPDATE IP core.
EPCQ-L device Choose the configuration device you are using.
—
Enable this if you need to write configuration
parameters.
Enable reconfig POF
—
Not available as it is not required
checking
Ports
Table 4: Altera Remote Update IP Core Ports for Arria 10 Devices
Name Port Required? Description
read_param
Input
No Read signal for the parameter specified in param[]
input port and fed to data_out[] output port.
Signal indicating the parameter specified on the
param[] port should be read. The number of bits set
on data_out[] depends on the parameter type. The
signal is sampled at the rising clock edge. Assert the
signal for only one clock cycle to prevent the
parameter from being read again in a subsequent
clock cycle.
The busy signal is activated as soon as read_param is
read as active. While the parameter is being read, the
busy signal remains asserted, and data_out[] has
invalid data. When the busy signal is deactivated,
data_out[] is valid, another parameter can be read.
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Ports
Name Port Required? Description
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write_param
param[]
Input
Input
No Write signal for parameter specified in param[] and
with value specified in data_in[].
Signal indicating parameter specified with param[]
should be written into remote update block with the
value specified in data_in[]. The number of bits
read from data_in[] depends on the parameter type.
The signal is sampled at the rising clock edge. The
signal should be asserted for only one clock cycle to
prevent the parameter from being rewritten on a
subsequent clock cycle. The busy signal is activated as
soon as write_param is read as being active. While
the parameter is being written, the busy signal
remains asserted, and input to data_ in[] is ignored.
When the busy signal is deactivated, another
parameter can be written. This signal is only valid in
Factory configuration mode because parameters
cannot be written in Application configuration mode.
The signal cannot be used in Local update mode.
No Bus that specifies which parameter need to be read or
updated.
A 3-bit bus that selects the parameter to be read or
updated. If left unconnected, the default value for this
port is 000.
data_in[]
reconfig
Input
Input
No Data input for writing parameter data into the remote
update block. Input bus for parameter data.
For some parameters, not all bits are used. In this
case, the lower-order bits are used (for example,
status values use bits [4:0]).
If left unconnected, this bus defaults to 0. The port is
ignored if the current configuration is the Application
configuration.
A 32-bit bus width(4-bytes addressing configuration
device, for example EPCQ-L256) in the Quartus II
software version 14.0 or later.
Yes Signal indicating that reconfiguration of the part
should begin using the current parameter settings. A
value of 1 indicates reconfiguration should begin.
This signal is ignored while busy is asserted to ensure
all parameters are completely written before reconfi‐
guration begins.
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Name Port Required? Description
Ports
13
reset_timer
clock
reset
Input
Input
Input
No Reset signal for watchdog timer.
Signal indicating the internal watchdog timer should
be reset. Unlike other inputs, this signal is not
affected by the busy signal and can reset the timer
even when busy is asserted.
A falling edge of this signal triggers a reset of the user
watchdog timer.
This signal cannot be used in local update mode.
For the timing specification of this parameter, refer to
the specific device handbook.
Yes Clock input to the remote update block.
Clock input to control the machine and to drive the
remote update block during the update of parameters.
This port must be connected to a valid clock.
Yes This is an active high signal. Asserting this signal high
will reset the IP core.
Asynchronous reset input to the IP core to initialize
the machine to a valid state. The machine must be
reset before first use, otherwise the state is not
guaranteed to be valid.
busy
Output
No Busy signal that indicates when remote update block
is reading or writing data.
While this signal is asserted, the machine ignores
most of its inputs and cannot be altered until the
machine deasserts this signal. Therefore, changes are
made only when the machine is not busy.
This signal goes high when read_param or write_
param is asserted, and remains high until the read or
write operation completes.
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