Altera Reed-Solomon II MegaCore Function User Manual
Reed-Solomon II IP Core User Guide
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TOC-2
Contents
About the Reed-Solomon II IP Core...................................................................1-1
Reed-Solomon II IP Core Getting Started..........................................................2-1
Altera DSP IP Core Features...................................................................................................................... 1-1
Reed-Solomon II IP Core Features............................................................................................................1-1
DSP IP Core Device Family Support.........................................................................................................1-1
DSP IP Core Verification............................................................................................................................1-2
Reed-Solomon II IP Core Release Information.......................................................................................1-2
Reed-Solomon II IP Core Performance and Resource Utilization.......................................................1-3
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
Reed-Solomon II IP Core OpenCore Plus Timeout Behavior...................................................2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-4
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7
DSP Builder Design Flow............................................................................................................................2-8
Reed-Solomon II IP Core Functional Description.............................................3-1
Architecture..................................................................................................................................................3-1
Encoder..............................................................................................................................................3-1
Decoder............................................................................................................................................. 3-2
Multiple Input Channels.................................................................................................................3-4
Reed-Solomon II IP Core Parameters.......................................................................................................3-5
Reed-Solomon II IP Core Interfaces and Signals.................................................................................... 3-7
Avalon-ST Interfaces in DSP IP Cores..........................................................................................3-7
Reed-Solomon II IP Core Signals.................................................................................................. 3-7
Document Revision History................................................................................4-1
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2015.05.01
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101 Innovation Drive, San Jose, CA 95134
About the Reed-Solomon II IP Core
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Altera DSP IP Core Features
• Avalon® Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Reed-Solomon II IP Core Features
• High-performance encoder or decoder for error detection and correction:
• • Fully parameterizable:
• Number of channels
• Number of bits per symbol
• Number of symbols per codeword
• Number of check symbols per codeword
• Field polynomial
• Erasures-supporting decoder—-the decoder can correct symbol errors up to the number of check
symbols, if you give the location of the errors to the decoder
• Error symbol output—the decoder provides the error values
• Bit error output—either split count or full count
• Multiple channels for resource sharing
DSP IP Core Device Family Support
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
1-2
DSP IP Core Verification
Altera® offers the following device support levels for Altera IP cores:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.
Table 1-1: DSP IP Core Device Family Support
Device Family Support
Arria® II GX Final
Arria II GZ Final
Arria V Final
Arria 10 Final
Cyclone® IV Final
Cyclone V Final
MAX® 10 FPGA Final
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Stratix® IV GT Final
Stratix IV GX/E Final
Stratix V Final
Other device families No support
DSP IP Core Verification
Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality
and correctness. Altera generates custom variations of the IP core to exercise the various parameter
options and thoroughly simulates the resulting simulation models with the results verified against master
simulation models.
Reed-Solomon II IP Core Release Information
Use the release information when licensing the IP core.
Table 1-2: Release Information
Item Description
Altera Corporation
Version 15.0
Release Date May 2015
Ordering Code
IP-RSCODECII (Primary License)
IPR-RSCODECII (Renewal License)
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Item Description
Reed-Solomon II IP Core Performance and Resource Utilization
Product ID 00E5 (Encoder/Decoder)
Vendor ID 6AF7
Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Altera does not verify that the Quartus II software compiles IP core versions older than the previous
version. The Altera IP Release Notes lists any exceptions.
Related Information
• Altera IP Release Notes
• Errata for Reed-Solomon IP core in the Knowledge Base
Reed-Solomon II IP Core Performance and Resource Utilization
Table 1-3: Performance and Resource Utilization
Typical expected performance for a Reed-Solomon II IP Core using the Quartus II software with the Arria V
(5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices.
Device
Parameters
Type Check
Symbols
Bits Per
Symbol
Bits Per
Check
Symbol
ALM
Memory Registers
M10K M20K Primary Secondary
1-3
fMAX
(MHz)
Arria V Erasures
decoder
Arria V Erasures
variable
decoder
Arria V Full
error
decoder
Arria V Split
error
decoder
Arria V Standard
decoder
large
Arria V Standard
decoder
medium
Arria V standard
decoder
small
16 8 204 1,687 1 -- 1,765 291 217
16 8 204 1,688 1 -- 1,810 269 213
16 8 204 952 1 -- 989 170 239
16 8 204 976 1 -- 999 144 224
32 8 255 1,628 1 -- 1,751 285 215
16 8 204 944 1 -- 974 178 225
6 4 15 201 1 -- 272 23 315
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Reed-Solomon II IP Core Performance and Resource Utilization
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Device
Type Check
Arria V Standard
encoder
Arria V Variable
decoder
Arria V Variable
encoder
large
Arria V Variable
encoder
small
CycloneVErasures
decoder
CycloneVErasures
variable
decoder
CycloneVFull
error
decoder
Parameters
Symbols
Bits Per
Symbol
Bits Per
Check
Symbol
ALM
Memory Registers
M10K M20K Primary Secondary
fMAX
(MHz)
16 8 204 87 0 -- 164 0 422
16 8 204 964 1 -- 1,019 174 209
32 8 204 904 0 -- 299 0 234
16 8 204 444 0 -- 169 0 259
16 8 204 1,670 1 -- 1,769 366 192
16 8 204 1,683 1 -- 1,812 342 196
16 8 204 953 1 -- 989 232 215
CycloneVSplit
error
decoder
CycloneVStandard
decoder
large
CycloneVStandard
decoder
medium
CycloneVstandard
decoder
small
CycloneVStandard
encoder
CycloneVVariable
decoder
CycloneVVariable
encoder
large
CycloneVVariable
encoder
small
16 8 204 968 1 -- 1,003 198 209
32 8 255 1,631 1 -- 1,752 409 193
16 8 204 938 1 -- 972 227 222
6 4 15 200 1 -- 272 56 275
16 8 204 87 0 -- 164 0 372
16 8 204 968 1 -- 1,016 241 220
32 8 204 905 0 -- 299 0 188
16 8 204 444 0 -- 169 0 217
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Reed-Solomon II IP Core Performance and Resource Utilization
1-5
Device
Type Check
Stratix V Erasures
decoder
Stratix V Erasures
variable
decoder
Stratix V Full
error
decoder
Stratix V Split
error
decoder
Stratix V Standard
decoder
large
Stratix V Standard
decoder
medium
Parameters
Symbols
Bits Per
Symbol
Bits Per
Check
Symbol
ALM
Memory Registers
M10K M20K Primary Secondary
fMAX
(MHz)
16 8 204 1,648 -- 1 1,765 423 367
16 8 204 1,664 -- 1 1,802 405 368
16 8 204 955 -- 1 987 252 424
16 8 204 969 -- 1 1,003 248 424
32 8 255 1,624 -- 1 1,749 432 404
16 8 204 939 -- 1 972 281 410
Stratix V standard
decoder
small
Stratix V Standard
encoder
Stratix V Variable
decoder
Stratix V Variable
encoder
large
Stratix V Variable
encoder
small
6 4 15 197 -- 1 272 52 525
16 8 204 87 -- 0 164 0 610
16 8 204 966 -- 1 1,017 270 409
32 8 204 902 -- 0 299 0 397
16 8 204 435 -- 0 169 0 434
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2015.05.01
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Reed-Solomon II IP Core Getting Started
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Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license
for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation
and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance,
visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 2-1: IP Core Installation Path
Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
2-2
Reed-Solomon II IP Core OpenCore Plus Timeout Behavior
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
Reed-Solomon II IP Core OpenCore Plus Timeout Behavior
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, the time-out behavior of the other IP cores may mask the timeout behavior of a specific IP core .
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, a specific IP core's time-out behavior may be masked by the
time-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus
II software uses OpenCore Plus Files (.ocp) in your project directory to identify your use of the OpenCore
Plus evaluation program. After you activate the feature, do not delete these files..
When the evaluation time expires, for encoders out_data goes low, rst goes high; for decoders, data
goes low, rst goes high .
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Related Information
• AN 320: OpenCore Plus Evaluation of Megafunctions
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note:
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your
project. You can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no
project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, and view links to documentation.
• Click Search for Partner IP, to access partner IP information on the Altera website.
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