Altera 10-Gbps Ethernet MAC MegaCore Function User Manual

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10-Gbps Ethernet MAC MegaCore Function User Guide

10-Gbps Ethernet MAC MegaCore Function

User Guide

101 Innovation Drive San Jose, CA 95134

www.altera.com

UG-01083-3.3

Document last updated for Altera Complete Design Suite version:

Document publication date:

February 2014

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Copyright © 2014 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other words and logos identified as trademarks and/or service marks are the property of Altera Corporation or their respective owners. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 1. About This IP Core

1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.2. Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

1.3. Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.4. IP Core Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

1.4.1. Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

1.4.2. Compatibility Testing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

1.5. Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Getting Started with Altera IP Cores

2.1. Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.2. Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.3. MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.3.1. Specifying Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.3.2. Simulate the IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

2.4. Qsys System Integration Tool Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.4.1. Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.4.2. Complete the Qsys System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2.4.3. Simulate the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2.5. 10GbE MAC Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Chapter 3. 10GbE MAC Design Examples

3.1. Software and Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.2. 10GbE Design Example Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.2.0.1. Ethernet Loopback Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3.2.0.2. Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

3.3. 10GbE Design Example Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

3.4. Creating a New 10GbE Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

3.5. 10GbE Design Example Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.6. 10GbE Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.6.1. 10GbE Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.6.2. 10GbE Testbench Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3.6.3. 10GbE Testbench Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3.6.4. 10GbE Testbench Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

3.6.5. Simulating the 10GbE Testbench with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . 3–11

3.6.6. Enabling Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

3.6.7. 10GbE Simulation Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

3.7. 10GbE Design Example Compilation and Verification in Hardware . . . . . . . . . . . . . . . . . . . . . . . . 3–15

3.7.1. Compiling the 10GbE Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

3.7.2. Verifying the 10GbE Design in Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

3.7.3. Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

3.7.4. 10GbE Design Transmit and Receive Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

3.7.5. 10GbE Design Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19

Chapter 4. 10GbE MAC with IEEE1588v2 Design Example

4.1. Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.2. 10GbE with IEEE 1588v2 Design Example Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

4.2.1. Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

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4.3. 10GbE with IEEE 1588v2 Design Example Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

4.4. Creating a New 10GbE with IEEE 1588v2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

4.5. 10GbE with IEEE 1588v2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

4.5.1. 10GbE with IEEE 1588v2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

4.5.2. 10GbE with IEEE 1588v2 Testbench Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

4.5.3. 10GbE with IEEE 1588v2 Testbench Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

4.5.4. 10GbE with IEEE 1588v2 Testbench Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

4.5.5. Simulating 10GbE with IEEE 1588v2 Testbench with ModelSim Simulator . . . . . . . . . . . . . . . 4–7

Chapter 5. 1G/10GbE MAC Design Example

5.1. Software and Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2. 1G/10GbE Design Example Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

5.2.1. Reconfiguration Bundle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

5.2.2. Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

5.3. 1G/10GbE Design Example Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.4. Creating a New 1G/10GbE Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5.5. 1G/10GbE Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5.5.1. 1G/10GbE Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5.5.2. 1G/10GbE Testbench Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5.5.3. 1G/10GbE Testbench Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5.5.4. 1G/10GbE Testbench Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.5.4.1. 1G/10Gb Ethernet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.5.4.2. Backplane-KR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

5.5.5. Simulating the 1G/10GbE Testbench with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . 5–10

5.5.6. 1G/10GbE Simulation Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

5.6. 1G/10GbE Design Example Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

5.6.1. Compiling the 1G/10GbE Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

5.6.2. 1G/10GbE Design Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14

Chapter 6. 10M-10GbE MAC with IEEE 1588v2 Design Example

6.1. Software and Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6.2. 10M-10GbE MAC with IEEE 1588v2 Design Example Components . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6.2.1. Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

6.3. 10M-10GbE MAC with IEEE 1588v2 Design Example Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

6.4. Creating a New 10M-10GbE MAC with IEEE 1588v2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

6.5. 10M-10GbE with IEEE 1588v2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.5.1. 10M-10GbE with IEEE 1588v2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.5.2. 10M-10GbE with IEEE 1588v2 Testbench Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.5.3. 10M-10GbE MAC with IEEE 1588v2 Testbench Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

6.5.4. 10M-10GbE MAC with IEEE 1588v2 Testbench Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . 6–7

6.5.5. Simulating 10M-10GbE MAC with IEEE 1588v2 Testbench with ModelSim Simulator . . . . . 6–7

Chapter 7. Functional Description

7.1. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.2. Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

7.2.1. Avalon-ST Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

7.2.2. SDR XGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2.3. GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2.4. MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2.5. Avalon-MM Control and Status Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.3. Frame Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5

7.4. Transmit Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5

7.4.1. Frame Payload Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5

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7.4.2. Address Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6

7.4.3. Frame Check Sequence (CRC-32) Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6

7.4.4. XGMII Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

7.4.5. Inter-Packet Gap Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

7.4.6. SDR XGMII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

7.5. Receive Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

7.5.1. Minimum Inter-Packet Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

7.5.2. XGMII Decapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

7.5.3. Frame Check Sequence (CRC-32) Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

7.5.4. Address Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

7.5.5. Frame Type Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

7.5.6. Length Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13

7.5.7. CRC-32 and Pad Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14

7.5.8. Overflow Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

7.6. Transmit and Receive Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

7.7. Congestion and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

7.7.1. IEEE 802.3 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16

7.7.1.1. Pause Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16

7.7.1.2. Pause Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16

7.7.2. Priority-Based Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19

7.7.2.1. PFC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19

7.7.2.2. PFC Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20

7.8. Error Handling (Link Fault) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20

7.9. IEEE 1588v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21

7.9.1. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–23

7.9.2. Transmit Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24

7.9.3. Receive Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25

7.9.4. Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25

7.9.4.1. PTP Packet in IEEE 802.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25

7.9.4.2. PTP Packet over UDP/IPv4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26

7.9.4.3. PTP Packet over UDP/IPv6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27

Chapter 8. Registers

8.1. MAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

8.1.1. Rx_frame_control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16

8.1.2. Rx_pfc_control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17

8.2. MAC Registers for IEEE 1588v2 Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18

8.2.1. Configuring PMA Analog and Digital Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19

8.3. Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19

Chapter 9. Interface Signals

9.0.1. Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2

9.0.2. Avalon-ST Transmit and Receive Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2

9.0.2.1. Timing Diagrams—Avalon-ST Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3

9.0.2.2. Timing Diagrams—Avalon-ST Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6

9.0.3. SDR XGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8

9.0.3.1. Timing Diagrams—SDR XGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9

9.0.4. GMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11

9.0.5. MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11

9.0.6. Avalon-MM Programming Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12

9.0.7. Avalon-ST Status and Pause Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13

9.0.8. 10M-10GbE MAC Speed Control Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20

9.0.9. IEEE 1588v2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

vi Contents

9.0.9.1. IEEE 1588v2 Timestamp Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20

9.0.9.2. ToD Clock Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25

9.0.9.3. Path Delay Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25

9.0.9.4. Timing Diagrams—IEEE 1588v2 Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–27

Chapter 10. Design Considerations

10.1. SDR XGMII to DDR XGMII Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

10.1.1. ALTDDIO_IN Megafunction Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

10.1.2. ALTDDIO_OUT Megafunction Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

10.2. 10GbE MAC and PHY Connection with XGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

10.3. Sharing TX and RX Clocks for Multi-Port System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

10.4. Sharing Reference Clocks for Multi-Port System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3

Appendix A. Frame Format

A.1. Ethernet Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

A.2. VLAN and Stacked VLAN Tagged MAC Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

A.3. Pause Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

A.4. Priority-Based Flow Control Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

Appendix B. Time-of-Day (ToD) Clock

B.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

B.2. Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

B.3. Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

B.4. Parameter Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2

B.5. ToD Clock Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2

B.5.1. Avalon-MM Control Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3

B.5.2. Avalon-ST Transmit Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3

B.6. ToD Clock Configuration Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–4

B.6.1. Adjusting ToD’s Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–5

Appendix C. Packet Classifier

C.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

C.2. Packet Classifier Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2

C.2.1. Common Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2

C.2.2. Avalon-ST Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–2

C.2.3. Ingress Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–3

C.2.4. Control Insert Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–4

C.2.5. Timestamp Field Location Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–4

Appendix D. ToD Synchronizer

D.1. Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

D.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2

D.3. ToD Synchronizer Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3

D.4. ToD Synchronizer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–4

D.4.1. Common Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–4

D.4.2. Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–4

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–4

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–4

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

1. About This IP Core

Avalon-ST

Interface

Client

Module

Altera FPGA

10GbE MAC or

1G/10GbE MAC or

10M/100M/

1000M/10GbE MAC

External PHY

XAUI or

10GBASE-R or

Backplane Ethernet

10GBASE-KR PHY or

1G/10Gbps Ethernet

SDR XGMII/

GMII/MII

Serial

Interface

The 10-Gbps Ethernet (10GbE) Media Access Controller (MAC) IP core is a configurable component that implements the IEEE 802.3-2008 specification. The IP core offers the following modes:

■ 10 Gbps mode—uses the Avalon

side and the single data rate (SDR) XGMII on the network side.

■ 1 Gbps/10 Gbps mode— uses the Avalon-ST interface on the client side and

GMII/SDR XGMII on the network side.

■ 10 Mbps/100 Mbps/1 Gbps/10 Gbps (10M-10G) mode—uses the Avalon-ST

interface on the client side and MII/GMII/SDR XGMII on the network side.

To build a complete Ethernet subsystem in an Altera external device, you can use the 10GbE MAC IP core with an Altera PHY IP core such as a soft XAUI PHY in FPGA fabric, hard silicon-integrated XAUI PHY, a 10GBASE-R PHY, a Backplane Ethernet 10GBASE-KR PHY, or a 1G/10 Gbps Ethernet PHY IP.

Streaming (Avalon-ST) interface on the client

device and connect it to an

Figure 1–1 illustrates a system with the 10GbE MAC IP core.

Figure 1–1. Typical Application of 10GbE MAC

1.1. Features

The 10GbE MAC supports the following features:

■ Operating modes: 10 Mbps, 100 Mbps, 1 Gbps and 10 Gbps.

■ Support for full duplex only.

■ Avalon-ST 64-bit wide client interface running at 156.25 MHz.

■ Direct interface to 4-bit MII running at 125 MHZ with clock enable; 2.5 MHz for

10 Mbps and 25 MHz for 100 Mbps.

■ Direct interface to 8-bit GMII running at 125 MHZ.

■ Direct interface to 64-bit SDR XGMII running at 156.25 MHZ.

■ Virtual local area network (VLAN) and stacked VLAN tagged frames filtering as

specified by IEEE 802.IQ and 802.1ad (Q-in-Q) standards respectively.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

1–2 Chapter 1: About This IP Core

■ Optional cyclic redundancy code (CRC)-32 computation and insertion on the

Release Information

transmit datapath; CRC checking on the receive datapath with optional forwarding of the frame check sequence (FCS) field to the client application.

■ Checking of receive frames for FCS error, undersized and oversized frames, and

payload length error.

■ Deficit idle counter (DIC) for optimized performance with average inter-packet

gap (IPG) of 12 bytes for LAN applications.

■ Optional statistics collection on the transmit and receive datapaths.

■ Packets termination when the transmit datapath receives incomplete packets.

■ Programmable maximum length of transmit and receive frames up to

64 Kbytes (KB).

■ Programmable promiscuous (transparent) mode.

■ Optional Ethernet flow control and priority-based flow control (PFC) using pause

frames with programmable pause quanta. The PFC supports up to 8 priority queues.

■ Optional padding termination on the receive datapath and insertion on the

transmit datapath.

■ Design examples with optional loopback and testbench for design verification.

■ Optional preamble passthrough mode on the transmit and receive datapaths. The

preamble passthrough mode allows you to define the preamble in the client frame.

■ Programmable datapath option to allow separate instantiation of MAC TX block,

MAC RX block, or both MAC TX and MAC RX blocks.

■ Optional IEEE 1588v2 feature for the following configurations:

■ 10GbE MAC with 10GBASE-R PHY MegaCore function

■ 1G/10GbE MAC with Backplane Ethernet 10GBASE-KR PHY MegaCore

function

■ Multi-speed 10M-10GbE MAC with Backplane Ethernet 10GBASE-KR PHY

MegaCore function

1.2. Release Information

Tab le 1– 1 lists information about this release of the 10GbE MAC IP core.

Table 1–1. Release Information

Version 13.1

Release Date November 2013

Ordering Code IP-10GETHMAC

Product ID ID 00D9

Vendor ID 6AF7

Item Description

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 1: About This IP Core 1–3

Device Family Support

1.3. Device Family Support

MegaCore functions provide the following support for Altera device families:

■ Preliminary support—Altera verifies the IP core with preliminary timing models for

this device family. The core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

■ Final support—Altera verifies the IP core with final timing models for this device

family. The core meets all functional and timing requirements for the device family and can be used in production designs.

Tab le 1– 2 shows the level of support offered by the 10GbE MAC for the following

Altera device family.

Table 1–2. Device Family Support for 10GbE MAC

Device Family Support

II GX, GZ Final

Arria

Arria V GT, GX, and GZ Preliminary

Arria V SoC Preliminary

Cyclone

Cyclone V Preliminary

Cyclone V SoC Preliminary

Stratix

Stratix IV Final

Stratix V Preliminary

IV GX Final

III Final

Tab le 1– 3 shows the devices supported by the different configurations.

Table 1–3. Device Family Support for Configurations

Configuration Arria V GT Arria V GZ Stratix V

Multi-Speed 10M-10GbE MAC — vv Multi-Speed 10M-10GbE MAC with IEEE 1588v2 — vv 10GbE MAC with 10GBASE-R PHY vvv

10GbE MAC with 10GBASE-R PHY and IEEE 1588v2

Multi-Speed 10M-10GbE MAC with Backplane Ethernet 10GBASE-KR PHY

Multi-Speed 10M-10GbE MAC with Backplane Ethernet 10GBASE-KR PHY and IEEE 1588v2

Multi-Speed 10M-10GbE MAC with 1G/10Gbps Ethernet PHY

Multi-Speed 10M-10GbE MAC with 1G/10Gbps Ethernet PHY and IEEE 1588v2

Note for Table 1–3:

(1) Supports only Arria V GT devices with speed grade of 3_H3.

v (1) vv

— vv

———

— vv — vv

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

1–4 Chapter 1: About This IP Core

IP Core Verification

1.4. IP Core Verification

To ensure compliance with the IEEE specification, Altera performs extensive validation of the 10GbE MAC IP core. Validation includes both simulation and hardware testing.

1.4.1. Simulation Environment

Altera performs the following tests in the simulation environment:

■ Directed tests that test all types and sizes of transaction layer packets and all bits of

the configuration space.

■ Error injection tests that inject errors in the link, transaction layer packets, and data

link layer packets, and check for the proper response from the IP core.

■ Random tests that test a wide range of traffic patterns across one or more virtual

channels.

1.4.2. Compatibility Testing Environment

Altera has performed significant hardware testing of the 10GbE MAC IP core to ensure a reliable solution. The IP core has been tested with the following devices:

■ Arria V, Stratix IV, and Stratix V

■ Soft XAUI PHY

■ Soft and hard 10GBASE-R PHY

■ Hard Backplane Ethernet 10GBASE-KR PHY

■ 1G/10Gbps Ethernet PHY

The IP core has passed all interoperability tests conducted by the UNH. In addition, Altera internally tests every release with the Spirent Ethernet and 10G testers.

1.5. Performance and Resource Utilization

Tab le 1– 4 provides the estimated performance and resource utilization of the 10GbE

MAC for the Cyclone IV device family. The estimates are obtained by compiling the 10GbE MAC with the Quartus II software targeting a Cyclone IV (EP4CGX110DF31C7) device with speed grade –7.

1 To achieve your timing requirement in the Quartus II software, Altera recommends

that you use multiple seeds in the Design Space Explorer to find the optimal Fitter settings for your design, follow the recommendations of the Timing Optimization Advisor, apply the Speed Optimization Technique and use the LogicLock regions.

Table 1–4. Cyclone IV Performance and Resource Utilization

Settings Logic Elements Logic Registers Memory Block (M9K) f

All options disabled

All options enabled with memory-based statistics counters

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

4,424 3,245 2 >156.25

11,845 8,355 11 >156.25

MAX

(MHz)

Chapter 1: About This IP Core 1–5

Performance and Resource Utilization

Tab le 1– 5 provides the estimated performance and resource utilization of the

10GbE MAC for the Stratix IV device family. The estimates are obtained by compiling the 10GbE MAC with the Quartus II software targeting a Stratix IV GX (EP4SGX70HF35C2) device with speed grade –2.

Table 1–5. Stratix IV Performance and Resource Utilization

Settings Combinational ALUTs Logic Registers Memory Block (M9K) f

All options disabled

All options enabled with memory-based statistics counters

All options enabled with register-based statistics counters

1,954 3,157 0 >156.25

5,684 8,349 7 >156.25

8,135 10,117 3 >156.25

Tab le 1– 6 provides the estimated performance and resource utilization of the

10GbE MAC for the Cyclone V device family. The estimates are obtained by compiling the 10GbE MAC with the Quartus II software targeting a Cyclone V GX (5CGXFC7D6F31C6) device with speed grade –6.

Table 1–6. Cyclone V Performance and Resource Utilization

Settings Combinational ALUTs Logic Registers Memory Block (M10K) f

All options disabled

All options enabled with memory-based statistics counters

All options enabled with register-based statistics counters

2,322 3,444 2 >156.25

4,417 5,464 6 >156.25

6,867 7,113 2 >156.25

MAX

(MHz)

Tab le 1– 7 provides the estimated performance and resource utilization of the

10GbE MAC for the Stratix V device family. The estimates are obtained by compiling the 10GbE MAC with the Quartus II software targeting a Stratix V GX (5SGXEA7H3F35C3) device with speed grade –3.

Table 1–7. Stratix V Performance and Resource Utilization for 10GbE MAC (Part 1 of 2)

Settings Combinational ALUTs

All options disabled

All options enabled with memory-based statistics counters

All options enabled with register-based statistics counters

2,001 3,077 0 >156.25

5,772 8,197 7 >156.25

8,202 9,965 3 >156.25

Dedicated Logic

Registers

Memory Block (M20K) f

MAX

(MHz)

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

1–6 Chapter 1: About This IP Core

Performance and Resource Utilization

Table 1–7. Stratix V Performance and Resource Utilization for 10GbE MAC (Part 2 of 2)

Settings Combinational ALUTs

Dedicated Logic

Registers

IEEE 1588v2 feature enabled with 2-step synchronization

■ Timestamping is enabled

■ ptp_1step is disabled

4,827 5,921 8 >156.25

IEEE 1588v2 feature enabled with 1-step and 2-step synchronization

■ Timestamping is enabled

■ ptp_1step is disabled

6,822 7,926 11 >156.25

Tab le 1– 8 provides the estimated performance and resource utilization of the

multi-speed 10M-10GbE MAC for the Stratix V device family. The estimates are obtained by compiling the 10M-10GbE MAC with the Quartus II software targeting a Stratix V GX (5SGXEA7H3F35C3) device with speed grade –3.

Table 1–8. Stratix V Performance and Resource Utilization for 10M-10GbE MAC

Settings Combinational ALUTs

All options disabled

All options enabled with memory-based statistics counters

All options enabled with register-based statistics counters

3,654 4,645 7 >156.25

4,877 5,797 11 >156.25

7,313 7,544 7 >156.25

Dedicated Logic

Registers

Memory Block (M20K) f

MAX

(MHz)

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

2. Getting Started with Altera IP Cores

<path>

Contains the IP core files and documentation

common

Contains shared components

Installation directory

Contains the Altera IP Library and third-party IP cores

altera

Contains the Altera IP Library

This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports. The following sections describe the general design flow and use of Altera IP cores.

2.1. Installation and Licensing

The Altera IP Library is distributed with the Quartus II software and downloadable from the Altera website (www.altera.com).

Figure 2–1 shows the directory structure after you install an Altera IP core, where

path> is the installation directory. The default installation directory on Windows is

C:\altera\<version number>; on Linux it is /opt/altera<version number>.

Figure 2–1. IP core Directory Structure

You can evaluate an IP core in simulation and in hardware until you are satisfied with its functionality and performance. Some IP cores require that you purchase a license for the IP core when you want to take your design to production. After you purchase a license for an Altera IP core, you can request a license file from the Altera Licensing page of the Altera website and install the license on your computer. For additional information, refer to Altera Software Installation and Licensing.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

2–2 Chapter 2: Getting Started with Altera IP Cores

Design Flows

2.2. Design Flows

You can use the following flow(s) to parameterize Altera IP cores:

■ “MegaWizard Plug-In Manager Flow”

■ “Qsys System Integration Tool Design Flow”

Figure 2–2 shows the design flows for the MegaWizard Plug-In Manager and Qsys

system integration tool.

Figure 2–2. Design Flows

Select Design Flow

Perform

Functional Simulation

Does

Simulation Give

Expected Results?

Debug Design

Qsys

Flow

Specify Parameters

Complete

Qsys System

Optional

Yes

and Compile Design

MegaWizard Flow

Specify Parameters

Add Constraints

IP Complete

2.3. MegaWizard Plug-In Manager Flow

The MegaWizard Plug-In Manager flow allows you to customize the 10GbE MAC IP core and manually integrate the function into your design.

2.3.1. Specifying Parameters

To specify the 10GbE MAC IP core parameters with the MegaWizard Plug-In Manager, follow these steps:

1. Open an existing Quartus II project or create a new project using the New Project Wizard available from the File menu.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 2: Getting Started with Altera IP Cores 2–3

MegaWizard Plug-In Manager Flow

2. In the Quartus II software, launch the MegaWizard Plug-in Manager from the Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation.

3. In the Installed Plug-Ins list on page 2a of the MegaWizard Plug-In Manager interface, expand the Interfaces folder and then the Ethernet folder. Select Ethernet 10G MAC. Specify the type and name of the output file you want to create.

4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to “10GbE MAC Parameter Settings” on page 2–6.

5. Specify appropriate options in the wizard to generate a simulation model.

1 Altera IP supports a variety of simulation models, including

simulation-specific IP functional simulation models and encrypted RTL models. These are all cycle-accurate models. The models allow for fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators.

f For more information about functional simulation models for Altera IP

cores, refer to Simulating Altera Designs in volume 3 of the Quartus II Handbook.

c Use the simulation models only for simulation and not for synthesis or any

other purposes. Using these models for synthesis creates a nonfunctional design.

6. Click Finish. The parameter editor generates the top-level HDL code for the 10GbE MAC IP core and a simulation directory which includes files for simulation.

1 The Finish button may be unavailable until all parameterization errors

listed in the messages window are corrected.

7. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects.

You can now integrate your custom 10GbE MAC IP core instance in your design, simulate, and compile.

f For information about the Quartus II software and the MegaWizard Plug-In Manager,

refer to Quartus II Help.

2.3.2. Simulate the IP Core

You can simulate the 10GbE MAC IP core with the functional simulation model generated by the Quartus II software. To perform a successful simulation of the 10GbE MAC IP core using the MegaWizard Plug-In Manager flow, you are required to compile all files listed in the <project directory>/<variation name>_sim output file. Otherwise, the simulation may fail.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

2–4 Chapter 2: Getting Started with Altera IP Cores

DDR3

SDRAM

Ethernet

Subsystem

Ethernet

Embedded Cntl

PCI Express

Subsystem

Qsys System PCIe to Ethernet Bridge

PCIe

CSR

Mem

Mstr

Mem

Slave

PHY

Cntl

Mem

Mstr

CSR

DDR3

SDRAM

Controller

Qsys System Integration Tool Design Flow

f For more information about simulating Altera IP cores, refer to Simulating Altera

Designs in volume 3 of the Quartus II Handbook.

2.4. Qsys System Integration Tool Design Flow

You can use the Qsys system integration tool to build a system that includes your customized IP core. You easily can add other components and quickly create a Qsys system. Qsys automatically generates HDL files that include all of the specified components and interconnections. In Qsys, you specify the connections you want. The HDL files are ready to be compiled by the Quartus II software to produce output files for programming an Altera device.

Figure 2–3 shows a high level block diagram of an example Qsys system.

Figure 2–3. Example Qsys System

f For more information about the Qsys system interconnect, refer to the Qsys

Interconnect chapter in volume 1 of the Quartus II Handbook and to the Avalon Interface Specifications.

f For more information about the Qsys tool and the Quartus II software, refer to the

System Design with Qsys section in volume 1 of the Quartus II Handbook and to Quartus

II Help.

2.4.1. Specify Parameters

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

To specify parameters for your IP core using the Qsys flow, follow these steps:

1. Open an existing Quartus II project or create a new project using the New Project Wizard available from the File menu.

2. On the Tools menu, click Qsys.

3. On the Component Library tab, expand the Interfaces Protocols list and then the Ethernet list. Double-click Ethernet 10G MAC to add it to your system. The relevant parameter editor appears.

Chapter 2: Getting Started with Altera IP Cores 2–5

Qsys System Integration Tool Design Flow

4. Specify the required parameters in the Qsys tool. For detailed explanations of these parameters, refer to “10GbE MAC Parameter Settings” on page 2–6.

5. Click Finish to complete the IP core instance and add it to the system.

2.4.2. Complete the Qsys System

To complete the Qsys system, follow these steps:

1. Add and parameterize any additional components.

2. Connect the components using the Connections panel on the System Contents tab.

3. In the Export As column, enter the name of any connections that should be a top-level Qsys system port.

4. If you intend to simulate your Qsys system, on the Generation tab, turn on one or more options under Simulation to generate desired simulation files.

5. If you want to generate synthesis RTL files, turn on Create HDL design files for synthesis.

6. Click Generate to generate the system. Qsys generates the system and produces the <system name>.qip file that contains the assignments and information required to process the IP core or system in the Quartus II Compiler.

7. In the Quartus II software, click Add/Remove Files in Project on the Project menu and add the .qip file to the project.

8. Compile your design in the Quartus II software.

2.4.3. Simulate the System

During system generation, Qsys generates a functional simulation model which you can use to simulate your system easily in any Altera-supported simulation tool.

f For information about the latest Altera-supported simulation tools, refer to the

Quartus II Software Release Notes.

f For general information about simulating Altera IP cores, refer to Simulating Altera

Designs in volume 3 of the Quartus II Handbook.

f For information about simulating Qsys systems, refer to the System Design with Qsys

section in volume 1 of the Quartus II Handbook.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

2–6 Chapter 2: Getting Started with Altera IP Cores

10GbE MAC Parameter Settings

2.5. 10GbE MAC Parameter Settings

You customize the 10GbE MAC by specifying the parameters on the MegaWizard Plug-in Manager, or Qsys in the Quartus II software. Tab le 2– 1 describes the parameters and how they affect the behavior of the IP core.

Table 2–1. 10GbE Parameters

Parameter Description

Use this parameter to select the speed options. By default, the 10G MAC option is

Speed select for 10G MAC

Preamble pass-through mode

Priority-based flow control (PFC)

Number of PFC priorities

Datapath option

Supplementary address

CRC on transmit path

Statistics collection Turn on this parameter to collect statistics on the transmit and receive datapaths.

Statistics counters

Enable time stamping

Enable PTP 1-step clock support

Timestamp fingerprint width

selected. Select Enable 1G/10G MAC to implement the 10-Gbps and 1-Gbps MAC; select Enable Multi-Speed 10M-10Gb MAC to implement the 10-Mbps, 100-Mbps, 1- Gbps, and 10-Gbps MAC.

Turn on this parameter to enable the preamble passthrough mode. To enable the preamble passthrough mode, you must turn on this parameter and set the

tx_preamble_control, rx_lane_decoder_preamble_control rx_preamble_inserter_control

This parameter is disabled if you selected Enable 1G/10G MAC.

Turn on this parameter to enable PFC. Refer to “Priority-Based Flow Control” on

page 7–19 for more information on PFC and its operations.

Indicates the number of PFC priority levels that the 10GbE MAC IP core supports. The valid range is from 2 to 8. This option is enabled only if you turn on the Priority-based flow control (PFC) parameter.

Use this parameter to select the datapath option that determines the MAC variation to instantiate. By default, the TX & RX option is selected. The default datapath instantiates the MAC TX and MAC RX blocks. Selecting TX only instantiates the MAC TX block; selecting RX only instantiates the MAC RX block.

Turn on this parameter to enable supplementary addresses. To enable supplementary addresses, you must turn on this parameter and set the

rx_frame_control

Turn on this parameter to calculate and insert CRC on the transmit datapath. To compute and insert CRC on the transmit datapath, you must turn on this parameter and set the

When you turn on Statistics collection, the default implementation of the statistics counters is Memory-based.

Use Memory-based statistics counters to free up the logic elements (the MAC does not clear the statistic counters after the counters are read); Register-based statistics counters to free up the memory (the MAC clears the statistic counters after the counters are read).

Turn on this parameter to enable time stamping on the transmitted and received frames.

Turn on this parameter to insert time stamp on PTP messages for 1-step clock based on the TX Egress Timestamp Insert Control interface.

This parameter is disabled if you do not turn on Enable time stamping.

Use this parameter to set the width in bits for the time stamp fingerprint on the TX path. The default value is 4 bits.

tx_crcins_control

registers to 1.

EN_SUPP0/1/2/3

[1] register bit to 1.

, and

bits in the

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

3. 10GbE MAC Design Examples

You can use the following 10GbE design examples and testbenches to help you get started with the 10GbE MAC IP core and use the core in your design:

■ 10GbE MAC with XAUI PHY

■ 10GbE MAC with 10GBASE-R PHY

1 XAUI PHY and 10GBASE-R PHY do not support Stratix III devices.

3.1. Software and Hardware Requirements

Altera uses the following hardware and software to test the 10GbE design examples and testbenches:

■ Quartus II software 13.1

■ Stratix IV GX FPGA development kit (for XAUI PHY)

■ Transceiver Signal Integrity development kit, Stratix IV GT Edition (for

10GBASE-R PHY)

■ ModelSim

-AE 6.6c, ModelSim-SE 6.6c or higher

f For more information on the development kits, refer to the following documents:

■ Stratix IV GX Development Kit User Guide

■ Stratix IV GX Development Kit Reference Manual

■ Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Guide

■ Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

Ethernet

Loopback

JTAG to Avalon Master

Bridge

Pipeline Bridge

10GbE MAC

XAUI

10GBASE-R

PHY

External

PHY

MDIO

64-bit Avalon-ST

32-bit

Avalon-MM

MDIO Signals

32-bit Avalon-MM

System Console

(for debugging)

XAUI / 10GBASE-R

72-bit SDR XGMII

Tx FIFO Buffer

Rx FIFO Buffer

Client

Application

Altera FPGA

Design Example

Client Application

(Configuration, Status, and

Statistics)

Avalon-ST

Single-Clock / Dual-Clock

FIFO

Configuration and Debugging Tools

3–2 Chapter 3: 10GbE MAC Design Examples

10GbE Design Example Components

3.2. 10GbE Design Example Components

You can use the 10GbE MAC IP core design example to simulate a complete 10GbE design in an Altera FPGA. You can compile the design example using the simulation files generated by the Quartus II software and program the targeted Altera device after a successful compilation.

Figure 3–1 shows the block diagram of the 10GbE design examples.

Figure 3–1. 10GbE Design Example Block Diagram

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–3

10GbE Design Example Components

The design example comprises the following components:

■ 10GbE Ethernet MAC—the MAC IP core with default settings. This IP core

includes memory-based statistics counters.

■ XAUI PHY or 10GBASE-R PHY—the PHY IP core with default settings. The XAUI

PHY is set to Hard XAUI by default.

■ Ethernet Loopback— the loopback module provides a mechanism for you to

verify the functionality of the MAC and PHY. Refer to Section 3.2.0.1, Ethernet

Loopback Module for more information about this module.

■ RX and TX FIFO buffers—Avalon-ST Single-Clock or Dual-Clock FIFO cores that

buffer receive and transmit data between the MAC and client. These FIFO buffers are 64 bits wide and 512 bits deep. The default configuration is Avalon-ST Single-Clock FIFO, which operates in store and forward mode and you can configure it to provide packet-based flushing when an error occurs.

1 To enable the Avalon-ST Single-Clock FIFO to operate in cut through mode,

turn off the Use store and forward parameter in the Avalon-ST Single Clock FIFO parameter editor.

■ Configuration and debugging tools—provides access to the registers of the

following components via the Avalon Memory-Mapped (Avalon-MM) interface: MAC, MDIO, Ethernet loopback, PHY, and FIFO buffers. The provided testbench includes an Avalon driver which uses the pipeline bridge to access the registers. You can use the system console to access the registers via the JTAG to Avalon Master Bridge core when verifying the design in the hardware.

f To learn more about the components, refer to the respective documents:

■ XAUI PHY and 10GBASE-R PHY, refer to Altera Transceiver PHY IP Core User

Guide.

■ Avalon-ST Single-Clock or Dual-Clock FIFO, JTAG to Avalon Master Bridge, and

MDIO cores, refer to Embedded Peripherals IP User Guide.

■ Pipeline bridge, refer to Avalon Memory-Mapped Bridges in volume 4 of the Quartus

II Handbook.

■ System Console, refer to Analyzing and Debugging Designs with the System Console in

volume 3 of the Quartus II Handbook.

3.2.0.1. Ethernet Loopback Module

You can enable one of the following loopback types:

■ Local loopback—turn on this loopback to verify the functionality of the MAC

during simulation. When you enable the local loopback, the Ethernet loopback module takes the transmit frame from the MAC XGMII TX and loops it back to the MAC XGMII RX datapath. During this cycle, the loopback module also forwards the TX frame to the PHY. While the local loopback is turned on, the loopback module ignores any frame it receives from the PHY.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–4 Chapter 3: 10GbE MAC Design Examples

■ Line loopback—turn on this loopback to verify the functionality of the PHY when

10GbE Design Example Components

verifying the design example in hardware. When you enable the line loopback, the Ethernet loopback module takes the XGMII RX signal received from the PHY and loops it back to the PHY’s XGMII TX signal. During this cycle, the loopback module also forwards the XGMII RX signal to the MAC. While the line loopback is turned on, the loopback module ignores any frame transmitted from the MAC.

Tab le 3– 1 describes the registers you can use to enable or disable the desired loopback.

Table 3–1. Loopback Registers

Byte Offset Register Description

0x00

0x04 Reserved —

0x08

line loopback

local loopback

Set this register to 1 to enable line loopback; 0 to disable it.

Set this register to 1 to enable local loopback; 0 to disable it.

3.2.0.2. Base Addresses

Tab le 3– 2 lists the design example components that you can reconfigure to suit your

verification objectives. To reconfigure the components, write to their registers using the base addresses listed in the table and the register offsets described in the components' user guides. Refer to Tab le 3– 1 for the Ethernet loopback registers.

Table 3–2. Base Addresses of Design Example Components

Component Base Address

10GbE MAC 0x000

XAUI or 10GBASE-R PHY 0x40000

MDIO 0X10000

Ethernet loopback 0x10200

RX FIFO (Avalon-ST Single-Clock FIFO) 0x10400

TX FIFO (Avalon-ST Single-Clock FIFO) 0x10600

1 This design example uses a 19-bit width address bus to access the base address of

components other than the MAC.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–5

10GbE Design Example Files

3.3. 10GbE Design Example Files

Figure 3–2 shows the directory structure for the design examples and testbenches. The

..\csr_script directory contains the design example script files.

Figure 3–2. Design Example Folders

<ip_lib>/ethernet/altera_eth_10g_design_example

altera_eth_10g_mac_base_r

testbench

altera_eth_10g_mac_base_r_sv

testbench

altera_eth_10g_mac_xaui

testbench

altera_eth_10g_mac_xaui_sv

testbench

csr_scripts

design_example_components

source

Tab le 3– 3 lists the design example files. For the description of testbench files, refer to Table 3–5 on page 3–10.

Table 3–3. 10GbE Design Example Files (Part 1 of 2)

File Name Description

A Tcl script that creates a new Quartus II project

setup_proj.tcl

and sets up the project environment for your design example. Not applicable for Stratix V design.

A Tcl script that creates a new Quartus II project

setup_proj_sv.tcl

for Stratix V design and sets up the project environment for your design example.

A Qsys file for the 10GbE MAC and XAUI PHY

altera_eth_10g_design_mac_xaui.qsys

design example. The PHY is set to hard XAUI by default.

A Qsys file for the 10GbE MAC and XAUI PHY

altera_eth_10g_design_mac_xaui_sv.qsys

design example with the Quartus II software targeting the Stratix V device. The PHY is set to hard XAUI by default.

altera_eth_10g_design_mac_base_r.qsys

A Qsys file for the 10GbE MAC and 10GBASE-R PHY design example.

A Qsys file for the 10GbE MAC and 10GBASE-R

altera_eth_10g_design_mac_base_r_sv.qsys

PHY design example with the Quartus II software targeting the Stratix V device.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–6 Chapter 3: 10GbE MAC Design Examples

Table 3–3. 10GbE Design Example Files (Part 2 of 2)

File Name Description

A Tcl script that sets the pin assignments and I/O

setup_SIVGX230C2ES.tcl

setup_EP4S100G5H40I3.tcl

setup_5SGXEA7N2F40C2ES.tcl

top.sdc

top.v

top_sv.v

common.tcl

config.tcl A Tcl script that configures the design example.

csr_pkg.tcl

show_stats.tcl

altera_eth_10g_design_example_hw.tcl

standards for the Stratix IV GX FPGA development board. Use this Tcl script for the 10GbE MAC with XAUI PHY design example.

A Tcl script that sets the pin assignments and I/O standards for the Stratix IV GT Signal Integrity development board. Use this Tcl script for the 10GbE MAC with 10GBASE-R PHY design example.

A Tcl script that sets the pin assignments and I/O standards for the Stratix V GX Signal Integrity development board. Use this Tcl script for the 10GbE MAC with 10GBASE-R PHY design example.

The Quartus II SDC constraint file for use with the TimeQuest timing analyzer.

The top-level entity file of the design example for verification in hardware. Not applicable for Stratix V design.

The top-level entity file of the design example— with the Quartus II software targeting the Stratix V device—for verification in hardware.

A Tcl script that contains basic functions based on the system console APIs to access the registers through the Avalon-MM interface.

A Tcl script that maps address to the Avalon-MM control registers. The script contains APIs which is used by config.tcl and show_stats.tcl.

A Tcl script that displays the MAC statistics counters.

A hardware Tcl script that contains the composition of the Ethernet system.

Creating a New 10GbE Design

3.4. Creating a New 10GbE Design

You can use the Quartus II software to create a new 10GbE design. Altera provides a customizable Qsys design example file to facilitate the development of your 10GbE design. Follow these steps to create the design:

1. Copy the respective design example directory to your preferred project directory: altera_eth_10g_mac_xaui or altera_eth_10g_mac_base_r from <ip library>/ethernet/altera_eth_10g_design_example.

2. Launch the Quartus II software and open the top.v file from the project directory.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–7

Creating a New 10GbE Design

3. Open the Quartus II Tcl Console window by pointing to Utility Windows on the View menu and then selecting Tcl Co ns ol e. In the Quartus II Tcl Console window, type the following command to set up the project environment:

source setup_proj.tcl

4. Load the pin assignments and I/O standards for the development board:

■ For the 10GbE MAC with XAUI PHY design example, type the following

command:

source setup_SIVGX230C2ES.tcl

This command assigns the XAUI serial interface to the pins that are connected to the HSMC Port A of the Stratix IV GX development board.

■ For the 10GbE MAC with 10GBASE-R design example, type the following

command:

source setup_EP4S100G2F40I1.tcl

This command assigns the 10GBASE-R serial interface to the pins that are connected to the SMA connectors (J38 to J41) of the Stratix IV GT development board.

f For more information about the development boards, refer to the respective

reference manuals: Stratix IV GX Development Kit Reference Manual or

Transceiver Signal Integrity Development kit, Stratix IV GT Edition Reference Manual.

5. Launch Qsys from the Tools menu and open the altera_eth_10g_mac_base_r.qsys or altera_eth_10g_mac_xaui.qsys file. For design targeting the Stratix V device family, use the altera_eth_10g_mac_base_r_sv.qsys or altera_eth_10g_mac_xaui_sv.qsys file.

1 By default, the design example targets the Stratix IV device family. To

change the target device family, click on the Project Settings tab and select the desired device from the Device family list.

6. Turn off the additional module under the Use column if your design does not require them. This action disconnects the module from the 10GbE system.

7. Double-click eth_10g_design_example_0 to launch the parameter editor.

8. Specify the required parameters in the parameter editor. For detailed explanations of these parameters, refer to “10GbE Design Example Parameter Settings” on

page 3–8.

9. Click Finish.

10. On the Generation tab, select either a Verilog HDL or a VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on.

11. Click Generate to generate the simulation and synthesis files.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–8 Chapter 3: 10GbE MAC Design Examples

10GbE Design Example Parameter Settings

3.5. 10GbE Design Example Parameter Settings

You can customize the 10GbE design example by specifying the parameters using the parameter editor. Ta ble 3–4 describes these parameters.

Table 3–4. Design Example Parameters

Name Value Description

Configuration

Specifies whether the Ethernet system requires a MDIO core to access the external PHY device management registers for configuration and management purposes.

Specifies which protocol-specific PHY IP core to use for the Ethernet system. For XAUI PHY, you can choose to implement the system in soft or hard logic.

Specifies which FIFO buffer to use for the Ethernet system. The Avalon-ST Single Clock FIFO operates with a common clock for the input and output ports while the Avalon-ST Dual Clock FIFO operates with independent clocks for the input and output ports.

You cannot enable a different FIFO option for TX datapath and RX datapath. If you select Avalon-ST Single Clock FIFO, the design includes single clock FIFO at both TX and RX datapaths.

MDIO

PHY IP

FIFO

MDIO

None

XAUI PHY

10GBase-R PHY

None

Avalon-ST Single Clock FIFO

Avalon-ST Dual Clock FIFO

Avalon-ST Single Clock FIFO + Avalon-ST Dual Clock FIFO

None

1 The parameter values you select on Configuration tab correspond with the

other tabs that require further parameterization. You should only parameterize the components you selected and omit the others. Editing the component parameters that were not selected may cause the system generation to fail.

f For more information about the parameter settings of other components,

refer to the respective documents:

■ 10GbE MAC, refer to “10GbE MAC Parameter Settings” on page 2–6.

■ Avalon-ST Single-Clock or Dual-Clock FIFO and MDIO core, refer to

Embedded Peripherals IP User Guide.

■ XAUI PHY and 10GBASE-R PHY, refer to Altera Transceiver PHY IP Core

User Guide.

3.6. 10GbE Testbenches

Altera provides testbenches for you to verify the design examples. The following sections in this document describe the testbench, its components, and use.

3.6.1. 10GbE Testbench

The testbenches operate in loopback mode. Figure 3–3 shows the flow of the packets.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–9

10GbE Testbenches

Figure 3–3. Testbench Block Diagram

Testbench

Ethernet

Packet

Avalon-MM

Control

Avalon-ST

Transmit

Frame

Generator

Monitor

Avalon-ST

DUT

Avalon-MM

Loopback on XGMII

Avalon-ST

Receive

Frame

Monitor

avalon_bfm_wrapper.sv

Avalon Driver

Avalon-ST

Ethernet

Monitor

3.6.2. 10GbE Testbench Component

The 10GbE testbench comprises the following modules:

■ Device under test (DUT)—the design example.

■ Avalon driver—uses Avalon-ST bus functional models (BFMs) to exercise the

transmit and receive paths. The driver also utilizes the Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.

■ Packet monitors—monitors the transmit and receive datapaths, and displays the

frames in the simulator console.

3.6.3. 10GbE Testbench Files

The following directories contain the 10GbE testbench files which are in clear text:

Packet

■ 10GbE MAC and XAUI PHY testbench—<ip library>/ethernet/

altera_eth_10g_design_example/altera_eth_10g_mac_xaui/testbench

■ 10GbE MAC and 10GBASE-R PHY testbench— <ip library>/ethernet/

altera_eth_10g_design_example/altera_eth_10g_mac_base_r/testbench

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–10 Chapter 3: 10GbE MAC Design Examples

10GbE Testbenches

Tab le 3– 5 describes the files that implement the testbench.

Table 3–5. Testbench Files

File Name Description

avalon_bfm_wrapper.sv

A wrapper for the Avalon BFMs that the avalon_driver.sv file uses.

A SystemVerilog HDL driver that utilizes the BFMs to exercise

avalon_driver.sv

the transmit and receive path, and access the Avalon-MM interface.

A SystemVerilog HDL testbench that contains parameters to

avalon_if_params_pkg.sv

configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file.

avalon_st_eth_packet_monitor.sv

eth_mac_frame.sv

eth_register_map_params_pkg.sv

tb_run.tcl

tb_run_sv.tcl

A SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receive interfaces.

A SystemVerilog HDL class that defines the Ethernet frames. The avalon_driver.sv file uses this class.

A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers.

A Tcl script that starts a simulation session in the ModelSim simulation software. Not applicable for Stratix V design.

A Tcl script that starts a simulation session in the ModelSim simulation software for Stratix V design only.

The top-level testbench file. This file includes the customized

tb.sv

10GbE MAC which is the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks. Not applicable for Stratix V design.

The top-level testbench file for Stratix V design only. This file

tb_sv.sv

includes the customized 10GbE MAC which is the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks.

wave.do

A signal tracing macro script to be used with the ModelSim simulation software to display testbench signals.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–11

10GbE Testbenches

3.6.4. 10GbE Testbench Simulation Flow

Upon a simulated power-on reset, each testbench performs the following operations:

1. Initializes the DUT by configuring the following options via the Avalon-MM interface:

a. In the MAC, enables address insertion on the transmit path and sets the

transmit primary MAC address to EE-CC-88-CC-AA-EE.

b. In the TX and RX FIFO (Avalon-ST Single Clock FIFO core), enables drop on

error.

2. Starts packet transmission. The testbench sends a total of eight packets:

a. 64-byte basic Ethernet frame

b. Pause frame

c. 1518-byte VLAN frame

d. 1518-byte basic Ethernet frame

e. 64-byte stacked VLAN frame

f. 500-byte VLAN frame

g. Pause frame

h. 1518-byte stacked VLAN frame

3. Ends the transmission and displays the MAC statistics in the transcript pane.

3.6.5. Simulating the 10GbE Testbench with the ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

1. Copy the respective design example directory to your preferred project directory: altera_eth_10g_mac_xaui or altera_eth_10g_mac_base_r from <ip library>/ethernet/altera_eth_10g_design_example.

2. The design example and testbench files are set to read only. Altera recommends that you turn off the read-only attribute of all design example and testbench files.

3. Launch the Quartus II software and open the top.v file from the project directory.

4. Open the Quartus II Tcl Console window by pointing to Utility Windows on the View menu and then selecting Tcl Co ns ol e. In the Quartus II Tcl Console window, type the following command to set up the project environment:

source setup_proj.tcl

5. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_r.qsys or altera_eth_10g_mac_xaui.qsys in the File menu.

6. For the 10GbE MAC with XAUI design example, the default setting of the XAUI PHY is Hard XAUI. Follow these steps if you want to set the PHY to Soft XAUI:

a. Double-click the XAUI PHY module to open the parameter editor.

b. On the General Options tab, select Soft XAUI for XAUI Interface Type.

7. On the Generation tab, select Verilog simulation model.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–12 Chapter 3: 10GbE MAC Design Examples

10GbE Testbenches

8. Click Generate to generate the system.Launch the ModelSim simulator software.

9. Change the working directory to <project directory>/<design example directory>/testbench in the File menu.

10. Run the following command to set up the required libraries, compile the generated IP Functional simulation model, and exercise the simulation model with the provided testbench:

do tb_run.tcl

The ModelSim transcript pane in Main window displays messages from the testbench reflecting the current task being performed.

Upon a successful simulation, the simulator displays the following and

TX Statistics

# framesOK = 8 # framesErr = 0 # framesCRCErr = 0 # octetsOK = 5138 # pauseMACCtrlFrames = 2 # ifErrors = 0 # unicastFramesOK = 4 # unicastFramesErr = 0 # multicastFramesOK = 1 # multicastFramesErr = 0 # broadcastFramesOK = 1 # broadcastFramesErr = 0 # etherStatsOctets = 5310 # etherStatsPkts = 8 # etherStatsUndersizePkts = 0 # etherStatsOversizePkts = 0 # etherStatsPkts64Octets = 4 # etherStatsPkts65to127Octets = 0 # etherStatsPkts128to255Octets = 0 # etherStatsPkts256to511Octet = 1 # etherStatsPkts512to1023Octets = 0 # etherStatsPkts1024to1518Octets = 3 # etherStatsPkts1519OtoXOctets = 0 # etherStatsFragments = 0 # etherStatsJabbers = 0 # etherStatsCRCErr = 0 # unicastMACCtrlFrames = 1 # multicastMACCtrlFrames = 1 # broadcastMACCtrlFrames = 0

RX Statistics

3.6.6. Enabling Local Loopback

You can turn on local loopback to verify the functionality of the MAC during simulation. Follow these steps to enable local loopback:

1. Open the tb.sv file.

2. Insert the command offset is the sum of the base address of the loopback module and the register offset, and value is the value to write to the register.

3. Set value to 1 to enable local loopback; 0 to disable it. Altera recommends that you insert the command after the command that configures the RX FIFO. For example, the following code segment enables local loopback:

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

U_AVALON_DRIVER.avalon_mm_csr_wr(offset,value)

where

Chapter 3: 10GbE MAC Design Examples 3–13

csr_clk_clk

csr_reset_reset_n

csr_address [18:0]

csr_read

csr_readdata [31:0]

csr_write

csr_writedata [31:0]

csr_waitrequest

40084

00000002

10GbE Testbenches

// Configure the RX FIFO U_AVALON_DRIVER.avalon_mm_csr_wr(RX_FIFO_DROP_ON_ERROR_ADDR,RX_FIFO_DROP_ON_ERROR);

// Read the configured registers U_AVALON_DRIVER.avalon_mm_csr_rd(RX_FIFO_DROP_ON_ERROR_ADDR, readdata); $display("RX FIFO Drop on Error Enable = %0d", readdata[0]);

U_AVALON_DRIVER.avalon_mm_csr_wr(32'h948, 1)

4. Run the following command again to reconfigure the loopback module, set up the required libraries, compile the generated IP Functional simulation model, and exercise the simulation model:

do tb_run.tcl

3.6.7. 10GbE Simulation Timing Diagrams

Figure 3–4 shows the reset and initial configuration sequence. The first read or write

transaction must be at least one clock cycle after the completes.

Figure 3–4. Reset and Configuration

csr_reset_reset_n

signal

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–14 Chapter 3: 10GbE MAC Design Examples

10GbE Testbenches

Figure 3–5 shows the transmission of the first 60-byte frame upon a successful reset

and initial configuration. The same frame is looped back to the receive datapath.

Figure 3–5. Frame Transmission and Reception

Loopback

tx_clk_clk

avalon_st_tx_ready

avalon_st_tx_valid

avalon_st_tx_startofpacket

avalon_st_tx_endofpacket

avalon_st_tx_data [63:0]

avalon_st_tx_empty [2:0]

avalon_st_tx_error

0 4 0

rx_clk_clk

avalon_st_rx_ready

avalon_st_rx_valid

avalon_st_rx_startofpacket

avalon_st_rx_endofpacket

avalon_st_rx_data [63:0]

avalon_st_rx_empty [2:0]

avalon_st_rx_error [5:0]

0 4

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–15

10GbE Design Example Compilation and Verification in Hardware

3.7. 10GbE Design Example Compilation and Verification in Hardware

Figure 3–6 shows the components in the top-level file provided with the 10GbE

design example.

Figure 3–6. 10GbE Top-Level Components

Altera Development Board

Address Swapper

Avalon-ST

The address swapper swaps the destination address and source address in the receive frame before sending the frame onto the transmit path. You must connect the DUT— design example—to a remote partner that generates, transmits, and receives frames.

3.7.1. Compiling the 10GbE Design

You can use the Quartus II software to compile the design example and program the targeted Altera device after a successful compilation.

Follow these steps to compile the design and program the device:

1. Copy the respective design example directory to your preferred project directory: altera_eth_10g_mac_xaui or altera_eth_10g_mac_base_r from <ip library>/ethernet/altera_eth_10g_design_example.

2. Launch the Quartus II software and open top.v from the project directory.

3. Open the Quartus II Tcl Console window by pointing to Utility Windows on the View menu then clicking Tc l Co ns o le . In the Quartus II Tcl Console window, type the following command to set up the project environment:

DUT

XAUI/

10GBASE-R

Remote Partner

source setup_proj.tcl

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–16 Chapter 3: 10GbE MAC Design Examples

10GbE Design Example Compilation and Verification in Hardware

4. Load the pin assignments and I/O standards for the development board:

■ For the 10GbE MAC with XAUI PHY design example, type the following

command:

source setup_SIVGX230C2ES.tcl

This command assigns the XAUI serial interface to the pins that are connected to the HSMC Port A of the Stratix IV GX development board.

■ For the 10GbE MAC with 10BASE-R design example, type the following

command:

source setup_EP4S100G2F40I1.tcl

This command assigns the 10GBASE-R serial interface to the pins that are connected to the SMA connectors (J38 to J41) of the Stratix IV GT development board.

f For more information about the development boards, refer to the respective

reference manuals: Stratix IV GX Development Kit Reference Manual or

Transceiver Signal Integrity Development kit, Stratix IV GT Edition Reference Manual.

5. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_r.qsys or altera_eth_10g_mac_xaui.qsys.

6. For the 10GbE MAC with XAUI PHY design example, the default setting of the PHY is Hard XAUI. Follow these steps if you want to set the PHY to Soft XAUI:

a. Double-click the XAUI PHY module to open the parameter editor.

b. On the General Options tab, select Soft XAUI for XAUI Interface Type.

7. Click Save on the File menu.

8. On the Generation tab, turn on Create Synthesis RTL Files.

9. Click Generate to generate the system.

10. Click Start Compilation on the Processing menu to compile the design example.

11. Upon a successful compilation, click Programmer on the Tools menu to program the device.

f For more information about device programming, refer to Quartus II Programmer in

volume 3 of the Quartus II Handbook.

1 If you are not using the Stratix IV GX FPGA development board or the Transceiver

Signal Integrity development board, Stratix IV GT Edition, modify setup_proj.tcl and setup_SIVGX230C2ES.tcl or setup_EP4S100G2F40I1.tcl to suit your hardware.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–17

10GbE Design Example Compilation and Verification in Hardware

3.7.2. Verifying the 10GbE Design in Hardware

After programming the targeted Altera device, follow these steps to verify your design and collect the statistics:

1. Copy the csr_scripts directory to the design example directory.

2. Launch Qsys and access the System Console by clicking System Console on the Tools menu.

3. Change the working directory to <project directory>/csr_scripts.

4. Type the following command to configure the design example:

source config.tcl

5. Start frame transmission on your remote partner to exercise the datapaths.

6. Type the following command to read and view the statistics:

source show_stats.tcl

1 The

config.tcl

connection.

3.7.3. Debugging

You can use the system console to perform the following tasks for debugging purposes:

■ Reconfigure the design example components and retrieve the registers during

runtime by following these steps:

a. Create a new Tcl script.

b. Add the following commands:

source common.tcl

# establishes the connection open

jtag

# use rd32 to retrieve the register value # base address = base address of the component # offset = byte offset of the register rd32 <base address> 0 <offset>

# use wr32 to configure the register # base address = base address of the component # offset = byte offset of the register # value = value to be written to the register wr32 <base address> 0 <offset> <value>

# closes the connection close

jtag

and

show_stats.tcl

scripts support only one USB-Blaster

Save and close the Tcl script and type the following command:

source

■ Retrieve and view the statistics counters by typing the following command:

source show_stats.tcl

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

.tcl

3–18 Chapter 3: 10GbE MAC Design Examples

■ Turn on the line loopback to verify the functionality of the XAUI/10GBASE-R

10GbE Design Example Compilation and Verification in Hardware

PHY by following these steps:

a. Edit the script config.tcl.

b. Add the command

write_line_loopback(value)

immediately after the command that establishes the JTAG connection. Set the argument value, to 1 to enable line loopback; 0 to disable line loopback. For example, the following codes enable line loopback:

open_jtag write_line_loopback 1

c. Save and close config.tcl, and type the following command:

source config.tcl

f For more information on the System Console, refer to Analyzing and Debugging Designs

with the System Console in volume 3 of the Quartus II Handbook.

3.7.4. 10GbE Design Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies:

■ Transmit latency is the number of clock cycles the MAC function takes to transmit

the first byte on the network-side interface (XGMII SDR) after the bit was first available on the Avalon-ST interface.

■ Receive latency is the number of clock cycles the MAC function takes to present

the first byte on the Avalon-ST interface after the bit was received on the network-side interface (XGMII SDR).

Tab le 3– 6 shows the transmit and receive nominal latencies of the design example.

Table 3–6. Transmit and Receive Latencies of the 10GbE Design Example

Latency (Clock Cycles) (1) (2)

Configuration

(with respect to TX clock)

Tra nsmit

Receive

(with respect to RX clock)

MAC and Ethernet loopback 10 13

Dual Core FIFO 6 6

Single Core FIFO 10 10

Soft XAUI PHY 41 (3)

Hard XAUI PHY 24 (3)

Soft 10GBASE-R PHY 56 (3)

Notes to Table 3–6:

(1) The clocks in all domains are running at the same frequency. (2) The latency values are based on the assumption that there is no backpressure on the Avalon-ST TX and RX

interface.

(3) Total latency for both transmit and receive in this design example targeting the Stratix IV device family.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 3: 10GbE MAC Design Examples 3–19

10GbE Design Example Compilation and Verification in Hardware

3.7.5. 10GbE Design Performance and Resource Utilization

Tab le 3– 7 provides the estimated performance and resource utilization of the 10GbE

design example obtained by compiling the design with the Quartus II software targeting the Stratix IV GX (EP4SGX230KF40C2ES) device with speed grade –2.

Table 3–7. Stratix IV Performance and Resource Utilization

Components

Combinational

ALUTs

Memory

ALUTs

Logic

Registers

Memory Block

(M9K)

MAX

(MHz)

MAC 4,054 36 4,710 6 156.25

Loopback 293 0 182 4 156.25

RX SC FIFO 23102105156.25

TX SC FIFO 212 0 210 4 156.25

Hard XAUI PHY 1,892 0 1,215 0 156.25

MDIO 11601330156.25

JTAG Master 523 0 440 1 156.25

Address Swapper 66 0 71 0 156.25

Qsys Fabric 993 2 1,018 0 156.25

Total Resource Utilization 7,840 38 8,019 20 156.25

Tab le 3– 8 provides the estimated performance and resource utilization of the 10GbE

design example obtained by compiling the design with the Quartus II software targeting the Cyclone V GX (5CGXFC7D6F31C6) device with speed grade –6.

Table 3–8. Cyclone V Performance and Resource Utilization

Components

Combinational

ALUTs

Logic Registers

Memory Block

(M10K)

MAX

(MHz)

MAC 4,417 5,464 6 156.25

Loopback 291 199 4 156.25

RX SC FIFO 242 231 4 156.25

TX SC FIFO 215 232 4 156.25

MDIO 118 144 0 156.25

Soft XAUI 1,642 1,750 3 156.25

JTAG Master 537 468 1 156.25

Address Swapper 66 71 0 156.25

Qsys Fabric 444 688 1 156.25

Total Resource Utilization 7,972 9,247 23 156.25

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

3–20 Chapter 3: 10GbE MAC Design Examples

10GbE Design Example Compilation and Verification in Hardware

Tab le 3– 9 provides the estimated performance and resource utilization of the 10GbE

design example obtained by compiling the design with the Quartus II software targeting the Stratix V GX (5SGXEA7N2F40C2ES) device with speed grade –2.

Table 3–9. Stratix V Performance and Resource Utilization

Components

Combinational

ALUTs

Memory ALUTs Logic Registers

Memory Block

(M9K)

MAX

(MHz)

MAC 4,110 17 5,212 4 156.25

Loopback 290 0 187 4 156.25

RX SC FIFO 234 0 236 2 156.25

TX SC FIFO 220 0 246 2 156.25

MDIO 11501460156.25

10GBASE-R PHY 112 0 114 0 156.25

JTAG Master 519 0 508 1 156.25

Address Swapper 66 0 74 0 156.25

Qsys Fabric 441 0 679 0 156.25

Total Resource Utilization 6,107 0 7,402 13 156.25

Tab le 3– 10 provides the estimated performance and resource utilization of the design

example with the IEEE 1588v2 feature enabled, obtained by compiling the design with the Quartus II software targeting a Stratix V (5SGTMC5K2F40C2) device with speed grade -2.

Table 3–10. Stratix V Performance and Resource Utilization with IEEE 1588v2 Feature

Components

Combinational

ALUTs

Logic Registers

Memory Block

(M20K)

DSP Block f

MAX

(MHz)

MAC 6,822 7,459 10 2 156.25

Loopback 291 264 4 0 156.25

10GBASE-R PHY 1,066 1,675 6 0 156.25

Time-of-Day (ToD) Clock 812 2,268 0 0 156.25

Transceiver Reconfiguration

1,245 871 6 0 156.25

Qsys Fabric 83 73 0 0 156.25

Total Resource Utilization 10,319 12,610 26 2 156.25

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

This section describes the 10GbE MAC with IEEE 1588v2 design example, testbench and its components.

1 10GBASE-R PHY does not support Stratix III devices.

4.1. Software Requirements

Altera uses the following software to test the 10GbE with IEEE 1588v2 design example and testbench:

■ Quartus II software 13.1

■ ModelSim-SE 10.0b or higher

4. 10GbE MAC with IEEE1588v2 Design Example

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

4–2 Chapter 4: 10GbE MAC with IEEE1588v2 Design Example

Ethernet

Packet

Classifier

Pulse Per

Second Module

Time of

Day

Clock

Time of Day

10GbE MAC

Avalon MM Master

Translator

Client Application

(Configuration,

Status & Statistics)

Transceiver

Reconfiguration

Controller

10GBASE-R PHY

External PHY

10GBASE-R

72-Bit SDR

XGMII

64-Bit

Avalon ST

Time

of Day

32-Bit

Avalon MM

Reconfiguration

32-Bit

Avalon MM

64-Bit

Avalon ST

Pulse Per

Second

Timestamp & Fingerprint

Client Application

Altera FPGA

Design Example

Ethernet Loopback

72-Bit SDR

XGMII

10GbE with IEEE 1588v2 Design Example Components

4.2. 10GbE with IEEE 1588v2 Design Example Components

You can use the 10GbE MAC IP core design example to simulate a complete 10GbE with IEEE 1588v2 design in a simulator. You can compile the design example using the Quartus II software and program the targeted Altera device after a successful compilation.

Figure 4–1 shows the block diagram of the 10GbE with IEEE 1588v2 design example.

Figure 4–1. 10GbE with IEEE 1588v2 Design Example Block Diagram

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 4: 10GbE MAC with IEEE1588v2 Design Example 4–3

10GbE with IEEE 1588v2 Design Example Components

The 10GbE with IEEE 1588v2 design example comprises the following components:

■ Altera Ethernet 10G design example—the default 10G design example that has the

following settings:

■ 10GbE Ethernet MAC—the MAC IP core with IEEE 1588v2 option enabled.

■ 10GBASE-R PHY—the PHY IP core with IEEE 1588v2 option enabled.

■ Ethernet Loopback—the loopback module provides a mechanism for you to

verify the functionality of the MAC and PHY.

■ MDIO and FIFO features turned off.

■ Transceiver Reconfiguration Controller—dynamically calibrates and reconfigures

the features of the PHY IP cores.

■ Ethernet Packet Classifier—decodes the packet type of incoming PTP packets and

returns the decoded information to the 10GbE Ethernet MAC.

■ Ethernet Time-of-Day (ToD) Clock—provides 64-bits and/or 96-bits time-of-day to

TX and RX of 10GbE Ethernet MAC.

■ Pulse Per Second Module—returns pulse per second (pps) to user.

■ Avalon MM Master Translator—provides access to the registers of the following

components through the Avalon-MM interface:

■ MAC and Ethernet Loopback

■ Transceiver Reconfiguration Controller

■ ToD

f For more information about ToD clock, refer to Appendix B, Time-of-Day (ToD)

Clock; and for more information about Packet Classifier, refer to Appendix C, Packet Classifier.

4.2.1. Base Addresses

Tab le 4– 1 lists the design example components that you can reconfigure to suit your

verification objectives. To reconfigure the components, write to their registers using the base addresses listed in the table and the register offsets described in the components' user guides.

Table 4–1. Base Addresses of 10GbE with IEEE 1588v2 Design Example Components

Component Base Address

MAC and Ethernet Loopback 0x00000

Transceiver Reconfiguration Controller 0x80400

Time of Day Clock 0x81000

1 This design example uses a 19-bit width address bus to access the base address of

components other than the MAC.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

4–4 Chapter 4: 10GbE MAC with IEEE1588v2 Design Example

10GbE with IEEE 1588v2 Design Example Files

4.3. 10GbE with IEEE 1588v2 Design Example Files

Tab le 4– 2 shows the directory structure for the 10GbE with IEEE 1588v2 design

examples and testbenches.

Figure 4–2. 10GbE with IEEE 1588v2 Design Example Folders

<ip_lib>/ethernet/altera_eth_10g_design_example

altera_eth_10g_mac_base_r_1588

testbench

Tab le 4– 2 lists the files in the

Table 4–2. 10GbE with IEEE 1588v2 Design Example Files

File Name Description

altera_eth_10g_mac_base_r_1588_top.v

altera_eth_10g_mac_base_r_1588_top.sdc

altera_eth_10g_mac_base_r_1588.qsys

..\altera_eth_10g_mac_base_r_1588 directory.

The top-level entity file of the design example for verification in hardware.

The Quartus II SDC constraint file for use with the TimeQuest timing analyzer.

A Qsys file for the 10GbE MAC and 10GBASE-R PHY design example with IEEE 1588v2 option enabled.

4.4. Creating a New 10GbE with IEEE 1588v2 Design

You can use the Quartus II software to create a new 10GbE with IEEE 1588v2 design. Altera provides a Qsys design example file that you can customize to facilitate the development of your 10GbE with IEEE 1588v2 design.

To create the design, perform the following steps:

1. Launch the Quartus II software and open the altera_eth_10g_mac_base_r_1588_top.v file from the project directory.

2. Launch Qsys from the Tools menu and open the altera_eth_10g_mac_base_r_1588.qsys file. By default, the design example targets the Stratix V device family. To change the target device family, click on the Project Settings tab and select the desired device from the Device family list.

3. Turn off the additional module under the Use column if your design does not require it. This action disconnects the module from the 10GbE with IEEE 1588v2 system.

4. Double-click on eth_10g_design_example_0 to launch the parameter editor.

5. Specify the required parameters in the parameter editor.

6. Click Finish.

7. On the Generation tab, select either a Verilog HDL or VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 4: 10GbE MAC with IEEE1588v2 Design Example 4–5

10GbE with IEEE 1588v2 Testbench

8. Click Generate to generate the simulation and synthesis files.

4.5. 10GbE with IEEE 1588v2 Testbench

Altera provides testbench for you to verify the 10GbE with IEEE 1588v2 design example. The following sections in this document describe the testbench, its components, and use.

4.5.1. 10GbE with IEEE 1588v2 Testbench

The testbenches operate in loopback mode. Figure 4–3 shows the flow of the packets.

Figure 4–3. Testbench

Testbench

Ethernet

Packet

Avalon-MM

Control

Monitor

Avalon-MM

Avalon-ST

Transmit

Frame

Generator

Avalon-ST

Receive

Frame

Monitor

avalon_bfm_wrapper.sv

Avalon Driver

Avalon-ST

DUT

Avalon-ST

Ethernet

Packet

Monitor

4.5.2. 10GbE with IEEE 1588v2 Testbench Components

The testbenches comprise the following modules:

■ Device under test (DUT)—the design example.

■ Avalon driver—uses Avalon-ST bus functional models (BFMs) to exercise the

transmit and receive paths. The driver also utilizes the Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.

■ Packet monitors—monitors the transmit and receive datapaths, and displays the

frames in the simulator console.

Loopback on XGMII

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

4–6 Chapter 4: 10GbE MAC with IEEE1588v2 Design Example

10GbE with IEEE 1588v2 Testbench

4.5.3. 10GbE with IEEE 1588v2 Testbench Files

The <ip library>/ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_base_r_1588

/testbench directory contains the testbench files.

Tab le 4– 3 describes the files that implement the 10GbE with IEEE 1588v2 testbench.

Table 4–3. 10GbE with IEEE 1588v2 Testbench Files

File Name Description

avalon_bfm_wrapper.sv

avalon_driver.sv

avalon_if_params_pkg.sv

avalon_st_eth_packet_monitor.sv

default_test_params_pkg.sv

eth_mac_frame.sv

eth_register_map_params_pkg.sv

ptp_timestamp.sv

tb_run_simulation.tcl

tb_testcase.sv

tb_top.sv

wave.do

A wrapper for the Avalon BFMs that the avalon_driver.sv file uses.

A SystemVerilog HDL driver that utilizes the BFMs to exercise the transmit and receive path, and access the Avalon-MM interface.

A SystemVerilog HDL testbench that contains parameters to configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file.

A SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receive interfaces.

A SystemVerilog HDL package that contains the default parameter settings of the testbench.

A SystemVerilog HDL class that defines the Ethernet frames. The avalon_driver.sv file uses this class.

A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers.

A SystemVerilog HDL class that defines the timestamp in the testbench.

A Tcl script that starts a simulation session in the ModelSim simulation software.

A SystemVerilog HDL testbench file that controls the flow of the testbench.

The top-level testbench file. This file includes the customized 10GbE MAC, which is the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks.

A signal tracing macro script for use with the ModelSim simulation software to display testbench signals.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 4: 10GbE MAC with IEEE1588v2 Design Example 4–7

10GbE with IEEE 1588v2 Testbench

4.5.4. 10GbE with IEEE 1588v2 Testbench Simulation Flow

Upon a simulated power-on reset, each testbench performs the following operations:

1. Initializes the DUT by configuring the following options through the Avalon-MM interface:

■ Configures the MAC. In the MAC, enables address insertion on the transmit

path and sets the transmit and receive primary MAC address to EE-CC-88-CCAA-EE. Also enables CRC insertion on transmit path.

■ Configures Timestamp Unit in the MAC, by setting periods and path delay

adjustments of the clocks.

■ Configures ToD clock by loading a predefined time value.

■ Configures clock mode of Packet Classifier to Ordinary Clock mode.

2. Starts packet transmission with different clock mode. The testbench sends a total of four packets:

■ 64-byte basic Ethernet frames

■ 1-step PTP Sync message over Ethernet

■ 1-step PTP Sync message over UDP/IPv4 with VLAN tag

■ 2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag

3. Configures clock mode of Packet Classifier to End-to-end Transparent Clock mode.

4. Starts packet transmission. The testbench sends a total of three packets:

■ 1-step PTP Sync message over Ethernet

■ 2-step PTP Sync message over UDP/IPv4 with VLAN tag

■ 1-step PTP Sync message over UDP/IPv6 with stacked VLAN tag

5. Ends the transmission.

4.5.5. Simulating 10GbE with IEEE 1588v2 Testbench with ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

1. Copy the respective design example directory to your preferred project directory: altera_eth_10g_mac_base_r_1588 from <ip library>/ethernet/altera_eth_10g_design_example.

2. Launch Qsys from the Tools menu and open the altera_eth_10g_mac_base_r_1588.qsys file.

3. On the Generation tab, select either a Verilog HDL or VHDL simulation model.

4. Click Generate to generate the simulation and synthesis files.

5. Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench:

do tb_run_simulation.tcl

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5. 1G/10GbE MAC Design Example

This section describes the 1G/10GbE MAC with Backplane Ethernet Backplane Ethernet 10GBASE-KR PHY design example, the testbench, and its components. You can configure the Backplane Ethernet 10GBASE-KR PHY IP to the following modes:

■ Backplane-KR mode to interface with copper backplane

■ 1G/10Gb Ethernet mode to interface with optical SFP+ modules or copper PHY

devices

1 Backplane Ethernet 10GBASE-KR PHY only supports Arria V GZ and Stratix V

devices.

5.1. Software and Hardware Requirements

Altera uses the following hardware and software to test the 1G/10GbE design example and testbench:

■ Altera Complete Design Suite 13.0

■ Backplane Ethernet 10GBASE-KR PHY

■ Transceiver Signal Integrity Development Kit, Stratix V GX Edition

■ ModelSim-AE 6.6c, ModelSim-SE 6.6c or higher

1 The 1G/10GbE mode is only supported in the production silicon version of the

development board.

f For more information about the development kit, refer to Transceiver Signal Integrity

Development Kit, Stratix V GX Edition User Guide.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–2 Chapter 5: 1G/10GbE MAC Design Example

System Console

(for Debugging)

Client Application

(Configuration, Status,

and Statistics)

JTAG to Avalon

Master Bridge

Pipeline Bridge

Configuration and Debugging Tools

PHY IP

Reset Controller

PHY IP

Reset Controller

1G/10GbE MAC

10GBASE-KR PHY

External PHY

64-Bit

Avalon-ST

GIGE/

10GBASE-R

TX FIFO

Buffer

RX FIFO

Buffer

Avalon-ST Single-Clock FIFO

1G/10GbE MAC

10GBASE-KR PHY

External PHY

64-Bit

Avalon-ST

GIGE/

10GBASE-R

TX FIFO

Buffer

RX FIFO

Buffer

Avalon-ST Single-Clock FIFO

Reconfiguration

Bundle

Altera FPGA

1G/10GbE Design Example Components

5.2. 1G/10GbE Design Example Components

You can use the 1G/10GbE MAC IP core design example to simulate a complete 1G/10GbE design in an Altera FPGA. You can compile the design example using the simulation files generated by the Quartus II software and program the targeted Altera device after a successful compilation.

Figure 5–1 shows the block diagram of a two-channel 1G/10GbE design example.

Figure 5–1. Two-Channel 1G/10GbE Design Example Block Diagram

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 5: 1G/10GbE MAC Design Example 5–3

Single-Clock

FIFO

Single-Clock

FIFO

PLL

JTAG to Avalon

Master Bridge

Pipeline

Bridge

10GBASE-KR

PHY

1G/10GbE

MAC

Configure

Reconfig

gmii_rx_clk

gmii_tx_clk

rx_coreclkin_1g

rx_clkout_1g

xgmii_rx_clk

tx_clkout_1g

xgmii_tx_clk

tx_coreclkin_1g

rx_clk

ref clk

322.265625

ref clk

125

mm clk

100

tx_clk

125 Mhz

156.25 Mhz

Reconfiguration

Bundle

PHY IP

Reset Controller

1G/10GbE Design Example Components

Figure 5–2 shows the clocking scheme for the design example.

Figure 5–2. 1G/10GbE Design Example Clocking Scheme

The 1G/10GbE design example comprises the following components:

■ 1G/10GbE Ethernet MAC—the MAC IP core with default settings. This IP core

includes memory-based statistics counters.

■ Backplane Ethernet 10GBASE-KR PHY—the PHY IP core operating as either

■ Reconfiguration Bundle—comprises the reconfiguration controller that switches

1000BASE-X PHY or 10GBASE-R PHY.

the speed between 1 Gbps and 10 Gbps, and the management ROM that stores MIF information for 1/10GbE PHY or HSSI or hard PCS. This block arbitrates the access to the reconfiguration controller and requests the reconfiguration controller to start streaming MIF information.

■ Single-Clock FIFO—Avalon-ST Single-Clock RX and TX FIFO cores that buffer

receive and transmit data between the MAC and the client. These FIFO buffers are 64 bits wide and 2048 bits deep. The Single-Clock FIFO operates in store and forward mode, and you can configure it to provide packet-based flushing when an error occurs.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–4 Chapter 5: 1G/10GbE MAC Design Example

1G/10GbE Design Example Components

1 To enable the Avalon-ST Single-Clock FIFO to operate in cut through mode,

turn off the Use store and forward parameter in the Avalon-ST Single Clock FIFO parameter editor.

■ PHY IP Reset Controller—configurable IP core that you can use to reset the

transceivers. Refer to the Transceiver PHY Reset Controller IP Core chapter in the

Altera Transceiver PHY IP Core User Guide for more information.

■ Configure Reconfiguration Block—provides the Avalon-MM interface to drive the

reconfiguration bundle component to switch speed.

1 This component is required only if the automatic speed detection parameter

in the Backplane Ethernet 10GBASE-KR PHY is not enabled.

5.2.1. Reconfiguration Bundle Parameters

Tab le 5– 1 lists the parameters for the reconfiguration bundle block.

Table 5–1. Reconfiguration Bundle Parameters

Parameter Description

PMA_RD_AFTER_WRITE

CHANNELS

PLLS

SYNTH_1588_1G

SYNTH_1588_10G

KR_PHY_SYNTH_LT

KR_PHY_SYNTH_AN

KR_PHY_SYNTH_GIGE

Always set this parameter to 0.

The number of channels instantiated for the Backplane Ethernet 10GBASE-KR PHY IP.

The number of PLLs.

If you turn on the 1G mode in the Backplane Ethernet 10GBASE-KR PHY IP, this value will be two times the value of the CHANNELS parameter.

Set this parameter to 1 if you use 1G mode with the 1588 options turned on in the Backplane Ethernet 10GBASE-KR PHY IP.

Set this parameter to 1 if you use 10G mode with the 1588 options turned on in the Backplane Ethernet 10GBASE-KR PHY IP.

Set this parameter to 1 if the Enable Link Training (LT) option is turned on in the Backplane Ethernet 10GBASE-KR PHY IP.

Set this parameter to 1 if the Enable Auto Negotiation (AN) option is turned on in the Backplane Ethernet 10GBASE-KR PHY IP.

Set this parameter to 1 if you use 1G mode in the Backplane Ethernet 10GBASE-KR PHY IP.

5.2.2. Base Addresses

Tab le 5– 2 lists the design example components that you can configure to suit your

verification objectives. To configure the components, write to their registers using the base addresses listed in the table and the register offsets described in the components' user guides.

Table 5–2. Base Addresses of 1G/10GbE Design Example Components

Component Base Address

1G/10GbE MAC Channel 0 0x00000

1G/10GbE MAC Channel 1 0x20000

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 5: 1G/10GbE MAC Design Example 5–5

1G/10GbE Design Example Files

Table 5–2. Base Addresses of 1G/10GbE Design Example Components

Component Base Address

10GBASE-KR Channel 0 0x80000

10GBASE-KR Channel 1 0x80800

Configure Reconfiguration Channel 0 0x80400

Configure Reconfiguration Channel 1 0x80500

RX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 0x10400

TX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 0x10600

RX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 0x30400

TX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 0x30600

1 This design example uses a 19-bit width address bus to access the base address of

components other than the MAC.

f For more information about the 10GBASE-KR, refer to the 10GBASE-KR PHY IP Core

chapter in the Altera Transceiver PHY IP Core User Guide.

5.3. 1G/10GbE Design Example Files

Figure 5–3 shows the directory structure for the 1G/10GbE design examples and

testbenches.

Figure 5–3. 1G/10GbE Design Example Folders

<ip_lib>/ethernet/altera_eth_10g_design_example

altera_eth_10g_mac_base_kr

Tab le 5– 3 lists the files in the

Table 5–3. 1G/10GbE Design Example Files

File Name Description

altera_eth_10g_mac_base_kr_top.v

altera_eth_10g_mac_base_kr_top.sdc

setup_proj.tcl

altera_eth_10g_mac_base_kr.qsys

reconfig.v

..\altera_eth_10g_mac_base_kr directory.

testbench

reconfig

The top-level entity file of the design example for verification in hardware.

The Quartus II SDC constraint file for use with the TimeQuest timing analyzer.

A Tcl script that creates a new Quartus II project and sets up the project environment for your design example.

A Qsys file for the 1G/10GbE MAC and 10G BASE-KR PHY design example with the Quartus II software targeting the Stratix V device.

A top-level entity file for the transceiver reconfiguration controller IP.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–6 Chapter 5: 1G/10GbE MAC Design Example

Creating a New 1G/10GbE Design

5.4. Creating a New 1G/10GbE Design

You can use the Quartus II software to create a new 1G/10GbE design. Altera provides a Qsys design example file that you can customize to facilitate the development of your 1G/10GbE design.

To create the design, perform the following steps:

1. Launch the Quartus II software and open the altera_eth_10g_mac_base_kr_top.v file from the project directory.

2. Open the Quartus II Tcl Console window by pointing to Utility Windows on the View menu and then selecting Tcl Co ns ol e. In the Quartus II Tcl Console window, type the following command to set up the project environment and load the necessary pins assignment for Stratix V GX signal integrity development kit board:

source setup_proj.tcl

f For more information about the development kit, refer to Signal Integrity

Development Kit, Stratix V GX Edition User Guide.

3. Launch Qsys from the Tools menu and open the altera_eth_10g_mac_base_kr.qsys file.

1 At this point you can edit the settings to suit your design using the

parameter editor.

4. Click Finish.

5. On the Generation tab, select either a Verilog HDL or VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on.

6. Click Generate to generate the simulation and synthesis files.

7. Launch the MegaWizard Plug-in Manager from the Tools menu. Select Edit an

existing custom megafunction variation and regenerate reconfig.v from the reconfig folder.

8. Click Finish.

5.5. 1G/10GbE Testbench

Altera provides testbench for you to verify the 1G/10GbE design example. The following sections describe the testbench, its components, and use.

5.5.1. 1G/10GbE Testbench

The testbench operates in loopback mode. Figure 5–4 shows the flow of the packets in the design example.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 5: 1G/10GbE MAC Design Example 5–7

1G/10GbE Testbench

Figure 5–4. 1G/10GbE Testbench Block Diagram

Testbench

Ethernet

Packe t

Avalon-MM

Control

Avalon-ST

Transmit

Frame

Generator

Monitor

Avalon-ST

DUT

Avalon-MM

Ordinary Clock

Channel-0

Loopback

on Serial

Avalon-ST

Receive

Frame

Monitor

avalon_bfm_wrapper.sv

Avalon Driver

Avalon-ST

Ethernet

Packe t

Monitor

5.5.2. 1G/10GbE Testbench Components

The testbenches comprise the following modules:

■ Device under test (DUT)—the design example.

■ Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise

the transmit and receive paths. The driver also uses the Avalon-MM master BFM to access the Avalon-MM interfaces of the design example components.

■ Packet monitors—monitors the transmit and receive datapaths, and displays the

frames in the simulator console.

5.5.3. 1G/10GbE Testbench Files

The <ip library>/ethernet/altera_eth_10g_design_example/testbench directory contains the testbench files.

Channel-1

Transparent Clock

Tab le 5– 4 describes the files that implement the 1G/10GbE testbench.

Table 5–4. 1G/10GbE Testbench Files

File Name Description

avalon_bfm_wrapper.sv

A wrapper for the Avalon BFMs that the avalon_driver.sv file uses.

A SystemVerilog HDL driver that utilizes the BFMs to exercise

avalon_driver.sv

the transmit and receive path, and access the Avalon-MM interface.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–8 Chapter 5: 1G/10GbE MAC Design Example

1G/10GbE Testbench

Table 5–4. 1G/10GbE Testbench Files

File Name Description

A SystemVerilog HDL testbench that contains parameters to

avalon_if_params_pkg.sv

configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file.

avalon_st_eth_packet_monitor.sv

eth_mac_frame.sv

eth_register_map_params_pkg.sv

tb_run.tcl

A SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receive interfaces.

A SystemVerilog HDL class that defines the Ethernet frames. The avalon_driver.sv file uses this class.

A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers.

A Tcl script that starts a simulation session in the ModelSim simulation software.

The top-level testbench file. This file includes the customized

tb.sv

1G/10GbE design example, which is the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks.

wave.do

A signal tracing macro script for use with the ModelSim simulation software to display testbench signals.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 5: 1G/10GbE MAC Design Example 5–9

1G/10GbE Testbench

5.5.4. 1G/10GbE Testbench Simulation Flow

The 1G/10GbE testbench provides two modes for simulation:

■ 1G/10Gb Ethernet mode

■ Backplane-KR mode

By default the testbench runs in 1G/10Gb Ethernet mode.

To switch to backplane-KR mode, open the tb.sv file and specify the

MODE_1G10G_KR_BAR

5.5.4.1. 1G/10Gb Ethernet Mode

Upon a simulated power-on reset, the testbench performs the following operations:

1. Initializes the DUT by configuring the following options through the Avalon-MM interface:

a. Changes both channel 1 and channel 0 to be operating speed at 10 Gbps.

b. Configures the MAC. In the MAC, enables address insertion on the transmit

path and sets the transmit primary MAC address to EE-CC-88-CC-AA-EE.

parameter to 0.

c. In the TX and RX FIFO buffers (Avalon-ST Single Clock FIFO core), enables

drop on error.

d. Waits for both the MAC and PHY to be ready to receive data.

2. Starts packet transmission. The testbench sends a total of eight packets:

a. Three 64-byte basic Ethernet frames

b. 1518-byte VLAN frame

c. 1518-byte basic Ethernet frame

d. 64-byte stacked VLAN frame

e. 500-byte VLAN frame

f. 1518-byte stacked VLAN frame

3. Displays the MAC statistics in the transcript panel.

4. Changes the operating speed for both channels.

a. Changes the operating speed for both channels to 1 Gbps.

b. Disables clause 37 auto-negotiation for both channels.

c. Waits for both the MAC and PHY to be ready to receive data

5. Starts packet transmission. The testbench sends a total of eight packets:

a. Three 64-byte basic Ethernet frames

b. 1518-byte VLAN frame

c. 1518-byte basic Ethernet frame

d. 64-byte stacked VLAN frame

e. 500-byte VLAN frame

f. 1518-byte stacked VLAN frame

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–10 Chapter 5: 1G/10GbE MAC Design Example

1G/10GbE Testbench

6. Displays the MAC statistics in the transcript panel.

5.5.4.2. Backplane-KR Mode

To run backplane-KR mode in simulation, perform the following steps:

1. Open the altera_eth_10g_mac_base_kr.qsys file and edit the following 10GBASE-KR PHY instances of channels 1 and 0:

■ IP variant = Backplane-KR

■ Turn o n Enable Automatic Speed Detection.

■ Turn o n Enable Auto-negotiation.

■ Regenerate the Qsys system.

2. Change the default setting to backplane-KR mode.

3. Run simulation.

Upon a simulated power-on reset, the testbench performs the following operations:

1. Initializes the DUT by configuring the following options via the Avalon-MM interface:

a. Configures the MAC. In the MAC, enables address insertion on the transmit

path and sets the transmit primary MAC address to EE-CC-88-CC-AA-EE.

b. In the TX and RX FIFO buffers (Avalon-ST Single Clock FIFO core), enables

drop on error.

c. Checks if auto-negotiation status is completed.

d. Waits for both the MAC and PHY to be ready to receive data.

2. Starts packet transmission. The testbench sends a total of eight packets:

a. Three 64-byte basic Ethernet frames

b. 1518-byte VLAN frame

c. 1518-byte basic Ethernet frame

d. 64-byte stacked VLAN frame

e. 500-byte VLAN frame

f. 1518-byte stacked VLAN frame

3. Displays the MAC statistics in the transcript panel.

5.5.5. Simulating the 1G/10GbE Testbench with the ModelSim Simulator

To use the ModelSim simulator to simulate the 1G/10GbE testbench design, perform the following steps:

1. Copy the

<ip library>/ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_bas e_kr directory to your preferred project directory.

2. The design example and testbench files are set to read only. Altera recommends that you turn off the read-only attribute of all design example and testbench files.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 5: 1G/10GbE MAC Design Example 5–11

1G/10GbE Testbench

3. Launch the Quartus II software and open the altera_eth_10g_mac_base_kr_top.v file from the project directory.

source setup_proj.tcl

5. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_kr.qsys in the File menu.

6. On the Generation tab, select Verilog simulation model.

By default, the system will be running in 1G/10Gb Ethernet mode. To run in backplane-KR mode, edit the following Backplane Ethernet 10GBASE-KR PHY instances of channels 1 and 0:

■ IP variant = Backplane-KR

■ Turn o n Enable Automatic Speed Detection.

■ Turn o n Enable Auto-negotiation.

7. Click Generate to generate the system.

8. Launch the ModelSim simulator software.

9. Change the working directory to <project directory>/<design example directory>/testbench in the File menu.

10. Run the following command to set up the required libraries, compile the generated IP Functional simulation model, and exercise the simulation model with the provided testbench:

do tb_run.tcl

By default the system will be running in 1G/10Gb Ethernet mode. To run in backplane-KR mode, open the tb.sv file and change the

MODE_1G10G_KR_BAR

parameter to 0, then run the command.

11. The ModelSim transcript pane in Main window displays messages from the testbench reflecting the current task being performed.

Upon a successful simulation, the simulator displays the following and

TX Statistics

# framesOK = 8

# framesErr = 0

# framesCRCErr = 0

# octetsOK = 5142

# pauseMACCtrlFrames = 0

# ifErrors = 0

# unicastFramesOK = 6

# unicastFramesErr = 0

# multicastFramesOK = 1

# multicastFramesErr = 0

# broadcastFramesOK = 1

RX Statistics

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–12 Chapter 5: 1G/10GbE MAC Design Example

csr_clk_clk

csr_reset_reset_n

csr_address [18:0]

csr_read

csr_readdata [31:0]

csr_write

csr_writedata [31:0]

csr_waitrequest

40084

00000002

1G/10GbE Testbench

# broadcastFramesErr = 0

# etherStatsOctets = 5310

# etherStatsPkts = 8

# etherStatsUndersizePkts = 0

# etherStatsOversizePkts = 0

# etherStatsPkts64Octets = 4

# etherStatsPkts65to127Octets = 0

# etherStatsPkts128to255Octets = 0

# etherStatsPkts256to511Octet = 1

# etherStatsPkts512to1023Octets = 0

# etherStatsPkts1024to1518Octets = 3

# etherStatsPkts1519OtoXOctets = 0

# etherStatsFragments = 0

# etherStatsJabbers = 0

# etherStatsCRCErr = 0

# unicastMACCtrlFrames = 0

# multicastMACCtrlFrames = 0

# broadcastMACCtrlFrames = 0

1 The same message will appear twice if you use 1G/10G Ethernet mode

because the system resets the statistic counters after changing the MAC operating speed.

5.5.6. 1G/10GbE Simulation Timing Diagrams

Figure 5–5 shows the reset and initial configuration sequence. The first read or write

transaction must be at least one clock cycle after the completes.

Figure 5–5. Reset and Configuration

csr_reset_reset_n

signal

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 5: 1G/10GbE MAC Design Example 5–13

1G/10GbE Design Example Compilation

5.6. 1G/10GbE Design Example Compilation

You can use the Quartus II software to compile the 1G/10GbE design example and program the targeted Altera device after a successful compilation.

5.6.1. Compiling the 1G/10GbE Design

Perform the following steps to compile the design and program the device:

1. Copy the

<ip library>/altera_eth_10g_design_example/altera_eth_10g_mac_base_kr

directory to your preferred project directory.

2. Launch the Quartus II software and open altera_eth_10g_mac_base_kr_top.v from the project directory.

source setup_proj.tcl

f For more information about the development kit, refer to Signal Integrity

Development Kit, Stratix V GX Edition User Guide.

4. Launch Qsys from the Tools menu and open altera_eth_10g_mac_base_kr.qsys.

5. Click Save on the File menu.

6. On the Generation tab, turn on Create Synthesis RTL Files.

7. Click Generate to generate the system.

8. Click Start Compilation on the Processing menu to compile the design example.

9. Upon a successful compilation, click Programmer on the Tools menu to program the device.

10. Launch the MegaWizard Plug-in Manager. Select Edit an existing custom megafunction variation and regenerate reconfig.v from the reconfig folder.

1 If you want to share the PLL clock, connect the

controller to the Ethernet 10GBASE-KR PHY IP. For example, the

pll_powerdown

10GBASE-KR PHY IP.

pll_powerdown

signal from channel 0 and channel 1 of the Backplane Ethernet

signal from different channels of the Backplane

signal from reset controller 0 connects to the

pll_powerdown

signal from the reset

For more information about device programming, refer to Quartus II Programmer in volume 3 of the Quartus II Handbook.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

5–14 Chapter 5: 1G/10GbE MAC Design Example

1G/10GbE Design Example Compilation

5.6.2. 1G/10GbE Design Performance and Resource Utilization

Tab le 5– 5 provides the estimated performance and resource utilization of the

1G/10GbE design example obtained by compiling the design with the Quartus II software targeting the Stratix V GX (EP5SGXEA7N2F40C2) device with speed grade –2.

Table 5–5. Stratix V Performance and Resource Utilization

Components ALM Needed

1G/10GbE MAC Channel 0 3,272 3,900 9

1G/10GbE MAC Channel 1 3,302 3,891 9

10GBASE-KR Channel 0 547 685 1

10GBASE-KR Channel 1 547 690 1

Reconfiguration Bundle 1,644 1,940 8

JTAG Master 341 424 1

RX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 142 172 2

TX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 140 180 2

RX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 138 176 2

TX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 139 176 2

Other Components 2,628 3,123 8

Total Resource Utilization 12,840 15,357 45

ALM in Final

Placement

Memory Block

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

6. 10M-10GbE MAC with IEEE 1588v2 Design Example

This section describes the 10M/100M/1G/10 Gbps Ethernet (10M-10GbE) MAC with IEEE 1588v2 design example, the testbench, and its components.

6.1. Software and Hardware Requirements

Altera uses the following hardware and software to test the 10M-10GbE MAC with IEEE 1588v2 design example and testbench:

■ Altera Complete Design Suite 13.0

■ Stratix V GX FPGA Development Kit

■ ModelSim-SE 10.0b or higher

6.2. 10M-10GbE MAC with IEEE 1588v2 Design Example Components

You can use the 10M-10GbE MAC IP core design example to simulate a complete 10M-10GbE MAC with IEEE 1588v2 design in a simulator. You can compile the design example using the Quartus II software and program the targeted Altera device after a successful compilation.

Figure 6–1 shows the block diagram of a 10M-10GbE MAC with IEEE 1588v2 design

example.

1 For the purpose of simplification, this diagram shows only one of the two channels in

the design example. Each channel has its own components but they share the Avalon-MM Master Translator and Reconfiguration Bundle blocks.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

6–2 Chapter 6: 10M-10GbE MAC with IEEE 1588v2 Design Example

Ethernet

Packe t

Classifier

Pulse Per

Second Module

Time of

Day

Clock

Time of Day

1M/100M/1G/10G MAC

Avalon MM Master

Translator

Client Application

(Configuration,

Status & Statistics)

Reconfiguration

Bundle

10GBASE-KR PHY

External PHY

10GBASE-KR

72-Bit SDR

XGMII/10-bits

GMII

64-Bit

Avalon ST

Time

of Day

32-Bit

Avalon MM

Reconfiguration

32-Bit

Avalon MM

64-Bit

Avalon ST

Pulse Per

Second

Timestamp & Fingerprint

Client Application

Altera FPGA

Design Example

10M-10GbE MAC with IEEE 1588v2 Design Example Components

Figure 6–1. 10M-10GbE MAC with IEEE 1588v2 Design Example Block Diagram

The 10M-10GbE MAC with IEEE 1588v2 design example comprises the following components:

■ Altera Ethernet 10M-10GbE design example—the default 1G/10G design that has

■ Backplane Ethernet 10GBASE-KR PHY—the PHY IP core with IEEE 1588v2 option

■ Reconfiguration Bundle—comprises the reconfiguration controller that switches

■ Ethernet Packet Classifier—decodes the packet type of incoming PTP packets and

the following parameter settings:

enabled.

■ 10M-10GbE Ethernet MAC—the MAC IP core with IEEE 1588v2 option

■ MDIO and FIFO features turned off.

enabled.

returns the decoded information to the 10M-10GbE MAC.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 6: 10M-10GbE MAC with IEEE 1588v2 Design Example 6–3

10M-10GbE MAC with IEEE 1588v2 Design Example Files

■ Ethernet ToD Clock—provides 64-bits and/or 96-bits time-of-day to TX and RX of

10GbE Ethernet MAC.

■ Pulse Per Second Module—returns pulse per second (pps) to user.

■ Avalon-MM Master Translator—provides access to the registers of the following

components through the Avalon-MM interface:

■ MAC

■ Backplane Ethernet 10GBASE-KR PHY

■ Transceiver Reconfiguration Controller

■ ToD C l ock

6.2.1. Base Addresses

Tab le 6– 1 lists the design example components that you can reconfigure to suit your

verification objectives. To reconfigure the components, write to their registers using the base addresses listed in the table and the register offsets described in the components' user guides.

Table 6–1. Base Addresses of 10M-10GbE MAC with IEEE 1588v2 Design Example Components

Component Base Address

MAC Channel 0 0x00000

MAC Channel 1 0x20000

Backplane Ethernet 10GBASE-KR PHY Channel 0 0x80000

Backplane Ethernet 10GBASE-KR PHY Channel 1 0x80800

Configure Reconfiguration Channel 0 0x80400

Configure Reconfiguration Channel 1 0x80500

Time of Day Clock (1G) Channel 0 0x81100

Time of Day Clock (10G) Channel 0 0x81000

Time of Day Clock (1G) Channel 1 0x81300

Time of Day Clock (10G) Channel 1 0x81200

1 This design example uses a 19-bit width address bus to access the base address of

components other than the MAC.

6.3. 10M-10GbE MAC with IEEE 1588v2 Design Example Files

Figure 6–2 shows the directory structure for the 10M-10GbE MAC with IEEE 1588v2

design examples and testbenches.

Figure 6–2. 10M-10GbE MAC with IEEE 1588v2 Design Example Folders

<ip_lib>/ethernet/altera_eth_10g_design_example

altera_eth_10g_mac_base_kr_1588

testbench

reconfig

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

6–4 Chapter 6: 10M-10GbE MAC with IEEE 1588v2 Design Example

Creating a New 10M-10GbE MAC with IEEE 1588v2 Design

Tab le 6– 2 lists the files in the ..\altera_eth_10g_mac_base_kr_1588 directory.

Table 6–2. 10M-10GbE MAC with IEEE 1588v2 Design Example Files

File Name Description

altera_eth_10g_mac_base_kr_1588_top.sv

altera_eth_10g_mac_base_kr_1588_top.sdc

altera_eth_10g_mac_base_kr_1588.qsys

The top-level entity file of the design example for verification in hardware.

The Quartus II SDC constraint file for use with the TimeQuest timing analyzer.

A Qsys file for the 10M-10GbE MAC and 10GBASE-KR PHY design example with IEEE 1588v2 option enabled.

6.4. Creating a New 10M-10GbE MAC with IEEE 1588v2 Design

You can use the Quartus II software to create a new 10M-10GbE MAC with IEEE 1588v2 design. Altera provides a Qsys design example file that you can customize to facilitate the development of your 10M-10GbE MAC with IEEE 1588v2 design.

To create the design, perform the following steps:

1. Launch the Quartus II software and open a new Quartus II Project.

2. Run add_design_example_files.tcl in the Quartus II software to add the required design example files to the project.

3. Launch Qsys from the Tools menu and open the altera_eth_10g_mac_base_kr_1588.qsys file.

4. Turn off the additional module under the Use column if your design does not require it. This action disconnects the module from the 10M-10GbE MAC with IEEE 1588v2 system.

5. Double-click on eth_10g_design_example_0 and eth_10g_design_example_1 to launch the parameter editor.

6. Specify the required parameters in the parameter editor.

7. Click Finish.

8. On the Generation tab, select either a Verilog HDL or VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on.

9. Click Generate to generate the simulation and synthesis files.

10. Launch the MegaWizard Plug-in Manager from the Tools menu. Select Edit an

existing custom megafunction variation and regenerate reconfig.v from the reconfig folder.

11. Click Finish.

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

Chapter 6: 10M-10GbE MAC with IEEE 1588v2 Design Example 6–5

10M-10GbE with IEEE 1588v2 Testbench

6.5. 10M-10GbE with IEEE 1588v2 Testbench

Altera provides testbench for you to verify the 10M-10GbE with IEEE 1588v2 design example. The following sections describe the testbench, its components, and use.

6.5.1. 10M-10GbE with IEEE 1588v2 Testbench

The testbench operates in loopback mode. Figure 6–3 shows the flow of the packets in the design example.

Figure 6–3. Testbench Block Diagram

Testbench

Ethernet

Packe t

Avalon-MM

Control

Avalon-ST

Transmit

Frame

Generator

Monitor

Avalon-ST

DUT

Avalon-MM

Ordinary Clock

Channel-0

Loopback

on Serial

Avalon-ST

Receive

Frame

Monitor

avalon_bfm_wrapper.sv

Avalon Driver

Avalon-ST

Ethernet

Packe t

Monitor

Channel-1

Transparent Clock

6.5.2. 10M-10GbE with IEEE 1588v2 Testbench Components

The testbenches comprise the following modules:

■ Device under test (DUT)—the design example.

■ Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise

the transmit and receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.

■ Packet monitors—monitors the transmit and receive datapaths, and displays the

frames in the simulator console.

February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide

6–6 Chapter 6: 10M-10GbE MAC with IEEE 1588v2 Design Example

10M-10GbE with IEEE 1588v2 Testbench

6.5.3. 10M-10GbE MAC with IEEE 1588v2 Testbench Files

The <ip library>/ethernet/altera_eth_10g_design_example/testbench directory contains the testbench files.

Tab le 6– 3 describes the files that implement the 10M-10GbE MAC with IEEE 1588v2

testbench.

Table 6–3. 10M-10GbE MAC with IEEE 1588v2 Testbench Files