Aiwa CSDA-220 Schematic

CSD-A220

HA, LH

CSD-A229

LH

SERVICE MANUAL

COMPACT DISC STEREO

RADIO CASSETTE RECORDER

• This Service Manual is the “Revision Publishing” and replaces “Simple Manual”
(S/M Code No. 09-002-427-8T1).

BASIC TAPE MECHANISM : TN-21ZVC-2000
BASIC CD MECHANISM : DA11T3C

S/M Code No. 09-005-427-8R1

REVISION

DATA

WIRING – 2 (FRONT / H.P. / POWER / BATT / VOLTAGE)

101112131415161718192021222324

1234567892526272829303132

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

– 11 –

R

S

T

U

SCHEMATIC DIAGRAM – 3 (FRONT)

– 12 –

WIRING – 3 (TUNER)

123456789101112131415

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

– 13 –

R

S

T

U

SCHEMATIC DIAGRAM – 4 (TUNER)

– 14 –

WIRING – 4 (MOTOR)

123456789101112131415

A

B

C

I MOTOR C.B

M2

+

(SLED MOTOR)

_

(INSIDE LIMIT SW)

SW1

PIN3

FROM B CD C.B CNA402

PICK UP ASSY

SF-P101NR

M2

SW1

(SPINDLE MOTOR)

_

M1

M1

D

E

F

G

H

+

I

J

K

L

16

M

N

CN1

O

P

1

Q

FC401

R

FROM B CD C.B CN401

S

T

U

– 15 –

IC BLOCK DIAGRAM

– 16 –

IC DESCRIPTION

IC, LC78622ED

Pin No. Pin Name I/O Description

1 DEFI I Defect detection signal (DEF) input.

2 TAI I Test input. A pull-down resistor is built in. Must be connected to 0V.

3 PDO O External VCO control phase comparator output.

4 VVSS – Internal VCO ground. Must be connected to 0V.

5 ISET O PDO output current adjustment resistor connection.

6 VVDD – Internal VCO power supply.

7 FR I VCO frequency range adjustment.

8 VSS – Digital system ground. Must be connected to 0V.

9 EFMO O Slice level control; EFM signal output.

10 EFMIN I Slice level control; EFM signal input.

11 T2 I Test input. A pull-down resistor is built in. Must be connected to 0V.

12 CLV+

O

13 CLV–

Disc motor control output.
Three-value ouput is also possible when specified by microprocessor command.

14 V/P O

15 HFL I Track detection signal input. This is a Schmitt input.

16 TES I Tracking error signal input. This is a Schmitt input.

17 TOFF O Tracking off output.

18 TGL O Tracking gain switching output. Increase the gain when low.

19 JP+

O

20 JP–

21 PCK O

22 FSEQ O signal detected from the EFM signal and the internally generated synchronization signal

23 VDD – Digital system power supply.

24 SL+

O Serial data command sled signal output terminal from microprocessor.

25 SL–

26 CONT3 – Not used.

27 PU IN I CD pickup inside limit switch.

Rough servo/phase control automatic switching monitor output. Outputs a high level
during rough servo and a low level during phase control.

Track jump output.
Three-value output is also possible when specified by microprocessor command.

EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.
(Not used)

Synchronization signal detection ouput. Outputs a high level when the synchronization

agree. (Not used)

28 RW O Serial data command sled output terminal from microprocessor.

29 EMPH O

30 C2F O C2 flag output. (Not used)

31 DOUT O Digital output (EIAJ format). (Not used)

32 T3

33 T4

34 NC – Unused. Must be left open.

35 MUTEL O Left channel one-bit D/A converter mute output. (Not used)

36 LVDD – Left channel one-bit D/A converter power supply.

37 LCHO O Left channel one-bit D/A converter output.

De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk.
(Not used)

I Test input. A pull-down resistor is built in. Must be connected to 0V.

– 17 –

Pin No. Pin Name I/O Description

38 LVSS – Left channel one-bit D/A converter ground. Must be connected to 0V.

39 RVSS – Right channel one-bit D/A converter ground. (Must be connected to 0V.)

40 RCHO O Right channel onr-bit D/A converter output.

41 RVDD – Right channel one-bit D/A converter power supply.

42 MUTER O Right channel one-bit D/A converter mute output. (Not used)

43 XVDD – Crystal oscillator power supply.

44 XOUT O

45 XIN I

46 XVSS – Crystal oscillator ground. (Must be connected to 0V.)

47 SBSY O Subcode clock synchronization signal output. (Not used)

48 EFLG O C1, C2, sigle an double error correction monitor. (Not used)

49 PW O Subcode P, Q, R, S, T, U and W output. (Not used)

50 SFSY O

51 SBCK I Subcode readout clock input. This is a Schmitt input.

52 FSX O Output pin for the 7.35 kHZ synchronization signal divided from the crystal oscillator. (Not used)

53 WRQ O Subcode Q output standby output.

54 RWC I Read/write control input. This is a Schmitt input.

55 SQOUT O Subcode Q output.

56 COIN I Command input pin from control microprocessor.

57 CQCK I

58 RES I Reset input. This pin must be set low briefly after power is first applied.

59 T11 O Test output. Leave open. (Normally output a low level). (Not used)

Connections for a 16.9344 MHz crystal oscillator element.

Subcode frame synchronization signal output. This signal falls when the subcode are

in standby state. (Not used)

Input for both the command input acquisition clock and the SQOUT pin subcode

readout clock input pin. This is Schmitt input.

60 16M O 16.9344 MHz output. (Not used)

61 4.2M O 4.2336 MHz output.

62 T5 I Test input. A pull-down resistor is built-in. (Must be connected to 0V.)

63 CS I

64 T1 I Test input. No pull-down resistor. (Must be connected to 0V.)

Chip seledt input. A pull-down resistor is built-in.

(Must be connected to 0V if not controlled.)

– 18 –

IC, LA9241ML

Pin No.

1 FIN2 O

2 FIN1 O For the connection of the pickup photodiode.

3EO

4 F O For the connection of the pickup photodiode.

5 TB I Inputs the DC components in the TE signal.

6 TE– O

7 TE O TE signal output.

8 TESI I TES (track error sense) comparator input.The TE signal is passed through a BPF.

9 SCI I Shock detection input.

10 TH I Sets the time constant for the tracking gain.

11 TA O TA amp output.

12 TD– I Composes the tracking phase compensation constant between the TD and VR pins.

13 TD O Sets the tracking phase compensation.

14 JP I Sets the amplitude of the tracking jump signal (kick pulses).

Pin Name I/O

For the connection of the pickup photodiode. Addition to the FIN1 pin creates an RF

signal and subtraction from it create an EF signal.

For the connection of the pickup photodiode. Subtraction from the F pin creates a TE

signal.

For the connection of a resistor which sets the gain of the TE signal between this pin

and the TE pin.

Description

15 TO O Tracking control signal output.

16 FD O Focusing control signal output.

17 FD– I Composes the focusing phase compensation constant between the FD and FA pins.

18 FA O Composes the focusing phase compensation constant between the FD- and FA- pins.

19 FA– I Composes the focusing phase compensation constant between the FA and FE pins.

20 FE O FE signal output.

21 FE– I

22 AGND O Ground of analog signals.

23 SP O Single-ended output of the signals input to the CV+ and CV- pins.

24 SPI I Spindle amp input.

25 SPG I For the connection of a resistor which sets the gain in the spindle 12cm mode.

26 SP– I For the connection of the spindle phase compensation constant with the SPD pin.

27 SPD O Spindle control signal output.

28 SLEQ I For the connection of sled phase compensation constant.

29 SLD O Sled control signal output.

30 SL–

31 SL+

For the connection of a resistor which sets the gain of the FE signal between this pin

and the TE pin.

I Sled feed signal input from the microprocessor.

32 JP–

33 JP+

34 TGL I Tracking gain control signal input from the DSP. Low gain when TGL is "H".

35 TOFF I Tracking off control signal input from the DSP. Off when TOFF is "H".

36 TES O TES signal output to the DSP.

I Tracking signal input from the DSP.

– 19 –