HP 4142B Application
aa
HEWLETT
PACKARD
HIGH SPEED MEASUREMENT OF FET
Reprinted from the IEEE proceedings of
Microelectronic Test Structures Conference
March 1989
ANALOG FEEDBACKUNIT
;-- ---- ------ ------------
Vth
AT LOW Id
Proc. IEEE 1989 Int. Conference on Microelectronic Test Structures, Vol 2,
NO.
1, March 1989
31
HIGH SPEED MEASUREMENT OF FET Kh AT LOW
HIDEYUKI NORIMATSU
Yokogawa Hewlett Packard
9-l,Takakura-cho, Hachioji, Tokyo, Japan
Phone: 0426-42-1231
Abstract,: High speed measurement of FET threshold voltage at low drain current has been achieved by using an analog
feedback method with proper guarding techniques. The method
can be oplied to process control test structure FETs and/or to
characterize parasitic FETs which may be formed in high density hlOSLS1 circuits.
Introduction
It is popular to monitor LSI manufacturing process by mea-
suring characteristics of test devices. There are many measure-
ment items such as leakage current, breakdown voltage, transistor characteristics etc. Measurement of FET threshold voltage
(C;,) is very useful, but it is time consuming. Fast and accurate
I/t,, measurement at lower drain current is required especially
for recent high density device/process evaluation.
For spot
Vt,,
measurements, the gate voltage has to be controlled to set the drain current to a defined value. To control
the gate kroltage, two different methods are available, digital
feedback and analog feedback. Digital feedback is widely used
because of its easy and stable operation. But measurement requires a great deal of time. Analog feedback allows high speed
and accurate measurement, but it needs some technical skill to
Id
get optimum circuit parameters without oscillation problems.
We have developed a system to provide fast, accurate a.nd stable
Vth
measurements using analog feedback method.
Analog Feedback unit (AFU)
Fig.1 shows a block diagram of the system (analog block),
which consists of two Source/Monitor Units (SMUs) and an
Analog Feedback Unit (AFU). AFU controls the Search channel SMU so that the monitor value of the Sense channel SMU
sets to preset value. SMU has two modes of operations, voltage
source and current source. In the Vth measurement, voltage
source mode is used. The output current and voltage of SMUs
can be measured by the A/D converter, which is not shown in
Fig.1, in the instrument.
Measurement steps are as follows:
(1) Set gate voltage to the search start value, and apply
drain voltage.
(2) A voltage ramp, of a selected slew rate, is applied to the
gate searching for a target value. In this mode the analog
feedback loop is open. (Search mode)
IMcasurement system
I
,_______--___-___-_-____________________----------------
1
1 I
1 I
I
Search SMU
feedback loop
I
Semr SMU
Pig.1 ScIlcmat,ic drawing of ;malog block
CH26Y3-0/X9/0000-031$01 .00~:198’) IEEE
’ I
I
I
Proc. IEEE 1989 Int. Conference on Microelectronic Test Structures, Vol 2, No. 1, March 1989
32
(3) When dram current (Id)
gate voltage stops changing, and the analog feedback loop
is closed. (Balance mode)
(4) After convergence period, the gate voltage is measured.
(5) Reduce the gate and drain voltages to former values.
A high slew rate ramp voltage in the search mode allows
a faster approach, from start to target value, than the speed
obtained by closed loop circuit characteristics in the balance
mode. But an excessively high slew rate results in overshoot
problems due to the response delay of circuits. An optimized
slew rate should be selected to limit overshoot within 10 % of
target Id.
In the balance mode, closed loop characteristics are determined by the transconductance of DUT, drain current detector
gain, integrator gain etc. It can be optimized by selecting of the
best value of the integrator’s time constant. Improper setting of
the time constant causes an oscillation or a longer measurement
time.
Proper setting of time constant of integrator, ramp slew
rate, and convergence wait time is the key to a faster and more
stable measurement. It requires knowledge about the circuit
constants and calculations to get proper parameter values. For
ease of operation, software was prepared to calculate proper
setting parameters automatically from key parameter inputs.
The user only has to supply DUT parameters and measurement
conditions such as drain voltage, target Id, gate start and stop
voltage, gate-drain capacitance (C&t), and so on. Cg& should
include‘not only the capacitance of DUT itself (C&), but also the
capacitance of the measurement syst&m (capacitance between
pins of probe card, for example).
Measurement Ranges / Accuracies
General measurement ranges and accuracies are shown be-
low. Not all ranges can be combined at the same time.
Drain voltage : 0 to 200 V
Drain current : 100 pA to 900 mA
reaches the preset value, the
Gate voltage : -200 to +200 V
Search ramp slew rate : 5 mV te 100 1’ /msec
I,j programming accumcy : ,0.8 % ( @ 1OuA )
V,
measuring accuracy : 0.1 % ( @ 20 V )
Low Current Measurement
Fig.2 shows a typical hardware configuration of the system.
Measurement instruments, relay matrix and prober are con-
nected- to a host computer by an HP-IB interface (IEEE 488).
Measurement procedures are controlled by user program, written in BASIC, in the host computer.
When measuring low current, there are many degradation
sources such as leakage conductance to the voltage source nearby,
stray capacitance to the co’nductor whose voltage is varying, dielectric absorption of that capacitance, and so on. The effective
countermeasure for those problems is a guard. The concept of
guard is easy, it is to enclose the aimed signal line by a conductor having practically the same potential as the signal line
itself. Co-axial st,ructure is widely used. It is not easy to apply
the guard technique throughout the total measurement system.
On the probe card, signal conductor usually have no guarding
enclosure. Naturally, the case in which the aimed signal pin,
where low current is monitored, and the voltas source pin are
next to each other is the worst condition for both leakage conductance .and stray capacitance. If it is possible to put a guard
pin between those two pins, leakage conductance and stray capacitance can be reduced. Dirtiness.ori printed circuit boards
can cause a trouble, so it is also important to keep the surface
clean.
In the case of our system, the most critical parasitic param-
eter is Cgdt especially at lower current condition. Current, pro-
duced by gate voltage change, flows to drain through c,& and
causes an error on the Id monitor. This results in errors at the
end point of the search mode, delay of mode change from search
mode to balance mode and excess Id overshoot. Cs,jt makes an
undesirable feedback loop in the system, and its loop characteristics set the limit ,of stable operation. So in the case of low
Probe-card
R.&y
matrix
I I
Cables
MCRSUI.CI~C~~.
iust,rlunc:nt,s
Colnplltcr
Proc. IEEE 1989 Int. Conference on Microelectronic Test Structures, Vol 2, No. 1, March 1989
33
b
current
ramp slew rate and minimum integrator time constant.
the major portion of Csdt
surement system. Guard for 1d monitor is effective to reduce the
actual system stray capacitance. Table.1 shows the effectiveness
of putting a guard pin between adjacent pins. In our system, instruments and cables have almost no problems. The structure of
SMU’s output is tri-axial and an inner shield is used as a guard.
Cables are quad-axial and a second shield is ,used as a guard.
The relay matrix used here has nine instrument ports and 48
DUT pins, one of the ports is designed specially for low current
measurements. Stray capacitance between the signal line of this
port and the other ports is very small (only 0.5 pF maximum).
This value becomes maximum when the DUT pins used as the
low current port and another port are next to each other. It
can be effectively reduced by using the DUT pins next to the
aimed pin as guard and the other pin apart from the aimed pin
as another port. (less than 0.03 pF typical) On the probe card,
the case in which Id monitor pin and gate voltage driver pin are
next to each other is the worst condition. If it is possible to put
a guard pin between the
can be reduced effectively.
used as guard must be free for applying a specific voltage (e.q.,
same as drain voltage). Concern is only for stray capacitance
Vt,,
measurements, the C,,, value determines maximum
Usually, C,, of the DUT is very small in LSI processing, and
is the stray capacitance of the mea-
I,J
monitor and gate voltage drive, C,,,
To apply the guard technique for
Table 1 Capacitance of measurement system
V,,,
measurements, a pin
( Typical value )
Table 2 Comparison of measurement time
( Typical value )
Digital
feedback
280
mS
1400 mS
in this case, but, applying a constant voltage is enough (e.q.,
ground or source voltage of FET).
Measurement Speed / Variation
Fig.3 shows the timing chart for a P-channel MOSFET sam-
ple. This sample is a discrete packaged device whose C,, is
about 1 pF, and source and drain voltage is set -10 V initially
to make the same condition as the DUT which has high enhance-
ment
Vt,,
voltage. Id target is 10 nA and the guard technique,
above, is adopted. C&t is only about 1.5 pF. The entire measurement takes about 40 mS, from trigger to data entry of the
computer. Measurement conditions are set prior to making the
measurement. In Fig.3, measurement procedures are as follows.
Drain voltage is set in period A. Gate voltage ram is applied
(Search mode) in period B. Feedback loop is made (Balance
mode) and
are reduced to former values in period D.
V,
is measured in period C. Drain and gate voltage
Adjacent
Guard is
applied
0.56
0.06
pF
pF
4.0
0.4
pF
pF
Fig.4 shows the timing chart for the same DUT, but wit,h-
out applying a guard pin between the gate pin and the drain
pin, with target Id=10 nA. Since C,& is more dominant, value
is about 5 pF, ramp slew rate must be lower, integrator time
constant must be longer, and the measurement takes longer time
(about 70 mS).
Fig.5 shows the variation over 1000
two cases of
I
10 mS
Id
(10 nA and 1 nA). In both cases, variations are
Vth
measurements for
( vs- -10 v )
34
P~oc. IEEE
very small. The guard technique is adopted for the measurements, but without the guard technique the variatipn value is
almost the same.
1989 Int. Conference on Microelectronic Test Structures, Vol 2, No. 1, March 1989
Comparison with the Digital Feedback
In the digital feedback method,
measured. That value is compared to the target value to decide
the next
target value (closely enough). There are several types commonly
used, checking of measured
in the instrument or by the computer, deciding next value of
by constant step from former value or by dichotomizing search
(binary search). Measured Id checked by CPU in the instrument
is one of the fastest methods. Table.2 shows the measurement
time comparison between the analog feedback method of our
system and the digital feedback method of the dichotomizing
search. The analog feedback method has an obvious advant,age
on the measurement speed. As to measurement res@tion, the
digital feedback approach is not favorable, because’ the higher
resolution requires more repeated measurements and each measurement requires better accuracy which results in long measurement time.
bility has been achieved using the ana!og feedback method. Ease
of operation has been augmented by dedicated software. With
correct application of the guard technique, it has been proved
that
measurement time.
Vg
value and the operation is until measured 1, reaches
Id
Conclusion
High speed measurement of
Vth
at low Id such as 1 nA can be measured in a reasonable
V,
is applied and ,then Id is
and target value is done by CPU
V,
Vt,,
with high accuracy and sta-
Acknowledeements
The author wishes to acknowledge the guidance and encouragement of Mr. Haruo Ito and Mr. Susumu Takagi and Mr.
Hideo Akama. The author also wishes to thank Mr. Shinichi
Tanida and Mr. Hiroshi Nada for their contributions to the
system.
Id= 1 nA
0.4mV
-
All
1
413 4%
10G
54
Fig.5 Variations in Vth mcasuremcnts
Id = 10 nA
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