Advantech RISC SOM-A2558 User Manual

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User’s Manual for Advantech SOM-A2558 series module V1.00

Advantech RISC SOM-A2558 Series Module

System Module with Intel XScale PXA255 processor, Advantech EVA-C210 I/O

enhancement Chip with Windows® CE.NET

User’s Manual

Of

Released Version:V1.00

Released Date: May. 19. 2004

Advantech Co., Ltd

Risc Embedded Computing Division

http://www.advantech.com/risc

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2

ABSTRACT

This manual describes the SOM-A2558 series module functions.

Copyright

This document is copyrighted, © 2003. All rights are reserved. The original manufacturer
reserves the right to make improvements to the products described in this document at any
time without notice.

No part of this document may be reproduced, copied, translated or transmitted in any
form or by any means without the prior written permission of the original manufacturer.
Information provided in this document is intended to be accurate and reliable. However, the
original manufacturer assumes no responsibility for its use, nor for any infringements upon the
rights of third parties that may result from such use.

User’s Manual for Advantech SOM-A2558 series module V1.00

Acknowledgements

IBM, PC/AT, PS/2 and VGA are trademarks of International Business Machines Corporation.
Intel® is trademark of Intel Corporation.
Microsoft® Windows® CE.NET is a registered trademark of Microsoft Corp.
All other product names or trademarks are properties of their respective owners.

For more information on this and other Advantech products please visit our
website at：

http://www.advantech.com
http://www.advantech.com/risc

For technical support and service for please visit our support website at：

http://eservice.advantech.com.tw/eservice/

Or directly mail to Advantech RISC platform application engineer：

[e-mail]

Advantech RISC SOM design-in member can login-in the Advantech SOM
Design-in Zone for professional & real-time technical support & service：

http://risc-designin.advantech.com.tw

PS. The RISC design-in zone web portal is only for SOM design-in member
only.

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Revision History

Version

V1.00 2004.05.19 1st Official released version. (For

User’s Manual for Advantech SOM-A2558 series module V1.00

Date Reason

9696255201, 9696255801, 9696255F01

& 9696255F12)

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User’s Manual for Advantech SOM-A2558 series module V1.00

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Chapter 1 SOM-A2558 series Architecture

1.1 Introduction

Advantech SOM-A2558 module uses a dual-chip design principle.
SOM-A2558 series System On Module integrates both an Intel XScale
PXA255 ultra low power CPU with Advantech's EVA-C210 companion chip.
This offers the advantage of integrated controllers, but with multiple I/Os, such
as CF, PCMCIA, USB Host, USB Client, RS-232/UART, PCI Bus Rev. 2.2,
10/100Base-T Ethernet, PS/2 ports and RS-485.

SOM-A2558 series Design highlight:

l 68 mm x 68 mm x 6.8 mm compact size module
l Power management ready support with Normal, Idle, Suspend,

Off mode utilities.

l OS-ready package for Windows CE .NET/Linux Installation

(Windows CE .NET 4.2 BSP ready)

l Local bus(AMI Bus), comprehensive I/O interfaces as PS/2 port,

Ethernet, USB Host and PCI I/F support

l Boot option by onboard Flash or CFC makes easy maintenance

and cost savings

l Provide a variety of reconfi guration options to fulfi ll specifi c

requirements

l Design-in Kit package is available for complete design-in support
l Optional RISC CE-Builder assists for customer own image

development

SOM-A200 architecture

SOM-A255x series are based on Advantech SOM-A200 architecture to
design. SOM-A200 is Advantech RISC ultra-low power series SOM
architecture. The following block diagram is the SOM-A200 architecture.

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Based on SOM-A200 architecture to design, SOM-A255x (SOM-A2552,
SOM-A2558 and SOM-A255F) series have two kinds of PCB form factors.

l SOM-A2552 & SOM-A2558 series: 68mm x 68mm x 6.8mm
l SOM-A255F series: 68mm x 102mm x 6.8mm

SOM-A2558 benefit

The SOM-A2558 series are very compact (68mm x 68mm x 6.8mm) and

highly integrated system module. SOM-A2558 series products have a
standardized form factor and standardized connectors (DDR-SODIMM
Memory Connector and two 100-pin board-to-board connectors) that carry a
specified set of signals. This standardization allows users to create
application-specified User Solution Board (CSB) which can accept a variety of
present and future SOM-A200 series modules.

SOM-A2558 series include popular & common peripheral functions such
as serial ports, LAN, USB, PCI, etc. The CSB designer can optimize exactly
how each of these functions is physically implemented. Connectors can be
placed precisely where they are needed for the application, on a baseboard
designed to optimally fit the system configuration and layout.

A CSB design may be used with a range of SOM-A2558 modules. This
flexibility can be used to differentiate products at various price/ performance
points, or to design “future proof” systems that have a built-in upgrade path.
The modularity of an SOM-A2558 solution also insures against obsolescence
as computer technology continues to evolve. A properly designed SOM-A2558
CSB can be used with several successive generations of SOM-A2558
modules. An SOM-A2558 CSB design thus has many of the advantages of a
custom computer board design, but delivers better obsolescence protection,
greatly reduced engineering effort, and faster time to market.

Based embedded platform integrates both low-level hardware and

software design and is always agreed to require heavy R&D resources, huge
development effort, risk as well as long time to market lead-time. Moreover,
the fast develop RISC SoC technology and short product life that has been
challenging System Integrators how to make a right product development
approach while foreseeing the huge advantage & benefit by adopting
RISC-base solution.

SOM-A2558 series are an innovate platform architecture of

WinCE.NET-ready complete functional system in a low profit module with
SODIMM 200-pin unified I/O ready bus interface that is designed to fit into
application-specified User Solution Board (CSB) with easy, risk-less, robust,
fast implementation approach. Dual expansion interface and Pre-select
Embedded OS also are well integrated on module. OS Board Support
Package (BSP) and advantech own-develop system utility & tools are also
supported for an easy design-in business philosophy.

SOM-A2558 series Application

SOM-A2558 series is designed for Ideal for power critical & I/O intensive
required base Applications

l Mobile, battery-powered device platform with multi-I/O I/F

demands

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l Compact diagnostic, monitoring, control equipment or HMI

terminals

l Outdoor, fully enclosured, Intelligent remote I/O controllers
l LCD-based vehicle/telemetric platforms for navigation &

communication.

SOM-A2558 series design-in package

The Design-in Kit package provides developer complete reference
design-in suit for application evaluation/ development and own Customer
Solution Board (CSB) development. It contains the needed information,
documentation and tools for starting their hands-on work as the followings
items:

l Target SOM (SOM-A2558-440B0): SOM-A2558 standard version

board.
SOM-A255x series Reference Carrier Board (RCB): Sample CSB
for developer reference. The board can be used in SOM-A255x
series board. (SOM-A255x means SOM-A2558, SOM-A2558 and
SOM-A2558)

l 64MB compact flash card : the CF card is empty without any file

inside.

l SOM-A255x series support CD : includes

- sample image & boot loader

- manuals & datasheets

- SOM-A255x series CSB design guide

- S/W utility(upgrade utility, testing utility)

- SOM-A255x series WinCE 4.2 BSP & SDK

- Application note

l Testing Set:

It is designed for sample CSB or user own CSB/mass production test.
It includes:

- H/W testing tools: RS232 loop-back testing tool, ADAM-4520
for RS485 testing, null MODEM cable, JTAG cable, USB
ActiveSync cable, Audio cable, RS232 cable and RS485
cable.

- S/W testing Utility: Advantech-developed testing Utility. Testing
process will be implemented by S/W testing Utility and H/W
testing tools.

- Document: “User's manual of SOM-A255x series testing kit”.
User can base on the documents to know how to implement
testing process.

l Software Development Tools:

Software tools is the complete package for user developed their
target image to align with their target CSB and applications

- BSP: Binary Board Support Package of target SOM Design-in Kit.

User can integrate their target WinCE platform in components &
Apps & drivers

- SDK: For user target Apps development

- Reference Image: Reference Image for the selected model of

SOM.

- Bootloader: Bootloader for the SOM-A255x series board.

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- Upgrade Utility: User can use Upgrade utility to upgrade boot

logo, image & bootloader.

Except the Design-in package, Advantech also supply many types of LCD
kits for users to reduce their developing effort. The LCD kit include the
following items:

l LCD
l Inverter
l Cables: includes LCD signals cable, Inverter signals cable.
l Document: The LCD kit installation guide.

Advantech supply the following LCD kits for user to choose

l LCD-A057-STQ1-0 (Optional item)

5.7” STN QVGA LCD kit. The kit includes 5.7” STN QVGA LCD
(NAN-YA/ LCBFBTB61M23), 4-wires resistive T/S, inverter, cables
and installation guide. SOM-A2552 & SOM-A255F series don’t
support 320*240 STN panel in this moment, if user have this kind of
requirement, please contact with [e-mail] or
advantech regional sales for further support.
l LCD-A064-TTV1-0 (Optional item)

6.4” TFT VGA LCD kit. The kit includes 6.4” TFT VGA LCD
kit(PRIMEVIEW PD064VT2), 4-wires resistive T/S, inverter, cables
and installation guide. All SOM-A255x series support this LCD kit in
reference image.
l LCD-A104-TTS1-0 (Optional item)

10.4” TFT SVGA LCD kit. The kit includes 10.4” TFT SVGA LCD
(AUO/ G104SN03v2), 4-wires resistive T/S, inverter, cables and
installation guide. Only SOM-A255F & SOM-A2552 series can
support this LCD-out mode.
l LCD-A150-TTX2-0 (Optional item)
15” TFT XGA LCD kit. The kit includes 15” TFT XGA LCD (AUO/
M150XN07), 4-wires resistive T/S, inverter, cables and installation
guide. Only SOM-A255F & SOM-A2552 series can support this
LCD-out mode.

SOM-A2558 series design-in kit(SOM-ADK2558-B00) is not included
any LCD kit. If user needs LCD kit to evaluate, please order your suitable
size LCD kit.

Risc CE-Builder

SOM-A255x series all support the Advantech optional RISC CE-Builder by
which developers can manage the BSP for their own platform development
thru a friendly users interface over the web.

RISC CE-Builder Solution is constituted by two parts: Web Image Builder
and CE-TUner.

Web Image Builder offers developers an online image building
mechanism through a friendly user interface to remotely conduct low-level
software and platform customization / integration for their target application
without knowing / using Microsoft Platform Builder. The image building
machine links to Advantech’s Board Support Package (BSP) library so
developers can leverage Advantech’s low-level software solution database.

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CE-TUner is a powerful value-added system utility / tool suit for
developers easily and simply develop, validate and upgrade their own SW
platform solution. CE-Tuner helps users fine-tune their target SW image for
optimized performance, verify settings, and platform tests before the
production image is certified.

RISC CE-Builder is not included in Design-in kit. If you need more
information about it, please contact with [e-mail] or
advantech regional sales for further support.

1.12 SOM-A2558 Block diagram

SOM-A2558 series bases on Dual-Chips design concept, SoC Intel
XScale PXA255 & I/O enhancement chip Advantech EVA-C210. The Block
diagram is as following:

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SoC Intel XScale PXA255 introduction

Intel XScale PXA255 processor is continuing the advance in handheld
multimedia functionality.

PXA255 is Low power, high performance 32-bit Intel XScale® core-based
CPU (200, 300 and 400 MHz). The SoC is ARM Architecture v.5TE compliant.

0.18µ process for high core speeds at low power.
Intel® Media Processing Technology including 40-bit accumulator and 16-bit
SIMD to enhance audio/video decode performance.
In power field, Low Power and Turbo modes enables enhanced optimal
battery life. 32 KB data and 32 KB instruction caches, 2 KB Mini data cache for
streaming data.
About PXA255 I/O expansion function, Integrated Memory and
PCMCIA/Compact Flash Controller with 100 MHz Memory Bus, 16-bit or 32-bit
ROM/Flash/SRAM (six banks), 16-bit or 32-bit SDRAM, SMROM (four banks),
as well as PCMCIA and Compact Flash for added functionality and
expandability. System Control Module includes 17 dedicated general-purpose
interruptible I/O ports, real-time clock, watchdog and interval timers, power
management controller, interrupt controller, reset controller, and two on-chip
oscillators.
Peripheral Control Module offers 16 channel configurable DMA controller,
integrated LCD controller with unique DMA for fast color screen support,
Bluetooth** I/F, serial ports including IrDA, I2C, I2S, AC97, three UARTs(1 Full
H/W flow control), SPI and enhanced SSP, USB end point interface, and
MMC/SD Card Support for expandable memory and I/O functionality.
About Intel PXA255 SoC detail information, user could visit Intel web site
for more.

Enhance I/O chip Advantech EVA-C210 introduction

The Advantech EVA-C210 Companion Chip is a companion chip to
the Intel® PXA255 processor based on XScaleTM technology. It provides a
variety of functions suitable for use in a high performance computer system.
The integrated on-chip functions include:

- Companion to Intel® PXA255 processor

- System Bus Interface (SBI) to AHB Wrapper

- Shared Memory Controller supports SDRAM

- Two PS/2 ports are provided for use with keyboards and mice

- Real Time Clock (RTC) with calendar function

- I2C Controller

- UART Controller with auto-flow-control function for RS485

- 16550-compatible UART

- Provide up to 32 bits of General Purpose I/O (GPIO)

- Two independent 16-bit Timers

- Two ports USB Host Controllers with PHY which are compliant with

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USB Spec. Rev. 1.1

- PCI Bus Controller (FPCI) which is compliant with PCI Spec. Rev. 2.2

- One port Ethernet 10/100 MAC Controller

- Interrupt Controller

- Power Management Unit with Normal, Sleep, Deep Sleep mode and

Power-off mode.

- 3.3V power supply with 3V/5V tolerant

- 256 BGA package

System Memory

SOM-A2558 SDRAM can be configured as 4/8/16/32/64/128/256MB.
Users can base on their requirement to reconfigure the SDRAM size.

There are two functions Flash on SOM-A2558 series. One is Boot Flash,
the other is Storage Flash.

Boot Flash is 1MB NOR flash. In standard SOM-A2558 series product,
Advantech will pre-install the WinCE bootloader in it.

Storage Flash is used to save image & user APs. Storage Flash size is
also reconfigurable. The Storage Flash is M-system Flash. Storage Flash size
could be 0/16/32/64 MB. SOM-A2558 series have Multiple boot options
through the on-board Flash or Compact Flash Card (CFC) for easy maintain
and cost saving. If Storage Flash is 0MB that means user should put the image
in Compact Flash Card.

CPLD

SOM-A2558 series have one CPLD on board. The CPLD take charges of
the following function:

l System memory assignments

l I/O control

l RTC control

Base on Advantech policy, Advantech won’t release the CPLD code to
user. In fact, when user designs their own target carrier board, they don’t need
to know the CPLD code. Advantech will release memory map of available
memory block and available GPIOs. These are fully enough to users to
develop their own carrier board.

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Model

Boot loader Flash

conn. Include PCI,ZV &

AC’97 codec on board.

1.2 System Specifications

The following table is SOM-A2558 series functional specifications.

SOM-A2558 standard product specification table

SOM-A2558-440B0

Func.
CPU PXA255- 400MHz 200/300/400 MHz
I/O Enhance Chip Advantech EVA-C210
Graphic Chip PXA255 built-in -

System
Memory(SDRAM)

On-board Flash
(Image &
Storage )
OS Image
Storage

AMI Bus(X1 bus)
Feature

Extension Bus
(X2 Bus)

Watch Dog PXA255 Built-in ­RTC EVA-C210 Built-in

System Backup
battery

Serial Port

Ethernet 1x 10/100 Base-T

64MB SDRAM 16/32/64/128 MB

1MB NOR Flash -

0MB 0/16/32/64MB

Thru CFC -

100-pin B2B conn w/

buffer drive

100-pin B2B conn (the

SD/MMC I/F)

For RTC/SDRAM -

3x Full RS-232 (TTL);
1x 2-wires RS-232
(TTL);
1x 3-wires for RS-232
or RS-485

Reconfiguration

Option

-

Yes

Yes

-

-

-

PCMCIA/
Compact Flash

USB Host 2x USB 1.1 Host ­USB Client 1x USB 1.1 Client

SD/MMC

PS/2 2x Ch for K/B & MS -

LCD( TTL level)
T/S 4-wire resistive Yes

Audio Codec

Buzzer control Yes ­SM Bus Yes -

2 Slots PCMCIA/CF or

1xPCMCIA & 1xCF

1xCh( support 1 bit

memory mode)

Up to VGA LCD-16-bit

TFT/STN/DSTN

Support Mic-in,

Line-in, Line-out

speaker-out

-

-

-

Yes

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Hardware Reset
Software Reset Yes ­Resume Yes -

OS support WinCE.NET
Power input 3.3V/5V -

Operating
temperature

Operating
humidity

Certification FCC/CE -
Form factor 68mm*68mm*6.8mm

Ps.. “Reconfiguration Option” column provide users many choices. “-“means
no option. If standard product SOM-A2558-440B0’s spec. doesn’t fit user’s
requirement, user could contact with Advantech for SOM-A2558
reconfiguration.

* Advantech SOM-A255x series have wide temperature products. About detail product
information, user could visit website http://www.advantech.com.tw/epc/phoenix/ . User also
could contact with [e-mail] or advantech regional sales for further
information.

Yes -

Linux(By customer

request)

0~60℃

0%~90% -

Optional for -10~60℃

& -20~80℃

-

SOM-A2558-440B0 is off-the-shelf standard product. Advantech welcome
SOM-A2558 re-configuration demand. Users could base on the column of
SOM-A2558 spec. to re-configurate userized SOM-A2558. “Reconfiguration
Option” column provide users many choices. “-“means no option. If standard
product SOM-A2558-440B0’s spec. doesn’t fit user’s requirement, user could
contact with Advantech for SOM-A2558 reconfiguration.

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1.2.1 Mechanical Specification

Following figure shows the mechanical drawing of SOM-A2558 series.

The above figure shows the SOM-A2558 mechanical drawing. Users
could follow the above figure to implement the layout procedure.
1st drawing shows the SOM-A2558 module PCB mechanical data. When
users enter the layout procedure, user could follow the 1st drawing to place the
connector. SOM-A2558 series PCB form factor is 68mm*68mm*68mm.

The 2nd drawing shows the PCB thickness limitation. The component side
height is 2.8mm, and the solder side maximum height is 3.00mm and the PCB
thickness is 1.00mm.

The 3rd drawing shows allied mechanical data of SOM-A2558 series
board and CSB. Users could see that the matting height is 3.00mm and the
solder side maximum height of SOM-A2558 is also 3.00mm. So, Advantech

don’t suggest users to place any components between SOM module and
CSB in layout stage. It could be short!

Most users will question the height of SOM structure product. Does
product be too thick based on SOM structure product? User could see the

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answer in the 3rd mechanical drawing. Maximum height of SOM module allied
with CSB is 5.20mm. One port USB 1.1 host connector height is 8.37mm, 1
DB-9 RS-232 connector is 12.53mm, 1 type-II CF slot is 8.72mm. So, this is
the answer! If users want to use any standard I/O connector on CSB, then
SOM structure is not the maximum height maker. The maximum highness is
decided by I/O connector, not SOM structure.

1.2.2 Power System Requirement

SOM-A2558 Operating DC value table

Symbol Description Min. Typ.

SYS_VCC3P3 SOM system DC 3.3V DC-in

power source 3 3.3 3.6

SYS_VCC
BAT_VCC

SOM system DC 5.0V DC-in
power source 4.5 5.5 5.5
Back-up power source for RTC &
SDRAM -

Input DC Operating Conditions

VIH

VIL

Input High Voltage, all standard
input and I/O pins
Input Low Voltage, all standard
input and I/O pins VSS

0.8*VCC

Output DC Operating Conditions

VOH

VOL

Output High Voltage, all standard
output and I/O pins VCC-0.1
Output Low Voltage, all standard
output and I/O pins VSS

Max.

SYS_VC

C3P3

VCC

0.2*VCC

VCC

VSS+0.4

1.2.3 Power Consumption

In WinCE O.S. environment, SOM-A2558 series products have 3 kinds of
operating model :

l Normal mode: I/O and system all work well. All components on

SOM-A55x are powered.

l Idle mode: I/O and system all work well except backlight control

circuit. In order to do power-saving, LCD backlight control circuit
will disable the LCD backlight inverter.

l Suspend mode: all devices are no-powered except SDRAM,

RTC(real time clock) & some CPU(PXA255) power pins. In
suspend mode, SOM-A255x series are only powered by
BAT_VCC pin ( Li-ion 3.0V coin battery from CSB).If user doesn’t
design coin battery to power BAT_VCC pin, then Suspend mode
doesn’t work on SOM-A55x series products.

About detail power consumption of every SOM-A255x series, please
contact with [e-mail].

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Chapter 2 Assignments and Descriptions

2.1 Connector Locations

Figure SOM-A2558 series component side

Figure SOM-A2558 series solder side

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SOM Connector vendor table

Connector vendor PN

AMI bus (X1) Matsushita electric works,

AXK600335

LTD.

SOM-R200 (X2) Standard Golden finger

-

200-pin

Feature extension bus

(X3)

JP1 PXA255 JTAG pin header

Matsushita electric works,

LTD.

AXK600335

-

JP2 SOM CPLD JTAG port -

PS.JP1 & JP2 are 2.00 mm 6*1 pin-headers.

CSB Mating Connector table

Connector vendor PN

AMI bus (X1) Matsushita electric works,

AXK500135

LTD.

SODIMM-200 (X2) QUASAR SYSTEM INC. CA0075-200N31

Feature extension bus

(X3)

Matsushita electric works,

LTD.

AXK500135

In advantech RISC SOM-A200 ultra low power series (SOM-A2552,
SOM-A2558 and SOM-A2558) all follow the same pin definition in X1,X2 and
X3. So, users could design their own CSB to be compatible with all advantech
RISC ultra low power series SOM easily. In this way, users’ CSB will have
powerful upgrade capability & option choice.

X1: AMI bus

AMI bus connector is PXA255 ARM bus. It includes complete system
address lines, data lines, GPIOs (for interrupt source) and Chip select pins
(nCS). Users could use this bus to extend any other IC controller on CSB to
implement the function which SOM modules not provide. In order to keep the
system bus signals well, every address lines and data lines are driven by
buffers. Buffers’ signals direction controls are implemented by CPLD.

X2: SODIMM-200 connector

Most I/O functions fog in X2. X2 includes PCMCIA/CF, T/S, Audio, system
reset control, SOM system power input pins, I2C, USB host, USB client,
RS-232 ports, RS-485 port, LCD out and PS/2 ports. Every I/O functions will
be described in the following content in detail.

X3: Feature Extension connector

Advantech SOM-A200 series products use dual-chip or triple-chip design
concepts. The companion chip’s I/O function will come out through the X3. In
SOM-A2558 series, PCI, SD/MMC I/F is included in X3.

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RECD SOM is a powerful and helpful architecture for internal or users use
to implement a RISC system. There are three types of interfaces. One is
SO-DIMM 200 gold finger interface and two 100-pin B2B connectors.

Pin Definition

¦JP1 PXA255 JTAG pin header

Pin Num. Description Note

1 TCK
2 TDI
3 TDO
4 TMS
5 nJTAGTRST
6 GND
7 nRESET

Pin type

P : DC power pin or system ground pin
I : digital input pin
O : digital output pin
IO : bidirectional pin
AI : analog input pin
AO : analog output pin

- : no function

¦SODIMM-200 Pin Out Table (X2)

Pin
No.

1 SA_SKT_D0 AIO PCMCIA/CF data 0 No pulling
2 SA_SKT_D8 IO PCMCIA/CF data 8 No pulling
3 SA_SKT_D1 IO PCMCIA/CF data 1 No pulling
4 SA_SKT_D9 IO PCMCIA/CF data 9 No pulling
5 SA_SKT_D2 IO PCMCIA/CF data 2 No pulling
6 SA_SKT_D10 IO PCMCIA/CF data 10 No pulling
7 SA_SKT_D3 IO PCMCIA/CF data 3 No pulling
8 SA_SKT_D11 IO PCMCIA/CF data 11 No pulling
9 SA_SKT_D4 IO PCMCIA/CF data 4 No pulling

10 SA_SKT_D12 IO PCMCIA/CF data 12 No pulling
11 SA_SKT_D5 IO PCMCIA/CF data 5 No pulling
12 SA_SKT_D13 IO PCMCIA/CF data 13 No pulling
13 SA_SKT_D6 IO PCMCIA/CF data 6 No pulling
14 SA_SKT_D14 IO PCMCIA/CF data 14 No pulling
15 SA_SKT_D7 IO PCMCIA/CF data 7 No pulling
16 SA_SKT_D15 IO PCMCIA/CF data 15 No pulling
17 SA_SKT_A14 IO PCMCIA/CF address 14 No pulling

Signals Typ

e

Description Default state

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18 SA_SKT_A15 IO PCMCIA/CF address 15 No pulling
19 SA_SKT_A12 IO PCMCIA/CF address 12 No pulling
20 SA_SKT_A13 IO PCMCIA/CF address 13 No pulling
21 SA_SKT_A10 IO PCMCIA/CF address 10 No pulling
22 SA_SKT_A11 IO PCMCIA/CF address 11 No pulling
23 SA_SKT_A8 IO PCMCIA/CF address 8 No pulling
24 SA_SKT_A9 IO PCMCIA/CF address 9 No pulling
25 SA_SKT_A6 IO PCMCIA/CF address 6 No pulling
26 SA_SKT_A7 IO PCMCIA/CF address 7 No pulling
27 SA_SKT_A4 IO PCMCIA/CF address 4 No pulling
28 SA_SKT_A5 IO PCMCIA/CF address 5 No pulling
29 SA_SKT_A2 IO PCMCIA/CF address 2 No pulling
30 SA_SKT_A3 IO PCMCIA/CF address 3 No pulling
31 SA_SKT_A0 IO PCMCIA/CF address 0 No pulling
32 SA_SKT_A1 IO PCMCIA/CF address 1 No pulling
33 SA_SKT_A16 IO PCMCIA/CF address 16 No pulling
34 SA_SKT_A17 IO PCMCIA/CF address 17 No pulling
35 SA_SKT_A18 IO PCMCIA/CF address 18 No pulling
36 SA_SKT_A19 IO PCMCIA/CF address 19 No pulling
37 SA_SKT_A20 IO PCMCIA/CF address 20 No pulling
38 SA_SKT_A21 IO PCMCIA/CF address 21 No pulling
39 SA_SKT_A22 IO PCMCIA/CF address 22 No pulling
40 nSA_SKT_IOR O PCMCIA I/O read. Performs read

No pulling
transactions from PCMCIA I/O
space.

41 SA_SKT_A24 IO PCMCIA/CF address 24 No pulling
42 XP AI 4-wires resistive touch screen

No pulling
signals: X+ Position Input.

43 nSA_SKT_WE O PCMCIA write enable. (output)

No pulling
Performs writes to PCMCIA
memory and to PCMCIA attribute
space. Also used as the write
enable signal for Variable Latency
I/O.

44 YP AI 4-wires resistive touch screen

No pulling
signals: Y+ Position Input.

45 nSA_SKT_IOW O PCMCIA I/O write signal. (output)

No pulling
Performs write transactions to
PCMCIA I/O space.

46 XN AI 4-wires resistive touch screen

No pulling
signals: X– Position Input

47 nSA_SKT_REG O PCMCIA Register select. (output)

No pulling
Indicates that the target address
on a memory transaction is
attribute space. Has the same
timing as the address bus.

48 YN AI 4-wires resistive touch screen

No pulling
signals: Y– Position Input

49 SA_SKT_A23 IO PCMCIA/CF address 23 No pulling

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PCMCIA/CF slot 0 card enable pin

PCMCIA/CF slot 0 card enable pin

PCMCIA/CF slot 1 card enable pin

Pull high with

Pull high with

PCMCIA/CF slot 0 card enable pin

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

PCMCIA/CF slot 0 wait signals.

Driven low by the PCMCIA card to

he length of the transfers

Pull high with

PCMCIA/CF slot 1 card detect pin

50 GND P Ground -
51 SA_SKT_A25 IO PCMCIA/CF address 25 No pulling
52 AC97_EAPD O External audio Amplifier power

No pulling
down control

53 nSA_SKT_OE O PCMCIA output enable. (output)

No pulling
Reads from PCMCIA memory and
to PCMCIA attribute space.

54 LINEOUT_R AO Audio line-Out right channel ­55 nSA_SKT1_CD1 I PCMCIA/CF slot 0 card detect pin No pulling

56 LINEOUT_L AO Audio line-Out left channel ­57 nSA_SKT0_CD1 I PCMCIA/CF slot 1 card detect pin

No pulling

1.

58 AC97_LINEIN_R AI Audio line input right channel. ­59 nSA_SKT1_CE1 O

1.

60 AC97_LINEIN_L AI Audio line input left channel. ­61 nSA_SKT0_CE1 O

1.

62 MIC_IN AI First Microphone input ­63 nSA_SKT1_CE2 O

2.

64 GND P Ground -
65 SA_SKT1_VCC P PCMCIA/CF slot 1 power pin ­66 nSA_SKT0_VS1 I PCMCIA/CF slot 0 voltage sense

pin 1.

67 nSA_SKT1_VS1 I PCMCIA/CF slot 1 voltage sense

pin 1.

68 nSA_SKT0_CE2 O

2.

69 SA_SKT1_RDY I PCMCIA/CF slot 1 ready pin.
70 SA_SKT0_RDY I PCMCIA/CF slot 0 ready pin.
71 nSA_SKT0_VS2 I PCMCIA/CF slot 0 voltage sense

pin 2.

72 nSA_SKT1_VS2 I PCMCIA/CF slot 1 voltage sense

pin 2.

73 SA_SKT0_RST O PCMCIA/CF slot 0 reset pin.
74 SA_SKT1_RST O PCMCIA/CF slot 1 reset pin.
75 nSA_SKT0_W

I

AIT

extend t
to/from the PXA255 processor.

76 nSA_SKT1_CD I

No pulling

No pulling

No pulling

10Kohm

10Kohm

No pulling

10Kohm

10Kohm

10Kohm

10Kohm

10Kohm

10Kohm

10Kohm

No pulling

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Pull high with

PCMCIA/CF slot 0 card detect pin

Pull high with

Pull high with

System suspend/wakeup input pin.

Pull high with

Exception,

Pull high with

Pull high with

assertion time for nVDD_FAULT is

Pull high with

nRESET is asserted and deasserts

2 2.

77 nSA_SKT1_W

AIT

I PCMCIA/CF slot 1 wait signals.

Driven low by the PCMCIA card to

10Kohm
extend the length of the transfers
to/from the PXA255 processor.

78 nSA_SKT0_CD2 I

No pulling

2.

79 nSA_SKT0_IOI

S16

I IO Select 16. (input) Acknowledge

from the PCMCIA card that the

10Kohm
current address is a valid 16 bit
wide I/O address.

80 SA_SKT0_VCC P PCMCIA/CF slot 0 power pin. Powered
81 nSA_SKT1_IOI

S16

I PCMCIA/CF slot 0 IO Select 16.

Acknowledge from the PCMCIA

10Kohm
card that the current address is a
valid 16 bit wide I/O address.

82 nSA_PWR_ON I

Falling edge triggered.

10Kohm

83 nBATT_FALT I Main Battery Fault. Signals that

main battery is low or removed.

100Kohm
Assertion causes PXA255
processor to enter sleep mode or
force an Imprecise Data
which cannot be masked. PXA255
processor will not recognize a
wakeup event while this signal is
asserted. Minimum assertion time
for nBATT_FAULT is 1 ms.

84 nSW_RESET I System software reset input pin.

Falling edge triggered.

10Kohm

85 nVDD_FALT I VDD Fault. Signals that the main

power source is going out of

100Kohm
regulation. nVDD_FAULT causes
the PXA255 processor to enter
sleep mode or force an Imprecise
Data Exception, which cannot be
masked. nVDD_FAULT is ignored
after a wakeup event until the
power supply timer completes
(approximately 10 ms). Minimum

86 nRESET_OUT O Reset Out. Asserted when

87 GND P Ground -

1 ms.

No pulling
after nRESET is deasserted but

before the first instruction fetch.
nRESET_OUT is also asserted for
“soft” reset events: sleep,
watchdog reset, or GPIO reset.

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remove power to the core because

Pull high with

ion coin battery positive

to start the processor from a known

low until the power supply is stable

Pull high with

device

powered by DC 3.3V even in sleep

powered by DC 3.3V even in sleep

System Management Bus clock

pin. The pin is implemented by

Pull high with

powered by DC 3.3V even in sleep

88 PWR_EN

Power Enable for the power

O

supply. (output) When negated, it
signals the power supply to

the system is entering sleep mode.

89 BAT_VCC P 3.0V li-

pole input pin.

90 nRESET I System hardware reset input pin.

Falling edge triggered. Hard reset.
(input) Level sensitive input used

address. Assertion causes the
current instruction to terminate
abnormally and causes a reset.
When nRESET is driven high, the
processor starts execution from
address 0. nRESET must remain

and the internal 3.6864 MHz
oscillator has stabilized.

91 nDC_IN I System DC input indicator pin.

When the pin is low, it means
system is powered by external DC
power source. If user target
is not power by battery, use could
use this pin as GPIO. The pin
connects to SoC PXA255 GPIO16.

92 SYS_VCC P SOM system DC power 5V input

pin. SYS_VCC should always be
powered by DC 5V even in sleep
mode.

93 SYS_VCC3P3 P SOM system DC power 3.3V input

pin. SYS_VCC should always be

100Kohm

No pulling

10Kohm

Pull low with

1Kohm

-

-

94 SYS_VCC P SOM system DC power 5V input

95 SYS_VCC3P3 P SOM system DC power 3.3V input

96 SMBUS_CLK IO

97 SYS_VCC3P3 P SOM system DC power 3.3V input

mode.

­pin. SYS_VCC should always be
powered by DC 5V even in sleep
mode.

­pin. SYS_VCC should always be

mode.

4.7Kohm
SoC PXA255 I2C bus.

­pin. SYS_VCC should always be

mode.

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22

System Management Bus data pin.

Pull high with

ed by DC 3.3V even in sleep

powered by DC 3.3V even in sleep

powered by DC 3.3V even in sleep

client link status indicator pin.

function, user could use this pin as

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

doesn’t need UART2 function, user

Pull high with

doesn’t need UART3 function, user

Pull high with

Pull high with

98 SMBUS_DAT IO

The pin is implemented by SoC
PXA255 I2C bus.

99 SYS_VCC3P3 P SOM system DC power 3.3V input

pin. SYS_VCC should always be
power
mode.

100

USB_CP IO USB Client Positive pin No pulling

101 SYS_VCC3P3 P SOM system DC power 3.3V input

pin. SYS_VCC should always be
mode.

102

USB_CN IO USB Client Negative pin. No pulling

103 SYS_VCC3P3 P SOM system DC power 3.3V input

pin. SYS_VCC should always be
mode.

104 BUZZER_OUT O Buzzer-out control signals. User

can use the pin to control buzzer
power pin.

105 USB_LINK_5V I USB

When the pin is high, it means
USB client port has been
plugged-in USB device.

106 UART2_RTS O UART2 Request-to-Send signal

pin. If user doesn’t need UART2

4.7Kohm

-

Powered

-

No pulling

Pull low with
100Kohm

100Kohm

GPIO. The pin connects to SoC
PXA255 GPIO45.

107

GND P Ground -

108 UART2_DCD I UART2 data-Carrier-Detect signal

pin.

109 UART3_DCD I UART3 data-Carrier-Detect signal

pin.

110 UART2_DSR I UART2 Data-Set-Ready signal pin.
111 UART3_DSR I UART3 Data-Set-Ready signal pin.
112 UART2_TXD O UART2 Transmit signal pin. If user

could use this pin as GPIO. The
pin connects to SoC PXA255
GPIO43.

113 UART3_RXD I UART3 Receive signal pin. If user

could use this pin as GPIO. The
pin connects to SoC PXA255
GPIO46.

114 UART2_RXD I UART2 Receive signal pin. If user

100Kohm
100Kohm
100Kohm
100Kohm
100Kohm

100Kohm

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doesn’t need UART2 function, user

Pull high with

ignal pin. If

user doesn’t need UART2 function,

Pull high with

UART3 Transmit signal pin. If user

doesn’t need UART3 function, user

The

pin connects to SoC PXA255

Pull high with

Ready signal

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Active states indicate the good link

operations. It is also an active LED

with

could use this pin as GPIO. The
pin connects to SoC PXA255
GPIO42.

115 UART3_RTS O UART3 Request-to-Send signal

pin.

116 UART2_CTS I UART2 Clear-to-Send s

user could use this pin as GPIO.
The pin connects to SoC PXA255
GPIO44.

117 UART3_TXD O

could use this pin as GPIO.
GPIO47.

118 UART2_DTR O UART Data-Terminal-

pin.

119 UART3_CTS I UART3 Clear-to-Send signal pin.
120

UART2_RI I UART2 Ring Indicator signal pin.

121 UART3_DTR O UART3 Data-Terminal-Ready

signal pin.

122

UART3_RI I UART3 Ring Indicator signal pin.

123 UART1_DSR I UART1 Data-Set-Ready signal pin.
124 UART1_DCD I UART1 Data-Carrier-Detect signal

pin.

125 UART1_CTS I UART1 Clear-to-Send signal pin.
126 UART1_RXD I UART1 Receive signal pin.
127 UART1_RTS O UART1 Request-to-Send signal

pin.

128 UART1_TXD O UART1 Transmit signal pin.
129 UART1_DTR O UART1 Data-Terminal-Ready

signal pin.

130
131

132

GND P Ground -

UART1_RI I UART Ring Indicator signal pin. Pull high with

TX- O 10/100 BASE-T transmit Data

negative pin.

133 nLINK_LED O Link LED & Activity LED.

for 10Mbps and 100Mbps

100Kohm

100Kohm
100Kohm

100Kohm

100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm
100Kohm

100Kohm
No pulling

Pull high
10Kohm

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24

T transmit Data

ith

logic power MOS switch to achieve

control STN LCD VEE power MOS

Pull high with

function when transmitting or
receiving data. Active states see
LED configuration OP2: (power up
reset latch input) This pin is used
to control the forced or advertised
operating mode of the DM9161
according to the Table A. The
value is latched into the DM9161
registers at power-up/reset

134

TX+ O 10/100 BASE-

positive pin.

135 nSPEED_LED O Speed LED. Active states indicate

the 100Mbps mode. Active states
see LED configuration When bit 6
of Register 16 is set high, it
controls the SPEED LED as
100Base-TX SD signal output. For
debug only OP1: (power up reset
latch input) This pin is used to
control the forced or advertised
operating mode of the DM9161
according to the Table A. The
value is latched into the DM9161
registers at power-up/reset

136
137

GND P Ground -

VDD_ENA O LCD power control signal. User

can use this pin to control the LCD

No pulling
Pull high w

10Kohm

No pulling

power-saving.

138

RX- I 10/100 BASE-T receive data

negative pin.

139

VEE_ENA O STN LCD VEE power control

signal. User can use this pin to
switch to achieve power-saving.

140

RX+ I 10/100 BASE-T receive data

negative pin.

141

VBK_ENA O LCD back light inverter power

control signal. User can use this
pin to control the LCD backlight
inverter to achieve power-saving.

142
143
144
145
146
147

USB_N1 IO USB host port1 D- data line. No pulling
USB_N2 IO USB host port2 D- data line. No pulling

USB_P1 IO USB host port1 D+ data line. No pulling
USB_P2 IO USB host port2 D+ data line. No pulling

N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -

148 UART5_RXD I UART5 Receive signal pin.

No pulling
No pulling

No pulling
No pulling

100Kohm

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with

Ready

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

Pull high with

One of LCD inverter backlight

l signals.

ncrease

or decrease Wiper Control.

Advantech suggests to connect the

One of LCD inverter backlight

brightness control signals.

Up/Down

Control. Advantech suggests to

One of LCD inverter backlight

brightness control signals.

is used be chip select

Advantech suggests to

One of STN LCD contrast control

is used be

. Advantech suggests to

One of STN LCD contrast control

is used be

. Advantech

suggests to connect the pin to

One of STN LCD contrast control

VCONR_UnD is used be

149 UART4_RXD I UART5 Receive signal pin.
150 UART5_RTS O UART5 Data-Terminal-

signal pin.

151 UART4_TXD O UART4 Transmit signal pin.
152 UART5_TXD O UART5 Transmit signal pin.

153
154

MSCLK IO PS/2 mouse clock

KBDATA IO PS/2 keyboard data

155

MSDATA IO PS/2 mouse data

156

KBCLK IO PS/2 keyboard clock

157 nVBRIR_INC O

brightness contro
nVBRIR_INC is used to i

pin to DS1804 1st pin.

158

N.C. - N.C. just float this pin. -

159 nVBRIR_UnD O

Pull high
100Kohm

100Kohm
100Kohm
100Kohm
10Kohm
10Kohm
10Kohm
10Kohm

No pulling

No pulling

160
161

162

N.C. - N.C. just float this pin. -

VBRIR_CS O

N.C. - N.C. just float this pin. -

163 nVCONR_INC O

164

N.C. - N.C. just float this pin. -

165 VCONR_CS O

166

N.C. - N.C. just float this pin. -

167 VCONR_UnD O

nVBRIR_UnD is used be
connect the pin to DS1804 2nd pin.

No pulling

VBRIR_CS
pin.
connect the pin to DS1804 7th pin.

No pulling
signals. nVCONR_INC
increase/decrease Wiper Control
pin
connect the pin to DS1804 1st pin.

No pulling
signals. VCONR_CS
chip select pin

DS1804 7th pin.

No pulling
signals.

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26

Up/Down Control. Advantech

suggests to connect the pin to

Reserved for future use. User can

CRT I2C data

Pull high with

Reserved for future use. User can

connect the pin to CRT I2C clock

Pull high with

STN displays, this output connects

DS1804 2nd pin.

168

CRT_SDA -

connect the pin to
pin or just float it.

169

CRT_CLK -

pin or just float it.

170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195

B0 O B0 in 24-bit TFT mode. No pulling
B1 O B in 24-bit TFT mode. No pulling
B2 O B in 24-bit TFT mode. No pulling
B3 O B in 24-bit TFT mode. No pulling
B4 O B in 24-bit TFT mode. No pulling
B5 O B in 24-bit TFT mode. No pulling
B6 O B in 24-bit TFT mode. No pulling
B7 O B in 24-bit TFT mode. No pulling
G0 O G in 24-bit TFT mode. No pulling
G1 O G in 24-bit TFT mode. No pulling
G2 O G in 24-bit TFT mode. No pulling
G3 O G in 24-bit TFT mode. No pulling
G4 O G in 24-bit TFT mode. No pulling
G5 O G in 24-bit TFT mode. No pulling
G6 O G in 24-bit TFT mode. No pulling
G7 O G in 24-bit TFT mode. No pulling
R0 O R in 24-bit TFT mode. No pulling
R1 O R in 24-bit TFT mode. No pulling
R2 O R in 24-bit TFT mode. No pulling
R3 O R in 24-bit TFT mode. No pulling
R4 O R in 24-bit TFT mode. No pulling
R5 O R in 24-bit TFT mode. No pulling
R6 O R in 24-bit TFT mode. No pulling

R7 O R in 24-bit TFT mode. No pulling
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -

196 FLM_VSYNC O Flat Panel TFT Vertical Sync/STN

Frame Pulse. For TFT displays,
this output connects to the Vertical
Sync input of the LCD panel. For

4.71Kohm

4.71Kohm

No pulling

197 LP_HSYNC O Flat Panel TFT Vertical Sync/STN

to the Frame Clock input of the
LCD panel.
This output indicates the start of a
new frame of pixels. The panel
needs to reset its line pointers to
the top of the screen.

No pulling
Frame Pulse. For TFT displays,
this output connects to the Vertical

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STN displays, this output connects

Flat Panel Display Enable. This

signal is used as a data enable

when the pixel clock needs to latch

connects to the TXCLK input of the

Chip selects to

static memory devices such as ROM

and Flash. Individually

programmable in the memory

configuration registers. This pin can

be used with variable latency I/O

devices. nBUF_CS2 directly connect

could

use this pin as chip select pin to

control the solution IC on carrier

board. This pin is reserved for user

Connect

Sync input of the LCD panel. For
to the Frame Clock input of the

LCD panel.
This output indicates the start of a
new frame of pixels. The panel
needs to reset its line pointers to
the top of the screen.

198
199

GND P Ground -

M_DE O

No pulling

pixel data.

200

SHCLK O Flat Panel Pixel Clock. The active

No pulling
edge of FPCLK is programmable.
The LCD panel uses this clock
when loading pixel data into its
Line Shift register. This signal

LVDS transmitter.

¦100-pin B2B connector Pin Out Table (X1 connector, For AMI
interface)

Pin
No.

Signals Type

Description

Static chip selects.

Default

state

Pull-high

B1 nBUF_CS2 O

to SoC PXA255 nCS2. User

with 100K

ohm

to use.

A1 ADDR15 O SoC PXA255 system address 15 No pulling
B2 ADDR14 O SoC PXA255 system address 14 No pulling
A2 ADDR13 O SoC PXA255 system address 13 No pulling
B3 ADDR12 O SoC PXA255 system address 12 No pulling
A3 ADDR11 O SoC PXA255 system address 11 No pulling
B4 ADDR10 O SoC PXA255 system address 10 No pulling
A4 ADDR9 O SoC PXA255 system address 9 No pulling
B5 ADDR8 O SoC PXA255 system address 8 No pulling
A5 ADDR24 O SoC PXA255 system address 24 No pulling
B6 ADDR25 O SoC PXA255 system address 25 No pulling
A6 nBUF_OE O Memory output enable pin.

No pulling

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28

to the output enables of memory

Connect to the

Signals that the current transaction

Variable Latency I/O Ready pin.

Notifies the memory controller when

an external bus device is ready to

Connect to the row

address strobe (RAS) pins for all

Connect to

for SDRAM.

For the PXA255 processor

SDRAM DQM for data byte 0.

Connect to the data output mask

SDRAM DQM for data byte 2.

SDRAM DQM for data byte 3.

Connect to the data output mask

(input) Driven low by

the PCMCIA card to extend the

devices to control data bus drivers.

B7 ADDR20 O SoC PXA255 system address 20 No pulling

Memory write enable.

A7 nBUF_WE O

write

No pulling

enables of memory devices.

B8 ADDR22 O SoC PXA255 system address 22 No pulling

BUF_RD_nW

A8

R

Read/Write for static interface.

O

is a read or write.

No pulling

B9 GND P Ground -

Pull high

A9 BUF_RDY I

transfer data.

with

100Kohm

B10 DATA15 IO SoC PXA255 system data 15 No pulling
A10 DATA14 IO SoC PXA255 system data 14 No pulling
B11 DATA13 IO SoC PXA255 system data 13 No pulling
A11 DATA12 IO SoC PXA255 system data 12 No pulling
B12 DATA11 IO SoC PXA255 system data 11 No pulling
A12 DATA10 IO SoC PXA255 system data 10 No pulling
B13 DATA9 IO SoC PXA255 system data 9 No pulling
A13 DATA8 IO SoC PXA255 system data 8 No pulling
B14 DATA31 IO SoC PXA255 system data 31 No pulling
A14 DATA30 IO SoC PXA255 system data 30 No pulling
B15 DATA29 IO SoC PXA255 system data 29 No pulling
A15 DATA28 IO SoC PXA255 system data 28 No pulling
B16 DATA27 IO SoC PXA255 system data 27 No pulling
A16 DATA26 IO SoC PXA255 system data 26 No pulling
B17 DATA25 IO SoC PXA255 system data 25 No pulling
A17 DATA24 IO SoC PXA255 system data 24 No pulling

nBUF_SDRA

B18

S

SDRAM RAS.

O

banks of SDRAM.

No pulling

SDRAM CS for bank 0.

nBUF_SDCS

A18

0

the chip select (CS) pin

O

No pulling

nBUF_SDCS0 can be Hi-Z.

B19 BUF_DQM0 O

A19 BUF_DQM2 O

B20 BUF_DQM3 O

A20 nBUF_PWAIT I

enables (DQM) for SDRAM.
Connect to the data output mask

enables (DQM) for SDRAM.

enables (DQM) for SDRAM.
PCMCIA wait.

No pulling

No pulling

No pulling

Pull high

with

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29

o/from the

Connect SDCLK

[1] to the clock pins of SDRAM in

bank pairs 0/1. They are driven by

either the internal memory controller

clock, or the internal memory

ided by 2. At

reset, all clock pins are free running

at the divide by 2 clock speed and

may be turned off via free running

control register bits in the memory

controller. The memory controller

also provides control register bits for

sertion of

each SDCLK pin. SDCLK[2:1]

control register assertion bits are

SDRAM and/or Synchronous Static

Connect to

the clock enable pins of SDRAM. It is

ep.

BUF_SDCKE1 is always deasserted

upon reset. The memory controller

provides control register bits for

255F

length of the transfers t

100Kohm

PXA255 processor.

SDRAM Clock 1.

controller clock div

BUF_SDCLK

B21

1

O

No pulling

clock division and deas

always deasserted upon reset.
Memory clock enable.

No pulling

(For

BUF_SDCKE

A21

1

deasserted during sle

O

SOM-

is

BUF_SDC

KE1)

deassertion.

B22 GND P Ground -
A22 ADDR0 O SoC PXA255 system address 0 No pulling
B23 ADDR1 O SoC PXA255 system address 1 No pulling
A23 ADDR2 O SoC PXA255 system address 2 No pulling
B24 ADDR3 O SoC PXA255 system address 3 No pulling
A24 ADDR4 O SoC PXA255 system address 4 No pulling
B25 ADDR5 O SoC PXA255 system address 5 No pulling
A25 ADDR6 O SoC PXA255 system address 6 No pulling
B26 ADDR7 O SoC PXA255 system address 7 No pulling
A26 ADDR16 O SoC PXA255 system address 16 No pulling
B27 ADDR17 O SoC PXA255 system address 17 No pulling
A27 ADDR18 O SoC PXA255 system address 18 No pulling
B28 ADDR19 O SoC PXA255 system address 19 No pulling
A28 ADDR21 O SoC PXA255 system address 21 No pulling
B29 ADDR23 O SoC PXA255 system address 23 No pulling
A29 DATA0 IO SoC PXA255 system data 0 No pulling
B30 DATA1 IO SoC PXA255 system data 1 No pulling
A30 DATA2 IO SoC PXA255 system data 2 No pulling
B31 DATA3 IO SoC PXA255 system data 3 No pulling
A31 DATA4 IO SoC PXA255 system data 4 No pulling
B32 DATA5 IO SoC PXA255 system data 5 No pulling
A32 DATA6 IO SoC PXA255 system data 6 No pulling
B33 DATA7 IO SoC PXA255 system data 7 No pulling

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30

Connect to the

strobe (CAS) pins

the chip select (CS) pins for SDRAM.

For the PXA255 processor nSDCS0

1.

Connect to the data output mask

Connect

BUF_SDCLK[2] to the clock pins of

SDRAM in bank pairs 2/3. They are

driven by either the internal memory

controller clock, or the internal

y controller clock divided by

2. At reset, all clock pins are free

running at the divide by 2 clock

speed and may be turned off via free

running control register bits in the

memory controller. The memory

controller also provides control

lock division and

deassertion of each SDCLK pin.

SDCLK[2:1] control register

assertion bits are always deasserted

. Acknowledge from the

PCMCIA card that the current

address is a valid 16 bit wide I/O

Performs

writes to PCMCIA memory and to

PCMCIA attribute space. Also used

as the write enable signal for

GPIO pin. Advantech default

tion is used as matrix Keypad

IRQ. The pin directly connects to

PXA255 GPIO2 (L13 pin). If user

doesn’t use the matrix key pad

A33 DATA16 IO SoC PXA255 system data 16 No pulling
B34 DATA17 IO SoC PXA255 system data 17 No pulling
A34 DATA18 IO SoC PXA255 system data 18 No pulling
B35 DATA19 IO SoC PXA255 system data 19 No pulling
A35 DATA20 IO SoC PXA255 system data 20 No pulling
B36 DATA21 IO SoC PXA255 system data 21 No pulling
A36 DATA22 IO SoC PXA255 system data 22 No pulling
B37 DATA23 IO SoC PXA255 system data 23 No pulling

nBUF_SDCA

A37

S

SDRAM CAS.

O

column address
for all banks of SDRAM.

No pulling

SDRAM CS for banks 2. Connect to

nBUF_SDCS

B38

2

O

No pulling

can be Hi-Z, Nsdcs1-3 cannot.
SDRAM DQM for data bytes

A38 BUF_DQM1 O

No pulling

enables (DQM) for SDRAM.

SDRAM Clock 2.

BUF_SDCLK

B39

2

O

A39 nBUF_IOIS16 I

B40 nBUF_PWE O

A40 KEYPAD_IRQ I

memor

register bits for c

upon reset.
IO Select 16

address.
PCMCIA write enable.

Variable Latency I/O.
func

No pulling

Pull high

with

100Kohm

No pulling

No pulling

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31

function, use can use this pin as

Advantech use this pin to control

unction. The pin

is not available for CSB design of

A255F

A2552 &

A255F user must float this pin.

This pin is directly connected to SoC

GPIO pin. The pin directly connects

IO7 (G15 pin). This

255F

Advantech default function is used

as external 16C950 solution IC IRQ.

o PXA255

GPIO10 (F7 pin). If user doesn’t

design 16C950 on CSB to expand

COM function, user could use this

Advantech default function is used

as external LAN solution IC IRQ. The

pin directly connects to PXA255

7 (D12 pin). If user doesn’t

design the other LAN chip on CSB to

expand LAN function, user could use

Advantech default function is used

as external USB host solution IC

IRQ. The pin directly connects to

IO27 (B9 pin). If user

doesn’t design the other USB

solution chip on CSB to expand USB

host function, user could use this pin

Advantech default function is used

as external 16C954 solution IC IRQ.

ts to PXA255

GPIO32 (A16 pin). If user doesn’t

design 16C950 on CSB to expand

COM function, user could use this

GPIO pin. The pin directly connects

to PXA255 GPIO81 (F16 pin). This

GPIO pin. The pin directly connects

GPIO pin.
display chip as IRQ f

DISPLAY_IR

B41

Q

-

A41 PXA_GP7 IO

B42

A42

N.C. - N.C. just float this pin. -

C950_485_IR
Q

I

B43 LAN1_IRQ I

SOM-A2552 & SOM­platform. SOM­SOM-

PXA255 GPIO3(K14).

to PXA255 GP
GPIO pin is available for user to use.

The pin directly connects t

pin as GPIO.

GPIO1

-

No pulling

(For

SOM-

is

PXA_GPIO

7)

No pulling

No pulling

A43 USB_IRQ I

B44 C954_IRQ I

A44 PXA_GP81 IO
B45 PXA_GP82 IO

this pin as GPIO.

PXA255 GP

as GPIO.

The pin directly connec

pin as GPIO.

GPIO pin is available for user to use.

No pulling

No pulling

No pulling
No pulling

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32

to PXA255 GPIO82 (E16 pin). This

GPIO pin. The pin directly connects

to PXA255 GPIO83 (E15 pin). This

GPIO pin. The pin directly connects

to PXA255 GPIO84 (D16 pin). This

Chip selects to

static memory devices such as ROM

nd Flash. Individually

programmable in the memory

configuration registers. nBUF_CS1

can be used with variable latency I/O

devices. Advantech default uses this

pin as storage flash chip select pin. If

no special application, Advantech

to open this

Chip selects to

static memory devices such as ROM

programmable in the memory

CS3

can be used with variable latency I/O

Advantech uses the pin as I/O

memory block. About detail

description, please reference

A255x series Memory and

to

static memory devices such as ROM

and Flash. Individually

programmable in the memory

configuration registers. nBUF_CS5

can be used with variable latency I/O

Advantech default uses the pin as

display chip chip select pin.

or SM501 on

A255F series. If

no special application, Advantech

strongly suggest user to open this

Notifies

the DMA Controller that an external

ransaction. If

user wants to design a controller in

GPIO pin is available for user to use.

A45 PXA_GP83 IO

B46 PXA_GP84 IO

A46 nBUF_CS1 O

B47

N.C. - N.C. just float this pin. -

A47 nBUF_CS3 O

GPIO pin is available for user to use.

GPIO pin is available for user to use.
Static chip selects.

a

strongly suggest user
pin in CSB.

Static chip selects.
and Flash. Individually
configuration registers. nBUF_
devices.

No pulling

No pulling

Pull high

with

100Kohm

Pull high

with

100Kohm

B48 nBUF_CS5 O

A48 DMA_REQ1 I

“SOM­Interrupt Map”.

Static chip selects. Chip selects

devices.

nBUF_CS4 pin is used f
SOM-A2552 & SOM-

pin in CSB.
Channel 1 DMA Request.

device requires a DMA t

Pull high

with

100Kohm

Pull low

with 1Kohm

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33

CSB with DMA mode, please check

first.

If use doesn’t want to use this pin as

DMA_REQ, use could use the pin as

n connects to SoC

Memory Controller alternate bus

Allows an external

device to request the system bus

from the Memory Controller. If user

wants to design a controller in CSB

tion, please check

If use doesn’t want to use this pin as

DMA_REQ, use could use the pin as

GPIO. The pin connects to SoC

Channel 1 DMA acknowledge.

Notifies an external device that it has

been acknowledged the DMA

controller. If user wants to design a

controller in CSB with DMA mode,

please check with

If use doesn’t want to use this pin as

DMA_ACK, use could use the pin as

GPIO. The pin connects to SoC

Notifies an

external device that it has been

granted the system bus. If user

nts to design a controller in CSB

with this pin function, please check

first.

If use doesn’t want to use this pin as

MBGNT, use could use the pin as

oC

Output from

with [e-mail]

GPIO. The pi
PXA255 GPIO19.

master request.

B49 MBREQ I

A49 DMA_ACK1 O

B50 MBGNT O

with this pin func
with [e-mail] first.

PXA255 GPIO14.

[e-mail] first.

PXA255 GPIO22.
Memory Controller grant.

wa
with [e-mail]

Pull low

with 1Kohm

No pulling

Pull low

with 1Kohm

A50 3M6864 O

¦100-pin B2B connector Pin Out Table (X3 connector for PCI, ZV port,

MMC interface and Misc. function)

Pin
No.

B1 PCIAD0 IO PCI address/data 0 No pulling
A1 PCIAD1 IO PCI address/data 1 No pulling

Signals Typ

GPIO. The pin connects to S
PXA255 GPIO13.

3.6864 MHz clock.

3.6864 MHz oscillator.

Model Default state

e

No pulling

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B2 PCIAD2 IO PCI address/data 2 No pulling
A2 PCIAD3 IO PCI address/data 3 No pulling
B3 PCIAD4 IO PCI address/data 4 No pulling
A3 PCIAD5 IO PCI address/data 5 No pulling
B4 PCIAD6 IO PCI address/data 6 No pulling
A4 PCIAD7 IO PCI address/data 7 No pulling
B5 nCBE0

PCI bus command and bytes

IO

enable signal

No pulling

A5 PCIAD8 IO PCI address/data 8 No pulling
B6 PCIAD9 IO PCI address/data 9 No pulling
A6 PCIAD10 IO PCI address/data 10 No pulling
B7 PCIAD11 IO PCI address/data 11 No pulling
A7 nPCIRST O PCI bus reset signal No pulling
B8 PCICLKO

A8 nCBE3

PCI bus clock output (Typical

IO

period: 31.2ns)
PCI bus command and bytes

IO

enable signal

No pulling
No pulling

B9 nINTD I PCI bus interrupt D No pulling
A9 nINTC I PCI bus interrupt C No pulling

B10
A10
B11
A11
B12
A12
B13
A13
B14
A14
B15
A15
B16
A16
B17
A17
B18
A18

B19
A19
B20
A20
B21
A21
B22
A22
B23
A23

GND P Ground -
nINTB I PCI bus interrupt B No pulling
nINTA I PCI bus interrupt A No pulling

nGNT3 O PCI bus grant signal No pulling
nREQ3 I PCI bus request signal No pulling
nGNT2 O PCI bus grant signal No pulling
nREQ2 I PCI bus request signal No pulling
nGNT1 O PCI bus grant signal No pulling
nREQ1 I PCI bus request signal No pulling

GND P Ground -
PCIAD31 IO PCI address/data 31 No pulling
PCIAD30 IO PCI address/data 30 No pulling
PCIAD12 IO PCI address/data 12 No pulling
PCIAD13 IO PCI address/data 13 No pulling
PCIAD14 IO PCI address/data 14 No pulling
PCIAD15 IO PCI address/data 15 No pulling

GND P Ground -

nCBE1

PCI bus command and bytes

IO

enable signal

No pulling

PAR IO PCI bus parity bit No pulling

GND P Ground -

nSERR IO PCI bus system error signal No pulling
nPERR IO PCI bus parity error signal No pulling
nSTOP IO PCI bus stop signal No pulling

nDEVSEL IO PCI bus device select signal No pulling

nTRDY IO PCI bus target ready signal No pulling

nIRDY IO PCI bus initiator ready signal No pulling

nFRAME IO PCI bus cycle frame signal No pulling

nCBE2 IO PCI bus command and bytes No pulling

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35

function, user could use this pin as

need MMC/SD function, user could

Chip select pin for MMC controller.

function, user could use this pin as

No pulling (For

B24
A24
B25
A25
B26
A26
B27
A27
B28
A28
B29
A29
B30
A30
B31
A31
B32
A32
B33
A33
B34
A34
B35

A35

B36

A36
B37

A37

B38

User’s Manual for Advantech SOM-A2558 series module V1.00

enable signal

PCIAD16 IO PCI address/data 16 No pulling
PCIAD17 IO PCI address/data 17 No pulling
PCIAD18 IO PCI address/data 18 No pulling
PCIAD19 IO PCI address/data 19 No pulling
PCIAD20 IO PCI address/data 20 No pulling
PCIAD21 IO PCI address/data 21 No pulling
PCIAD22 IO PCI address/data 22 No pulling
PCIAD23 IO PCI address/data 23 No pulling
PCIAD24 IO PCI address/data 24 No pulling
PCIAD25 IO PCI address/data 25 No pulling
PCIAD26 IO PCI address/data 26 No pulling
PCIAD27 IO PCI address/data 27 No pulling
PCIAD28 IO PCI address/data 28 No pulling
PCIAD29 IO PCI address/data 29 No pulling

N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -
N.C. - N.C. float this pin. -

SD/MMC interface card detect pin.
If user doesn’t need MMC/SD

Pull high with

100Kohm

nMMCD I

GPIO. The pin connects to SoC
PXA255 GPIO12.
MMC clock. Clock signal for the

No pulling

MMC Controller. If user doesn’t

MMCLK O

use this pin as GPIO. The pin
connects to SoC PXA255 GPIO6.

MMDAT3/

MMCCS0

If user doesn’t need MMC/SD

O

GPIO. The pin connects to SoC

SOM-255F is

MMCCS0)

PXA255 GPIO8.

MMCMD IO

MMDAT0 IO

Multimedia Card Command.
Multimedia Card Data pin.

Pull high with

10Kohm
Pull high with
10Kohm (For
SOM-255F is

MMCDAT)

No connection. Just float this pin. N.C. (For

N.C. -

SOM-255F is

Reserved)

N.C. -

No connection. Just float this pin. N.C. (For

SOM-255F is

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Reserved)

A38
B39
A39
B40
A40
B41
A41
B42
A42
B43
A43
B44
A44
B45
A45
B46
A46
B47
A47
B48
A48
B49
A49
B50
A50

N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -

GND P Ground -

N.C. - N.C. just float this pin. -
N.C. - N.C. just float this pin. -

2.2 function description

2.2.1 System Bus

System Bus includes PXA255 address bus, data bus, memory control
signals and GPIOs.
System Bus enters CSB by X1. In order to make sure that system bus
signals have perfect electrical waves, System Bus signals are driven by buffers
to enhance signals performance.

Data Bus

Strengthed Data Bus

PXA255

Address Bus

Memory Control
signals

Buffers

Buffers

Buffers

Strengthed Address Bus

Strengthed Memory Control
signals

X1 conn.

The buffers signals direction control is control by CPLD on SOM-A255x

module.

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2.2.2 COM

SOM-A255x series (SOM-A2552, SOM-A2558, SOM -A255F) all support 5
x RS-232 ports: 3 full function (FF) RS-232 ports, 1x 2-wire (RX, TX) RS-232
and 1x 3-wire (RX, TX, RTS) RS-232 port. COM port function assignments are
as following:

Ø COM1: FF RS-232
Ø COM2: FF RS-232
Ø COM3: FF RS-232
Ø COM4: 2-wire (RX, TX) RS-232
Ø COM5: 3-wire (RX, TX, RTS) RS-232

All RS-232 ports are TTL levels.

According to user target CSB demand, user could define COM5 as 3-wire
(RX, TX, RTS) RS-232 port or pass through RS-485 transceiver to act as
RS-485 function. User could references “Advantech SOM-A255x series CSB
design guide “to design the COM5.

2.2.3 USB 1.1 Host

SOM-A255F & SOM-A2558 series supports 2 USB host ports.
SOM-A2552 series supports 1 USB host port. The USB host ports on the
SOM-A255x are USB 1.1 compatible. The default Windows CE.NET and Linux
on board support USB keyboards, mice and mass storage devices. User could
check the " SOM-A255x series verified compatible peripherals list " to know the
verified compatible peripherals. If user wants to connect other devices, it may
take customization on the Windows CE.

2.2.4 USB 1.1 client
The USB client port on the SOM-A255x is USB 1.1 compatible. USB client

connector is used to communicate with master device (ex: PC) for ActiveSync.
About SOM-A255x series ActiveSync installation, please reference to

“Installation Guide-Advantech RISC platform with Microsoft ActiveSync 3.7”.

2.2.5 T/S

SOM-A255x series supports 4-wires (X+, X-, Y+, Y-) resistive T/S
interface.

2.2.6 PCMCIA/CF

All SOM-A255x series supports 2 PCMCIA interface (I/F) or 2 CF I/F or 1
PCMCIA & 1 CF I/F. User could check “ SOM-A255x Series Carrier Board
Design Guide “ to know how to design the I/F.
PCMCIA/CF I/F power control circuit is designed on SOM module, so
PCMCIA/CF I/F is hot-swappable.
Advantech strongly suggest user to design one CF or one PCMCIA

slot on user’s target carrier board, even user doesn’t need this port in
target product. Advantech platform always use CF or PCMCIA slot to be
system S/W upgrading port. If user doesn’t design 1 CF or PCMCIA slot
on carrier board, user will run into trouble when user wants to upgrade
image, boot loader & boot-logo.

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2.2.7 SD/MMC

All SOM-A255x series supports 1 slot SD/MMC port. The Multi Media
Card (MMC) is a low cost data storage and communication media. The MMC
controller in the SOM-A255x is compliant with The Multi Media Card System
Specification, Version 2.1. The only exception is one and three byte data
transfers are not supported.
SD/MMC I/F in SOM-A255x only support 1-bit memory mode, not support
I/O mode.

2.2.8 Audio (AC’97 Codec on board)

All SOM-A255x uses Realtek ALC202 AC97 audio Codec on SOM
module. SOM-A255x series provides mono microphone-in, stereo line-in, and
stereo line-out interface. If users want to drive speakers, users could follow the
“Advantech SOM-A255x series CSB design guide “to design the audio
amplifier on CSB.

2.2.9 CRT-out

SOM-A255F & SOM-A2552 series supplies CRT-out I/F which resolution
is up to 1024*768. CRT-out function comes from SM501. CRT-out signals are
all analog signals; user must follow the analog signals layout rules.
SOM-A2558 series doesn’t support CRT-out function, but user could
design CRT-out solution IC on CSB to add the function on SOM-A2558
platform. About detail implement way, please check “Advantech SOM-A255x
series CSB design guide “.

2.2.10 LCD TTL interface w/LCD Brightness & Contrast Control
interface

SOM-A2552 & SOM-A255F series LCD-out interface comes from SM501.
SOM-A2552 & SOM-A255F LCD-out supports 24 bit and resolution up to
1024*768. SOM-A2552 & SOM-A255F supports both active and passive LCD
displays. SOM-A2558 series LCD-out function comes from SoC PXA255.
SOM-A2558 LCD-out supports 16 bit and resolution up to 800*600.

The LCD signals are 3.3V level in X2. If users’ CSB want to drive 5V level
panel, users could design buffers on CSB to translate LCD signals level. User
could refer “Advantech SOM-A255x series CSB design guide “.
Advantech design LCD brightness control circuit & LCD contrast control
circuit on SOM-A255x series modules. STN LCD panel needs contrast control
signals. In X2, LCD contrast control signals are nVCONR_INC, VCONR_CS
and VCONR_UnD. The control signals are based on DALLAS DS1804 NV
Trimmer Potentiometer to design. Users could check the “Advantech
SOM-A255x series CSB design guide “ to know how to wire. User could check
“to know how to control.

Brightness control signals are used to control the LCD backlight inverter
lamp current. In X2, LCD brightness control signals are nVBRIR_INC,
VBRIR_CS and nVBRIR_UnD. The control signals are based on DALLAS
DS1804 NV Trimmer Potentiometer to design. Users could check the
“Advantech SOM-A255x series CSB design guide “to know how to wire. User
could check appendix about SOM-A255F memory map to know how to control.

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If user wants to connect CSB to LVDS type LCD, user could reference
“Advantech SOM-A255x series CSB design guide “to design LVDS
Transmitter on CSB. SOM-A255x series only support 1 channel LVDS LCD
panel.

The sample images of SOM-A2552, SOM-A255F series could support 4
kinds of display modes:

l 320x240 TFT: In SOM-A2552 & SOM-A255F module, user

CAN’T verify the performance by Advantech LCD kit
LCD-A057-STQ1-0. Because SOM-A2552 & SOM-A255F
supports 320x240 TFT mode, but LCD-A057-STQ1-0 is 320x240
STN panel.

l 640x480 TFT: user could verify the performance by Advantech

LCD kit LCD-A064-TTV1-0.

l 800x600 TFT: user could verify the performance by Advantech

LCD kit LCD-A104-TTS1-0.

l 1024x768 TFT: user could verify the performance by Advantech

LCD kit LCD-A150-TTX2-0.

Except 320x240 TFT mode, user could verify the LCD-out function by
Advantech LCD kit. Advantech LCD kit LCD-A057-STQ1-0 is 320x240 STN
type LCD, not TFT type, so user couldn’t verify the 320x240 TFT function by
sample images.

The sample images of SOM-A2558 series could support 4 kinds of display
modes:

l 320x240 STN: User can use Advantech LCD kit

LCD-A057-STQ1-0 to evaluate the LCD-out performance of
SOM-A2558 platform.

l 640x480 TFT: User can use Advantech LCD kit

LCD-A064-TTV1-0 to evaluate the LCD-out performance of
SOM-A2558 platform.

2.2.11 Zoom Video (ZV) port

SOM-A255F & SOM-A2552 series ZV port comes from SM501.
SOM-A2558 series don’t support the function. ZV Port can interface with video
decoders, such as NTSC/PAL decoders, MPEG-2 decoders, and JPEG Codec.
The ZV Port supports resolutions up to 1280x1024. It directly accepts digitized
RGB or YUV signals, and does not accept analog signals.

In 16-bit mode, the ZV [15:8] signals are the most-significant eight video
pixel inputs. In 8-bit mode, these signals are not used. In 16-bit mode, the ZV
[7:0] signals are the least-significant eight video pixel inputs. In 8-bit mode,
these signals are the only eight video pixel inputs.
About how to wire the ZV port with NTSC/PAL decoders, please check
“Advantech SOM-A255x series CSB design guide “.

2.2.12 System Reset Interface

SOM-A255x series all supply 3 kinds of System reset interface as
following:

Ø nRESET : hardware reset input pin. The pin is pulled high in

SOM-A255F. The pin is triggered by signal falling edge.

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Ø nSW_RESET : software rest input pin. The pin is pulled high in

SOM-A255F. The pin is triggered by signal falling edge.

Ø nSA_PWR_ON : Suspend/wake-up pin. The pin is pulled high in

SOM-A255F. The pin is triggered by signal falling edge.

2.2.13 Buzzer Control Interface

SOM-A255x series all support this function. Buzzer-out control signal is
designed to control the buzzer on/off status.

If users want to design buzzer on CSB to be reminding or alarm system,
user could reference “Advantech SOM-A255x series CSB design guide “.

If users want to control the buzzer, users can check the memory map to
do it.

2.2.14 System Management Bus (SM Bus) interface

SOM-A255x series SM Bus is implemented by PXA255 I2C bus. If users’ CSB is
powered by battery pack with SM bus battery gauge IC, then users could connect the
SOM-A255x SM Bus to battery pack to monitor battery status. SOM-A255x series SM
bus directly support TI BQ2040 gas gauge IC.

2.2.15 Power-input

SOM-A255x needs 3.3V & 5V DC power inputs. The power sources (3.3V,
5V) must always be supplied even in system sleep mode. SOM-A255x power
management is completely implemented on itself; users’ CSB doesn’t need to
control the power supply to SOM-A255x.

2.2.16 Back-up power input

If user want to keep the real time clock(RTC) works well in power off mode,
user should connect the coin battery positive pin to BAT-VCC in X2
directly .The back-up power pin (BAT_VCC) is the only power source to supply
RTC power when SOM-A255x system power (3.3V, 5V) is off.
The coin battery must be 3.0V Li-ion coin type.
The coin battery charging circuit is designed on SOM-A255x, so user
shouldn’t and needn’t design the charging circuit on CSB.
If users don’t need RTC function in CSB, just let the BAT_VCC pin open.

2.2.17 PCI I/F (Thru X3)
SOM-A2558 & SOM-A255F could support 4 channels PCI device

controllers on CSB. The PCI clock is 33 MHz. PCI I/F comes from Advantech
EVA-C210 I/O enhancement chip. The PCI I/F feature is as followings:

- Compatible with PCI specification version 2.2

- 32-bit data bus interface

- Built-in PCI bus arbiter

- Supports up to 3 individual external bus master devices

- Support PCI Bus Controller (FPCI) to PCI slave I/O read/write,

memory read/write, configuration read/write cycle

- PCI Bus master support all disconnect types (Master-Abort,
Target-Abort, Target-Retry, Disconnect with data, Disconnect without

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data)

SOM-A2552 series don’t support PCI I/F.

User’s Manual for Advantech SOM-A2558 series module V1.00