ADLINK nanoX-BT User Manual

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nanoX-BT

User’s Manual

Manual Revision: 1.01

Revision Date: September 24, 2014

Part Number: 50-1J053-1010

Revision History

Revision Description Date By

1.00 Initial release 2014-07-24 JC

1.01 Add BIOS Checkpoints, Beep Codes; correct SD signal support; add SEMA CPU temperature limitation

2014-09-24 JC

Page 2 nanoX-BT

Preface

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

nanoX-BT Page 3

Revision History ............................................................................................................ 2

Preface............................................................................................................................ 3

1. Introduction......................................................................................................... 8

2. Specifications....................................................................................................... 9

2.1. Core System..............................................................................................................................9

2.2. Expansion Busses......................................................................................................................9

2.3. SEMA Board Controller.............................................................................................................9

2.4. Debug Headers .........................................................................................................................9

2.5. Video...................................................................................................................................... 10

2.6. Audio...................................................................................................................................... 10

2.7. LAN ........................................................................................................................................ 10

2.8. Multi I/O and Storage ............................................................................................................ 10

2.9. Power Specifications ............................................................................................................. 10

2.10. Power Consumption.............................................................................................................. 11

2.11. Operating Temperatures ....................................................................................................... 11

2.12. Environmental ....................................................................................................................... 11

2.13. Specification Compliance ...................................................................................................... 11

2.14. Operating Systems................................................................................................................. 11

2.15. Functional Diagram................................................................................................................ 12

2.16. Mechanical Dimensions......................................................................................................... 13

3. Pinouts and Signal Descriptions......................................................................

3.1. AB Pin Definitions .................................................................................................................. 14

3.2. Signal Description Terminology............................................................................................. 17

3.3. AB Signal Description............................................................................................................. 18

3.3.1. Audio Signals ...............................................................................................................................18

3.3.2. LVDS/eDP ....................................................................................................................................18

3.3.3. DDI0 Channel...............................................................................................................................19

3.3.4. Gigabit Ethernet ..........................................................................................................................19

3.3.5. SATA ............................................................................................................................................20

3.3.6. PCI Express ..................................................................................................................................20

3.3.7. Express Card................................................................................................................................20

3.3.8. LPC Bus ........................................................................................................................................21

3.3.9. USB 1.1/2.0..................................................................................................................................21

3.3.10. USB 3.0 Extension .......................................................................................................................22

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3.3.11. USB Root Segmentation ..............................................................................................................22

3.3.12.

3.3.13. Miscellaneous..............................................................................................................................23

3.3.14. SMBus..........................................................................................................................................23

3.3.15. I2C Bus.........................................................................................................................................23

3.3.16. General Purpose I/O (GPIO) ........................................................................................................23

3.3.17. Serial Interface Signals ................................................................................................................24

3.3.18. Power And System Management................................................................................................24

3.3.19.

4. Module interfaces .............................................................................................

SPI (BIOS only)

Power and Ground

.............................................................................................................................22

......................................................................................................................25

4.1. Connector, Switch and LED Locations ................................................................................... 26

4.1.1. nanoX-BT and the DB40 Module connected...............................................................................26

4.2. 40-pin Multipurpose Connector ............................................................................................ 27

4.3. Status LEDs ............................................................................................................................ 28

4.4. XDP Debug Header ................................................................................................................ 29

5. Smart Embedded Management Agent (SEMA) ............................................. 30

5.1. Board Specific SEMA Functions ............................................................................................. 31

5.1.1. Voltages.......................................................................................................................................31

5.1.2. Main Current...............................................................................................................................31

5.1.3. BMC Status..................................................................................................................................31

5.1.4. Exception Codes ..........................................................................................................................32

5.1.5. BMC Flags....................................................................................................................................32

6. System Resources..............................................................................................

6.1. System Memory Map ............................................................................................................ 33

6.2. I/O Map.................................................................................................................................. 33

6.3. Interrupt Request (IRQ) Lines................................................................................................ 34

6.3.1. PIC Mode.....................................................................................................................................34

6.3.2. APIC Mode...................................................................................................................................34

6.4. PCI Configuration Space Map ................................................................................................ 36

6.5. PCI Interrupt Routing Map .................................................................................................... 37

6.6. SMBus Address Table ............................................................................................................ 37

7. BIOS Setup .........................................................................................................

7.1. Menu Structure ..................................................................................................................... 38

7.2. Main....................................................................................................................................... 39

7.2.1. System Information.....................................................................................................................39

7.2.2. Processor Information.................................................................................................................39

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7.2.3. VGA Firmware Version ................................................................................................................39

7.2.4. Memory Information...................................................................................................................39

7.2.5. SOC Information..........................................................................................................................39

7.2.6. System Management ..................................................................................................................40

7.2.7. System Date and Time.................................................................................................................42

7.3. Advanced ............................................................................................................................... 43

7.3.1. CPU..............................................................................................................................................43

7.3.2. Memory.......................................................................................................................................44

7.3.3. Graphics ......................................................................................................................................44

7.3.4. SATA ............................................................................................................................................45

7.3.5. USB ..............................................................................................................................................45

7.3.6. Network.......................................................................................................................................46

7.3.7. PCI and PCIe ................................................................................................................................46

7.3.8. Super IO.......................................................................................................................................48

7.3.9. ACPI and Power Management ....................................................................................................49

7.3.10. Sound ..........................................................................................................................................49

7.3.11. Serial Port Console ......................................................................................................................50

7.3.12. Thermal .......................................................................................................................................51

7.3.13. Miscellaneous..............................................................................................................................51

7.4. Boot ....................................................................................................................................... 52

7.4.1. Boot Configuration......................................................................................................................52

7.5. Security.................................................................................................................................. 54

7.5.1. Password Description..................................................................................................................54

7.6. Save & Exit ............................................................................................................................. 54

8. BIOS Checkpoints, Beep Codes........................................................................

8.1. Checkpoint Ranges ................................................................................................................ 56

8.2. Standard Checkpoints............................................................................................................ 56

8.2.1. SEC Phase ....................................................................................................................................56

8.2.2. SEC Beep Codes...........................................................................................................................57

8.2.3. PEI Phase .....................................................................................................................................57

8.2.4. PEI Beep Codes............................................................................................................................59

8.2.5. DXE Phase....................................................................................................................................59

8.2.6. DXE Beep Codes ..........................................................................................................................62

8.2.7. ACPI/ASL Checkpoint...................................................................................................................62

8.3. OEM-Reserved Checkpoint Ranges ....................................................................................... 63

9. Mechanical Information ................................................................................... 64

9.1. Board-to-Board Connectors .................................................................................................. 64

9.2. Thermal Solution ................................................................................................................... 65

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9.2.1. Heat Spreaders............................................................................................................................65

9.2.2. Heat Sinks....................................................................................................................................65

9.2.3. Installation...................................................................................................................................65

9.3. Mounting Methods................................................................................................................ 67

9.4. Standoff Types....................................................................................................................... 68

Safety Instructions ...................................................................................................... 69

Getting Service ............................................................................................................ 70

nanoX-BT Page 7

1. Introduction

The nanoX-BT is a COM Express® COM.0 R2.1 Type 10 module supporting Intel® Atom™ processor E3800 Series and Intel® Celeron® processor system-on-chip (SoC). The nanoX-BT is specifically designed for customers who need high-level processing and graphics performance with low power consumption in a long product life solution.

The nanoX-BT features Intel® Atom™ processor E3800 and Intel® Celeron® processor supporting non-ECC type DDR3L single-channel memory at 1066/1333 MHz to provide excellent overall performance. Integrated Intel® Gen7 HD Graphics includes features such as OpenGL 3.1, DirectX 11, OpenCL 1.1 and support for H.264, MPEG2, VC1, VP8 hardware decode. Graphics outputs include DDI ports supporting HDMI/DVI/DisplayPort and single-channel 18/24-bit LVDS (eDP is optional). The nanoX-BT is specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of their systems for reduced development time.

The nanoX-BT has soldered type non-ECC DDR3L memory up to 2 GB (4GB TBD). In addition, onboard eMMC memory (8GB/16GB/32GB) and SD signals are optionally supported.

The nanoX-BT features a single onboard Gigabit Ethernet port, USB 3.0 ports and USB 2.0 ports, and SATA 3 Gb/s ports. Support is provided for SMBus and I CMOS backup, hardware monitor, and watchdog timer.

C. The module is equipped with SPI AMI EFI BIOS, supporting embedded features such as remote console,

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2. Specifications

2.1. Core System

¾ CPU: Single, dual or quad-core Intel® Atom™ or Celeron® Processor

• Atom™ E3845 1.91 GHz 542/792 (Turbo) 10W (4C/1333)

• Atom™ E3827 1.75 GHz 542/792 (Turbo) 8W (2C/1333)

• Atom™ E3826 1.46 GHz 533/667 (Turbo) 7W (2C/1066)

• Atom™ E3825 1.33 GHz 533 (No Turbo) 6W (2C/1066)

• Atom™ E3815 1.46 GHz 400 (No Turbo) 5W (1C/1066)

• Celeron® N2930 1.83/2.16 (Burst) GHz, 313/854 (Turbo) 7.5W (4C/1333)

• Celeron® J1900 2.0/2.42 (Burst) GHz, 688/854 (Turbo) 10W (4C/1333)

Supports: Single, dual or quad Out-of-Order Execution (OOE) processor cores, Intel® VT-x, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture, IA 32-bit, PCLMULQDQ Instruction, DRNG, Intel® Thermal Monitor (TM1 & TM2)

Note: Availability of features may vary between processor SKUs.

¾ Cache: Primary 32 kB, 8-way L1 instruction cache and 24 kB, 6-way L1 write-back data cache

¾ Memory: Single channel non-ECC 1333/1066 MHz soldered DDR3L memory up to 2GB (4GB TBD)

Note: Availability of features may vary between processor SKUs.

¾ Embedded BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS

2.2. Expansion Busses

¾ 3 PCI Express x1 GEN2 (AB): lanes 0/1/2 (build option: PCIe x4, lose GbE) ¾ LPC bus, SMBus (system) , I

C (user)

2.3. SEMA Board Controller

¾ Type: ADLINK Smart Embedded Management Agent (SEMA) ¾ Supports:

• Voltage/Current monitoring

• Power sequence debug support

• AT/ATX mode control

• Logistics and Forensic information

• Flat Panel Control

• General Purpose I

• Failsafe BIOS (dual BIOS )

• Watchdog Timer and Fan Control

2.4. Debug Headers

¾ 40-pin multipurpose flat cable connector, used in combination with DB-40 debug module providing BIOS POST code LED, BMC

access, SPI BIOS flashing, Power Testpoints, Debug LEDs

¾ Optional 60-pin XDP header for ICE debug of SOC on breakount PCB extension

nanoX-BT Page 9

2.5. Video

¾ GPU Feature Support: 7th generation graphics Intel core architecture with four execution units supporting two independent displays

• 3D graphics hardware acceleration

• Support for DirectX11, OCL 1.1, OGL ES Halt/2.0/1.1, OGL 3.2

• Video decode hardware acceleration including support for H.264, MPEG2, VC-1, WMV and VP8 formats

• Video encode hardware acceleration including support for H.264, MPEG2 and MVC formatsPlayback of Blu-ray disc S3D content using HDMI

(1.4a spec compliant with 3D)

Note: Availability of features may vary between operating systems

¾ Display Interface support

• LVDS

Single channel 18/24-bit LVDS from eDP (one lane)

Build option upon request to support eDP output

• DDI0

Supports DisplayPort / HDMI / DVI / eDP

2.6. Audio

¾ Integrated: Intel® HD Audio integrated in SOC ¾ Audio Codec: located on evaluation carrier miniBase-10R (ALC262 standard supported)

2.7. LAN

¾ Type: Intel® i210 (MAC/PHY) Ethernet controller ¾ Interface: 10/100/1000 GbE connection

2.8. Multi I/O and Storage

¾ Integrated in SOC ¾ USB:

• 1x USB. 1.1/2.0/3.0 (USB 0)

• 3x USB. 1.1/2.0 (USB 1,2,3)

• 1x USB. 1.1/2.0 Client (USB 7)

¾ SATA: 2x ports SATA 3Gb/s (SATA0, SATA1) ¾ eMMC: optional soldered on module bootable eMMC flash storage (8GB/16GB/32GB) ¾ Serial: 2x UART ports COM 0/1 (COM 1 supports console redirection) ¾ SD: optional SD signal support mulitplexed over GPIO pins ¾ GPIO: 4x GPO and 4x GPI with interrupt

2.9. Power Specifications

¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA) ¾ Standard Voltage Input: ATX = 12V±5%, 5Vsb ±5% or AT = 12V ±5% ¾ Wide Voltage Input: ATX = 5~14 V, 5Vsb ±5% or AT = 5 ~14V ¾ Power Management: ACPI 4.0 compliant, Smart Battery support ¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5) ¾ ECO mode: supports deep S5 for 5Vsb power saving

Page 10 nanoX-BT

2.10. Power Consumption

TBD

2.11. Operating Temperatures

¾ Standard Operating Temperature: 0°C to 60°C (wide voltage input) ¾ Extreme Rugged Operating Temperature (optional)*: -40°C to 85°C (standard voltage input)

*Intel® Atom™ E3800 Series processors only

2.12. Environmental

¾ Humidity: 5-90% RH operating, non-condensing

5-95% RH storage (and operating with conformal coating).

¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

¾ Halt: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

2.13. Specification Compliance

¾ PICMG COM.0: Rev 2.1 Type 10, mini size 84 x 55

2.14. Operating Systems

¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit ¾ Extended Support (BSP): WES7/8, WEC7, Linux, VxWorks

nanoX-BT Page 11

2.15. Functional Diagram

eDP (optional)

LVDS

eDP to LVDS

RTL2132

DDI2

4 lanes

1x USB 1.1/2.0/3.0 (port 0)

3x USB 1.1/2.0 (port 1~3)

1x USB 1.1/2.0 client (port 7)

3 PCIe x1 Gen2

(port 0~2)

GbE

i210

2x SATA 3Gb/s

(port 0/1)

HD Audio

DDI1

eDP 1 lane

alternative

PCIe x1 Gen2

(port 3)

PCIe x1

route

Intel® Atom™

E3845 E3827 E3826 E3825 E3815

Intel® Celeron®

N2930

J1900

“Baytrail”

Soldered

1~2 GB DDR3L non ECC (only)

On break-out board

XDP

60-pin

eMMC

8GB/16GB/

32GB

2 UART (Tx/Rx)

LPC Bus

SD/MMC port 0 (optional)

4x GP0, 4x GPI

SMBus

GP I2C

DDC I2C

GPIO

PCA9535

SPI_CS#

SPI

SEMA

BMC

SPI0

BIOS

LM73

to CPU

Page 12 nanoX-BT

2.16. Mechanical Dimensions

connector on bottom side

op View

Side View

All tolerances ± 0.05 mm

Other tolerances ± 0.2 mm

nanoX-BT Page 13

3. Pinouts and Signal Descriptions

3.1. AB Pin Definitions

The nanoX-BT is a Type 10 module supporting USB3.0 and DDI channel on the AB connector

In below table all standard pins of the COM Express specification are described, also those not supported on the nanoX-BT !

Note: Signals not supported on the nanoX-BT module are crossed out

Type 10 COM.0 Rev. 2.1

Row A Row B

Pin Name Pin Name

1 GND(FIXED) 1 GND(FIXED)

2 GBE0_MDI3- 2 GBE0_ACT#

3 GBE0_MDI3+ 3 LPC_FRAME#

4 GBE0_LINK100# 4 LPC_AD0

5 GBE0_LINK1000# 5 LPC_AD1

6 GBE0_MDI2- 6 LPC_AD2

7 GBE0_MDI2+ 7 LPC_AD3

8 GBE0_LINK# 8 LPC_DRQ0#

9 GBE0_MDI1- 9 LPC_DRQ1#

10 GBE0_MDI1+ 10 LPC_CLK

11 GND(FIXED) 11 GND(FIXED)

12 GBE0_MDI0- 12 PWRBTN#

13 GBE0_MDI0+ 13 SMB_CK

14 GBE0_CTREF 14 SMB_DAT

15 SUS_S3# 15 SMB_ALERT#

16 SATA0_TX+ 16 SATA1_TX+

17 SATA0_TX- 17 SATA1_TX-

18 SUS_S4# 18 SUS_STAT#

19 SATA0_RX+ 19 SATA1_RX+

20 SATA0_RX- 20 SATA1_RX-

21 GND(FIXED) 21 GND(FIXED)

22 USB_SSRX0- 22 USB_SSTX0-

23 USB_SSRX0+ 23 USB_SSTX0+

24 SUS_S5# 24 PWR_OK

25 USB_SSRX1- 25 USB_SSTX1-

26 USB_SSRX1+ 26 USB_SSTX1+

27 BATLOW# 27 WDT

28 (S)ATA_ACT# 28 AC/HDA_SDIN2

29 AC/HDA_SYNC 29 AC/HDA_SDIN1

30 AC/HDA_RST# 30 AC/HDA_SDIN0

31 GND(FIXED) 31 GND(FIXED)

32 AC/HDA_BITCLK 32 SPKR

33 AC/HDA_SDOUT 33 I2C_CK

34 BIOS_DIS0# 34 I2C_DAT

Page 14 nanoX-BT

Row A Row B

Pin Name Pin Name

35 THRMTRIP# 35 THRM#

36 USB6- 36 USB7-

37 USB6+ 37 USB7+

38 USB_6_7_OC# 38 USB_4_5_OC#

39 USB4- 39 USB5-

40 USB4+ 40 USB5+

41 GND(FIXED) 41 GND(FIXED)

42 USB2- 42 USB3-

43 USB2+ 43 USB3+

44 USB_2_3_OC# 44 USB_0_1_OC#

45 USB0- 45 USB1-

46 USB0+ 46 USB1+

47 VCC_RTC 47 EXCD1_PERST#

48 EXCD0_PERST# 48 EXCD1_CPPE#

49 EXCD0_CPPE# 49 SYS_RESET#

50 LPC_SERIRQ 50 CB_RESET#

51 GND(FIXED) 51 GND(FIXED)

52 RSVD 52 RSVD

53 RSVD 53 RSVD

54 GPI0 54 GPO1

55 RSVD 55 RSVD

56 RSVD 56 RSVD

57 GND 57 GPO2

58 PCIE_TX3+ * 58 PCIE_RX3+ *

59 PCIE_TX3- * 59 PCIE_RX3- *

60 GND(FIXED) 60 GND(FIXED)

61 PCIE_TX2+ 61 PCIE_RX2+

62 PCIE_TX2- 62 PCIE_RX2-

63 GPI1 63 GPO3

64 PCIE_TX1+ 64 PCIE_RX1+

65 PCIE_TX1- 65 PCIE_RX1-

66 GND 66 WAKE0#

67 GPI2 67 WAKE1#

68 PCIE_TX0+ 68 PCIE_RX0+

69 PCIE_TX0- 69 PCIE_RX0-

70 GND(FIXED) 70 GND(FIXED)

71 LVDS_A0+ / eDP_TX2+ 71 DDI0_PAIR0+

72 LVDS_A0- / eDP_TX2- 72 DDI0_PAIR0-

73 LVDS_A1+ / eDP_TX1+ 73 DDI0_PAIR1+

74 LVDS_A1- / eDP_TX1- 74 DDI0_PAIR1-

75 LVDS_A2+ / eDP_TX0+ 75 DDI0_PAIR2+

76 LVDS_A2- / eDP_TX0- 76 DDI0_PAIR2-

77 LVDS_/eDP_VDD_EN 77 DDI0_PAIR4+

78 LVDS_A3+ 78 DDI0_PAIR4-

79 LVDS_A3- 79 LVDS_/eDP_BKLT_EN

nanoX-BT Page 15

Row A Row B

Pin Name Pin Name

80 GND(FIXED) 80 GND(FIXED)

81 LVDS_A_CK+ / eDP_TX3+ 81 DDI0_PAIR3+

82 LVDS_A_CK- / eDP_TX3- 82 DDI0_PAIR3-

83 LVDS_I2C_CK / eDP_AUX+ 83 LVDS_/eDP_BKLT_CTRL

84 LVDS_I2C_DAT / eDP_AUX- 84 VCC_5V_SBY

85 GPI3 85 VCC_5V_SBY

86 RSVD 86 VCC_5V_SBY

87 eDP_HPD 87 VCC_5V_SBY

88 PCIE_CLK_REF+ 88 BIOS_DIS1#

89 PCIE_CLK_REF- 89 DD0_HPD

90 GND(FIXED) 90 GND(FIXED)

91 SPI_POWER 91 DDI0_PAIR5+

92 SPI_MISO 92 DDI0_PAIR5-

93 GPO0 93 DDI0_PAIR6+

94 SPI_CLK 94 DDI0_PAIR6-

95 SPI_MOSI 95 DDI0_DDC_AUX_SEL

96 TPM_PP 96 USB_HOST_PRSNT

97 TYPE10# 97 SPI_CS#

98 SER0_TX 98 DDI0_CTRLCLK_AUX+

99 SER0_RX 99 DDI0_CTRLDATA_AUX-

100 GND(FIXED) 100 GND(FIXED)

101 SER1_TX / CAN_TX 101 FAN_PWMOUT

102 SER1_RX / CAN_RX 102 FAN_TACHIN

103 LID# 103 SLEEP#

104 VCC_12V 104 VCC_12V

105 VCC_12V 105 VCC_12V

106 VCC_12V 106 VCC_12V

107 VCC_12V 107 VCC_12V

108 VCC_12V 108 VCC_12V

109 VCC_12V 109 VCC_12V

110 GND(FIXED) 110 GND(FIXED)

Notes:

- LID# and SLEEP# signals are not natively supported on the SOC, they instead connect to GPIO pins simulating their behaviour.

- eDP can be supported by BOM option with loss of LVDS.

- PCIe (port 3) can be supported by BOM option (lose GbE)

Page 16 nanoX-BT

3.2. Signal Description Terminology

The following terms are used in the COM Express AB/CD Signal Descriptions below.

I Input to the Module

O Output from the Module

I/O Bi-directional input / output signal

OD Open drain output

I 3.3V Input 3.3V tolerant

I 5V Input 5V tolerant

O 3.3V Output 3.3V signal level

O 5V Output 5V signal level

I/O 3.3V Bi-directional signal 3.3V tolerant

I/O 5V Bi-directional signal 5V tolerant

I/O 3.3Vsb Input 3.3V tolerant active in standby state

P Power Input/Output

REF Reference voltage output that may be sourced from a module power plane.

PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.

The signal is used to indicate the PICMG module type to the Carrier Board.

PU ADLINK implemented pull-up resistor on module

PD ADLINK implemented pull-down resistor on module

nanoX-BT Page 17

3.3. AB Signal Description

3.3.1. Audio Signals

Signal Pin # Description I/O PU/PD Comment

AC_RST# / HDA_RST#

AC_SYNC / HDA_SYNC

AC_BITCLK / HDA_BITCLK

AC _SDOUT / HDA_SDOUT

AC _SDIN[2:0] HDA_SDIN[2:0]

A30 Reset output to CODEC, active low. O 3.3VSB

A29 Sample-synchronization signal to the CODEC(s). O 3.3V

A32 Serial data clock generated by the external CODEC(s). I/O 3.3V

A33 Serial TDM data output to the CODEC. O 3.3V

B28- B30 Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB AC_SDIN0: supported

AC_SDIN1: supported AC_SDIN2: not supported

3.3.2. LVDS/eDP

Signal Pin # Description I/O PU/PD Comment

LVDS_A0+ / eDP_TX2+ LVDS_A0- / eDP_TX2-

LVDS_A1+ / eDP_TX1+ LVDS_A1- / eDP_TX1-

LVDS_A2+ / eDP_TX0+ LVDS_A2- / eDP_TX0+

LVDS_A3+ LVDS_A3-

A71 A72

A73 A74

A75 A76

A78 A79

LVDS Channel A differential pairs

O LVDS

eDP by build option

LVDS_A_CK+ / eDP_TX3+ LVDS_A_CK- / eDP_TX3-

LVDS_VDD_EN / eDP_VDD_EN A77 LVDS panel power enable O 3.3V

LVDS_BKLT_EN / eDP_BKLT_EN B79 LVDS panel backlight enable O 3.3V

LVDS_BKLT_CTRL / eDP_BKLT_CTRL B83 LVDS panel backlight brightness

LVDS_I2C_CK / eDP_AUX+ A83 DDC lines used for flat panel

LVDS_I2C_DAT / eDP_AUX- A84 DDC lines used for flat panel

RSVD / eDP_HPD A87 Digital Display Interface Hot-Plug

A81 A82

LVDS Channel A differential clock

control

detection and control.

Detect

O LVDS

O 3.3V PD 100k Realtek eDP to

O 3.3V PU 2k2

I/O 3.3V PU 2k2

I 3.3V

LVDS requirement

3.3V

Page 18 nanoX-BT

3.3.3. DDI0 Channel

Signal Pin # Description I/O PU/PD Comment

DDI0_PAIR0+ DDI0_PAIR0DDI0_PAIR1+ DDI0_PAIR1DDI0_PAIR2+ DDI0_PAIR2DDI0_PAIR3+ DDI0_PAIR3DDI0_PAIR4+ DDI0_PAIR4DDI0_PAIR5+ DDI0_PAIR5DDI0_PAIR6+ DDI0_PAIR6-

DDI0_HPD B89 Digital Display Interface Hot-Plug Detect I 3.3V PD

DDI0_DDC_AUX_SEL B95 Selects the function of DDI1_CTRLCLK_AUX+ and

B71

Digital Display Interface differential pairs O PCIE Pair 4 to Pair 6 B72 B73 B74 B75 B76 B81 B82 B77 B78 B91 B92 B93 B94

IF DDI0_DDC_AUX_SEL is floating I/O PCIe DP AUX+ DDI0_CTRLCLK_AUX+ B98

IF DDI0_DDC_AUX_SEL pulled high I/O OD 3.3V HMDI0_CTRLC

IF DDI0_DDC_AUX_SEL is floating I/O PCIe DP AUX+ DDI0_CTRLCLK_AUX- B99

IF DDI0_DDC_AUX_SEL pulled high I/O OD 3.3V HMDI0_

I/O OD 3.3V PD 1M DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

are not supported

100k

CTRLDAT

3.3.4. Gigabit Ethernet

Gigabit Ethernet Pin # Description I/O PU/PD Comment

GBE0_MDI0+ GBE0_MDI0GBE0_MDI1+ GBE0_MDI1GBE0_MDI2+ GBE0_MDI2GBE0_MDI3+ GBE0_MDI3-

GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. OD

GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. OD

GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. OD

GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. OD

GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics

A13

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0,

A11

1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some

A10

pairs are unused in some modes according to the following:

1000 100 10

MDI[0]+/- B1_DA+/- TX+/- TX+/-

MDI[1]+/- B1_DB+/- RX+/- RX+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.

I/O Analog

3.3VSB

GND min

3.3V max

Twisted pair

signals for external transformer.

PD 10k

3.3VSB

nanoX-BT Page 19

3.3.5. SATA

Signal Pin # Description I/O PU/PD Comment

SATA0_TX+ SATA0_TX-

SATA0_RX+ SATA0_RX-

SATA1_TX+ SATA1_TX-

SATA1_RX+ SATA1_RX-

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V

A16 A17

A19 A20

B16 B17

B19 B20

Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module

Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module

Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module

Serial ATA channel 1, Receive Input differential pair. I SATA AC coupled on Module

3.3.6. PCI Express

Signal Pin # Description I/O PU/PD Comment

PCIE_TX0+ PCIE_TX0- A68

A69

PCIE_RX0+ PCIE_RX0- B68

B69

PCIE_TX1+ PCIE_TX1- A64

A65

PCI Express channel 0, Transmit Output differential pair.

PCI Express channel 0, Receive Input differential pair.

PCI Express channel 1, Transmit Output differential pair.

O PCIE AC coupled on module

I PCIE AC coupled off module

O PCIE AC coupled on module

PCIE_RX1+ PCIE_RX1- B64

B65

PCIE_TX2+ PCIE_TX2- A61

A62

PCIE_RX2+ PCIE_RX2- B61

B62

PCIE_TX3+ PCIE_TX3- A58

A59

PCIE_RX3+ PCIE_RX3- B58

B59

PCIE_CLK_REF+ PCIE_CLK_REF- A88

A89

PCI Express channel 1, Receive Input differential pair.

PCI Express channel 2, Transmit Output differential pair.

PCI Express channel 2, Receive Input differential pair.

PCI Express channel 3, Transmit Output differential pair.

PCI Express channel 3, Receive Input differential pair.

PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.

I PCIE AC coupled off module

O PCIE AC coupled on module

I PCIE AC coupled off module

O PCIE used by GbE

I PCIE used by GbE

O PCIE

3.3.7. Express Card

Signal Pin # Description I/O PU/PD Comment

EXCD0_CPPE# EXCD1_CPPE# A49

B48

EXCD0_PERST# EXCD1_PERST# A48

B47

PCI ExpressCard: PCI Express capable card request

PCI ExpressCard: reset O 3.3V

I 3.3V PU 10k 3.3V

Page 20 nanoX-BT

3.3.8. LPC Bus

Signal Pin # Description I/O PU/PD Comment

LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data

bus

LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V

LPC_DRQ0# LPC_DRQ1#

LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V

LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V

B8 B9

LPC serial DMA request I 3.3V

I/O 3.3V

Atom clock 33 MHz Celeron clock 25 MHz

3.3.9. USB 1.1/2.0

Signal Pin # Description I/O PU/PD Comment

USB0+ USB0-

USB1+ USB1-

USB2+ USB2-

USB3+ USB3-

A46 A45

B46 B45

A43 A42

B43 B42

USB differential data pairs for Port 0 I/O

3.3VSB

USB differential data pairs for Port 1 I/O

3.3VSB

USB differential data pairs for Port 2 I/O

3.3VSB

USB differential data pairs for Port 3 I/O

3.3VSB

USB 1.1/ 2.0

compliant

USB 1.1/ 2.0

compliant

USB 1.1/ 2.0

compliant

USB 1.1/ 2.0

compliant

USB4+ USB4-

USB5+ USB5-

USB6+ USB6-

USB7+ USB7-

USB_HOST_PRSNT B96 Module USB client may detect the presence of a USB host. A high value

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be

A40 A39

B40 B39

A37 A36

B37 B37

USB differential data pairs for Port 4 I/O

USB differential data pairs for Port 5 I/O

USB differential data pairs for Port 6 I/O

USB differential data pairs for Port 7 I/O

indicates that a host is present.

present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .

present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

3.3VSB

Not supported

Client only

PU 10k

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

Not supported

Do not pull high on carrier

nanoX-BT Page 21

3.3.10. USB 3.0 Extension

Signal Pin Description I/O PU/PD Comment

USB_SSRX0USB_SSRX0+

USB_SSTX0USB_SSTX0+

USB_SSRX1USB_SSRX1+

USB_SSTX1USB_SSTX1+

A22

Additional Receive signal differential pairs for the SuperSpeed

A23

USB data path on USB0

B22

Additional Transmit signal differential pairs for the SuperSpeed

B23

USB data path on USB0

A25

Additional Receive signal differential pairs for the SuperSpeed

A26

USB data path on USB1

B25

Additional Transmit signal differential pairs for the SuperSpeed

B26

USB data path on USB1

3.3.11. USB Root Segmentation

P1 P2 P3 P4

Port 0

(1/2.0)

EHCI Controller

Port 1

(1/2.0)

Port 2

(1/2.0)

Port 3 (1/2.0)

P1-P4

XHCI Controller

I PCIE

O PCIE AC coupled on Module

I PCIE Not supported

O PCIE Not supported

SSP

ULPI

Port 7 Client

Port 0

(3.0)

USB0- / A45

USB0+ / A46

3.3.12.

USB1- / B45

USB1+ / B46

USB2- / A42

USB2+ / A43

SPI (BIOS only)

USB3- / B42

USB3+ / B43

USB7- / B36

USB7+ / B37

USB_SSTX0-/B22

USB_SSRX0-/A22

USB_SSTX0+/B23

USB_SSRX0+/A23

Signal Pin # Description I/O PU/PD Comment

SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Only supports CS0

SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB

SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB

SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB

SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally

O P 3.3VSB

3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier

BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K

3.3V

Carrier shall pull to GND or leave not connected

BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K

3.3V

Carrier shall pull to GND or leave not connected

Page 22 nanoX-BT

3.3.13. Miscellaneous

Signal Pin # Description I/O PU/PD Comment

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V

WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V

THRM# B35 Input from off-module temp sensor indicating an over-temp situation. I 3.3V

THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V

FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to

control the fan’s RPM.

FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V

TPM_PP11 A96 Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM

chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.

O OD 3.3V

I 3.3V No TPM

supported

3.3.14. SMBus

Signal Pin # Description I/O PU/PD Comment

SMB_CK B13 System Management Bus bidirectional clock line. Power sourced through 5V standby

rail and main power rails.

SMB_DAT# B14 System Management Bus bidirectional data line. Power sourced through 5V standby

rail and main power rails.

SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI#

(System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.

I/O OD

3.3VSB

I/O OD

3.3VSB

I 3.3VSB PU 10k

PU 2k2

3.3VSB

PU 2k2

3.3VSB

3.3.15. I2C Bus

Signal Pin # Description I/O PU/PD Comment

I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB Source SEMA BMC or BayTrail SOC as

alternative

I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB Source SEMA BMC or BayTrail SOC as

alternative

3.3.16. General Purpose I/O (GPIO)

Signal Pin # Description I/O PU/PD Comment

GPO[0] A93 General purpose output pins. O 3.3V

GPO[1] B54 General purpose output pins. O 3.3V

GPO[2] B57 General purpose output pins. O 3.3V

GPO[3] B63 General purpose output pins. O 3.3V

GPI[0] A54 General purpose input pins. Pulled high internally on the

module.

GPI[1] A63 General purpose input pins. Pulled high internally on the

module.

GPI[2] A67 General purpose input pins. Pulled high internally on the

module.

GPI[3] A85 General purpose input pins. Pulled high internally on the

module.

I 3.3V PU 10K 3.3V PU not in PICMG suggest 10K

PU 10K 3.3V After hardware RESET output low

nanoX-BT Page 23

3.3.17. Serial Interface Signals

Signal Pin # Description I/O PU/PD Comment

SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V / 12V

SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V / 12V

SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V / 12V

SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V / 12V

3.3.18. Power And System Managemen

Signal Pin # Description I/O PU/PD Comment

PWRBTN# B12 Power button to bring system out of S5 (soft off), active on

falling edge.

SYS_RESET# B49 Reset button input. Active low request for module to reset and

reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.

CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued

by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.

PWR_OK B24 Power OK from main power supply. A high value indicates

that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.

SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC

devices.

SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low

output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the nonstandby power on a typical ATX power supply.

I 3.3VSB PU 10k 3.3VSB

O 3.3VSB

I 3.3V PU 100k

3.3VSB

O 3.3VSB

SUS_S4# A18 Indicates system is in Suspend to Disk state.

Active low output.

SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB Not supported,

WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k 3.3VSB Not supported,

WAKE1# B67 General purpose wake up signal. May be used to implement

wake-up on PS/2 keyboard or mouse activity.

BATLOW# A27 Battery low input. This signal may be driven low by external

circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.

LID# A103 LID button. Low active signal used by the ACPI operating

system for a LID switch.

SLEEP# B103 Sleep button. Low active signal used by the ACPI operating

system to bring the system to sleep state or to wake it up again.

O 3.3VSB

connect to SUS_S4#

connected to WAKE1#

I 3.3VSB PU 10k 3.3VSB

I OD 3.3VSB PU 10k 3.3VSB Emulate GPIO (BIOS)

I OD 3.3VSB PU 10K 3.3VSB Emulated GPIO (BIOS)

Page 24 nanoX-BT

3.3.19.

Signal Pin # Description I/O PU/PD Comment

VCC_12V A104-A109

VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. See section 7 “Electrical

VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P

GND A1, A11, A21, A31, A41, A51,

Power and Ground

B104-B109

A57, A66, A80, A90, A96, A100, A110, B1, B11, B21 ,B31, B41, B51, B60, B70, B80, B90, B100, B110

Primary power input: +12V nominal See section 7 “Electrical Specifications“ for allowable input range. All available VCC_12V pins on the connector(s) shall be used.

Specifications“ for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.

Ground - DC power and signal and AC signal return path. P

P 5~14 V

P 5Vsb

±5%

nanoX-BT Page 25

4. Module interfaces

This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification

4.1. Connector, Switch and LED Locations

Note: The optional XDP Debug Header is located on breakout PCB.

4.1.1. nanoX-BT and the DB40 Module connected

Page 26 nanoX-BT

4.2. 40-pin Multipurpose Connector

¾ FPC Connector Type: FCI 59GF Flex 10042867 ¾ Pin Orientation

1 40

¾ Pin Definitions (on COMe module)

Pin Interface Signal Remark Pin Interface Signal Remark

1 VCC_SPI_IN SPI Power Input from flash tool to

SPI Program interface

2 GND 22 RXD6

3 SPI_BIOS_CS0# 23 FUMD0

4 SPI_BIOS_CS1# 24 RESET_IN#

5 SPI_BIOS_MISO 25 DATA

6 SPI_BIOS_MOSI 26 CLK

8 3V3_LPC System power 3.3V provide from

LPC Bus

9 GND 29 PWRBTN#

10 BIOS_DIS0 30 SYS_RESET#

11 RST# 31 CB_RESET#

12 CLK33_LPC 32 CB_PWROK

13 LPC_FRAME# 33 SUS_S3#

SPI_BIOS_CLK 27 OCD0A Include a jumper to connect

module. HW need add MOS FET to switch SPI power for SPI ROM

COM module

21 TXD6

BMC Program interface (continued)

OCD0A via 1K0 pull-up to

3.3V_BMC

OCD0B Include a jumper to connect

OCD0A via 1K0 pull-up to

3.3V_BMC

Test points

14 LPC_AD3 34 SUS_S4#

15 LPC_AD2 35

16 LPC_AD1 always power 3.3V provide from

COM module

BMC

Program interface

19 3.3V_BMC always power 3.3V provide from

LPC_AD0 37 SEL_BIOS Connect to Jumper for

3.3V_BMC always power 3.3V provide from COM module

COM module

GND 40 Reserved

36 POSTWDT_DIS# Connect to Jumper for

38 BIOS_MODE Connect to Jumper for

BMC Debug signals

SUS_S5#

Debug

BMC_STATUS

Note: the pin description on the Debug Module is the inverse of that on the COM Express module.

nanoX-BT Page 27

4.3. Status LEDs

To facilitate easier maintenance, status LED’s are mounted on the board.

LED1 LED2 LED3

¾ LED Descriptions

Name Color Connection Function

LED1 Blue BMC output Power Sequence Status Code (BMC)

Power Changes, RESET

(see 5.1.4 Exception Codes below)

LED2 Green Power Source 3Vcc S0 LED ON

S3/S4/S5 LED OFF ECO mode LED OFF

LED3 Red BMC output and same

signal as WDT (B27) on BtB connector

Module power up LED OFF Watchdog counting LED OFF Watchdog timed out LED ON Watchdog RESET LED ON Rebooted after WD RESET LED ON Rebooted after PWRBTN LED ON Rebooted after RESET BTN LED OFF

Note: only a RESET not initiated by the BMC can clear the WD LED (user action)

Page 28 nanoX-BT

4.4. XDP Debug Header

Optionally available on breakout PCB. The debug port is a connection into a target-system environment that provides

access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec 60-pin BSH-030-01 series connector. Specific plating types, locking clips, and alignment pin details of this connector can be obtained from Samtec. No specific plating types, locking clips or alignment pins are required for the XDP tool.

Pin XDP Signal Target Signal I/O Device Pin XDP Signal Target Signal I/O Device

1 GND GND NA 2 GND GND NA

3 OBSFN_A0 TAP_PREQ# I/O SoC 4 OBSFN_C0 MCSI_GPIO[00] I SoC

5 OBSFN_A1 TAP_PRDY# I/O SoC 6 OBSFN_C1 GPIO_S5[22] I SoC

7 GND GND NA 8 GND GND NA

9 OBSDATA_A0 GPIO_S5[23] I/O SoC 10 OBSDATA_C0 GPIO_S0_NC[16] I/O SoC

11 OBSDATA_A1 GPIO_S5[24] I/O SoC 12 OBSDATA_C1 GPIO_S0_NC[17] I/O SoC

13 GND GND NA 14 GND GND NA

15 OBSDATA_A2 GPIO_S5[25] I/O SoC 16 OBSDATA_C2 GPIO_S0_NC[18] I/O SoC

17 OBSDATA_A3 GPIO_S5[26] I/O SoC 18 OBSDATA_C3 GPIO_S0_NC[19] I/O SoC

19 GND GND NA 20 GND GND NA

21 OBSFN_B0 OPEN 22 OBSFN_D0 OPEN

23 OBSFN_B1 OPEN 24 OBSFN_D1 OPEN

25 GND GND NA 26 GND GND NA

27 OBSDATA_B0 GPIO_S5[27] I/O SoC 28 OBSDATA_D0 GPIO_S0_NC[20] I SoC

29 OBSDATA_B1 GPIO_S5[28] I/O SoC 30 OBSDATA_D1 GPIO_S0_NC[21] I SoC

31 GND GND NA 32 GND GND NA

33 OBSDATA_B2 GPIO_S5[29] I/O SoC 34 OBSDATA_D2 GPIO_S0_NC[22] I/O SoC

35 OBSDATA_B3 GPIO_S5[30] I/O SoC 36 OBSDATA_D3 GPIO_S0_NC[23] I/O SoC

37 GND GND NA 38 GND GND NA

39 HOOK0 PMC_RSMRST# I SoC 40 ITPCLK/ HOOK4 Open NA

41 HOOK11 PMIC_PWRBTN# O System 42 ITPCLK#/ HOOK5 Open NA

43 VCC_OBS_AB V1P8A NA System 44 VCC_OBS_CD 1.8VS (Core) NA System

45 HOOK2 PMC_CORE_PW

ROK

I SoC 46 HOOK6/ RESET# PMC_PLTRST# I SoC

47 HOOK3 ILB_RTC_TEST# O SoC 48 HOOK7/ DBR# PMC_RSTBTN# O SoC

49 GND GND NA 50 GND GND NA

51 SDA1 SDA I/O System 52 TDO TAP_TDO I SoC

53 SCL1 SCL I/O System 54 TRSTn TAP_TRST# O SoC

55 TCK1 Open NA 56 TDI TAP_TDI O SoC

57 TCK0 TAP_TCK O SoC 58 TMS TAP_TMS O SoC

59 GND GND NA 60 GND GND

(or XDP_PRESENT# if required)

Refer to the " Bay Trail M/D/I Platform” Debug Port Design Guide (DPDG), Document Number: 512816, Revision: 2.1

nanoX-BT Page 29

5. Smart Embedded Management Agent (SEMA)

The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality.

The microcontroller communicates via the System Management Bus with the CPU/chipset.

The following functions are implemented

¾ Total operating hours counter. Counts the number of hours the module has been run in minutes. ¾ On-time minutes counter. Counts the seconds since last system start. ¾ Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in

flash.

¾ Power cycles counter ¾ Boot counter. Counts the number of boot attempts. ¾ Watchdog Timer (Type-II). Set / Reset / Disable Watchdog Timer. Features auto-reload at power-up. ¾ System Restart Cause. Power loss / BIOS Fail / Watchdog / Internal Reset / External Reset ¾ Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS. ¾ Flash area. 1kB Flash area for customer data ¾ 128 Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region. ¾ Board Identify. Vendor / Board / Serial number / Production Date ¾ Main-current & voltage. Monitors drawn current and main voltages

For a detailed description of SEMA features and functionality, please refer to the SEMA Technical Manual and SEMA Software Manual,

downloadable at:

Note: Due to limitations of the Intel “Bay Trail” platform, SEMA can only obtain CPU temperature readings when the OS is running.

http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1274

Page 30 nanoX-BT

5.1. Board Specific SEMA Functions

5.1.1. Voltages

The BMC of the nanoX-BT implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

ADC Channel Voltage Name Voltage Formula [V]

0 CPU-Vcore (MSB<<8 + LSB) x 3.3 / 1024

1 GFX-Vcore (MSB<<8 + LSB) x 3.3 / 1024

2 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024

3 Vmem (MSB<<8 + LSB) x 3.3 / 1024

4 +V1.0V (MSB<<8 + LSB) x 3.3 / 1024

5 +V3.3V (MSB<<8 + LSB) x 1.1 x 3.3 / 1024

6 +VIN (MSB<<8 + LSB) x 6.000 x 3.3 / 1024

7 (MAIN CURRENT) Use Main Current Function

5.1.2. Main Current

The BMC of the nanoX-BT implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.

Main Current = (MSB_n<<8 + LSB_n) x 8.06mA

5.1.3. BMC Status

This register shows the status of BMC controlled signals on the nanoX-BT.

Status Bit Signal

0 WDT_OUT

1 LVDS_VDDEN

2 LVDS_BKLTEN

3 BIOS_MODE

4 POSTWDT_DISn

5 SEL_BIOS

6 BIOS_DIS0n

7 BIOS_DIS1n

nanoX-BT Page 31

5.1.4. Exception Codes

In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

Exception Code Error Message

0 NOERROR

2 NO_SUSCLK

3 NO_SLP_S5

4 NO_SLP_S4

5 NO_SLP_S3

6 BIOS_FAIL

7 RESET_FAIL

8 POWER_FAIL

9 LOW_VIN

10 VCORE

11 VGFX

12 V1P05S

13 VMEM

14 V1P0A

15 V3P3A

16 +P12V_5V

18 CRITICAL_TEMP

19 NO_CB_PWROK

20 NO_HW_PWORK

21 NO_V1P24A_PG

5.1.5. BMC Flags

The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

Bit Description

[ 0 ~ 4 ] Exception Code

[ 6 ] 0 = AT mode

1 = ATX mode

[ 7 ] 0 = Standard BIOS

1 = Fail-safe BIOS.

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6. System Resources

6.1. System Memory Map

Address Range (decimal) Address Range (hex) Size Description

Start 128KB below 1MB 000E0000h-000FFFFFh Low Bios

Starts 20MB below 4GB FEC00000h-FEC0040h IO APIC

Start 19MB below 4GB FED00000h-FED003FFh HPET

Start 64 KB below 4GB FFFF0000h-FFFFFFFFh High Bios

0K –1MB 1MB DOS DRAM

6.2. I/O Map

Hex Range Device

20h-21h, 24h-25h, 28h-29h, 2Ch-2Dh, 30h-31h, 34h-5h, 38h-39h, 3Ch-3Dh

40h-43h, 50h-53h 8254s

61h, 63h, 65h, 67h NMI Controller

70h-77h RTC

80h-83h Port 80h

92h Init Register

A0h-A1h, A4h-A5h, A8h-A9h, ACh-ADh, B0h-B1h,B4h-B5h, B8h-B9h, BCh-BDh, 4D0h-4D1h

3F8h-3FFh PCU UART (COM1)

B2h-B3h Active Power Management

E000 Smbus base address for SB.

500 GPIO Base Address for SB

400 PM (ACPI) Base Address for SB

8259 Master

8259 Slave

nanoX-BT Page 33

6.3. Interrupt Request (IRQ) Lines

6.3.1. PIC Mode

IRQ# Typical Intterupt Resource Connected to Pin Available

0 Counter 0 N/A No

1 Keyboard controller IRQ1 via SERIRQ / PIRQ No

2 Cascade interrupt from slave PIC N/A No

3 Generic IRQ3 via SERIRQ / PIRQ Note (1)

4 PCU Serial Port (COM1) IRQ4 via SERIRQ / PIRQ Note (1)

5 Generic IRQ5 via SERIRQ / PIRQ Note (1)

6 Generic IRQ6 via SERIRQ / PIRQ Note (1)

7 Generic IRQ7 via SERIRQ / PIRQ Note (1)

8 Real-time clock N/A No

9 Generic IRQ9 via SERIRQ / PIRQ Note (1)

10 Generic IRQ10 via SERIRQ / PIRQ Note (1)

11 Generic IRQ11 via SERIRQ / PIRQ Note (1)

12 Generic IRQ12 via SERIRQ / PIRQ Note (1)

13 Math Processor N/A No

14 Primary IDE controller IRQ14 via SERIRQ / PIRQ Note (1)

15 Secondary IDE controller IRQ15 via SERIRQ / PIRQ Note (1)

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

6.3.2. APIC Mode

IRQ# Typical Intterupt Resource Connected to Pin Available

0 System timer N/A No

1 N/A N/A No

2 N/A N/A No

3 N/A N/A Note (1)

4 Serial Port 1 (COM1) IRQ4 via SERIRQ / PIRQ Note (1)

5 N/A N/A Note (1)

6 N/A N/A Note (1)

7 N/A N/A Note (1)

8 High precision event timer N/A No

9 N/A N/A Note (1)

10 N/A N/A Note (1)

11 N/A N/A Note (1)

Page 34 nanoX-BT

IRQ# Typical Intterupt Resource Connected to Pin Available

12 N/A IRQ12 via SERIRQ / PIRQ Note (1)

13 N/A N/A Note (1)

14 N/A N/A Note (1)

15 N/A N/A Note (1)

16 N/A PCIE Port 1/2/3/4, eMMC, IGD Note (1)

17 N/A PCIE Port 1/2/3/4 Note (1)

18 N/A PCIE Port 1/2/3/4, SD Device, HSUART Note (1)

19 N/A PCIE Port 1/2/3/4, AHCI controller Note (1)

20 N/A Gbe controller, xHCI controller Note (1)

21 N/A Low Power Audio Engine,TXE Note (1)

22 N/A Intel HDA Note (1)

23 N/A N/A Note (1)

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

nanoX-BT Page 35

6.4. PCI Configuration Space Map

Bus Number Device Number Function Number Routing Description

00h 00h 00h N/A Soc Transaction Router

00h 02h 00h Internal Graphics & Display

00h 12h 00h Internal Storage Control Cluster (SD Port)

00h 13h 00h Internal SATA

00h 14h 00h Internal xHCI USB

00h 17h 00h Internal Storage Control Cluster (MMC Port)

00h 1Ah 00h Internal Trusted Execution Engine

00h 1Bh 00h Internal HD Audio

00h 1Ch 00h Internal PCI Express Root port 1

00h 1Ch 01h Internal PCI Express Root port 2

00h 1Ch 02h Internal PCI Express Root port 3

00h 1Ch 03h Internal PCI Express Root port 4

00h 1Eh 00h Internal Serial IO(SIO:DMA)

00h 1Eh 03h Internal Serial IO(SIO:HSUART Port 1)

00h 1Dh 00h Internal EHCI USB

00h 1Fh 00h N/A Platform Controller Unit(LPC)

00h 1Fh 03h Internal SMBus Controller

02h 00h 00h Internal Ethernet Controller

04h 00h 00h Internal Ethernet Controller

Page 36 nanoX-BT

6.5. PCI Interrupt Routing Map

INT Line Intel IGD PCIE Root

Port#1

Int0 INTA:16 INTA:16 INTA:16 INTC:18

Int1 INTB:17

Int2 INTC:18

Int3 INTD:19

PCIE Root Port#2

PCIE Root Port#3

PCIE Root Port#4

SD Host # 0 eMMC

SD Host# 2 SD Card

INT Line SATA

Controller

Int0

Int1

Int2

Int3

INTE:20 INTF:21 INTF:21 INTG:22 INTH:23

INTC:18

INTD:19

xHCI Host Low Power

Audio Engine

TXE HD Audio EHCI

Controller

SMBus Controller

INT Line GbE Controller LPSS2 DMA LPSS2

HSUART#1

Int0

Int1

INTE:20 INTD:19

Int2

Int3

INTC:18

6.6. SMBus Address Table

Device

DIMM A

DIMM B

BMC

Extend GPIO

Address

A0h

A4h

50h

40h

nanoX-BT Page 37

7. BIOS Setup

7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting

options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

Main Advanced Boot Security Save & Exit

- System Information

- Processor Information

- VGA Firmware Version

- Memory Information

- SOC Information

- System ►

Management

- System Date

- System Time

Notes:

► indicates a submenu

Gray text indicates info only

- CPU ►

- Memory ►

- Graphics ►

- SATA ►

- USB ►

- Network ►

- PCI and PCIe ►

- Super IO ►

- ACPI and ►

Power Management

- Sound ►

- Serial Port ►

Console

- Thermal ►

- Miscellaneous ►

- Boot Configuration ►

CSM Parameters ►

- Password

Description

- Secure Boot

Menu ►

- Reset Options

- Save Options

Page 38 nanoX-BT

7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings.

7.2.1. System Information

Feature Options Description

BIOS Version Info only ADLINK BIOS version

Build Date and Time Info only Date the BIOS was built

7.2.2. Processor Information

Feature Options Description

CPU Brand String Info only Display CPU brand name

Max CPU Speed Info only Display CPU frequency

CPU Signature Info only Display CPU ID

Number of Processors Info only Display number of processor

7.2.3. VGA Firmware Version

Feature Options Description

IGFX VBIOS Version IGFX GOP Version

Info only Display legacy VBIOS or GOP driver version

7.2.4. Memory Information

Feature Options Description

Total Memory Info only Display total memory information

7.2.5. SOC Information

Feature Options Description

BayTrail Soc Info only Display SOC stepping

TXE FW Version Info only Display version of TXE

nanoX-BT Page 39

7.2.6. System Management

7.2.6.1. System Management > Board Information

Board Information Info only

SMC Firmware Read only Display SMC firmware

Build Date Read only Display SMC firmware build date

SMC Boot loader Read only Display SMC boot loader

Build Date Read only Display SMC boot loader build date

Hardware Version Read only Display SMC hardware version

PCBA Revision Read only Display PCBA revision

Serial Number Read only Display SMC serial number

Manufacturing Date Read only Display SMC manufacturing date

Last Repair Date Read only Display SMC last repair date

MAC ID Read only Display SMC MAC ID

SEMA Features: Read only Display SEMA features

7.2.6.2. System Management > Temperatures and Fan Speed

Feature Options Description

Temperatures and Fan Info only

Board Temperatures Info only

Current Read only Display current board temperature Startup Read only Display board startup temperature

Min Read only Display board min. temperature

Max Read only Display board max. temperature

CPU Fan Speed Read only Display CPU fan speed

System Fan Speed Read only Display system fan speed

7.2.6.3. System Management > Power Consumption

Feature Options Description

Power Consumption Info only

Current Input Current Read only Display input current Current Input Power Read only Display input power

GPU-Vcore Read only Display actual GPU-Vcore voltage

GFX-Vcore Read only Display actual GFX-Vcore voltage

V1.05 Read only Display actual V1.05 voltage

V1.35 Read only Display actual V1.35 voltage V1.00 Read only Display actual V1.00 voltage

Page 40 nanoX-BT

Feature Options Description

V3.30 Read only Display actual V3.30 voltage

VIN Read only Display actual VIN voltage

AIN7 Read only Display actual AIN7 voltage

7.2.6.4. System Management > Runtime Statistics

Feature Options Description

Runtime Statistics Info only

Total Runtime Read only The returned value specifies the total time in minutes the system

is running in S0 state.

Current Runtime Read only The returned value specifies the time in seconds the system is

running in S0 state. This counter is cleared when the system is removed from the

external power supply.

Power Cycles Read only The returned value specifies the number of times the external

power supply has been shut down

Boot Cycles Read only The Bootcounter is increased after a HW- or SW-Reset or after a

successful power-up.

Boot Reason Read only The boot reason is the event which causes the reboot of the

system.

7.2.6.5. System Management > Flags

Feature Options Description

Flags Info only

BMC Flags Read only

BIOS Select Read only Display the selection of current BIOS ROM

ATX/AT-Mode Read only Display ATX/AT-Mode

Exception Code Read only System exception reason

7.2.6.6. System Management > Power Up

Feature Options Description

Power Up Info only

Power Up watchdog Attention: F12 disables the Power Up

Watchdog.

Enabled

Disabled

The Power-Up Watchdog resets the system after a certain amount of time after power-up.

ECO Mode Disabled

Enable

Power-up Mode Attention: The Power-Up Mode only has effect,

if the module is in ATX-Mode.

Turn on

Remain off Last State

Reduces the power consumption of the system

Turn On: The machine starts automatically when the power supply is turned on. Remain Off: To start the machine the power button has to be pressed. Last State: When powered on during a power failure the system will automatically power on when power is restored.

nanoX-BT Page 41

7.2.6.7. System Management > LVDS Backlight

Feature Options Description

LVDS Backlight Info only

LVDS Backlight Bright 255 The value range starts at 0 and ends at 255.

7.2.6.8. System Management > Smart Fan

Feature Options Description

Smart Fan Info only

CPU Smart FanTemperature Source CPU Sensor

System Sensor

CPU Fan Mode AUTO (Smart Fan)

Fan Off Fan On

CPU Trigger Point 1 Read only

Trigger Temperature 15 Specifies the temperature threshold at which the BMC turns on

PWM Level 30 Select PWM level

CPU Trigger Point 2 Read only

Trigger Temperature 60 Specifies the temperature threshold at which the BMC turns on

PWM Level 40 Select PWM level

CPU Trigger Point 3 Read only

Trigger Temperature 70 Specifies the temperature threshold at which the BMC turns on

PWM Level 63 Select PWM level

CPU Trigger Point 4 Read only

Select CPU smart fan source

Select CPU fan mode

the CPU fan with the specified PWM level

CPU fan the specified PWM level

Trigger Temperature 80 Specifies the temperature threshold at which the BMC turns on

CPU fan the specified PWM level

PWM Level 100 Select PWM level

7.2.7. System Date and Time

Feature Options Description

System Date Day of Week, MM/DD/YYYY Requires the alpha-numeric entry of the day of the week, day of the

month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)

System Time HH/MM/SS Presented as a 24-hour clock setting in hours, minutes, and seconds

Page 42 nanoX-BT

7.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1. CPU

Feature Options Description

CPU Infor only

CPU Brand Name Info only Display CPU brand name

CPU Signature Info only Display CPU signature

Processor Family Info only Display processor family

Microcode Patch Info only Display microcode patch

Max CPU speed Info only Display max. CPU speed

Min CPU speed Info only Display min. CPU speed

Processor Cores Info only Display number of processor cores

Intel HT Technology Info only Display Intel HT Technology support

Intel VT-x Technology Info only Display Intel VT-x Technology support

64-bit Info only Display 64-bit support

L1 Data Cache Info only Display cache info

L1 Code Cache Info only Display cache info

L2 Cache Info only Display cache info

L3 Cache Inf o only Display cache info

Limit CPUID Maximum Disabled

Enabled

Execute Disabled Bit Disabled

Enabled

Intel Virtualization Technology Disabled

Enabled

SB CRID Revision ID

CRID 0 CRID 1 CRID 2

Disabled for Windows XP

XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.2, Red Hat Enterprise 3 Update 3.)

When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

Select the Revision ID (Revision ID, CRID 0, CRID 1, CRID 2) reflected in PCI config space

CPU Processor Power Management (PPM) Info only

EIST Disabled

Enabled

CPU C state Report Disabled

Enabled

CPU DTS Disabled

Enabled

Enable/Disable Intel SpeedStep

Enable/Disable CPU C state report to OS

Enabled/Disable digital thermal sensor

nanoX-BT Page 43

7.3.2. Memory

Feature Options Description

Memory Info only

Total Memory Info only Display total memory

DIMM#0/1 Info only Display DIMM#0/1

SPD Write Protect Enabled

Disabled

Max TOLUD Dynamic Maximum value of TOLUD

Enabled: Writes to SMBus slave addresses A0h – Aeh are disabled

7.3.3. Graphics

Feature Options Description

Graphics Info only

IGFX VBIOS Version Info only

Primary Display Auto

IGD

PCIE

Integrated Graphics Device Enabled

Disabled

Aperture Size 256MB Select the aperture size

DVMT Pre-Allocated 64M Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used

DVMT Total Gfx Mem 256MB Select DVMT5.0 Total Graphic Memory size used by the Internal

Select which graphics device (IGD/PCI) should be primary display

Enabled: Enable Integrated Graphics Device (IGD) when selected as the primary display; Disabled: Always disable IGD

by the Internal Graphics Device.

Graphics Device.

LVDS Backlight Mode BMC Mode

GTT Mode

AMI Graphics Output Protocol Policy [UEFI GOP only]

GT – Power Management Control Info only

RC6 (Render Standby) Enabled

Submenu User select monitor output by graphics output protocol

Disabled

7.3.3.1. AMI Graphics Output Protocol Policy

Feature Options Description

Intel(R) Valley View Graphics Controller Info only

Intel(R) GOP Driver Info only

Output Select [List connect device]

Brightness Setting [LFP device connect only]

BIST Enable Enabled

CRT Output Interface.

255 Set GOP Brightness value

Disabled

Select LVDS backlight control function.

Enable/Disable render standby support

Starts or stops the built-in self-test (BIST) on the integrated display panel.

Page 44 nanoX-BT

7.3.4. SATA

Feature Options Description

SATA Info only

SATA Controller(s) Enabled

Disabled

SATA Mode Selection IDE Mode

AHCI Mode

SATA Test Mode Enabled

Disabled

SATA Controller Speed Gen1

Gen2

SATA Port Configuration Submenu

7.3.4.1. SATA > SATA Port Configuration

Feature Options Description

SATA Port Configuration Info only

Port X Disabled

Enabled

HotPlug Enabled

Disabled

7.3.5. USB

Enable/Disable Serial ATA.

Select IDE/AHCI

Test Mode enable/disable

SATA speed support Gen1 or Gen2.

Enable/Disable SATA port X.

Enable/Disable SATA port X hotplug.

Feature Options Description

USB Info only

USB Module Version Info only

USB Devices Info only Drives, keyboards, mouse, hubs

Legacy USB Support Enabled

Disabled Auto

XHCI Hand-off Enabled

Disabled

EHCI Hand-off Enabled

Disabled

USB Mass Storage Driver Support Enabled

Disabled

Chipset USB Configuration Submenu

USB hardware delays and time-outs: Info only

USB transfer time-out 1 sec

5 sec 10 sec

20 sec

Enables legacy USB support. Auto option disables legacy support if no USB devices are

connected. Disable option will keep USB devices available only for EFI

applications and setup.

This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI OS driver.

This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by the EHCI OS driver.

Enable/Disable USB mass storage driver support.

The time-out value for control, bulk, and interrupt transfers

Device reset time-out 10 sec

20 sec

30 sec 40 sec

USB mass storage device Start Unit command time-out.

nanoX-BT Page 45

Feature Options Description

Device power-up delay Auto

Manual

Mass Storage Devices Info only List current USB mass storage devices.

Maximum time the device will take before it properly reports itself to the Host Controller. 'Auto' uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.

7.3.5.1. USB > Chipset USB Configuration

Feature Options Description

USB Configuration Info only

USB OTG Support Enabled

Disabled

USB VBUS On

Off

XHCI Mode Enabled

Disabled Auto

Smart Auto

USB 2.0 (EHCI) Support Enabled

Disabled

USB Per Port Control Enabled

Disabled

Enable/Disable USB OTG support.

VBUS Should be On in Host Mode. It should be Off in OTG device mode..

Mode of operation of xHCI controller.

Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled.

Control each of the USB ports (0~3). Enable: Enable USB per port; Disable: Use USB port x settings.

USB Port #0~3 Enabled

Disabled

Enable/Disable USB port 0-3.

7.3.6. Network

Feature Options Description

Network Info only

Network Stack Enabled

Disabled

LAN Controller Enabled

Disabled

Wake on LAN Disable

Enabled

Enable/Disable UEFI network stack.

Enable/Disable LAN controller.

If Enabled: LAN_PWR is always on; If Disabled: LAN_PWR is off after entering Suspend mode.

7.3.7. PCI and PCIe

Feature Options Description

PCI and PCIe Info only

PCI Common Settings Info only

PCI Latency 32 PCI Bus Clocks

64 PCI Bus Clocks 96 PCI Bus Clocks 128 PCI Bus Clocks 160 PCI Bus Clocks 192 PCI Bus Clocks 224 PCI Bus Clocks 248 PCI Bus Clocks

Value to be programmed into PCI latency timer register.

Page 46 nanoX-BT

Feature Options Description

VGA Palette Snoop Disabled

Enabled

PERR# Generation Enabled

Disabled

SERR# Generation Enabled

Disabled

PCI Express Settings Info only

Relaxed Ordering Disabled

Enabled

Extended Tag Disabled

Enabled

No Snoop Disabled

Enabled

Maximum Payload Auto

128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes

Maximum Read Request Auto

128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes

Enables or Disables VGA palette registers snooping.

Enable or Disable the PCI Express port 1 in the chipset.

Enables or Disables PCI Device to generate SERR#.

Enables or Disables PCI Express device relaxed ordering.

If Enabled, allows device to use 8-bit tag field as a requester.

Enables or Disables PCI Express device No Snoop option.

Set maximum payload of PCI Express device or allow system BIOS to select the value.

Set maximum read request size of PCI Express device or allow system BIOS to select the value.

PCI Express Link Register Settings Info only

ASPM Support WARNING: Enabling ASPM may cause some

PCI-E devices to fail

Extended Synch Disabled

Link Training Retry Disable

Link Training Timeout (Us) 1000 Defines number of microseconds software will wait before polling

Unpopulated Links Keep Link ON

Restore PCIE Registers Enabled

PCIe Configuration Info only

PCIe Configuration Submenu

Disabled

Auto Force L0s

Enabled

2 3

Disabled

Set the ASPM Level: Force L0s - Force all links to L0s Auto - BIOS auto configure Disabled - Disables ASPM

If enabled, allows generation of Extended Synchronization patterns.

Defines number of retry attempts software will take to retrain the link if previous training attempt was unsuccessful.

'Link Training' bit in Link Status register. Value range from 10 to 10000 uS.

In order to save power, software will disable unpopulated PCI Express links if this option set to Disabled.

On non-PCI Express aware OSes (pre Windows Vista) some devices may not be correctly reinitialized after S3. Enabling this restores PCI Express device configurations on S3 resume. Warning: Enabling this may cause issues with other hardware after S3 resume.

nanoX-BT Page 47

7.3.7.1. PCI and PCIe > PCIe Configuration

Feature Options Description

PCIe Configuration Info only

PCI Express Root Port x Submenu

7.3.7.2. PCI and PCIe > PCIe Configuration > PCI Express Port x

Feature Options Description

PCI Express Port x Enabled

Disabled

ASPM Auto PCI Express Active State Power Management settings. URR Disabled

Enabled

FER Disabled

Enabled

NFER Disabled

Enabled

CER Disabled

Enabled

SEFE Disabled

Enabled

SENFE Disabled

Enabled

SECE Disabled

Enabled

PME SCI Disabled

Enabled

Hot Plug Disabled

Enabled

Enable or disable the PCI Express port x in the chipset.

Enable or disable PCI Express Unsupported Request Reporting.

Enable or disable PCI Express Device Fatal Error Reporting.

Enable or disable PCI Express Device Non-Fatal Error Reporting.

Enable or disable PCI Express Device Correctable Error Reporting.

Enable or disable Root PCI Express System Error on Fatal Error.

Enable or disable Root PCI Express System Error on Non-Fatal Error.

Enable or disable Root PCI Express System Error on Correctable Error.

Enable or disable PCI Express PME SCI.

Enable or disable PCI Express hotplug.

Speed Auto

Gen 2

Gen 1

Configure PCIe port speed.

7.3.8. Super IO

Feature Options Description

Super IO Chip Info only

W83627DHG Super IO Configuration Info only

Serial Port 1 Configuration Serial Port

Device Settings

Change Settings

Page 48 nanoX-BT

Enabled

Disabled

IO=3F8h; IRQ=4

Auto

IO=3F8h; IRQ=4 IO=3F8h; IRQ=3,4,5,6,7,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,10,11,12

Enable/Disable Serial Port 1 (COM0).

Fixed configuration of serial port.

Select an optimal setting for Super IO device.

Feature Options Description

Serial Port 2 Configuration Serial Port

Device Settings

Change Settings

Parallel Port Configuration Parallel Port

Device Settings

Change Settings

Enabled

Disabled

IO=2F8h; IRQ=3

Auto

IO=2F8h; IRQ=3 IO=3F8h; IRQ=3,4,5,6,7,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,10,11,12

Enabled

Disabled

IO=378h; IRQ=5;

Auto

IO=378h; IRQ=5; IO=378h; IRQ=5,6,7,9,10,11,12; IO=278h; IRQ=5,6,7,9,10,11,12; IO=3BCh; IRQ=5,6,7,9,10,11,12;

Enable/Disable Serial Port 2 (COM1).

Fixed configuration of serial port.

Select an optimal setting for Super IO device.

Enable or Disable Parallel Port (LPT/LPTE)

Fixed configuration of parallel port.

Select an optimal setting for Super IO Device.

7.3.9. ACPI and Power Management

Feature Options Description

ACPI and Power Management Info only

Enable ACPI Auto Configuration Enabled

Disabled

Enable Hibernation Enabled

Disabled

ACPI Sleep State Suspend Disabled

S3 (Suspend to RAM)

Enables or disables BIOS ACPI Auto Configuration.

Enables or disables system's ability to hibernate (OS/S4 Sleep State). This option may be not effective with some OSes.

Select the highest ACPI sleep state the system will enter when the Suspend button is pressed.

7.3.10. Sound

Feature Options Description

Sound Info only

Azalia Disabled

Enabled

Control detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally enabled. Auto = Azalia will be enabled if present, disabled otherwise.

Azalia Docking Support Disabled

Enabled

Azalia PME Disabled

Enabled

Enable/Disable Azalia docking support of audio controller.

Enable/Disable power management capability of audio controller.

nanoX-BT Page 49

7.3.11. Serial Port Console

Feature Options Description

Serial Port Console Info only

COM0 Info only

Console Redirection Disabled

Enabled

Console Redirection Settings Submenu The settings specify how the host computer and the remote

COM1 Info only

Console Redirection Disabled

Enabled

Console Redirection Settings Submenu The settings specify how the host computer and the remote

Console Redirection enable or disable.

computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.

Console Redirection enable or disable.

computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.

7.3.11.1. Serial Port Console > Console Redirection Settings

Feature Options Description

COM0/COM1 Console Redirection Settings Info only

Terminal Type VT100

VT100+

VT-UTF8 ANSI

Bits per second 9600

19200 38400 57600

115200

Data Bits 7

Parity None

Even Odd Mark Space

Stop Bits 1

Flow Control None

Hardware RTS/CTS

VT-UTF8 Combo Key Support Disabled

Enable

Recorder Mode Disabled

Enable

Resolution 100x31 Disabled

Enable

Legacy OS Redirection 80x24

80x25

Putty KeyPad VT100

LINUX XTERMR6 SCO ESCN VT400

VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. ANSI: Extended ASCII char set.

Selects serial port transmission speed. The speed must be matched on the remote computer. Long or noisy lines may require lower speeds.

Select data bits.

Select parity.

Select number of stop bits.

Select flow control.

Enable VT-UTF8 combination key support for ANSI/VT100 terminals.

With this mode enabled only text will be sent. This is to capture terminal data.

Enables or disables extended terminal resolution

On legacy OSes, the number of rows and columns supported by redirection

Select FunctionKey and KeyPad on Putty.

Page 50 nanoX-BT

Feature Options Description

Redirection After BIOS Post Always Enabled

BootLoader

The Settings specify if BootLoader is selected, then legacy console redirection is disabled before booting to legacy OS. Default value is Always Enable which means legacy console redirection is enabled for legacy OS.

7.3.12. Thermal

Feature Options Description

Thermal Info only

CPU Temperature Info only Critical Trip Point Disabled

85 C 95 C

Active Cooling Trip Point Disabled

40 C 50 C 60 C 70 C

BMC Default

Passive Trip Point Disabled

90 C 80 C

Passive TC1 Value 1 This value sets the TC1 value for the ACPI Passive Cooling

Passive TC2 Value 5 This value value sets the TC2 value for the ACPI Passive Cooling

Passive TSP Value 10 This item sets the TSP value for the ACPI Passive Cooling Formula.

This value controls the temperature of the ACPI Critical Trip Point the point at which the OS will shut the system down.

Active Cooling Trip Point.

This value controls the temperature of the ACPI Passive Trip Point the point at which the OS will begin throtting the processor.

Formula. Range 1 - 16

It represents in tenths of a second how often the OS will read the temperature when passive cooling is enabled. Range 2 - 32

7.3.13. Miscellaneous

Feature Options Description

Miscellaneous Info only

High Precision Timer Enabled

Disabled

SCC Configuration Submenu

Security Info only

BIOS Security Configuration Submenu

Trusted Computing Submenu

Enable or disable the High Precision Event Timer.

7.3.13.1. Miscellaneous > SCC Configuration

Feature Options Description

OS Selection Windows 8.X

Android Windows 7

SCC Devices Mode ACPI mode

PCI mode

nanoX-BT Page 51

OS Selection

SCC devices mode setting.

Feature Options Description

SCC Configuration Info only

SCC eMMC Support Enable eMMC 4.5 Support

Enable eMMC 4.41 Support

eMMC AUTO MODE

Disable

SCC eMMC 4.5 DDR50 Support Enabled

Disabled

SCC eMMC 4.5 HS200 Support Enabled

Disabled

eMMC Secure Erase Enabled

Disabled

SCC SD Card Support Enabled

Disabled

SDR25 Support for SDCard Enabled

Disabled

MIPI HIS Support Enabled

Disabled

LPSS Configuration Info only

LPSS DMA #1 Support Enabled

Disabled

LPSS HSUART #1 Support Enabled

Disabled

SCC eMMC support enable/disable.

SCC eMMC 4.5 DDR50 support enable/disable.

SCC eMMC 4.5 HS200 support enable/disable.

Disable/Enable eMMC secure erase. When enabled, all the data on eMMC will be erased.

SCC SD card support enable/disable.

Disable/Enable SDR25 capability in SD Card controller.

MIPI HIS support enable/disable.

LPSS DMA #1 support enable/disable.

LPSS HSUART #1 support enable/disable.

7.3.13.2. Miscellaneous > BIOS Security Configuration

Feature Options Description

BIOS Security Configuration Info only Global SMI Lock Enabled

Disabled

Enable or disable SMI lock.

7.3.13.3. Miscellaneous > Trusted Computing

Feature Options Description

Coniguration Info only

Security Device Support Enabled

Disabled

Current Status Information Info only

Enables or disables BIOS support for security device. OS will not show security device. TCG EFI protocol and INT1A interface will not be available.

7.4. Boot

7.4.1. Boot Configuration

Feature Options Description

Boot Configuration Info only

Setup Prompt Timeout 1 Number of seconds to wait for setup activation key. 65535 (0xFFFF )

means indefinite waiting.

Page 52 nanoX-BT

Feature Options Description

Bootup NumLock State On

Off

Quiet Boot Disabled

Enabled

Fast Boot Disabled

Enabled

WIN8 Support Disabled

Enabled

Boot Option Priorities Info only

Hard Drive BBS Priorities Info only

CSM Parameters Submenu CSM configuration: Enable/Disable, Option ROM execution settings,

Select the keyboard NumLock state.

Enable or disables Quiet Boot option.

Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect on BBS boot options.

If enabled, some of default settings will be configured properly for Windows8.

Affected items: CSM Configuration->Boot option filter CSM Configuration->Video

etc.

7.4.1.1. Boot Configuration > CS M Parameters

Feature Options Description

Compatibility Support Module Configuration

CSM Support Enabled

CSM16 Module Version Info only

GataA20 Active Upon Request

Option ROM Messages Force BIOS

INT19 Trap Response Immediate

Boot option filter UEFI and Legacy

Option ROM execution order Info only

Network Do not launch

Storage Do not launch

Info

Disable

Always

Keep Current

Postponed

Legacy only UEFI only

UEFI only

Legacy only

UEFI only

Legacy only

Enable/Disable CSM Support.

Upon Request – GA20 can be disabled using BIOS services. Always – do not allow disabling of GA20; this option is useful

when any RT code is executed above 1MB.

Set display mode for Option ROM.

BIOS reaction on INT19 trapping by Option ROM: Immediate - execute the trap right away; Postponed – execute

the trap during legacy boot.

This option controls legacy/UEFI ROM priority.

Controls the execution of UEFI and legacy PXE OpROM.

Controls the execution of UEFI and legacy storage OpROM.

Video Do not launch

UEFI only

Legacy only

Other PCI devices UEFI only

Legacy only

Controls the execution of UEFI and legacy video OpROM.

Determines OpROM execution policy for devices other than network, storage or video.

nanoX-BT Page 53

7.5. Security

7.5.1. Password Description

Feature Options Description

Administrator Password Enter password

User Password Enter password

Secure Boot menu Submenu Customizable Secure Boot settings.

7.5.1.1. Security > Secure Boot Menu

Feature Options Description

System Mode Setup

Secure Boot Info only

Secure Boot Disabled

Enabled

Secure Boot Mode Standard

Custom

Secure Boot can be enabled if:

1. System running in User mode with enrolled Platform Key (PK)

2. CSM function is disabled.

Secure Boot mode selector. 'Custom' Mode enables users to change Image Execution policy and manage Secure Boot keys.

7.6. Save & Exit

Feature Options Description

Save Changes and Exit Yes No Exit system setup after saving the changes.

Discard Changes and Exit Yes No Exit system setup without saving any changes.

Save Changes and Reset Yes No Reset the system after saving the changes.

Discard Changes and Reset Yes No Reset system setup without saving any changes.

Save Options Info only

Save Changes Yes No Save Changes done so far to any of the setup options.

Discard Changes Yes No Discard Changes done so far to any of the setup options.

Restore Defaults Yes No Restore/Load Default values for all the setup options.

Save as User Defaults Yes No Save the changes done so far as User Defaults.

Restore User Defaults Yes No Restore the User Defaults to all the setup options.

Page 54 nanoX-BT

8. BIOS Checkpoints, Beep Codes

This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

• Security (SEC) – initial low-level initialization

• Pre-EFI Initialization (PEI) – memory initialization

• Driver Execution Environment (DXE) – main hardware initialization

• Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network,

Shell, …)

Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

Analogous to “bootblock” functionality of legacy BIOS

Analogous to “POST” functionality in legacy BIOS

nanoX-BT Page 55

8.1. Checkpoint Ranges

Status Code Range

0x01 – 0x0B SEC execution

0x0C – 0x0F SEC errors

0x10 – 0x2F PEI execution up to and including memory detection

0x30 – 0x4F PEI execution after memory detection

0x50 – 0x5F PEI errors

0x60 – 0x8F DXE execution up to BDS

0x90 – 0xCF BDS execution

0xD0 – 0xDF DXE errors

0xE0 – 0xE8 S3 Resume (PEI)

0xE9 – 0xEF S3 Resume errors (PEI)

0xF0 – 0xF8 Recovery (PEI)

0xF9 – 0xFF Recovery errors (PEI)

Description

8.2. Standard Checkpoints

8.2.1. SEC Phase

Status Code Description

0x00 Not used

Progress Codes

0x01 Power on. Reset type detection (soft/hard).

0x02 AP initialization before microcode loading

0x03 North Bridge initialization before microcode loading

0x04 South Bridge initialization before microcode loading

0x05 OEM initialization before microcode loading

0x06 Microcode loading

0x07 AP initialization after microcode loading

0x08 North Bridge initialization after microcode loading

0x09 South Bridge initialization after microcode loading

0x0A OEM initialization after microcode loading

0x0B Cache initialization

Page 56 nanoX-BT

SEC Error Codes

0x0C – 0x0D Reserved for future AMI SEC error codes

0x0E Microcode not found

0x0F Microcode not loaded

8.2.2. SEC Beep Codes

None

8.2.3. PEI Phase

Status Code Description

Progress Codes

0x10 PEI Core is started

0x11 Pre-memory CPU initialization is started

0x12 Pre-memory CPU initialization (CPU module specific)

0x13 Pre-memory CPU initialization (CPU module specific)

0x14 Pre-memory CPU initialization (CPU module specific)

0x15 Pre-memory North Bridge initialization is started

0x16 Pre-Memory North Bridge initialization (North Bridge module specific)

0x17 Pre-Memory North Bridge initialization (North Bridge module specific)

0x18 Pre-Memory North Bridge initialization (North Bridge module specific)

0x19 Pre-memory South Bridge initialization is started

0x1A Pre-memory South Bridge initialization (South Bridge module specific)

0x1B Pre-memory South Bridge initialization (South Bridge module specific)

0x1C Pre-memory South Bridge initialization (South Bridge module specific)

0x1D – 0x2A OEM pre-memory initialization codes

0x2B Memory initialization. Serial Presence Detect (SPD) data reading

0x2C Memory initialization. Memory presence detection

0x2D Memory initialization. Programming memory timing information

0x2E Memory initialization. Configuring memory

0x2F Memory initialization (other).

0x30 Reserved for ASL (see ASL Status Codes section below)

0x31 Memory Installed

0x32 CPU post-memory initialization is started

0x33 CPU post-memory initialization. Cache initialization

0x34 CPU post-memory initialization. Application Processor(s) (AP) initialization

nanoX-BT Page 57

Status Code Description

0x35 CPU post-memory initialization. Boot Strap Processor (BSP) selection

0x36 CPU post-memory initialization. System Management Mode (SMM) initialization

0x37 Post-Memory North Bridge initialization is started

0x38 Post-Memory North Bridge initialization (North Bridge module specific)

0x39 Post-Memory North Bridge initialization (North Bridge module specific)

0x3A Post-Memory North Bridge initialization (North Bridge module specific)

0x3B Post-Memory South Bridge initialization is started

0x3C Post-Memory South Bridge initialization (South Bridge module specific)

0x3D Post-Memory South Bridge initialization (South Bridge module specific)

0x3E Post-Memory South Bridge initialization (South Bridge module specific)

0x3F-0x4E OEM post memory initialization codes

0x4F DXE IPL is started

PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed

0x51 Memory initialization error. SPD reading has failed

0x52 Memory initialization error. Invalid memory size or memory modules do not match.

0x53 Memory initialization error. No usable memory detected

0x54 Unspecified memory initialization error.

0x55 Memory not installed

0x56 Invalid CPU type or Speed

0x57 CPU mismatch

0x58 CPU self test failed or possible CPU cache error

0x59 CPU micro-code is not found or micro-code update is failed

0x5A Internal CPU error

0x5B reset PPI is not available

0x5C-0x5F Reserved for future AMI error codes

S3 Resume Progress Codes

0xE0 S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)

0xE1 S3 Boot Script execution

0xE2 Video repost

0xE3 OS S3 wake vector call

0xE4-0xE7 Reserved for future AMI progress codes

S3 Resume Error Codes

0xE8 S3 Resume Failed

0xE9 S3 Resume PPI not Found

Page 58 nanoX-BT

Status Code Description

0xEA S3 Resume Boot Script Error

0xEB S3 OS Wake Error

0xEC-0xEF Reserved for future AMI error codes

Recovery Progress Codes

0xF0 Recovery condition triggered by firmware (Auto recovery)

0xF1 Recovery condition triggered by user (Forced recovery)

0xF2 Recovery process started

0xF3 Recovery firmware image is found

0xF4 Recovery firmware image is loaded

0xF5-0xF7 Reserved for future AMI progress codes

Recovery Error Codes

0xF8 Recovery PPI is not available

0xF9 Recovery capsule is not found

0xFA Invalid recovery capsule

0xFB – 0xFF Reserved for future AMI error codes

8.2.4. PEI Beep Codes

# of Beeps Description

1 Memory not Installed

1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)

2 Recovery started

3 DXEIPL was not found

3 DXE Core Firmware Volume was not found

4 Recovery failed

4 S3 Resume failed

7 Reset PPI is not available

8.2.5. DXE Phase

Status Code Description

0x60 DXE Core is started

0x61 NVRAM initialization

0x62 Installation of the South Bridge Runtime Services

0x63 CPU DXE initialization is started

0x64 CPU DXE initialization (CPU module specific)

nanoX-BT Page 59

Status Code Description

0x65 CPU DXE initialization (CPU module specific)

0x66 CPU DXE initialization (CPU module specific)

0x67 CPU DXE initialization (CPU module specific)

0x68 PCI host bridge initialization

0x69 North Bridge DXE initialization is started

0x6A North Bridge DXE SMM initialization is started

0x6B North Bridge DXE initialization (North Bridge module specific)

0x6C North Bridge DXE initialization (North Bridge module specific)

0x6D North Bridge DXE initialization (North Bridge module specific)

0x6E North Bridge DXE initialization (North Bridge module specific)

0x6F North Bridge DXE initialization (North Bridge module specific)

0x70 South Bridge DXE initialization is started

0x71 South Bridge DXE SMM initialization is started

0x72 South Bridge devices initialization

0x73 South Bridge DXE Initialization (South Bridge module specific)

0x74 South Bridge DXE Initialization (South Bridge module specific)

0x75 South Bridge DXE Initialization (South Bridge module specific)

0x76 South Bridge DXE Initialization (South Bridge module specific)

0x77 South Bridge DXE Initialization (South Bridge module specific)

0x78 ACPI module initialization

0x79 CSM initialization

0x7A – 0x7F Reserved for future AMI DXE codes

0x80 – 0x8F OEM DXE initialization codes

0x90 Boot Device Selection (BDS) phase is started

0x91 Driver connecting is started

0x92 PCI Bus initialization is started

0x93 PCI Bus Hot Plug Controller Initialization

0x94 PCI Bus Enumeration

0x95 PCI Bus Request Resources

0x96 PCI Bus Assign Resources

0x97 Console Output devices connect

0x98 Console input devices connect

0x99 Super IO Initialization

0x9A USB initialization is started

0x9B USB Reset

Page 60 nanoX-BT

Status Code Description

0x9C USB Detect

0x9D USB Enable

0x9E – 0x9F Reserved for future AMI codes

0xA0 IDE initialization is started

0xA1 IDE Reset

0xA2 IDE Detect

0xA3 IDE Enable

0xA4 SCSI initialization is started

0xA5 SCSI Reset

0xA6 SCSI Detect

0xA7 SCSI Enable

0xA8 Setup Verifying Password

0xA9 Start of Setup

0xAA Reserved for ASL (see ASL Status Codes section below)

0xAB Setup Input Wait

0xAC Reserved for ASL (see ASL Status Codes section below)

0xAD Ready To Boot event

0xAE Legacy Boot event

0xAF Exit Boot Services event

0xB0 Runtime Set Virtual Address MAP Begin

0xB1 Runtime Set Virtual Address MAP End

0xB2 Legacy Option ROM Initialization

0xB3 System Reset

0xB4 USB hot plug

0xB5 PCI bus hot plug

0xB6 Clean-up of NVRAM

0xB7 Configuration Reset (reset of NVRAM settings)

0xB8 – 0xBF Reserved for future AMI codes

0xC0 – 0xCF OEM BDS initialization codes

DXE Error Codes

0xD0 CPU initialization error

0xD1 North Bridge initialization error

0xD2 South Bridge initialization error

0xD3 Some of the Architectural Protocols are not available

0xD4 PCI resource allocation error. Out of Resources

nanoX-BT Page 61

Status Code Description

0xD5 No Space for Legacy Option ROM

0xD6 No Console Output Devices are found

0xD7 No Console Input Devices are found

0xD8 Invalid password

0xD9 Error loading Boot Option (LoadImage returned error)

0xDA Boot Option is failed (StartImage returned error)

0xDB Flash update is failed

0xDC Reset protocol is not available

8.2.6. DXE Beep Codes

# of Beeps Description

1 Invalid password

4 Some of the Architectural Protocols are not available

5 No Console Output Devices are found

5 No Console Input Devices are found

6 Flash update is failed

7 Reset protocol is not available

8 Platform PCI resource requirements cannot be met

8.2.7. ACPI/ASL Checkpoint

Status Code Description

0x01 System is entering S1 sleep state

0x02 System is entering S2 sleep state

0x03 System is entering S3 sleep state

0x04 System is entering S4 sleep state

0x05 System is entering S5 sleep state

0x10 System is waking up from the S1 sleep state

0x20 System is waking up from the S2 sleep state

0x30 System is waking up from the S3 sleep state

0x40 System is waking up from the S4 sleep state

0xAC System has transitioned into ACPI mode. Interrupt controller is in PIC mode.

0xAA System has transitioned into ACPI mode. Interrupt controller is in APIC mode.

Page 62 nanoX-BT

8.3. OEM-Reserved Checkpoint Ranges

Status Code Description

0x05 OEM SEC initialization before microcode loading

0x0A OEM SEC initialization after microcode loading

0x1D – 0x2A OEM pre-memory initialization codes

0x3F – 0x4E OEM PEI post memory initialization codes

0x80 – 0x8F OEM DXE initialization codes

0xC0 – 0xCF OEM BDS initialization codes

nanoX-BT Page 63

9. Mechanical Information

9.1. Board-to-Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

Tyco 3-1827253-6 Foxconn QT002206-2131-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.

• This connector can be used with 5 mm through-hole standoffs (SMT type).

Tyco 3-6318491-6 Foxconn QT002206-4141-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.

• This connector can be used with 8 mm through-hole standoffs (SMT type).

Common Specifications

• Current capacity: 0.5A per pin

• Rated voltage: 50 VAC

• Insulation resistance: 100M or greater @ 500 VDC

• Temperature rating: -40°C ~ 85°C

• UL certification (ECBT2.E28476)

• Copper alloy (contacts)

• Housing: thermo-plastic molded compound (L.C.P.)

Page 64 nanoX-BT

9.2. Thermal Solution

9.2.1. Heat Spreaders

The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.

9.2.2. Heat Sinks

A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements.

9.2.3. Installation

Install a heat spreader or heat sink using the following instructions.

Step 1: Place the COM Express module onto the connectors on the carrier board as shown.

Then press down on the module until it is firmly seated on the carrier board.

Step 2: Remove the protective membranes from the thermal pads.

nanoX-BT Page 65

Step 3: Put heatsink on the COM Express module and assemble the heatsink onto the COM Express module.

Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module.

Page 66 nanoX-BT

9.3. Mounting Methods

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

nanoX-BT Page 67

9.4. Standoff Types

The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.

5mm through-hole standoff (SMT type) P/N: 33-72000-0050

8mm through-hole standoff (SMT type) P/N: 33-72000-0080

5mm threaded standoff (DIP type) P/N: 33-72016-0050

8mm threaded standoff (DIP type) P/N: 33-72015-0050

Page 68 nanoX-BT

Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

• Please read these safety instructions carefully.

• Please keep this User‘s Manual for later reference.

• Read the specifications section of this manual for detailed information on the operating environment of this equipment.

• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.

• To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources.  Keep equipment away from high heat or high humidity.  Keep equipment properly ventilated (do not block or cover ventilation openings).  Make sure to use recommended voltage and power source settings.  Always install and operate equipment near an easily accessible electrical socket-outlet.  Secure the power cord (do not place any object on/over the power cord).  Only install/attach and operate equipment on stable surfaces and/or recommended mountings.  If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

nanoX-BT Page 69

Getting Service

ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan

Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com

Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com

ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park,Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com

ADLINK Technology Beijing

Address: Rm. 801, Power Creative E, No. 1, B/D, Shang Di East Rd. Beijing, 100085 China

Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com

ADLINK Technology Shenzhen

Address: 2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S. Shenzhen, 518054 China

Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com

LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com

Page 70 nanoX-BT

ADLINK Technology, Inc. (French Liaison Office)

Address: 6 allée de Londres, Immeuble Ceylan

91940 Les Ulis, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com

ADLINK Technology Japan Corporation

Address: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku Tokyo 101-0045, Japan

Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com

ADLINK Technology, Inc. (Korean Liaison Office)

Address: 802, Mointer B/D, 326 Seocho-daero, Seocho-Gu, Seoul 137-881, Korea

Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com

ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre Singapore 349584

Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com

ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: #50-56, First Floor, Spearhead Towers Margosa Main Road (between 16th/17th Cross), Malleswaram Bangalore - 560 055, India

Tel: +91-80-65605817, +91-80-42246107 Fax: +91-80-23464606 Email: india@adlinktech.com

ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 27 Maskit St., Corex Building PO Box 12777 Herzliya 4673300, Israel

Tel: +972-77-208-0230 Fax: +972-77-208-0230 Email: israel@adlinktech.com

ADLINK Technology, Inc. (UK Liaison Office)

Tel: +44 774 010 59 65 Email: UK@adlinktech.com

nanoX-BT Page 71

ADLINK nanoX-BT User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

nanoX-BT

Revision History

Preface

Table of Contents

1. Introduction

2. Specifications

2.1. Core System

2.2. Expansion Busses

2.3. SEMA Board Controller

2.4. Debug Headers

2.5. Video

2.6. Audio

2.7. LAN

2.8. Multi I/O and Storage

2.9. Power Specifications

2.10. Power Consumption

2.11. Operating Temperatures

2.12. Environmental

2.13. Specification Compliance

2.14. Operating Systems

2.15. Functional Diagram

2.16. Mechanical Dimensions

3. Pinouts and Signal Descriptions

3.1. AB Pin Definitions

3.2. Signal Description Terminology

3.3. AB Signal Description

3.3.1. Audio Signals

3.3.2. LVDS/eDP

3.3.3. DDI0 Channel

3.3.4. Gigabit Ethernet

3.3.5. SATA

3.3.6. PCI Express

3.3.7. Express Card

3.3.8. LPC Bus

3.3.9. USB 1.1/2.0

3.3.10. USB 3.0 Extension

3.3.11. USB Root Segmentation

SPI (BIOS only)

3.3.13. Miscellaneous

3.3.14. SMBus

3.3.15. I2C Bus

3.3.16. General Purpose I/O (GPIO)

3.3.17. Serial Interface Signals

Power and Ground

4. Module interfaces

4.1. Connector, Switch and LED Locations

4.1.1. nanoX-BT and the DB40 Module connected

4.2. 40-pin Multipurpose Connector

4.3. Status LEDs

4.4. XDP Debug Header

5. Smart Embedded Management Agent (SEMA)

5.1. Board Specific SEMA Functions

5.1.1. Voltages

5.1.2. Main Current

5.1.3. BMC Status

5.1.4. Exception Codes

5.1.5. BMC Flags

6. System Resources

6.1. System Memory Map

6.2. I/O Map

6.3. Interrupt Request (IRQ) Lines

6.3.1. PIC Mode

6.3.2. APIC Mode

6.4. PCI Configuration Space Map

6.5. PCI Interrupt Routing Map

6.6. SMBus Address Table

7. BIOS Setup

7.1. Menu Structure

7.2. Main

7.2.1. System Information

7.2.2. Processor Information

7.2.3. VGA Firmware Version

7.2.4. Memory Information

7.2.5. SOC Information

7.2.6. System Management

7.2.6.1. System Management > Board Information