ADLINK nanoX-BT User Manual
nanoX-BT
User’s Manual
Manual Revision: 1.01
Revision Date: September 24, 2014
Part Number: 50-1J053-1010
Revision History
Revision Description Date By
1.00 Initial release 2014-07-24 JC
1.01 Add BIOS Checkpoints, Beep Codes; correct SD signal support; add SEMA CPU temperature
limitation
2014-09-24 JC
Page 2 nanoX-BT
Preface
Copyright 2014 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.
nanoX-BT Page 3
Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1. Introduction......................................................................................................... 8
2. Specifications....................................................................................................... 9
2.1. Core System..............................................................................................................................9
2.2. Expansion Busses......................................................................................................................9
2.3. SEMA Board Controller.............................................................................................................9
2.4. Debug Headers .........................................................................................................................9
2.5. Video...................................................................................................................................... 10
2.6. Audio...................................................................................................................................... 10
2.7. LAN ........................................................................................................................................ 10
2.8. Multi I/O and Storage ............................................................................................................ 10
2.9. Power Specifications ............................................................................................................. 10
2.10. Power Consumption.............................................................................................................. 11
2.11. Operating Temperatures ....................................................................................................... 11
2.12. Environmental ....................................................................................................................... 11
2.13. Specification Compliance ...................................................................................................... 11
2.14. Operating Systems................................................................................................................. 11
2.15. Functional Diagram................................................................................................................ 12
2.16. Mechanical Dimensions......................................................................................................... 13
3. Pinouts and Signal Descriptions......................................................................
3.1. AB Pin Definitions .................................................................................................................. 14
3.2. Signal Description Terminology............................................................................................. 17
3.3. AB Signal Description............................................................................................................. 18
14
3.3.1. Audio Signals ...............................................................................................................................18
3.3.2. LVDS/eDP ....................................................................................................................................18
3.3.3. DDI0 Channel...............................................................................................................................19
3.3.4. Gigabit Ethernet ..........................................................................................................................19
3.3.5. SATA ............................................................................................................................................20
3.3.6. PCI Express ..................................................................................................................................20
3.3.7. Express Card................................................................................................................................20
3.3.8. LPC Bus ........................................................................................................................................21
3.3.9. USB 1.1/2.0..................................................................................................................................21
3.3.10. USB 3.0 Extension .......................................................................................................................22
Page 4 nanoX-BT
3.3.11. USB Root Segmentation ..............................................................................................................22
3.3.12.
3.3.13. Miscellaneous..............................................................................................................................23
3.3.14. SMBus..........................................................................................................................................23
3.3.15. I2C Bus.........................................................................................................................................23
3.3.16. General Purpose I/O (GPIO) ........................................................................................................23
3.3.17. Serial Interface Signals ................................................................................................................24
3.3.18. Power And System Management................................................................................................24
3.3.19.
4. Module interfaces .............................................................................................
SPI (BIOS only)
Power and Ground
.............................................................................................................................22
......................................................................................................................25
26
4.1. Connector, Switch and LED Locations ................................................................................... 26
4.1.1. nanoX-BT and the DB40 Module connected...............................................................................26
4.2. 40-pin Multipurpose Connector ............................................................................................ 27
4.3. Status LEDs ............................................................................................................................ 28
4.4. XDP Debug Header ................................................................................................................ 29
5. Smart Embedded Management Agent (SEMA) ............................................. 30
5.1. Board Specific SEMA Functions ............................................................................................. 31
5.1.1. Voltages.......................................................................................................................................31
5.1.2. Main Current...............................................................................................................................31
5.1.3. BMC Status..................................................................................................................................31
5.1.4. Exception Codes ..........................................................................................................................32
5.1.5. BMC Flags....................................................................................................................................32
6. System Resources..............................................................................................
6.1. System Memory Map ............................................................................................................ 33
6.2. I/O Map.................................................................................................................................. 33
6.3. Interrupt Request (IRQ) Lines................................................................................................ 34
6.3.1. PIC Mode.....................................................................................................................................34
6.3.2. APIC Mode...................................................................................................................................34
6.4. PCI Configuration Space Map ................................................................................................ 36
6.5. PCI Interrupt Routing Map .................................................................................................... 37
6.6. SMBus Address Table ............................................................................................................ 37
33
7. BIOS Setup .........................................................................................................
38
7.1. Menu Structure ..................................................................................................................... 38
7.2. Main....................................................................................................................................... 39
7.2.1. System Information.....................................................................................................................39
7.2.2. Processor Information.................................................................................................................39
nanoX-BT Page 5
7.2.3. VGA Firmware Version ................................................................................................................39
7.2.4. Memory Information...................................................................................................................39
7.2.5. SOC Information..........................................................................................................................39
7.2.6. System Management ..................................................................................................................40
7.2.7. System Date and Time.................................................................................................................42
7.3. Advanced ............................................................................................................................... 43
7.3.1. CPU..............................................................................................................................................43
7.3.2. Memory.......................................................................................................................................44
7.3.3. Graphics ......................................................................................................................................44
7.3.4. SATA ............................................................................................................................................45
7.3.5. USB ..............................................................................................................................................45
7.3.6. Network.......................................................................................................................................46
7.3.7. PCI and PCIe ................................................................................................................................46
7.3.8. Super IO.......................................................................................................................................48
7.3.9. ACPI and Power Management ....................................................................................................49
7.3.10. Sound ..........................................................................................................................................49
7.3.11. Serial Port Console ......................................................................................................................50
7.3.12. Thermal .......................................................................................................................................51
7.3.13. Miscellaneous..............................................................................................................................51
7.4. Boot ....................................................................................................................................... 52
7.4.1. Boot Configuration......................................................................................................................52
7.5. Security.................................................................................................................................. 54
7.5.1. Password Description..................................................................................................................54
7.6. Save & Exit ............................................................................................................................. 54
8. BIOS Checkpoints, Beep Codes........................................................................
8.1. Checkpoint Ranges ................................................................................................................ 56
8.2. Standard Checkpoints............................................................................................................ 56
8.2.1. SEC Phase ....................................................................................................................................56
8.2.2. SEC Beep Codes...........................................................................................................................57
55
8.2.3. PEI Phase .....................................................................................................................................57
8.2.4. PEI Beep Codes............................................................................................................................59
8.2.5. DXE Phase....................................................................................................................................59
8.2.6. DXE Beep Codes ..........................................................................................................................62
8.2.7. ACPI/ASL Checkpoint...................................................................................................................62
8.3. OEM-Reserved Checkpoint Ranges ....................................................................................... 63
9. Mechanical Information ................................................................................... 64
9.1. Board-to-Board Connectors .................................................................................................. 64
9.2. Thermal Solution ................................................................................................................... 65
Page 6 nanoX-BT
9.2.1. Heat Spreaders............................................................................................................................65
9.2.2. Heat Sinks....................................................................................................................................65
9.2.3. Installation...................................................................................................................................65
9.3. Mounting Methods................................................................................................................ 67
9.4. Standoff Types....................................................................................................................... 68
Safety Instructions ...................................................................................................... 69
Getting Service ............................................................................................................ 70
nanoX-BT Page 7
1. Introduction
The nanoX-BT is a COM Express® COM.0 R2.1 Type 10 module supporting Intel® Atom™ processor E3800 Series and Intel® Celeron®
processor system-on-chip (SoC). The nanoX-BT is specifically designed for customers who need high-level processing and graphics
performance with low power consumption in a long product life solution.
The nanoX-BT features Intel® Atom™ processor E3800 and Intel® Celeron® processor supporting non-ECC type DDR3L single-channel
memory at 1066/1333 MHz to provide excellent overall performance. Integrated Intel® Gen7 HD Graphics includes features such as
OpenGL 3.1, DirectX 11, OpenCL 1.1 and support for H.264, MPEG2, VC1, VP8 hardware decode. Graphics outputs include DDI ports
supporting HDMI/DVI/DisplayPort and single-channel 18/24-bit LVDS (eDP is optional). The nanoX-BT is specifically designed for customers
with high-performance processing graphics requirements who want to outsource the custom core logic of their systems for reduced
development time.
The nanoX-BT has soldered type non-ECC DDR3L memory up to 2 GB (4GB TBD). In addition, onboard eMMC memory (8GB/16GB/32GB)
and SD signals are optionally supported.
The nanoX-BT features a single onboard Gigabit Ethernet port, USB 3.0 ports and USB 2.0 ports, and SATA 3 Gb/s ports. Support is
provided for SMBus and I
CMOS backup, hardware monitor, and watchdog timer.
2
C. The module is equipped with SPI AMI EFI BIOS, supporting embedded features such as remote console,
Page 8 nanoX-BT
2. Specifications
2.1. Core System
¾ CPU: Single, dual or quad-core Intel® Atom™ or Celeron® Processor
• Atom™ E3845 1.91 GHz 542/792 (Turbo) 10W (4C/1333)
• Atom™ E3827 1.75 GHz 542/792 (Turbo) 8W (2C/1333)
• Atom™ E3826 1.46 GHz 533/667 (Turbo) 7W (2C/1066)
• Atom™ E3825 1.33 GHz 533 (No Turbo) 6W (2C/1066)
• Atom™ E3815 1.46 GHz 400 (No Turbo) 5W (1C/1066)
• Celeron® N2930 1.83/2.16 (Burst) GHz, 313/854 (Turbo) 7.5W (4C/1333)
• Celeron® J1900 2.0/2.42 (Burst) GHz, 688/854 (Turbo) 10W (4C/1333)
Supports: Single, dual or quad Out-of-Order Execution (OOE) processor cores, Intel® VT-x, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture,
IA 32-bit, PCLMULQDQ Instruction, DRNG, Intel® Thermal Monitor (TM1 & TM2)
Note: Availability of features may vary between processor SKUs.
¾ Cache: Primary 32 kB, 8-way L1 instruction cache and 24 kB, 6-way L1 write-back data cache
¾ Memory: Single channel non-ECC 1333/1066 MHz soldered DDR3L memory up to 2GB (4GB TBD)
Note: Availability of features may vary between processor SKUs.
¾ Embedded BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS
2.2. Expansion Busses
¾ 3 PCI Express x1 GEN2 (AB): lanes 0/1/2 (build option: PCIe x4, lose GbE)
¾ LPC bus, SMBus (system) , I
2
C (user)
2.3. SEMA Board Controller
¾ Type: ADLINK Smart Embedded Management Agent (SEMA)
¾ Supports:
• Voltage/Current monitoring
• Power sequence debug support
• AT/ATX mode control
• Logistics and Forensic information
• Flat Panel Control
• General Purpose I
• Failsafe BIOS (dual BIOS )
• Watchdog Timer and Fan Control
2
C
2.4. Debug Headers
¾ 40-pin multipurpose flat cable connector, used in combination with DB-40 debug module providing BIOS POST code LED, BMC
access, SPI BIOS flashing, Power Testpoints, Debug LEDs
¾ Optional 60-pin XDP header for ICE debug of SOC on breakount PCB extension
nanoX-BT Page 9
2.5. Video
¾ GPU Feature Support: 7th generation graphics Intel core architecture with four execution units supporting two independent displays
• 3D graphics hardware acceleration
• Support for DirectX11, OCL 1.1, OGL ES Halt/2.0/1.1, OGL 3.2
• Video decode hardware acceleration including support for H.264, MPEG2, VC-1, WMV and VP8 formats
• Video encode hardware acceleration including support for H.264, MPEG2 and MVC formatsPlayback of Blu-ray disc S3D content using HDMI
(1.4a spec compliant with 3D)
Note: Availability of features may vary between operating systems
¾ Display Interface support
• LVDS
Single channel 18/24-bit LVDS from eDP (one lane)
Build option upon request to support eDP output
• DDI0
Supports DisplayPort / HDMI / DVI / eDP
2.6. Audio
¾ Integrated: Intel® HD Audio integrated in SOC
¾ Audio Codec: located on evaluation carrier miniBase-10R (ALC262 standard supported)
2.7. LAN
¾ Type: Intel® i210 (MAC/PHY) Ethernet controller
¾ Interface: 10/100/1000 GbE connection
2.8. Multi I/O and Storage
¾ Integrated in SOC
¾ USB:
• 1x USB. 1.1/2.0/3.0 (USB 0)
• 3x USB. 1.1/2.0 (USB 1,2,3)
• 1x USB. 1.1/2.0 Client (USB 7)
¾ SATA: 2x ports SATA 3Gb/s (SATA0, SATA1)
¾ eMMC: optional soldered on module bootable eMMC flash storage (8GB/16GB/32GB)
¾ Serial: 2x UART ports COM 0/1 (COM 1 supports console redirection)
¾ SD: optional SD signal support mulitplexed over GPIO pins
¾ GPIO: 4x GPO and 4x GPI with interrupt
2.9. Power Specifications
¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA)
¾ Standard Voltage Input: ATX = 12V±5%, 5Vsb ±5% or AT = 12V ±5%
¾ Wide Voltage Input: ATX = 5~14 V, 5Vsb ±5% or AT = 5 ~14V
¾ Power Management: ACPI 4.0 compliant, Smart Battery support
¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5)
¾ ECO mode: supports deep S5 for 5Vsb power saving
Page 10 nanoX-BT
2.10. Power Consumption
TBD
2.11. Operating Temperatures
¾ Standard Operating Temperature: 0°C to 60°C (wide voltage input)
¾ Extreme Rugged Operating Temperature (optional)*: -40°C to 85°C (standard voltage input)
*Intel® Atom™ E3800 Series processors only
2.12. Environmental
¾ Humidity: 5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
¾ Halt: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.13. Specification Compliance
¾ PICMG COM.0: Rev 2.1 Type 10, mini size 84 x 55
2.14. Operating Systems
¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit
¾ Extended Support (BSP): WES7/8, WEC7, Linux, VxWorks
nanoX-BT Page 11
2.15. Functional Diagram
eDP (optional)
AB
LVDS
eDP to LVDS
RTL2132
DDI2
4 lanes
1x USB 1.1/2.0/3.0 (port 0)
3x USB 1.1/2.0 (port 1~3)
1x USB 1.1/2.0 client (port 7)
3 PCIe x1 Gen2
(port 0~2)
GbE
i210
2x SATA 3Gb/s
(port 0/1)
HD Audio
DDI1
eDP 1 lane
alternative
PCIe x1 Gen2
(port 3)
PCIe x1
route
Intel® Atom™
E3845
E3827
E3826
E3825
E3815
Intel® Celeron®
N2930
J1900
“Baytrail”
Soldered
1~2 GB DDR3L
non ECC (only)
On break-out board
XDP
60-pin
eMMC
8GB/16GB/
32GB
2 UART (Tx/Rx)
LPC Bus
SD/MMC port 0 (optional)
4x GP0, 4x GPI
SMBus
GP I2C
DDC I2C
GPIO
PCA9535
SPI_CS#
SPI
SEMA
BMC
SPI0
BIOS
LM73
to CPU
Page 12 nanoX-BT
T
2.16. Mechanical Dimensions
connector on bottom side
op View
Side View
All tolerances ± 0.05 mm
Other tolerances ± 0.2 mm
nanoX-BT Page 13
3. Pinouts and Signal Descriptions
3.1. AB Pin Definitions
The nanoX-BT is a Type 10 module supporting USB3.0 and DDI channel on the AB connector
In below table all standard pins of the COM Express specification are described, also those not supported on the nanoX-BT !
Note: Signals not supported on the nanoX-BT module are crossed out
Type 10 COM.0 Rev. 2.1
Row A Row B
Pin Name Pin Name
1 GND(FIXED) 1 GND(FIXED)
2 GBE0_MDI3- 2 GBE0_ACT#
3 GBE0_MDI3+ 3 LPC_FRAME#
4 GBE0_LINK100# 4 LPC_AD0
5 GBE0_LINK1000# 5 LPC_AD1
6 GBE0_MDI2- 6 LPC_AD2
7 GBE0_MDI2+ 7 LPC_AD3
8 GBE0_LINK# 8 LPC_DRQ0#
9 GBE0_MDI1- 9 LPC_DRQ1#
10 GBE0_MDI1+ 10 LPC_CLK
11 GND(FIXED) 11 GND(FIXED)
12 GBE0_MDI0- 12 PWRBTN#
13 GBE0_MDI0+ 13 SMB_CK
14 GBE0_CTREF 14 SMB_DAT
15 SUS_S3# 15 SMB_ALERT#
16 SATA0_TX+ 16 SATA1_TX+
17 SATA0_TX- 17 SATA1_TX-
18 SUS_S4# 18 SUS_STAT#
19 SATA0_RX+ 19 SATA1_RX+
20 SATA0_RX- 20 SATA1_RX-
21 GND(FIXED) 21 GND(FIXED)
22 USB_SSRX0- 22 USB_SSTX0-
23 USB_SSRX0+ 23 USB_SSTX0+
24 SUS_S5# 24 PWR_OK
25 USB_SSRX1- 25 USB_SSTX1-
26 USB_SSRX1+ 26 USB_SSTX1+
27 BATLOW# 27 WDT
28 (S)ATA_ACT# 28 AC/HDA_SDIN2
29 AC/HDA_SYNC 29 AC/HDA_SDIN1
30 AC/HDA_RST# 30 AC/HDA_SDIN0
31 GND(FIXED) 31 GND(FIXED)
32 AC/HDA_BITCLK 32 SPKR
33 AC/HDA_SDOUT 33 I2C_CK
34 BIOS_DIS0# 34 I2C_DAT
Page 14 nanoX-BT
Row A Row B
Pin Name Pin Name
35 THRMTRIP# 35 THRM#
36 USB6- 36 USB7-
37 USB6+ 37 USB7+
38 USB_6_7_OC# 38 USB_4_5_OC#
39 USB4- 39 USB5-
40 USB4+ 40 USB5+
41 GND(FIXED) 41 GND(FIXED)
42 USB2- 42 USB3-
43 USB2+ 43 USB3+
44 USB_2_3_OC# 44 USB_0_1_OC#
45 USB0- 45 USB1-
46 USB0+ 46 USB1+
47 VCC_RTC 47 EXCD1_PERST#
48 EXCD0_PERST# 48 EXCD1_CPPE#
49 EXCD0_CPPE# 49 SYS_RESET#
50 LPC_SERIRQ 50 CB_RESET#
51 GND(FIXED) 51 GND(FIXED)
52 RSVD 52 RSVD
53 RSVD 53 RSVD
54 GPI0 54 GPO1
55 RSVD 55 RSVD
56 RSVD 56 RSVD
57 GND 57 GPO2
58 PCIE_TX3+ * 58 PCIE_RX3+ *
59 PCIE_TX3- * 59 PCIE_RX3- *
60 GND(FIXED) 60 GND(FIXED)
61 PCIE_TX2+ 61 PCIE_RX2+
62 PCIE_TX2- 62 PCIE_RX2-
63 GPI1 63 GPO3
64 PCIE_TX1+ 64 PCIE_RX1+
65 PCIE_TX1- 65 PCIE_RX1-
66 GND 66 WAKE0#
67 GPI2 67 WAKE1#
68 PCIE_TX0+ 68 PCIE_RX0+
69 PCIE_TX0- 69 PCIE_RX0-
70 GND(FIXED) 70 GND(FIXED)
71 LVDS_A0+ / eDP_TX2+ 71 DDI0_PAIR0+
72 LVDS_A0- / eDP_TX2- 72 DDI0_PAIR0-
73 LVDS_A1+ / eDP_TX1+ 73 DDI0_PAIR1+
74 LVDS_A1- / eDP_TX1- 74 DDI0_PAIR1-
75 LVDS_A2+ / eDP_TX0+ 75 DDI0_PAIR2+
76 LVDS_A2- / eDP_TX0- 76 DDI0_PAIR2-
77 LVDS_/eDP_VDD_EN 77 DDI0_PAIR4+
78 LVDS_A3+ 78 DDI0_PAIR4-
79 LVDS_A3- 79 LVDS_/eDP_BKLT_EN
nanoX-BT Page 15
Row A Row B
Pin Name Pin Name
80 GND(FIXED) 80 GND(FIXED)
81 LVDS_A_CK+ / eDP_TX3+ 81 DDI0_PAIR3+
82 LVDS_A_CK- / eDP_TX3- 82 DDI0_PAIR3-
83 LVDS_I2C_CK / eDP_AUX+ 83 LVDS_/eDP_BKLT_CTRL
84 LVDS_I2C_DAT / eDP_AUX- 84 VCC_5V_SBY
85 GPI3 85 VCC_5V_SBY
86 RSVD 86 VCC_5V_SBY
87 eDP_HPD 87 VCC_5V_SBY
88 PCIE_CLK_REF+ 88 BIOS_DIS1#
89 PCIE_CLK_REF- 89 DD0_HPD
90 GND(FIXED) 90 GND(FIXED)
91 SPI_POWER 91 DDI0_PAIR5+
92 SPI_MISO 92 DDI0_PAIR5-
93 GPO0 93 DDI0_PAIR6+
94 SPI_CLK 94 DDI0_PAIR6-
95 SPI_MOSI 95 DDI0_DDC_AUX_SEL
96 TPM_PP 96 USB_HOST_PRSNT
97 TYPE10# 97 SPI_CS#
98 SER0_TX 98 DDI0_CTRLCLK_AUX+
99 SER0_RX 99 DDI0_CTRLDATA_AUX-
100 GND(FIXED) 100 GND(FIXED)
101 SER1_TX / CAN_TX 101 FAN_PWMOUT
102 SER1_RX / CAN_RX 102 FAN_TACHIN
103 LID# 103 SLEEP#
104 VCC_12V 104 VCC_12V
105 VCC_12V 105 VCC_12V
106 VCC_12V 106 VCC_12V
107 VCC_12V 107 VCC_12V
108 VCC_12V 108 VCC_12V
109 VCC_12V 109 VCC_12V
110 GND(FIXED) 110 GND(FIXED)
Notes:
- LID# and SLEEP# signals are not natively supported on the SOC, they instead connect to GPIO pins simulating their behaviour.
- eDP can be supported by BOM option with loss of LVDS.
- PCIe (port 3) can be supported by BOM option (lose GbE)
Page 16 nanoX-BT
3.2. Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module
nanoX-BT Page 17
3.3. AB Signal Description
3.3.1. Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
AC_SYNC /
HDA_SYNC
AC_BITCLK /
HDA_BITCLK
AC _SDOUT /
HDA_SDOUT
AC _SDIN[2:0]
HDA_SDIN[2:0]
A30 Reset output to CODEC, active low. O 3.3VSB
A29 Sample-synchronization signal to the CODEC(s). O 3.3V
A32 Serial data clock generated by the external CODEC(s). I/O 3.3V
A33 Serial TDM data output to the CODEC. O 3.3V
B28- B30 Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB AC_SDIN0: supported
AC_SDIN1: supported
AC_SDIN2: not supported
3.3.2. LVDS/eDP
Signal Pin # Description I/O PU/PD Comment
LVDS_A0+ / eDP_TX2+
LVDS_A0- / eDP_TX2-
LVDS_A1+ / eDP_TX1+
LVDS_A1- / eDP_TX1-
LVDS_A2+ / eDP_TX0+
LVDS_A2- / eDP_TX0+
LVDS_A3+
LVDS_A3-
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential
pairs
O LVDS
eDP
by build option
LVDS_A_CK+ / eDP_TX3+
LVDS_A_CK- / eDP_TX3-
LVDS_VDD_EN / eDP_VDD_EN A77 LVDS panel power enable O 3.3V
LVDS_BKLT_EN / eDP_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL / eDP_BKLT_CTRL B83 LVDS panel backlight brightness
LVDS_I2C_CK / eDP_AUX+ A83 DDC lines used for flat panel
LVDS_I2C_DAT / eDP_AUX- A84 DDC lines used for flat panel
RSVD / eDP_HPD A87 Digital Display Interface Hot-Plug
A81
A82
LVDS Channel A differential
clock
control
detection and control.
detection and control.
Detect
O LVDS
O 3.3V PD 100k Realtek eDP to
O 3.3V PU 2k2
I/O 3.3V PU 2k2
I 3.3V
LVDS
requirement
3.3V
3.3V
Page 18 nanoX-BT
3.3.3. DDI0 Channel
Signal Pin # Description I/O PU/PD Comment
DDI0_PAIR0+
DDI0_PAIR0DDI0_PAIR1+
DDI0_PAIR1DDI0_PAIR2+
DDI0_PAIR2DDI0_PAIR3+
DDI0_PAIR3DDI0_PAIR4+
DDI0_PAIR4DDI0_PAIR5+
DDI0_PAIR5DDI0_PAIR6+
DDI0_PAIR6-
DDI0_HPD B89 Digital Display Interface Hot-Plug Detect I 3.3V PD
DDI0_DDC_AUX_SEL B95 Selects the function of DDI1_CTRLCLK_AUX+ and
B71
Digital Display Interface differential pairs O PCIE Pair 4 to Pair 6
B72
B73
B74
B75
B76
B81
B82
B77
B78
B91
B92
B93
B94
IF DDI0_DDC_AUX_SEL is floating I/O PCIe DP AUX+ DDI0_CTRLCLK_AUX+ B98
IF DDI0_DDC_AUX_SEL pulled high I/O OD 3.3V HMDI0_CTRLC
IF DDI0_DDC_AUX_SEL is floating I/O PCIe DP AUX+ DDI0_CTRLCLK_AUX- B99
IF DDI0_DDC_AUX_SEL pulled high I/O OD 3.3V HMDI0_
I/O OD 3.3V PD 1M
DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down
to logic ground on the Module. If this input is floating the AUX
pair is used for the DP AUX+/- signals. If pulled-high the AUX
pair contains the CRTLCLK and CTRLDATA signals.
are not
supported
100k
LK
CTRLDAT
3.3.4. Gigabit Ethernet
Gigabit Ethernet Pin # Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3-
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. OD
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. OD
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. OD
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. OD
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics
A13
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0,
A11
1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some
A10
pairs are unused in some modes according to the following:
A9
1000 100 10
A7
MDI[0]+/- B1_DA+/- TX+/- TX+/-
A6
MDI[1]+/- B1_DB+/- RX+/- RX+/-
A3
MDI[2]+/- B1_DC+/-
A2
MDI[3]+/- B1_DD+/-
center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The reference
voltage output shall be current limited on the Module. In the case in which
the reference is shorted to ground, the current shall be 250 mA or less.
I/O
Analog
3.3VSB
3.3VSB
3.3VSB
3.3VSB
GND
min
3.3V
max
Twisted pair
signals for
external
transformer.
PD 10k
3.3VSB
nanoX-BT Page 19
3.3.5. SATA
Signal Pin # Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V
A16
A17
A19
A20
B16
B17
B19
B20
Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module
Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module
Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module
Serial ATA channel 1, Receive Input differential pair. I SATA AC coupled on Module
3.3.6. PCI Express
Signal Pin # Description I/O PU/PD Comment
PCIE_TX0+ PCIE_TX0- A68
A69
PCIE_RX0+ PCIE_RX0- B68
B69
PCIE_TX1+ PCIE_TX1- A64
A65
PCI Express channel 0, Transmit
Output differential pair.
PCI Express channel 0, Receive Input
differential pair.
PCI Express channel 1, Transmit
Output differential pair.
O PCIE AC coupled on module
I PCIE AC coupled off module
O PCIE AC coupled on module
PCIE_RX1+ PCIE_RX1- B64
B65
PCIE_TX2+ PCIE_TX2- A61
A62
PCIE_RX2+ PCIE_RX2- B61
B62
PCIE_TX3+ PCIE_TX3- A58
A59
PCIE_RX3+ PCIE_RX3- B58
B59
PCIE_CLK_REF+ PCIE_CLK_REF- A88
A89
PCI Express channel 1, Receive Input
differential pair.
PCI Express channel 2, Transmit
Output differential pair.
PCI Express channel 2, Receive Input
differential pair.
PCI Express channel 3, Transmit
Output differential pair.
PCI Express channel 3, Receive Input
differential pair.
PCI Express Reference Clock output
for all PCI Express and PCI Express
Graphics Lanes.
I PCIE AC coupled off module
O PCIE AC coupled on module
I PCIE AC coupled off module
O PCIE used by GbE
I PCIE used by GbE
O PCIE
3.3.7. Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE# EXCD1_CPPE# A49
B48
EXCD0_PERST# EXCD1_PERST# A48
B47
PCI ExpressCard: PCI Express
capable card request
PCI ExpressCard: reset O 3.3V
I 3.3V PU 10k 3.3V
Page 20 nanoX-BT
3.3.8. LPC Bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data
bus
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
B8
B9
LPC serial DMA request I 3.3V
I/O 3.3V
Atom clock 33 MHz
Celeron clock 25 MHz
3.3.9. USB 1.1/2.0
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
A46
A45
B46
B45
A43
A42
B43
B42
USB differential data pairs for Port 0 I/O
3.3VSB
USB differential data pairs for Port 1 I/O
3.3VSB
USB differential data pairs for Port 2 I/O
3.3VSB
USB differential data pairs for Port 3 I/O
3.3VSB
USB 1.1/ 2.0
compliant
USB 1.1/ 2.0
compliant
USB 1.1/ 2.0
compliant
USB 1.1/ 2.0
compliant
USB4+
USB4-
USB5+
USB5-
USB6+
USB6-
USB7+
USB7-
USB_HOST_PRSNT B96 Module USB client may detect the presence of a USB host. A high value
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be
A40
A39
B40
B39
A37
A36
B37
B37
USB differential data pairs for Port 4 I/O
USB differential data pairs for Port 5 I/O
USB differential data pairs for Port 6 I/O
USB differential data pairs for Port 7 I/O
indicates that a host is present.
present on the module. An open drain driver from a USB current monitor on
the carrier board may drive this line low.
present on the module. An open drain driver from a USB current monitor on
the carrier board may drive this line low. .
present on the module. An open drain driver from a USB current monitor on
the carrier board may drive this line low.
present on the module. An open drain driver from a USB current monitor on
the carrier board may drive this line low.
3.3VSB
3.3VSB
3.3VSB
3.3VSB
I
3.3VSB
I
3.3VSB
I
3.3VSB
I
3.3VSB
I
3.3VSB
Not supported
Client only
PU 10k
3.3VSB
PU 10k
3.3VSB
PU 10k
3.3VSB
PU 10k
3.3VSB
Not supported
Not supported
Do not pull high
on carrier
Do not pull high
on carrier
Do not pull high
on carrier
Do not pull high
on carrier
nanoX-BT Page 21
3.3.10. USB 3.0 Extension
Signal Pin Description I/O PU/PD Comment
USB_SSRX0USB_SSRX0+
USB_SSTX0USB_SSTX0+
USB_SSRX1USB_SSRX1+
USB_SSTX1USB_SSTX1+
A22
Additional Receive signal differential pairs for the SuperSpeed
A23
USB data path on USB0
B22
Additional Transmit signal differential pairs for the SuperSpeed
B23
USB data path on USB0
A25
Additional Receive signal differential pairs for the SuperSpeed
A26
USB data path on USB1
B25
Additional Transmit signal differential pairs for the SuperSpeed
B26
USB data path on USB1
3.3.11. USB Root Segmentation
P1 P2 P3 P4
Port 0
(1/2.0)
EHCI Controller
Port 1
(1/2.0)
Port 2
(1/2.0)
Port 3
(1/2.0)
P1-P4
XHCI Controller
P4
P5
I PCIE
O PCIE AC coupled on Module
I PCIE Not supported
O PCIE Not supported
SSP
1
ULPI
Port 7
Client
Port 0
(3.0)
USB0- / A45
USB0+ / A46
3.3.12.
USB1- / B45
USB1+ / B46
USB2- / A42
USB2+ / A43
SPI (BIOS only)
USB3- / B42
USB3+ / B43
USB7- / B36
USB7+ / B37
USB_SSTX0-/B22
USB_SSRX0-/A22
USB_SSTX0+/B23
USB_SSRX0+/A23
Signal Pin # Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Only supports CS0
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally
O P 3.3VSB
3.3V.
The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on the Carrier
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K
3.3V
Carrier shall pull to
GND or leave not
connected
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K
3.3V
Carrier shall pull to
GND or leave not
connected
Page 22 nanoX-BT
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