ADLINK Express-IB User Manual
Express-IB
User’s Manual
Manual Revision: 2.03
Revision Date: December 3, 2014
Part Number: 50-1J044-1030
Revision History
Revision Description Date By
2.00 Initial release 2013-08-30 JC
2.01 Correct CPU support spec (Intel® Core™ i7-3615QE); correct GBE0_MDI0- pin description 2013-10-25 JC
2.02 Add Celeron® SKUs; update PCIe expansion specifications 2014-07-04 JC
2.03 Add BIOS beep codes; remove Industrial Temp. SKU 2014-12-03 JC
Page 2 Express-IB
Preface
Copyright 2013-14 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.
Express-IB Page 3
Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1. Introduction......................................................................................................... 7
2. Specifications....................................................................................................... 8
2.1. Core System ..............................................................................................................................8
2.2. Expansion Busses......................................................................................................................8
2.3. Video.........................................................................................................................................8
2.4. Audio.........................................................................................................................................9
2.5. LAN ...........................................................................................................................................9
2.6. Multi I/O and Storage ...............................................................................................................9
2.7. Serial I/O on Module ................................................................................................................9
2.8. Super I/O (on Carrier using LPC -bus) .......................................................................................9
2.9. GPIO ..........................................................................................................................................9
2.10. Board Controller .......................................................................................................................9
2.11. TPM (Trusted Platform Module) ........................................................................................... 10
2.12. Fan Control ............................................................................................................................ 10
2.13. Debug..................................................................................................................................... 10
2.14. Power Specifications ............................................................................................................. 10
2.15. Mechanical and Environmental............................................................................................. 10
2.16. Specification Compliance ...................................................................................................... 10
2.17. Functional Diagram................................................................................................................ 11
2.18. Mechanical Drawing .............................................................................................................. 12
3. Pinouts and Signal Descriptions......................................................................
3.1. AB / CD Pin Definitions .......................................................................................................... 13
13
3.2. Signal Description Terminology............................................................................................. 16
3.3. AB Signal Descriptions ........................................................................................................... 17
3.3.1. Audio Signals....................................................................................................................................17
3.3.2. Analog VGA ......................................................................................................................................17
3.3.3. LVDS .................................................................................................................................................17
3.3.4. Gigabit Ethernet...............................................................................................................................18
3.3.5. Serial ATA .........................................................................................................................................19
3.3.6. PCI Express .......................................................................................................................................20
3.3.7. Express Card.....................................................................................................................................20
3.3.8. LPC bus.............................................................................................................................................21
Page 4 Express-IB
3.3.9. USB...................................................................................................................................................21
3.3.10. SPI (BIOS only).............................................................................................................................22
3.3.11. Miscellaneous..............................................................................................................................22
3.3.12. SMBus..........................................................................................................................................22
3.3.13. I2C Bus.........................................................................................................................................23
3.3.14. General Purpose I/O (GPIO) ........................................................................................................23
3.3.15. Power And System Management................................................................................................23
3.3.16. Power and Ground ......................................................................................................................24
3.4. CD Signal Descriptions ........................................................................................................... 25
3.4.1. USB 3.0 extension ............................................................................................................................25
3.4.2. PCI Express x1 ..................................................................................................................................25
3.4.3. DDI Channels....................................................................................................................................26
3.4.4. DDI to DP/HDMI/SDVO Mapping.....................................................................................................28
3.4.5. PCI Express Graphics x16 (PEG)........................................................................................................29
3.4.6. Module Type Definition ...................................................................................................................30
3.4.7. Power and Ground...........................................................................................................................30
4. Module Configuration ...................................................................................... 31
4.1. PCI Express Configuration Switch (SW1) ............................................................................... 31
4.2. PCIe x16-to-two-x8 Adapter Card.......................................................................................... 31
5. Embedded Functions ........................................................................................ 32
5.1. Watchdog Timer .................................................................................................................... 32
5.1.1. AIDI Demo Program - Watchdog Tab...............................................................................................32
5.2. GPIO ....................................................................................................................................... 33
5.2.1. AIDI Demo Program - GPIO Tab .......................................................................................................33
5.3. Hardware Monitoring ............................................................................................................ 34
5.3.1. AIDI Demo Program - HW Monitor Tab ...........................................................................................34
6. System Resources..............................................................................................
6.1. System Memory Map ............................................................................................................ 35
35
6.2. Direct Memory Access Channels ........................................................................................... 35
6.3. I/O Map........................................................................................................................ .......... 36
6.4. Interrupt Request (IRQ) Lines................................................................................................ 38
6.5. PCI Configuration Space Map ................................................................................................ 39
6.6. PCI Interrupt Routing Map .................................................................................................... 40
6.7. SMBus Address Table ............................................................................................................ 40
7. BIOS Setup .........................................................................................................
41
7.1. Starting the BIOS ................................................................................................................... 41
Express-IB Page 5
7.1.1. Setup Menu......................................................................................................................................42
7.1.2. Navigation........................................................................................................................................43
7.2. Main Setup ............................................................................................................................ 46
7.3. Advanced Setup..................................................................................................................... 47
7.3.1. ACPI Settings ....................................................................................................................................47
7.3.2. Trusted Computing ..........................................................................................................................48
7.3.3. CPU Configuration............................................................................................................................49
7.3.4. SATA Configuration..........................................................................................................................50
7.3.5. Intel TXT(LT) Configuration ..............................................................................................................50
7.3.6. PCH-FW Configuration .....................................................................................................................51
7.3.7. Intel Anti-Theft Technology Configuration ......................................................................................52
7.3.8. AMT Configuration...........................................................................................................................53
7.3.9. USB Configuration............................................................................................................................54
7.3.10. ADT 7490 H/W Monitor ..............................................................................................................55
7.3.11. W8362DHG Super IO Configuration............................................................................................55
7.3.12. Serial Port Console Redirection...................................................................................................56
7.3.13. CPU PPM Configuration ..............................................................................................................57
7.4. Chipset Setup......................................................................................................................... 58
7.4.1. PCH-IO Configuration.......................................................................................................................58
7.4.2. System Agent (SA) Configuration.....................................................................................................61
7.5. Boot Setup ............................................................................................................................. 67
7.6. Security Setup........................................................................................................................ 68
7.7. Save & Exit Menu................................................................................................................... 69
8. BIOS Checkpoints, Beep Codes........................................................................ 70
8.1. Status Code Ranges ............................................................................................................... 71
8.2. Standard Status Codes........................................................................................................... 71
8.2.1. SEC Status Codes..............................................................................................................................71
8.2.2. SEC Beep Codes................................................................................................................................72
8.2.3. PEI Status Codes...............................................................................................................................72
8.2.4. PEI Beep Codes.................................................................................................................................74
8.2.5. DXE Status Codes .............................................................................................................................74
8.2.6. DXE Beep Codes ...............................................................................................................................76
8.2.7. ACPI/ASL Checkpoint .......................................................................................................................77
8.3. OEM-Reserved Checkpoint Ranges ....................................................................................... 77
Safety Instructions ...................................................................................................... 78
Getting Service ............................................................................................................ 79
Page 6 Express-IB
1. Introduction
The Express-IB is a COM Express® COM.0 R2.1 Type 6 module supporting the 64-bit 3rd Generation Intel® Core™ i7/i5/3 and Celeron®
processor with CPU, memory controller, and graphics processor on the same chip. Based on the latest Mobile Intel® QM77 Express chipset,
the Express-IB is specifically designed for customers who need high-level processing and graphics performance in a long product life
solution.
The Express-IB features the Intel® Core™ i7/i5/i3 processor supporting Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and
DDR3 dual-channel memory at 1066/1333/1600 MHz to provide excellent overall performance. Intel® Flexible Display Interface and Direct
Media Interface provide high speed connectivity to the Intel® QM77 Express chipset.
Integrated HD Graphics 4000 includes features such as OpenGL 3.1, DirectX11, Intel® Clear Video HD Technology, Advanced Scheduler
2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics outputs
include VGA, LVDS and three DDI ports supporting HDMI / DVI / DisplayPort or SDVO. The Express-IB is specifically designed for
customers with high-performance processing graphics requirements who want to outsource the custom core logic of their systems for
reduced development time.
The Express-IB has dual stacked SODIMM sockets for up to 16 GB DDR3 memory. The Intel® Mobile QM77 Express chipset integrates
VGA and dual-channel 18/24-bit LVDS display output. In addition to the onboard integrated graphics, a multiplexed PCI Express x16
Graphics bus is available for discrete graphics expansion or general purpose x8 or x4 PCI Express connectivity.
The Express-IB features a single onboard Gigabit Ethernet port, four USB 3.0 ports and four USB 2.0 ports, two SATA 6 Gb/s ports and two
SATA 3 Gb/s ports. Support is provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting
embedded features such as remote console, CMOS backup, hardware monitor, and watchdog timer.
Express-IB Page 7
2. Specifications
2.1. Core System
¾ CPU: 3rd Generation Intel® Core™, Celeron® Processor, 2/4-core mobile processor with Integrated Graphics, BGA 1023 type
• Intel® Core™ i7-3615QE quad-core 2.3 GHz (3.3/3.1 GHz Turbo), 6MB L3 cache, 45W
• Intel® Core™ i7-3612QE quad-core 2.1 GHz (3.1/2.8 GHz Turbo), 6MB L3 cache, 35W
• Intel® Core™ i7-3555LE dual-core 2.5 GHz (3.2/3.1 GHz Turbo), 4MB L3 cache, 25W
• Intel® Core™ i7-3517UE dual-core 1.7 GHz (2.8/2.6 GHz Turbo), 4MB L3 cache, 17W
• Intel® Core™ i5-3610ME dual-core 2.7 GHz (3.3/3.1 GHz Turbo), 3MB L3 cache, 35W
• Intel® Core™ i3-3120ME dual-core 2.4 GHz (no Turbo), 3MB L3 cache, 35W
• Intel® Core™ i3-3127UE dual-core 1.6 GHz (no Turbo), 3MB L3 cache, 17W
• Intel® Celeron® 1020E dual-core 2.2 GHz (no Turbo) 35W
• Intel® Celeron® 1047UE dual-core 1.4 GHz (no Turbo) 17W
• Intel® Celeron® 927UE dual-core 1.5 GHz (no Turbo) 17W
¾ Cache: 2MB to 16MB LLC cache depending on CPU type
¾ Memory: dual stacked SO-DIMM socket memory on top
Dual channel DDR3 Memory DDR3 data transfer rates of 1066 MT/s, 1333 MT/s and 1600 MT/s
¾ Chipset: Mobile Intel® QM77 Express Chipset
¾ BIOS: AMI EFI with CMOS backup in 16 Mbit SPI BIOS
¾ Hardware Monitor: Supply voltages and CPU temperature
¾ Fan Control: through AB conenctor or mini connector on module routed from the same PWM source (ADMT controller)
¾ Debug Interface: XDP SFF-26 extension for ICE debug
¾ Management: Intel® AMT 8.0 (availability dependent on processor)
2.2. Expansion Busses
¾ PCI Express x16 Gen3/2* supporting up to 8GT/Sec transactions
Configurable as 1 x16 , 2 x8 or 1 x8-lane and 2 x4-lane (routed to CB connector PCIe x16)
*Core™ i7/i5 support Gen3, Core™ i3/Celeron support Gen2
¾ 6x PCIe x1 Gen2 (port 0~5) on AB connector
1x PCIe x1 Gen2 (port 6) on CD connector
¾ LPC bus, SPI bus (BIOS only)
2
¾ SMBus (system) , I
C (user)
2.3. Video
¾ Integrated in processor: Intel® HD Graphics 4000 or HD Graphics (dependent on processor)
¾ Supports: DirectX 11, OpenGL 3.1, OpenCL 1.1
¾ Features (dependent on processor):
• Intel Clear Video HD Technology
• Advanced Scheduler 2.0, 1.0, XPDM support
• DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode
¾ Multi-display Support: 3 independent displays
Page 8 Express-IB
¾ Display Types
• VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA (2048 x 1536)
• LVDS Interface Dual channel 18/24-bit LVDS
• Three Digital Display Ports
DDI0 supporting HDMI / DisplayPort / SDVO
DDI1 supporting HDMI / DisplayPort
DDI2 supporting HDMI / DisplayPort
2.4. Audio
¾ Integrated: Intel® HD Audio integrated in PCH QM77
¾ Audio Codec: Realtek ALC888/886 on Express-BASE6
2.5. LAN
¾ Integrated: LAN MAC integrated in PCH QM77
¾ Intel PHY: 82579 Gb Ethernet
¾ Interface: 10/100/1000 GbE connection
2.6. Multi I/O and Storage
¾ Integrated in PCH QM77
¾ USB ports: 4 ports USB 3.0 (USB0,1,2,3) and 4 ports USB 2.0 (USB4,5,6,7)
¾ SATA ports: two ports SATA 6Gb/s (SATA0, SATA1) two ports SATA 3 Gb/s (SATA2, SATA3)
2.7. Serial I/O on Module
¾ Not implemeted
2.8. Super I/O (on Carrier using LPC -bus)
¾ Chipset: Winbond W83627HG-AW AND W83627DHG-P
Without keyboard A20 line
¾ Parallel Port: LPT1
¾ Serial Ports: COM1 / COM2 (with console redirection)
2.9. GPIO
¾ Chipset: NXP PCA9535
¾ Description: 16-bit I2C-bus and SMBus, low power I/O port with interrupt
¾ GPO: 4 ports
¾ GPI: 4 ports with interrupt
2.10. Board Controller
¾ Type: Atmega168
¾ Functions:
• AT mode control
2
C supports 100/200/400 speed selectable in BIOS
• I
• Vdde control
• Backlight Enable
• Brightness through DDC to PWM on Carrier
• Watchdog
Express-IB Page 9
2.11. TPM (Trusted Platform Module)
¾ Chipset: Infineon SLB9635TT1.2
¾ Type: TPM 1.2
2.12. Fan Control
¾ Control Source: Temperature Sensor
¾ Location
• On AB connector (B101/102): PWM and TACH 12V based on carrier
• 4-pin Mini connector on module: PWM and TACH 5V based on module
¾ Connection: route single source to dual locations
2.13. Debug
¾ JTAG: SFF connector for XDP to CPU
¾ LPC header: for mounting POST CODE assembly
2.14. Power Specifications
¾ Power Modes: AT and ATX mode (AT mode start controlled by ADMT)
¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb or AT = 12V±5%
¾ Wide Voltage Input: ATX = 8.5~19V / 5Vsb or AT = 8.5 ~19V
¾ Power Management: ACPI 3.0 compliant, Smart battery support.
¾ Power States: supports C1-C6, S0, S1, S4, S3, S5 (Wake on USB S3/S4, WOL S3/S4/S5)
2.15. Mechanical and Environmental
¾ Standard Operating Temperature: 0 to 60°C (Wide Voltage Input)
2.16. Specification Compliance
¾ PICMG COM.0: Rev 2.1 Type 6, basic size 125 x 95
Page 10 Express-IB
2.17. Functional Diagram
Express-IB Page 11
2.18. Mechanical Drawing
Page 12 Express-IB
3. Pinouts and Signal Descriptions
The following information is a summary of the most important information regarding pinout and signal description in the official PICMG
COM.0 Rev 2.0 (soon 2.1)
The pinout is noted here to emphazise issues that have not been followed in the past. The following might have small inacuaracies so in
case of doubt the offical design guide of PICMG should be consulted.
3.1. AB / CD Pin Definitions
The Express-IB is a Type 6 module supporting USB3.0 and DDI channels on the CD connector
All pin in the specification are described also those not supported on the Express-IB. Those not supported on the Express-IB module are
crossed out
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
GND (FIXED)
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND (FIXED)
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF
SUS_S3#
SATA0_TX+
SATA0_TX-
SUS_S4#
SATA0_RX+
SATA0_RXGND (FIXED)
SATA2_TX+
SATA2_TX-
SUS_S5#
SATA2_RX+
SATA2_RX-
BATLOW#
(S)ATA_ACT#
AC/HDA_SYNC
AC/HDA_RST#
GND (FIXED)
AC/HDA_BITCLK
AC/HDA_SDOUT
BIOS_DIS0#
THRMTRIP#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
GND (FIXED)
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND (FIXED)
PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TX-
SUS_STAT#
SATA1_RX+
SATA1_RXGND (FIXED)
SATA3_TX+
SATA3_TX-
PWR_OK
SATA3_RX+
SATA3_RX-
WDT
AC/HDA_SDIN2
AC/HDA_SDIN1
AC/HDA_SDIN0
GND (FIXED)
SPKR
I2C_CK
I2C_DAT
THRM#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
GND FIXED)
GND
USB_SSRX0USB_SSRX0+
GND
USB_SSRX1USB_SSRX1+
GND
USB_SSRX2USB_SSRX2+
GND (FIXED)
USB_SSRX3USB_SSRX3+
GND
DDI1_PAIR6+
DDI1_PAIR6RSVD
RSVD
PCIE_RX6+
PCIE_RX6GND (FIXED)
PCIE_RX7+
PCIE_RX7DDI1_HPD
DDI1_PAIR4+
DDI1_PAIR4RSVD
RSVD
DDI1_PAIR5+
DDI1_PAIR5GND (FIXED)
DDI2_CTRLCLK_AUX+
DDI2_CTRLDATA_AUXDDI2_DDC_AUX_SEL
RSVD
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
GND FIXED)
GND
USB_SSTX0USB_SSTX0+
GND
USB_SSTX1USB_SSTX1+
GND
USB_SSTX2USB_SSTX2+
GND (FIXED)
USB_SSTX3USB_SSTX3+
GND
DDI1_CTRLCLK_AUX+
DDI1_CTRLDATA_AUX-
RSVD
RSVD
PCIE_TX6+
PCIE_TX6GND (FIXED)
PCIE_TX7+
PCIE_TX7RSVD
RSVD
DDI1_PAIR0+
DDI1_PAIR0RSVD
DDI1_PAIR1+
DDI1_PAIR1GND (FIXED)
DDI1_PAIR2+
DDI1_PAIR2-
DDI1_DDC_AUX_SEL
RSVD
Express-IB Page 13
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
USB6USB6+
USB_6_7_OC#
USB4USB4+
GND (FIXED)
USB2USB2+
USB_2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
GND (FIXED)
PCIE_TX5+
PCIE_TX5-
GPI0
PCIE_TX4+
PCIE_TX4GND
PCIE_TX3+
PCIE_TX3GND (FIXED)
PCIE_TX2+
PCIE_TX2GPI1
PCIE_TX1+
PCIE_TX1GND
GPI2
PCIE_TX0+
PCIE_TX0GND (FIXED)
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_VDD_EN
LVDS_A3+
LVDS_A3GND (FIXED)
USB7-
B36
USB7+
B37
USB_4_5_OC#
B38
USB5-
B39
USB5+
B40
GND (FIXED)
B41
USB3-
B42
USB3+
B43
USB_0_1_OC#
B44
USB1-
B45
USB1+
B46
EXCD1_PERST#
B47
EXCD1_CPPE#
B48
SYS_RESET#
B49
CB_RESET#
B50
GND (FIXED)
B51
PCIE_RX5+
B52
PCIE_RX5-
B53
GPO1
B54
PCIE_RX4+
B55
PCIE_RX4-
B56
GPO2
B57
PCIE_RX3+
B58
PCIE_RX3-
B59
GND (FIXED)
B60
PCIE_RX2+
B61
PCIE_RX2-
B62
GPO3
B63
PCIE_RX1+
B64
PCIE_RX1-
B65
WAKE0#
B66
WAKE1#
B67
PCIE_RX0+
B68
PCIE_RX0-
B69
GND (FIXED)
B70
LVDS_B0+
B71
LVDS_B0-
B72
LVDS_B1+
B73
LVDS_B1-
B74
LVDS_B2+
B75
LVDS_B2-
B76
LVDS_B3+
B77
LVDS_B3-
B78
LVDS_BKLT_EN
B79
GND (FIXED)
B80
C36
DDI3_CTRLCLK_AUX+
C37
DDI3_CTRLDATA_AUX-
C38
DDI3_DDC_AUX_SEL
DDI3_PAIR0+
C39
DDI3_PAIR0-
C40
GND (FIXED)
C41
DDI3_PAIR1+
C42
DDI3_PAIR1-
C43
DDI3_HPD
C44
RSVD
C45
DDI3_PAIR2+
C46
DDI3_PAIR2-
C47
RSVD
C48
DDI3_PAIR3+
C49
DDI3_PAIR3-
C50
GND (FIXED)
C51
PEG_RX0+
C52
PEG_RX0-
C53
TYPE0#
C54
PEG_RX1+
C55
PEG_RX1-
C56
TYPE1#
C57
PEG_RX2+
C58
PEG_RX2-
C59
GND (FIXED)
C60
PEG_RX3+
C61
PEG_RX3-
C62
RSVD
C63
RSVD
C64
PEG_RX4+
C65
PEG_RX4-
C66
RSVD
C67
PEG_RX5+
C68
PEG_RX5-
C69
GND (FIXED)
C70
PEG_RX6+
C71
PEG_RX6-
C72
GND
C73
PEG_RX7+
C74
PEG_RX7-
C75
GND
C76
RSVD
C77
PEG_RX8+
C78
PEG_RX8-
C79
GND (FIXED)
C80
DDI1_PAIR3+
D36
DDI1_PAIR3-
D37
RSVD
D38
DDI2_PAIR0+
D39
DDI2_PAIR0-
D40
GND (FIXED)
D41
DDI2_PAIR1+
D42
DDI2_PAIR1-
D43
DDI2_HPD
D44
RSVD
D45
DDI2_PAIR2+
D46
DDI2_PAIR2-
D47
RSVD
D48
DDI2_PAIR3+
D49
DDI2_PAIR3-
D50
GND (FIXED)
D51
PEG_TX0+
D52
PEG_TX0-
D53
PEG_LANE_RV#
D54
PEG_TX1+
D55
PEG_TX1-
D56
TYPE2#
D57
PEG_TX2+
D58
PEG_TX2-
D59
GND (FIXED)
D60
PEG_TX3+
D61
PEG_TX3-
D62
RSVD
D63
RSVD
D64
PEG_TX4+
D65
PEG_TX4-
D66
GND
D67
PEG_TX5+
D68
PEG_TX5-
D69
GND (FIXED)
D70
PEG_TX6+
D71
PEG_TX6-
D72
GND
D73
PEG_TX7+
D74
PEG_TX7-
D75
GND
D76
RSVD
D77
PEG_TX8+
D78
PEG_TX8-
D79
GND (FIXED)
D80
Page 14 Express-IB
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
LVDS_A_CK+
LVDS_A_CKLVDS_I2C_CK
LVDS_I2C_DAT
GPI3
RSVD
RSVD
PCIE0_CK_REF+
PCIE0_CK_REF-
GND (FIXED)
SPI_POWER
SPI_MISO
GPO0
SPI_CLK
SPI_MOSI
TPM_PP
TYPE10#
SER0_TX
SER0_RX
GND (FIXED)
SER1_TX
SER1_RX
LID#
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
LVDS_B_CK+
LVDS_B_CKLVDS_BKLT_CTRL
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
BIOS_DIS1#
VGA_RED
GND (FIXED)
VGA_GRN
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT
SPI_CS#
RSVD
RSVD
GND (FIXED)
FAN_PWMOUT
FAN_TACHIN
SLEEP#
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
PEG_RX9+
PEG_RX9-
TPM_PP
GND
PEG_RX10+
PEG_RX10GND
PEG_RX11+
PEG_RX11GND (FIXED)
PEG_RX12+
PEG_RX12GND
PEG_RX13+
PEG_RX13GND
RSVD
PEG_RX14+
PEG_RX14GND (FIXED)
PEG_RX15+
PEG_RX15GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
PEG_TX9+
PEG_TX9RSVD
GND
PEG_TX10+
PEG_TX10GND
PEG_TX11+
PEG_TX11GND (FIXED)
PEG_TX12+
PEG_TX12GND
PEG_TX13+
PEG_TX13GND
RSVD
PEG_TX14+
PEG_TX14GND (FIXED)
PEG_TX15+
PEG_TX15GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
Express-IB Page 15
3.2. Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module
Page 16 Express-IB
3.3. AB Signal Descriptions
3.3.1. Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
AC_SYNC /
HDA_SYNC
AC_BITCLK /
HDA_BITCLK
AC _SDOUT /
HDA_SDOUT
AC _SDIN[2:0]
HDA_SDIN[2:0]
A30 Reset output to CODEC, active low. O 3.3VSB
A29 Sample-synchronization signal to the CODEC(s). O 3.3V
A32 Serial data clock generated by the external
CODEC(s).
A33 Serial TDM data output to the CODEC. O 3.3V
B28
B30
Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB
I/O 3.3V
3.3.2. Analog VGA
Signal Pin # Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog If VGA is used than signal should
be pulled to GND by 150Ω on the
carrier
O Analog If VGA is used than signal should
be pulled to GND by 150Ω on the
carrier
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2 3.3V
O Analog If VGA is used than signal should
be pulled to GND by 150Ω on the
carrier
I/O OD 3.3V PU 2k2 3.3V
3.3.3. LVDS
Signal Pin # Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
LVDS_A_CK+
LVDS_A_CK-
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
LVDS Channel A differential pairs O LVDS
LVDS Channel A differential clock O LVDS
LVDS_B0+
LVDS_B0-
B71
B72
LVDS Channel B differential pairs O LVDS
Express-IB Page 17
Signal Pin # Description I/O PU/PD Comment
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
LVDS_B_CK+
LVDS_B_CK-
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V
B73
B74
B75
B76
B77
B78
B81
B82
LVDS Channel B differential clock O LVDS
3.3.4. Gigabit Ethernet
Gigabit Ethernet Pin # Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec
modes. Some pairs are unused in some modes according to the
following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/MDI[3]+/- B1_DD+/-
I/O Analog Twisted pair
signals for
external
transformer.
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2
magnetics center tap. The reference voltage is determined by the
requirements of the Module PHY and may be as low as 0V and as high
as 3.3V. The reference voltage output shall be current limited on the
Module. In the case in which the reference is shorted to ground, the
current shall be 250 mA or less.
GND min
3.3V max
Page 18 Express-IB
3.3.5. Serial ATA
Signal Pin # Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
SATA2_TX+
SATA2_TX-
SATA2_RX+
SATA2_RX-
SATA3_TX+
SATA3_TX-
SATA3_RX+
SATA3_RX-
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity
A16
A17
A19
A20
B16
B17
B19
B20
A22
A23
A25
A26
B22
B23
B25
B26
Serial ATA channel 0, Transmit Output
differential pair.
Serial ATA channel 0, Receive Input
differential pair.
Serial ATA channel 1, Transmit Output
differential pair.
Serial ATA channel 1, Receive Input
differential pair.
Serial ATA channel 2, Transmit Output
differential pair.
Serial ATA channel 2, Receive Input
differential pair.
Serial ATA channel 3, Transmit Output
differential pair.
Serial ATA channel 3, Receive Input
differential pair.
indicator, active low.
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O 3.3V
Express-IB Page 19
3.3.6. PCI Express
Signal Pin # Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
PCIE_RX0+
PCIE_RX0-
PCIE_TX1+
PCIE_TX1-
PCIE_RX1+
PCIE_RX1-
PCIE_TX2+
PCIE_TX2-
PCIE_RX2+
PCIE_RX2-
PCIE_TX3+
PCIE_TX3-
PCIE_RX3+
PCIE_RX3-
PCIE_TX4+
PCIE_TX4-
PCIE_RX4+
PCIE_RX4-
A68
A69
B68
B69
A64
A65
B64
B65
A61
A62
B61
B62
A58
A59
B58
B59
A55
A56
B55
B56
PCI Express channel 0, Transmit Output differential
pair.
PCI Express channel 0, Receive Input differential
pair.
PCI Express channel 1, Transmit Output differential
pair.
PCI Express channel 1, Receive Input differential
pair.
PCI Express channel 2, Transmit Output differential
pair.
PCI Express channel 2, Receive Input differential
pair.
PCI Express channel 3, Transmit Output differential
pair.
PCI Express channel 3, Receive Input differential
pair.
PCI Express channel 4, Transmit Output differential
pair.
PCI Express channel 4, Receive Input differential
pair.
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
PCIE_TX5+
PCIE_TX5-
PCIE_RX5+
PCIE_RX5-
PCIE_CLK_REF+
PCIE_CLK_REF-
A52
A53
B52
B53
A88
A89
PCI Express channel 5, Transmit Output differential
pair.
PCI Express channel 5, Receive Input differential
pair.
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE
3.3.7. Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
A49
B48
A48
B47
PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k
3.3V
PCI ExpressCard: reset O 3.3V Cannot be tested on Express-
BASE6 (DVT issue)
Page 20 Express-IB
3.3.8. LPC bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
B8
B9
LPC serial DMA request I 3.3V
3.3.9. USB
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
USB4+
USB4-
USB5+
USB5-
A46
USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
A45
B46
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
B45
A43
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
A42
B43
USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
B42
A40
USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
A39
B40
USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
B39
USB6+
USB6-
USB7+
USB7-
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up
A37
USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
A36
B37
USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
B37
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
Express-IB Page 21
3.3.10. SPI (BIOS only)
Signal Pin # Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module
– nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on
the Carrier
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND
O P 3.3VSB
or leave no- connect.
or leave no- connect
3.3.11. Miscellaneous
Signal Pin # Description I/O PU/PD Comment
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT
systems
WDT B27 Output indicating that a watchdog time-out event has
occurred.
THRM# B35 Input from off-module temp sensor indicating an over-temp
situation.
THERMTRIP# A35 Active low output indicating that the CPU has entered
thermal shutdown.
O 3.3V
O 3.3V
I 3.3V
O 3.3V
FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation
(PWM) technique to control the fan’s RPM.
FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V
TPM_PP11 C83 Trusted Platform Module (TPM) Physical Presence pin.
Active high. TPM chip has an internal pull down. This
signal is used to indicate Physical Presence to the TPM.
O OD 3.3V
I 3.3V PD 3.3V If TPM not installed on
module than remove PD
3.3V
3.3.12. SMBus
Signal Pin # Description I/O PU/PD Comment
SMB_CK B13 System Management Bus bidirectional clock line. Power
sourced through 5V standby rail and main power rails.
SMB_DAT# B14 System Management Bus bidirectional data line. Power
sourced through 5V standby rail and main power rails.
SMB_ALERT# B15 System Management Bus Alert – active low input can
be used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced
through 5V standby rail and main power rails.
Page 22 Express-IB
I/O OD 3.3VSB PU 2k2 3.3VSB
I/O OD 3.3VSB PU 2k2 3.3VSB
I 3.3VSB
3.3.13. I2C Bus
Signal Pin # Description I/O PU/PD Comment
I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB
I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB
3.3.14. General Purpose I/O (GPIO)
Signal Pin # Description I/O PU/PD Comment
GPO[0] A93 General purpose output pins. O 3.3V
GPO[1] B54 General purpose output pins. O 3.3V
GPO[2] B57 General purpose output pins. O 3.3V
GPO[3] B63 General purpose output pins. O 3.3V
GPI[0] A54 General purpose input pins.
Pulled high internally on the module.
GPI[1] A63 General purpose input pins.
Pulled high internally on the module.
GPI[2] A67 General purpose input pins.
Pulled high internally on the module.
GPI[3] A85 General purpose input pins.
Pulled high internally on the module.
I 3.3V PU 10K 3.3V PU not in PICMG
suggest 10K
I 3.3V PU 10K 3.3V PU not in PICMG
suggest 10K
I 3.3V PU 10K 3.3V PU not in PICMG
suggest 10K
I 3.3V PU 10K 3.3V PU not in PICMG
suggest 10K
3.3.15. Power And System Management
Signal Pin # Description I/O PU/PD Comment
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k
3.3VSB
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is not able to
reestablish control of the system, PWR_OK or a power cycle may be used.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.
I 3.3VSB PU 10k
3.3VSB
O 3.3VSB
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup to allow carrier
based FPGAs or other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted
copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be
used to enable the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB
WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k
I 3.3V TBD by R&D
in CPLD
O 3.3VSB
3.3VSB
Should have
weak pull up
Express-IB Page 23
Signal Pin # Description I/O PU/PD Comment
WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to
signal that the system battery is low, or may be used to signal some other
external power-management event.
LID# LID button. Low active signal used by the ACPI operating system for a LID
switch.
SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring
the system to sleep state or to wake it up again.
I 3.3VSB PU 10k
3.3VSB
I 3.3VSB PU 10k
3.3VSB
I OD
3.3VSB
I OD
3.3VSB
PU 10k
3.3VSB
PU 10K
3.3VSB
3.3.16. Power and Ground
Signal Pin # Description I/O PU/PD Comment
VCC_12V A104-A109
B104-B109
VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. See section 7 “Electrical
Primary power input: +12V nominal (5 ~ 19V). See section 7
“Electrical Specifications“ for allowable input range. All available
VCC_12V pins on the connector(s) shall be used.
Specifications“ for allowable input range. If VCC5_SBY is used,
all available VCC_5V_SBY pins on the connector(s) shall be used.
Only used for standby and suspend functions. May be left
unconnected if these functions are not used in the system design.
P 8.5~19 V
P 5Vsb ±5%
VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P
GND A1, A11, A21, A31,
A41, A51, A57, A66,
A80, A90, A96,
A100, A110, B1,
B11, B21 ,B31, B41,
B51, B60, B70, B80,
B90, B100, B110
Ground - DC power and signal and AC signal return path. P
Page 24 Express-IB
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