ACT ARX4808-2, ARX4808, ARX4868, ARX4868-2 Datasheet

eroflex Circuit T

– Data Bus Modules For The Future © SCD4808 REV A 3/9/98

ARX4808 Dual Transceivers for

MACAIR A3818, A5690, A5232, A4905

& MIL-STD-1553

Features

• ARX4808 Dual Transceiver meets
MIL-STD-1553A&B, Macair A3818, A5690, A5232
and A4905 specs

• Operates with ±12 V to ±15 V & +5 V Power Supplies

• Voltage source output for higher bus drive power

• Plug-in or Flat Package

• Monolithic construction using linear ASICs

• Low receiver data level version, ARX4868

• Processed and Screened to MIL-STD-883 specs

• DESC SMD (Standard Military Drawing ) Pending

ARX4808 Transceiver

TX DATA IN
TX DATA IN

TX INHIBIT

+5 V

VEE

RX DATA IN
RX DATA IN

VCC

STROBE

DRIVER

INPUT
AMP

SHAPING

V-

ACTIVE
FILTER

OUTPUT
STAGE

V+

COMP.

COMP.

Block Diagram (without Transformer), 1/2 of unit shown

TX DATA OUT
TX DATA OUT

RX DATA OUT

RX DATA OUT

CIRCUIT TECHNOLOGY

www.aeroflex.com/act1.htm

General Description:

The Aeroflex Laboratories transceiver
model ARX4808 is a new generation
Dual monolithic transceiver which
provides full compliance with Macair
and MIL-STD-1553 data bus
requirements
The model ARX4808 performs the
front-end analog function of inputting
and outputting data through a
transformer to a MIL-STD-1553 or
Macair data bus. The ARX4808 can
be considered a "Universal"
Transceiver in that it is compatible
with MIL-STD-1553A & B, Macair
A-3818, A-4905, A-5232 and A-5690.
Design of this transceiver reflects
particular attention to active filter
performance. This results in low bit
and word error rate with superior
waveform purity and minimal zero
crossover distortion. The ARX4808
series active filter design has
additional high frequency roll-off to
provide the required Macair low
harmonic distortion waveform
without increasing the pulse delay
characteristics significantly.
Efficient transmitter electrical and
thermal design provides low internal
power dissipation and heat rise at
high and well as low duty cycles.The
receiver input threshold is set
Internally.

Transmitter

The Transmitter section accepts
bi-phase TTL data at the input and
when coupled to the data bus with a
1:1 transformer, isolated on the data
bus side with two 52.5 Ohm fault
isolation resistors, and loaded by two
70 Ohm terminations plus additional

echnology

Aeroflex Circuit Technology SCD4808 REV A 3/9/98 Plainview NY [phone]

receivers, the data bus signal
produced is 7.5 volts minimum P-P
at A-A’ (See Figure 5.). When both
DATA and DATA

inputs are held low
or high, the transmitter output
becomes a high impedance and is
“removed” from the line. In addition,
an overriding “INHIBIT" input
provides for the removal of the
transmitter output from the line. A
logic “1” applied to the “INHIBIT”
takes priority over the condition of
the data inputs and disables the
transmitter. (See Transmitter Logic
Waveforms, Figure 1.)
The transmitter utilizes an active
filter to suppress harmonics above

Figure 1 Transmitter Logic Waveforms

DATA IN

1MHz to meet Macair specifications
A-3818, A-4905, A-5232 and
A-5690. The transmitter may be
safely operated for an indefinite
period at 100% duty cycle into a
data bus short circuit.

Receiver

The Receiver section accepts
bi-phase differential data at the input
and produces two TTL signals at the
output. The outputs are DATA and

, and represent positive and

DATA
negative excursions of the input
beyond a pre-determined threshold.
(See Receiver Logic Waveforms,
Figure 2.)

The internal threshold is nominally
set to detect data bus signals
exceeding 1.05 Volts P-P and
reject signals less than 0.6 volts
P-P when used with a 1:1 turns
ratio transformer. (See Figure 5
for transformer data and typical
connection.)

A low level at the Strobe input
inhibits the DATA and DATA
outputs. If unused, a 2K pull-up to
+5 Volts is recommended

DATA IN

INHIBIT

LINE TO LINE

OUTPUT

NOTES:

1. Line to line waveforms illustrate Macair signals, MIL-STD-1553 signals are trapezoidal

2. DATA and DATA

3. DATA and DATA

inputs must be complementary waveforms or 50% duty cycle average, with no delays between them.

must be in the same state during off time (both high or low).

Figure 2 Receiver Logic Waveforms

LINE TO LINE
INPUT

DATA OUT

DATA OUT

NOTE: Waveforms shown are for normally low devices. For normally high receiver output

level

devices, the receiver outputs are swapped as shown by the dashed lines

2

Note overlap