ACER Z01 Diagram

MODEL:

REV:

CHANGE LIST:

FIRST RELEASE1A

PAGE02. 1. R447,455,456 MODIFY to EP P/N:CS14752FB11 PAGE03. 1. STUFF HOLE6 P/N:FBZ01007010 , 2. STUFF HOLE7,8,15 P/N:FBED8001016 , 3. STUFF HOLE5 P/N:FBZ01006010 PAGE03. 1. STUFF HOLE23,25 P/N:FBZ01003010 , 2. STUFF HOLE18 P/N:FBZ01004010 , 3. STUFF HOLE31 P/N:FBZ01005010 PAGE05. 1. U22 MODIFY to GM965 P/N:AJ0QN120T04 , 2. R193,194 MODIFY to EP P/N:CS03902FB11 PAGE06. 1. R242 MODIFY to EP P/N:CS33002JB23

Z01 MotherBoard

D D

C C

B B

A A

PAGE08. 1. L52,53 MODIFY to EP P/N:CV01004KN00 PAGE11. 1. R332 MODIFY to EP P/N:CS23243F930 , 2. U6 MODIFY to ICH8 P/N:AJ0QM740T03 PAGE12. 1. R244,R347,R353 MODIFY to EP P/N:CS00004JA40 , 2. L28 MODIFY to P/N:CV-1005MZ01 PAGE13. 1. CN10 MODIFY to CRT P/N:DFDS15FR611 PAGE15. 1. R467 MODIFY to EP P/N:CS00004JA40,2. R50 MODIFY to EP P/N:CS31003J941,3.CN27 MODIFY to SATA P/N:DFHS22FR005 PAGE16. 1. CN16 MODIFY to RJ45/11 P/N:DFTJ15FR057 PAGE18. 1. R317,323 MODIFY to 0603 P/N:CS31003F949 , 2. R310 MODIFY to EP P/N:CS31003J941 PAGE20. 1. PR100 MODIFY to EP P/N:CS51002FB11 PAGE21. 1. PR86 MODIFY to EP P/N:CS24022FB13 , 2. PR38,82 MODIFY to 1% P/N:CS31002FB26 , 3. PR83 MODIFY to EP P/N:CS00004JA40 PAGE22. 1. PR1 MODIFY to EP P/N:CS32002FB29 , 2. PR6 MODIFY to 1% P/N:CS51003F934 PAGE23. 1. PR106 MODIFY to 0 ohm P/N:CS00002JB38 , 2. UN-STUFF PR107,PC111 PAGE24. 1. PR29 MODIFY to EP P/N:CS31003J941 2. PJ1 MODIFY to BATTERY P/N:DFHD07MR006 PAGE25. 1. PR70 MODIFY to EP P/N:CS32002FB29

PAGE02. 1. Connect VDDIO_CLK to +1.25V 2. un-stuff R292;R445;R308 3. stuff C575,C574,C576,C578,C573,C546 for EMI issue PAGE06. 1. Connect ICH_PWROK SIGNAL TO NB CLPWROK 2.un-stuff R242;R235;R422;R222;R421;R423 3. R360,R361 only stuff for UMA PAGE07. 1. MODIFY 22u to 10u PAGE08. 1. R489 MODIFY to 0805 2. Stuff L50;R182;C238 for EV@ (MXM) PAGE09. 1. Add PU for SMA_MA14 ; SMB_MA14 PAGE10. 1. un-stuff R337,C115,C127,C129,C298,C302,C294,C283,C291 PAGE11. 1. Q18 MODIFY to P/N:AL07SZ04C27 2.R395 connect to VCCRTC 3.R336;R251;R419;R255 un-stuff 4.R226 connect to +3V_S5 5.ICH_PWROK to SB CLPWROK PAGE11. 1. stuff C500,C509,C300,C513 33pF P/N:CH03306JB04 2. C507,C508 10pF change to 15pF P/N:CH01506JB06 , 3. stuff R238,R392,C2989 for Contr-LINK1 PAGE12. 1. VCCHDA & VCCSUSHDA change to 3V PAGE13. 1. ADD CRT DDC IN PU , 2. L8,L9,L10 P/N change to 0.47UH for MXM , 3. C22,C24,C25,C27,C31,C32 P/N change to 47pF for MXM PAGE14. 1. CN6 MODIFY CONN. to 5 PIN P/N:DFHD05MRD98 PAGE15. 1. MODIFY SWITCH BOARD PIN DEFINE 2. Modify FAN circuit , 2. MR1 P/N change to AL000268000 PAGE16. 1. C46,C47 27pF change to 33pF P/N:CH03306JB04 2. stuff C104,C105,C119,C112 0.1uF P/N:CH41003ZB35 PAGE17. 1. CARD READER COLAY TO CN28, DEL CN30 2. C311 change to 27pF P/N:CH02706JB06 3. stuff R209 4. un-stff R213,C325,U11 PAGE18. 1. CHANGE MDC & CODEC to 3V 2.Delete D12 3. stuff R314,R483,C393,C595 PAGE19. 1. SWAP NBSWON# & ACIN 2. C363,C364 5.6pF change to 18pF P/N:CH01806JB07 PAGE20. 1. Modify PQ19 P/N PAGE21. 1. Modify Capacitor P/N to meet ME height limit PAGE22. 1. stuff PR74,PC69 2. Remove JP Pad PAGE23. 1. stuff PR126,PC131,PC137 2. Remove JP Pad 3. un-stuff +1.8V PAGE25. 1. un-stuff PR101,PQ21,PR22,PQ2,PR26,PR9,PR5,PC33,PC38,PC39,PC19,PC22,PU2

PAGE02. 1. Change R293 to 2.2K for meet Intel Design checklist PAGE03. 1. Change XDP PU/PD resistors value to meet Intel Design checklist PAGE04. 1. Un-stuff C28,C457 PAGE05. 1. Add LVDS_VREF strap PAGE06. 1. Add SDVO I2C strap PAGE07. 1. Remove NB resistors to GND PAGE08. 1. Remove DIODE for D27 2. Remove VCCA_DPLLA&B for external VGA PAGE10. 1. Add CRT & LVDS I2C Strap PAGE11. 1. Un-stuff Control Link Vref1 PAGE12. 1. Remove reserve ICH8 HDA 1.5V power rail PAGE13. 1. Modify LCD_VCC enable power rail 2. Add LVDS INV I2C Strap PAGE14. 1. Add EMI solution for debug port PCI clock PAGE15. 1. Change Q33,Q34 to MOSFET PAGE16. 1. Add PIN 59 & 3 PAGE18. 1. Change CN31 pin2 to +3V_S5 for Modem can't wake up from S3 PAGE19. 1. Add GPIO46 , 47 PAGE20~25. 1. Add EMI solution 2. Update Power component P/N

PAGE10. 1. Add +2.5V & +1.8V capacitors for nVIDIA MXM card

PAGE11. 1. Change C507,C508 to 15pF for RTC PAGE13. 1. Add C609 & C610 to meet CM2009 specification PAGE14. 1. Reserve +5VPCU & Add Q40,R540 for CIR PAGE15. 1. Add C611 for PLC hall IC 2. Stuff R60 for G995 PAGE19. 1. CN24 un-stuff , 2. D322,D332 reserve for ESD PAGE21. 1. Modify PC85 value PAGE22. 1. Modify PR4,PC13 value for sequence PAGE23. 1. Add PQ22 for nVIDIA MXM +1.8V PAGE24. 1. Modify PF1 P/N PAGE25. 1. Add PU2 for nVIDIA MXM +2.5V

PAGE10. 1. Remove R337 & Add R542,Q41,Q42 for Nvidia ACIN function PAGE13. 1. Add D34~D36,D40 for ESD solution PAGE15. 1. R484,R485,R486 from 330 change to 220 ohm for LED light issue 2. Add D41,D42,D43 for ESD 3. Stuff Q39 PAGE16. 1. Add C621,C622 for EMI solution 2. C112,C119 change to 100pF/50V for EMI PAGE18. 1. Un-Stuff L55, Stuff U16,R470,R471 for internal Mic. issue PAGE19. 1. Modify D32,D33 package to 0402 for ESD PAGE23. 1. Add PR140,PR141 for +1.8V voltage PAGE25. 1. Stuff PR22,PR101,PQ2,PQ21 for nVIDIA MXM +1.8V & +2.5V Discharge

MODEL : Z01 MB

FROM

PAGE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

1A 2B 2B 2B 2B 2B 2B 2B 2A 3A 2B 2B 3A 3A 3A 3A 2A 2B 3A 2B 3A 3A 3A 3A 3A

3B 3B

3A 3B

Quanta Computer Inc.

PROJECT : ZO1

MB ASSY'S P/N : 31Z01MB00XX

APPROVE BY: JIM HSU DRAWING BY:JACKY CHENG

PROJECT LEADER: JIM HSU DOCUMENT NO: 204

REV 3A

DATE :2007/04/14

COVER SHEET 1 OF 1

14.318MHZ

Z01 SYSTEM BLOCK DIAGRAM

Clock Generator SLG8SP512T

U26

D D

Merom CPU

479 Pin uFCPGA

U21

FSB 667/800 Mhz

MXM

Type II

TV-OUT

CN20 STD H9. 9

TFT LCD Panel

14.1" WXGA

C C

CRT

PCI-Express X16 Lan TV-OUT

LVDS VGA

Intel NB

Crestline 965GM/965PM 1299 Pin FBGA

U22

X4 DMI interface

Dual Channel DDR2 533/667 Mhz

CPU

Thermal Sensor

DDRII SODIMM0 SODIMM1

CN19 - H5.2 CN18 - H9.2

SATA HDD

SATA0

PATA

USB 2.0

Bluetooth

CN6

USB4

USB Port x 2

CN21,23

USB3,5

CN27

PATA ODD

CN26

USB Port x 2

CN12 USB0,1

CCD

CN1

B B

USB2

32.768K

Realtek

AMP G1411

U19

Speaker

CN5

A A

AMP G1412

U18

SPDIF

Audio Codec ALC268

U17

Audio conn

CN9

MIC In

Internal MIC

CN7

Line in

MDC

CN31

Azalia

RJ11

CN17

Intel SB

ICH8M NB82801HBM 676 Pin BGA

RTC

CN23

Winbond

KBC PC8769L

BIOS

U14

CIR

U28

Touch Pad

CN4

K/B

CN3

FAN

CN15

LPC

PCI-e X1 PCI Bus interface

32.768KHZ

1394 +Cardreader Controller

Ricoh R5C832/R5C833

128 Pin TQFP

IEEE 1394

CN13

Card reader MMC SD

MS MS DU O

CN28,29,30

MiniCard

PCIE2 PCIE1

New Card

CN8CN14 U24

Y1 25MHz

BroadCom GIGA LAN BCM5787M

68 Pin QFN

Transformer RJ45

U20 CN16

POWER IC

PCIE3

Size Document Number Rev

Block Diagram

Date: Sheet

PROJECT : ZO1

Quanta Computer Inc.

226Thursday, May 17, 2007

Clock Generator

D D

REV:B MODIFY

VDDIO_CLK

+1.25V

C C

CLKREQ_A# : SRC0 / SRC2 CLKREQ_B# : LCDCLK / SRC4 CLKREQ_C# : SRC0 / SRC2 CLKREQ_D# : LCDCLK / SRC4 CLKREQ_E# : SRC6

L45

+3V

BK1608HS220_6_1A

C386

4.7u/6.3V_6

C385

4.7u/6.3V_6

C377 .1u/16V_4

Each Power pin have one 0.1u Capacitor

C378

C384

4.7u/6.3V_6

.1u/16V_4

REV:B MODIFY

C383 .1u/16V_4

C389 .1u/16V_4

C381 .1u/16V_4

C379 .1u/16V_4

SATACLKREQ#11 PCLK_LPC_DB14

PCLK_PCM17

PCLK_59119

PCLK_ICH11

CLKUSB_4811

14M_ICH11

VDD_CK_VDD

C391 .1u/16V_4

C376 .1u/16V_4

R455 475/F_4 R461 33_4 R465 33_4 R462 22_4

REV:C MODIFY

R469 33_4

R460 33_4

R446 33_4

C390 .1u/16V_4

C387 .1u/16V_4

C380 .1u/16V_4

C388 .1u/16V_4

SATACLKREQ#_R PCLK_LPC_DB_R PCLK_PCM_R PCLK_591_R SEL_LCDCLK# PCLK_ICH_R CG_XIN CG_XOUT FSA MCH_BSEL1 FSC

U26 CLOCK_GEN

VDD_48

VDD_PCI

VDD_PLL3

VDD_SRC

61 55

12 20 26 45 36 49

1 3 4 5 6

7 60 59 10 57 62

8 11 15 17 19 52 23 29 42 58

SLG8SP512

VDD_REF VDD_CPU

VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO

PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/SEL_LCDCLK# PCIF5/ITP_EN XTAL_IN XTAL_OUT USB_48/FSA FSB/TEST/MODE REF0/FSC/TESTSEL VSS_PCI

VSS_48 VSS_IO LCDCLK/27M VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF

CKPWRGD/PWRDWN#

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1_MCH

CPU1_MCH#

SRC8/ITP

SRC8#/ITP#

SRC10

SRC10#

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2

SRC2#

LCDCLK#/27MSS

SRC0/DOT96

SRC0#/DOT96#

SCL SDA

SMBCK

SMBDT

63 38

CLK_CPU_BCLK_R

CLK_CPU_BCLK#_R

CLK_MCH_BCLK_R

CLK_MCH_BCLK#_R

50 47

CLK_PCIE_3GPLL_R

CLK_PCIE_3GPLL#_R

CLK_MCH_REQ#

NEW_CLKREQ#_R

CLK_PCIE_NEW_C_R

CLK_PCIE_NEW_C#_R

CLK_PCIE_MXM_R

CLK_PCIE_MXM#_R

CLK_PCIE_ICH_R

CLK_PCIE_ICH#_R

CLK_PCIE_MINI1_R

CLK_PCIE_MINI1#_R

CLK_PCIE_LAN_R

CLK_PCIE_LAN#_R

CLK_PCIE_SATA_R

CLK_PCIE_SATA#_R

DREFSSCLK_R DREFSSCLK#_R

DREFCLK_R

DREFCLK#_R

14 56

CK_PWRGD 11

RN33 0_4P2R

1 2

1 2 1 2

1 2

43 43

RN34 0_4P2R

RN36 0_4P2R

R447 475/F_4 R456 475/F_4

RN43 0_4P2R

RN35 EV^0_4P2R

RN37 0_4P2R

RN42 0_4P2R

RN41 0_4P2R

RN40 0_4P2R

RN39 IV^0_4P2R

RN38 IV^0_4P2R

PM_STPPCI# 11 PM_STPCPU# 11

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

CLK_MCH_BCLK 5 CLK_MCH_BCLK# 5

CLK_PCIE_3GPLL 6 CLK_PCIE_3GPLL# 6

CLK_MCH_OE# 6 NEW_CLKREQ# 14

CLK_PCIE_NEW_C 14 CLK_PCIE_NEW_C# 14

CLK_PCIE_MXM 10 CLK_PCIE_MXM# 10

CLK_PCIE_ICH 11 CLK_PCIE_ICH# 11

CLK_PCIE_MINI1 14 CLK_PCIE_MINI1# 14

CLK_PCIE_LAN 16 CLK_PCIE_LAN# 16

CLK_PCIE_SATA 11 CLK_PCIE_SATA# 11

DREFSSCLK 6 DREFSSCLK# 6

DREFCLK 6 DREFCLK# 6

SLG8SP512T: AL8SP512K05

CLKREQ_F# : SRC8 CLKREQ_G# : SRC9 CLKREQ_H# : SRC10

B B

+3V

R464 10K_4

R466 *10K_4 R459 10K_4

R458 *10K_4

+3V

SEL_LCDCLK#

PCLK_ICH_R

CK505 0 : Pin 37,38 as SRC5 output 1 : pin 37,38 as PCI_STOP & CPU_STOP

CK505 0 : Pin 46,47 as SRC output 1 : Pin 46,47 as CPU output

C557

33p_4

C560

33p_4

CPU Clock select

A A

CPU_BSEL23 CPU_BSEL13 CPU_BSEL03

14.318MHz

REV:B MODIFY

R288 0_4

REV:B MODIFY

+1.05V +1.05V

R292 *1K_4

MCH_BSEL2

R290 *1K_4

CG_XIN

CG_XOUT

R293

2.2K_4

REV:C MODIFY

PU for ICS CLK GEN

0 : CPU & SRC overclock allow 1 : CPU & SRC overclock not allow

R441 0_4

SILEGO 0 : Pin 13,14 & 17,18 for Interna l VGA 1 : 27M & 27M_SS & SRC0 for external VGA

SILEGO 0 : Pin 46,47 as SRC output 1 : Pin 46,47 as CPU output

R453 10K_4

+3V

R443 10K_4

+3V

R454 10K_4

+3V

R457 10K_4

+3V

R496 *10K_4

REV:B MODIFY

R445 *1K_4

MCH_BSEL1

R448 *1K_4

NEW_CLKREQ#_R CLK_MCH_REQ# SATACLKREQ#_R

PCLK_PCM_R

REV:C MODIFY

MCH_BSEL06MCH_BSEL16MCH_BSEL26

Clock Gen I2C

+3V

PDAT_SMB11,14,16 SMBDT 9

PCLK_SMB11,14,16

Q29 2N7002

+3V

Q21 2N7002

R444

4.7K_4

SMBDT

R449

4.7K_4

SMBCK

BSEL Frequency Select Table

FSC FSB FSA Frequency

0 0

FSAMCH_BSEL0FSC

0 1 1

R306 0_4

REV:B MODIFY

+1.05V

R307 *1K_4

R308 *1K_4

R304

2.2K_4

SMBCK 9

0 0 1 1 0 0

Reserved for EMI

0 1 0 1 0 1

266Mhz0 133Mhz 200Mhz 166Mhz 333Mhz 100Mhz

400Mhz

Reserved

PCLK_LPC_DB PCLK_PCM

PCLK_591 CLKUSB_48

PCLK_ICH

14M_ICH

C575 22p_4

10p_4C574

REV:C MODIFY

*10p_4C576

C573 10p_4

10p_4C578

4.7p_4C546

PROJECT : ZO1

Quanta Computer Inc.

Size Document Number Rev

CLOCK GENERATOR CK505 W/REGULATOR

Date: Sheet

326Thursday, May 17, 2007

J4 L5 L4 K5

M3 N2

P5 P2 L2 P4 P1

U5 R3 W6 U4

U1 R4

T5 T3

W2 W5

W3 AA4 AB2 AA3

E2 G5 H5

F21

D20

B3 H4 C1 G2 G6

F4 G3

A22 A21

HOLE23 MDC_HOLE

HOLE14 MXM_HOLE

U21A

ADDRESS

CONTROL

HOLE25 MDC_HOLE

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]#

DATA

D[6]# D[7]# D[8]#

D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DINV[0]# DINV[1]# DINV[2]# DINV[3]#

DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]#

DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]#

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]#

ADSTB[0]# ADSTB[1]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# TRDY# HIT# HITM#

RS[0]# RS[1]# RS[2]#

HCLK

BCLK[0] BCLK[1]

CPU_SOCKET

UMA MODE: HOLE13,HOLE14 use FBZ01031010

MXM MODE: HOLE13,HOLE14 use FBZ01001010

HOLE7 CPU_HOLE

HOLE13 MXM_HOLE

PAD3 *EMIPAD

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_IERR#

H_RS#0 H_RS#1 H_RS#2

H_A#[35:3]5

D D

H_ADSTB0#5

H_ADSTB1#5

H_REQ#[4:0]5

C C

H_ADS#5 H_BNR#5 H_BPRI#5

H_DEFER#5

H_DRDY#5

H_DBSY#5

H_BREQ#05

H_INIT#11

H_LOCK#5

H_CPURST#5

H_TRDY#5

H_HIT#5

H_HITM#5

H_RS#[2:0]5

CLK_CPU_BCLK2

B B

CLK_CPU_BCLK#2

HOLE15

HOLE8

CPU_HOLE

HOLE17

HOLE16

MXM_HOLE

A A

PAD5 *EMIPAD

PAD6 *EMIPAD

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23

H25 N24 U22 AC20

H26 M26 AA26 AF24

J26 L26 Y26 AE25

HOLE5 DCB1_HOLE

PAD2 *EMIPAD

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

PAD1 *EMIPAD

HOLE6 DCB2_HOLE

H_D#[63:0] 5

H_DINV#[3:0] 5

H_DSTBP#[3:0] 5

H_DSTBN#[3:0] 5

HOLE18 NB_HOLE

HOLE19 MXM1_HOLE

HOLE30 *TP_HOLE

H_A20M#11

H_FERR#11

H_IGNNE#11

H_STPCLK#11

H_INTR11

H_NMI11

H_SMI#11

R120 *1K_4 R114 *1K_4

C48 *.1u/16V_4

CPU_BSEL02 CPU_BSEL12 CPU_BSEL22

HOLE31 TOP_HOLE

HOLE11 MXM1_HOLE

HOLE12

*H-C276D118P2-8

2 3 4

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

TRST# TMS TDO TDI TCK PREQ# PRDY# BPM[3]# BPM[2]# BPM[1]# BPM[0]#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]

GTLREF

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL[0] BSEL[1] BSEL[2]

H_GTLREF

ICH XDP / ITP

RESERVED

MISC

5 6 7

U21B

A6 A5

C4 D5

B4 A3

XDP_TRST# DBR# XDP_TMS XDP_TDO XDP_TDI XDP_TCK PREQ#

H_GTLREF

CPU_TEST1 CPU_TEST2

CPU_TEST4

HOLE32 *BATTERY_HOLE

HOLE33 *MB_HOLE

HOLE21

*H-TC217BC256D110P2

5 6 7

+1.05V

AB6 AB5 AB3 AA6 AC5 AC1 AC2 AC4 AD1 AD3 AD4

D22

AD26

C23 D25 C24

AF26

AF1 A26

B22 B23 C21

R42 1K/F_4

R45 2K/F_4

HOLE34 *MB_HOLE

2 3 4

M4 N5

T2 V3

B2 C3 D2

CPU_SOCKET

HOLE9 *H-C276D118P2-8

THERMAL

THERMDC

THERMDA

PROCHOT#

THERMTRIP#

DBR#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

SLP#

PSI#

PWRGOOD

HOLE2

*H-C276D118P2-8

2 3 4

HOLE3

*H-C276D118P2-8

2 3 4

HOLE27

*H-C276D118P2-8

2 3 4

XDP_TDO H_IERR# DBR#

PREQ# XDP_TMS XDP_TDI XDP_TCK XDP_TRST#

H_THERMDC

B25

H_THERMDA

A24

H_PROCHOT_R#

D21

THERMTRIP#_PWR

C20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1 E5

B5 D24

D7 AE6

HOLE1 *H-C276D118P2-8

HOLE22 *H-C276D118P2-8

HOLE26 *H-C276D118P2-8

R54 27.4/F_4 R53 54.9/F_4 R46 27.4/F_4 R49 54.9/F_4

R41 *54.9/F_4 R118 56.2/F_4 R119 54.9/F_4

R39 *54.9/F_4 R44 39/F_4 R51 150/F_4 R38 27.4/F_4 R36 680_4

5 6 7

ICH_DPRSTP# 6,11,21 H_DPSLP# 11 H_DPWR# 5

H_CPUSLP# 5 PSI# 21

H_PWRGD 11

+1.05V

HOLE4

*H-C276D118P2-8

2 3 4

HOLE28

*H-C276D118P2-8

2 3 4

9 ADOGND

HOLE20

*H-C276D118P2-8

2 3 4

5 6 7

REV:C MODIFY

HOLE29

*H-C276D118P2-8

2 3 4

HOLE10

*H-C276D118P2-8

2 3 4

SMBUS Address : 98

+3V

R82

KBSMDAT KBSMCLK

47_6

3V_THM

C131 .1u/16V_4

THERM_ALERT#_R

2ND_MBDATA19

2ND_MBCLK19

+1.05V

THERMTRIP#_PWR RR_THERMTRIP#

+1.05V

H_PROCHOT_R#

REV:D MODIFY for EMI reserved

5 6 7

+5V

C612 *.1u/16V_4

MAXIM 6657 : AL006657020 GMT G781 : AL000781101

+3V

R116

R117

10K_4

SDAT

SCLK

ALERT

VCC

GND

G781

R115 *0_4

R109 56_4 R90 33_4

R91

56.2/F_4

C613 *.1u/16V_4

OVT

6 2

DXP

DXN

2ND_MBDATA

2ND_MBCLK

IMVP_PWRGD6,11,19,21

R107 *0_4

MAX6648_OV# THERM_ALERT#_R

C138 2200p_4

+3V

Q13 2N7002

+3V

Q14 2N7002

REV:C MODIFY

C614 *.1u/16V_4

H_THERMDA

H_THERMDC

THERM_ALERT#

C615 *.1u/16V_4

10K_4

R92 10K_4

R93 10K_4

+1.05V

Q16

2N7002

R108 1K_4

Q15

MMBT3904

1 3

H_PROCHOT# 21

C616 *.1u/16V_4

.1u/16V_4C618 .1u/16V_4C619 .1u/16V_4C620

MAX6648_OV# 15

THERM_ALERT# 11

KBSMDAT

KBSMCLK

SYS_SHDN# 20

PROJECT : ZO1

Quanta Computer Inc.

Size Document Number Rev

CPU(1 of 2)/Thermal

Date: Sheet

426Thursday, May 17, 2007

+1.25V

CPU(Power)

C103

C442 10u/6.3V_8

D D

C C

B B

10u/6.3V_8

C434 10u/6.3V_8

C448 10u/6.3V_8

C77 10u/6.3V_8

C440 10u/6.3V_8

C121 10u/6.3V_8

C433 10u/6.3V_8

C78 10u/6.3V_8

C447 10u/6.3V_8

C439 10u/6.3V_8

C438 10u/6.3V_8

C444 10u/6.3V_8

C445 10u/6.3V_8

C123 10u/6.3V_8

C446 10u/6.3V_8

C81 10u/6.3V_8

C79

C441

10u/6.3V_8

C122

C443

10u/6.3V_8

C437

C96

10u/6.3V_8

C432

C455

10u/6.3V_8

REV:C Modify

C28

*330u/2.5V_7343

C80 10u/6.3V_8

C456 10u/6.3V_8

C102 10u/6.3V_8

C124 10u/6.3V_8

C457

330u/2.5V_7343

C83 *.1u/16V_4

EMI

C125 10u/6.3V_8

C95 10u/6.3V_8

C82 10u/6.3V_8

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

A7 A9

B7 B9

E7 E9

F7 F9

U21C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

CPU_SOCKET

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCC_COREVCC_CORE

+1.05V

C110

330u/2.5V_7343

+1.5V

H_VID0 21 H_VID1 21 H_VID2 21 H_VID3 21 H_VID4 21 H_VID5 21 H_VID6 21

R30 100/F_4

R32 100/F_4

C126 .1u/16V_4

.01u/16V_4C139 10u/6.3V_8C140

VCC_CORE

C106 .1u/16V_4

C90 .1u/16V_4

VCCSENSE 21

VSSSENSE 21

C86 .1u/16V_4

C89 .1u/16V_4

C97 .1u/16V_4

U21D

A4 A8

A11 A14 A16 A19 A23 AF2

B6 B8

B11 B13 B16 B19 B21 B24

C5 C8

C11 C14 C16 C19

C22 C25

D1 D4 D8

D11 D13 D16 D19 D23 D26

E3 E6 E8

E11 E14 E16 E19 E21 E24

F5 F8

F11 F13 F16 F19

F22 F25

G4 G1

G23 G26

H3 H6

H21 H24

J5 J22 J25

K4 K23 K26

L21 L24

M5 M22 M25

N4 N23 N26

P3 A25

VSS[082]

VSS[001] VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113] VSS[114]

VSS[033]

VSS[115]

VSS[034]

VSS[116]

VSS[035]

VSS[117]

VSS[036]

VSS[118]

VSS[037]

VSS[119]

VSS[038]

VSS[120]

VSS[039]

VSS[121]

VSS[040]

VSS[122]

VSS[041]

VSS[123]

VSS[042]

VSS[124]

VSS[043]

VSS[125]

VSS[044]

VSS[126]

VSS[045]

VSS[127]

VSS[046]

VSS[128]

VSS[047]

VSS[129]

VSS[048]

VSS[130]

VSS[049]

VSS[131]

VSS[050]

VSS[132]

VSS[051]

VSS[133]

VSS[052]

VSS[134]

VSS[053]

VSS[135]

VSS[054]

VSS[136]

VSS[055]

VSS[137]

VSS[056]

VSS[138]

VSS[057]

VSS[139]

VSS[058]

VSS[140]

VSS[059]

VSS[141]

VSS[060]

VSS[142]

VSS[061]

VSS[143]

VSS[062]

VSS[144]

VSS[063]

VSS[145]

VSS[064]

VSS[146]

VSS[065]

VSS[147]

VSS[066]

VSS[148]

VSS[067]

VSS[149]

VSS[068]

VSS[150]

VSS[069] VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081] VSS[162]

VSS[163]

CPU_SOCKET

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21

AF25

A A

Size Document Number Rev

CPU(2 of 2)Power

Date: Sheet

PROJECT : ZO1

Quanta Computer Inc.

526Thursday, May 17, 2007

GM965 QN12 : AJ0QN120T04 PM965 QN14 : AJ0QN140T04

M10 N12

W10

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9 AE11 AH12

AH5

AE7

AE5

AH2 AH13

E2 G2 G7 M6 H7 H3 G4

F3 N8 H2

N9 H5

P13

K9 M2

Y8 V4 M3

J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1

AJ9

AJ5 AJ6 AJ7

AJ2 AJ3

B3 C2

W1 W2

B6 E5

B9 A9

U22A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CRESTLINE

HOST

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_D#[63:0]3

D D

C C

B B

H_CPURST#3 H_CPUSLP#3

H_AVREF

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_A#[35:3] 3

H_ADS# 3 H_ADSTB0# 3 H_ADSTB1# 3 H_BNR# 3 H_BPRI# 3 H_BREQ#0 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 2 CLK_MCH_BCLK# 2 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3

H_DINV#[3:0] 3

H_DSTBN#[3:0] 3

H_DSTBP#[3:0] 3

H_REQ#[4:0] 3

H_RS#[2:0] 3

U22C

CRTIREF

H39 E39 E40 C37 D35 K40

L41 L43 N41 N40 D46 C45 D44 E42

G51 E51 F49

G50 E50 F48

G44 B47 B45

E44 A47 A45

E27 G27 K27

F27 L27 M35

P33

H32 G32 K29

F29 E29

K33 G35 F33 C32 E33

J40

J27

J29

CRESTLINE

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

PEG_COMPO

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

INT_LVDS_BKLT_PWM13

INT_LVDS_BLON10

LCD_INVCLK13

LCD_INVDAT13 INT_LVDS_EDIDCLK10 INT_LVDS_EDIDDATA10

INT_LVDS_DIGON10

INT_TXLCLKOUT-10 INT_TXLCLKOUT+10

INT_TXLOUT0-10 INT_TXLOUT1-10 INT_TXLOUT2-10

INT_TXLOUT0+10 INT_TXLOUT1+10 INT_TXLOUT2+10

INT_TV_COMP10

INT_TV_Y/G10

INT_TV_C/R10

R387 IV^2.2K_4

+3V

R388 IV^2.2K_4 R380 EV^0_4

R381 EV^0_4

REV:C MODIFY

INT_CRT_BLU10 INT_CRT_GRN10 INT_CRT_RED10

INT_CRT_DDCCLK10 INT_CRT_DDCDAT10

INT_HSYNC10

INT_VSYNC10

T51

LCD_INVCLK LCD_INVDAT

LVDS_IBG LVDS_VREF

INT_TV_COMP INT_TV_Y/G INT_TV_C/R

TV_DCONSEL_0 TV_DCONSEL_1

INT_CRT_BLU INT_CRT_GRN INT_CRT_RED

REV:B MODIFY

W: 10 mil

EXP_A_COMPX

N43 M43

PEG_RXN0

J51

PEG_RXN1

L51

PEG_RXN2

N47

PEG_RXN3

T45

PEG_RXN4

T50

PEG_RXN5

U40

PEG_RXN6

Y44

PEG_RXN7

Y40

PEG_RXN8

AB51

PEG_RXN9

W49

PEG_RXN10

AD44

PEG_RXN11

AD40

PEG_RXN12

AG46

PEG_RXN13

AH49

PEG_RXN14

AG45

PEG_RXN15

AG41

PEG_RXP0

J50

PEG_RXP1

L50

PEG_RXP2

M47

PEG_RXP3

U44

PEG_RXP4

T49

PEG_RXP5

T41

PEG_RXP6

W45

PEG_RXP7

W41

PEG_RXP8

AB50

PEG_RXP9

Y48

PEG_RXP10

AC45

PEG_RXP11

AC41

PEG_RXP12

AH47

PEG_RXP13

AG49

PEG_RXP14

AH45

PEG_RXP15

AG42

C_PEG_TXN0

N45

C_PEG_TXN1 PEG_TXN1

U39

C_PEG_TXN2

U47

C_PEG_TXN3

N51

C_PEG_TXN4

R50

C_PEG_TXN5

T42

C_PEG_TXN6

Y43

C_PEG_TXN7

W46

C_PEG_TXN8

W38

C_PEG_TXN9 PEG_TXN9

AD39

C_PEG_TXN10

AC46

C_PEG_TXN11

AC49

C_PEG_TXN12

AC42

C_PEG_TXN13

AH39

C_PEG_TXN14

AE49

C_PEG_TXN15

AH44

C_PEG_TXP0

M45

C_PEG_TXP1

T38

C_PEG_TXP2

T46

C_PEG_TXP3

N50

C_PEG_TXP4

R51

C_PEG_TXP5

U43

C_PEG_TXP6

W42

C_PEG_TXP7

Y47

C_PEG_TXP8

Y39

C_PEG_TXP9

AC38

C_PEG_TXP10

AD47

C_PEG_TXP11

AC50

C_PEG_TXP12

AD43

C_PEG_TXP13

AG39

C_PEG_TXP14

AE50

C_PEG_TXP15

AH43

R260 24.9/F_4

+VCCP_PEG

PEG_RXN[15:0] 10

PEG_RXP[15:0] 10

EV^.1u/10V_4C354 EV^.1u/10V_4C337 EV^.1u/10V_4C344 EV^.1u/10V_4C532 EV^.1u/10V_4C536 EV^.1u/10V_4C327 EV^.1u/10V_4C347 EV^.1u/10V_4C329 EV^.1u/10V_4C349 EV^.1u/10V_4C330 EV^.1u/10V_4C531 EV^.1u/10V_4C528 EV^.1u/10V_4C351 EV^.1u/10V_4C353 EV^.1u/10V_4C526 EV^.1u/10V_4C332

EV^.1u/10V_4C355 EV^.1u/10V_4C336 EV^.1u/10V_4C345 EV^.1u/10V_4C533 EV^.1u/10V_4C535 EV^.1u/10V_4C326 EV^.1u/10V_4C346 EV^.1u/10V_4C328 EV^.1u/10V_4C348 EV^.1u/10V_4C331 EV^.1u/10V_4C530 EV^.1u/10V_4C529 EV^.1u/10V_4C350 EV^.1u/10V_4C352 EV^.1u/10V_4C527 EV^.1u/10V_4C333

PEG_TXN0 PEG_TXN2

PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8

PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

PEG_TXN[15:0] 10

PEG_TXP[15:0] 10

+1.05V

A A

W: 10 mil / S: 20 mil

R349

221/F_4

H_SWING

R350

C474

100/F_4

.1u/16V_4

H_RCOMP

R348 24.9/F_4

W: 10 mil / S: 20 mil

H_SCOMP H_SCOMP#

+1.05V

R352 1K/F_4

R356

2K/F_4

R155 54.9/F_4 R164 54.9/F_4

C477 .1u/16V_4

REV:C MODIFY

+1.05V

H_AVREF

HVREF Width : 20mil Length < 100mil

<check list> For EV@ Connect to GND CRT R/G/B TV A/B/C HSYNC/VSYNC

R205 EV^0_4 R206 EV^0_4

0OHM (PD) FOR EV (TV)

R197 150/F_4 R198 150/F_4 R199 150/F_4

0OHM (PD) FOR EV (RGB)

R214 150/F_4 R216 150/F_4 R204 150/F_4

<check list> For IV@ Connect to 150ohm: CRT R/G/B TV A/B/C Connect to 30ohm: HSYNC/VSYNC

INT_HSYNC INT_VSYNC

INT_TV_COMP INT_TV_Y/G INT_TV_C/R

INT_CRT_BLU INT_CRT_GRN INT_CRT_RED

<check list & CRB> For Calero : 1.5K For Cresstline:2.4K

R247 IV^2.4K_4 R535 IV^0_4

REV:C MODIFY

IV&EV Dis/Enable setting

<check list & CRB> For Calero : 255 For Cresstline:1.3K/F For external VGA:0

R211 1.3K/F_4

<FAE> Flexible and safe

LVDS_IBG LVDS_VREF

CRTIREF

Size Document Number Rev

GMCH HOST & GRAPHICS

Date: Sheet

PROJECT : ZO1

Quanta Computer Inc.

626Thursday, May 17, 2007

All strap are sampled with respect to the leading edge of the GMCH PWROK Signal CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin

CFG[2:0]

CFG[4:3]

D D

CFG5

CFG6

CFG7

CFG8

CFG9

CFG[11:10]

CFG[13:12]

C C

CFG[15:14]

CFG16

CFG[18:17]

SDVO_CTRLDATA

CFG19

CFG20

B B

+3V

A A

FSB Frequency Select

Reserved

DMI X2 Select

001 = FSB 533 MHz 010 = FSB 800 MHz

011 = FSB 667 MHz

0 = DMI X2 1 = DMI X4(Default)

Reserved

CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

0 = Reserved 1 = Mobile CPU(Default)

0 = Normal mode 1 = Low Power mode

0 = Reverse Lanes 1 = Normal operation(Default)

Reserved

XOR/ALLZ

00 = Reserved 01 = XOR Mode Enable 10 = All-Z Mode Enabled 11 = Normal operation(Default)

Reserved

FSB Dynamic ODT

Reserved VCC selectCFG18 0 = 1.05V (Default)

SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

R192 *4.02K/F_4 R371 *4.02K/F_4 R183 *4.02K/F_4 R185 *4.02K/F_4 R191 *4.02K/F_4 R385 *4.02K/F_4 R386 *4.02K/F_4

MCH_CFG_5 MCH_CFG_9 MCH_CFG_16 MCH_CFG_12 MCH_CFG_13 MCH_CFG_19 MCH_CFG_20

0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

1 = 1.5V 0 = No SDVO Card present(Default)

1 = SDVO Card Present

0 = Normal operation(Default) 1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

SMA_MA149 SMB_MA149

T82 T83

MCH_BSEL02 MCH_BSEL12 MCH_BSEL22

T68 T66

T9 T19 T13

T20 T24

T18 T17

T15 T39

T12

R436 0_4 R219 0_4

R236 0_4 R187 100_4

PM_BMBUSY#11 ICH_DPRSTP#3,11,21

EXTTS#09 EXTTS#19

IMVP_PWRGD3,11,19,21

PLTRST#_NB11

PM_DPRSLPVR11,21

MCH_RSVD37 MCH_RSVD38

MCH_BSEL0 MCH_BSEL1 MCH_BSEL2 MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 MCH_CFG_19 MCH_CFG_20

PM_BMBUSY#_R ICH_DPRSTP#_R

PM_EXTTS#1_R RST_IN#_MCH

THRMTRIP#_MCH

GM965 QN12 : AJ0QN120T04 PM965 QN14 : AJ0QN140T04

U22B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

NC_10

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2 R32

NC_16 TEST_2

CRESTLINE

CFGRSVD

SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4

SM_CK#_0 SM_CK#_1 SM_CK#_3

SM_CK#_4 SM_CKE_0

SM_CKE_1 SM_CKE_3 SM_CKE_4

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0 SM_VREF_1

DDR MUXINGCLKDMI

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

GFX_VR_EN

GRAPHICS VIDME

CL_DATA

CL_PWROK

CL_RST# CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

CL_CLK

TEST_1

AV29 BB23 BA25 AV23

AW30 BA23 AW25 AW23

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

M_RCOMP

BL15

M_RCOMP#

BK14

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31

SMDDR_VREF_MCH

AR49 AW4

DREFCLK

B42

DREFCLK#

C42

DREFSSCLK

H48

DREFSSCLK#

H47 K44

K45

DMI_TXN0

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

DFGT_VID_0

E35

DFGT_VID_1

A39

DFGT_VID_2

C38

DFGT_VID_3

B39

DFGT_VR_EN

E36

AM49 AK50 AT43 AN49

+1.25V_CL_VREF

AM50

SDVO_CTRLCLK

H35

SDVO_CTRLDATA

K36

CLK_MCH_OE#

G39 G40

A37

GMCH_TEST2

CLK_SDRAM0 9 CLK_SDRAM1 9 CLK_SDRAM3 9 CLK_SDRAM4 9

CLK_SDRAM0# 9 CLK_SDRAM1# 9 CLK_SDRAM3# 9 CLK_SDRAM4# 9

SM_CKE0 9 SM_CKE1 9 SM_CKE3 9 SM_CKE4 9

SM_CS0# 9 SM_CS1# 9 SM_CS2# 9 SM_CS3# 9

SM_ODT0 9 SM_ODT1 9 SM_ODT2 9 SM_ODT3 9

R168 *10K_6 R169 *10K_6

R217 20K_4

+0.9VSUS

R170 0_6

+1.8VSUS

DREFCLK 2 DREFCLK# 2 DREFSSCLK 2 DREFSSCLK# 2

CLK_PCIE_3GPLL 2 CLK_PCIE_3GPLL# 2

DMI_TXN[3:0] 11

DMI_TXP[3:0] 11

DMI_RXN[3:0] 11

DMI_RXP[3:0] 11

CL_CLK0 11

CL_DATA0 11 ICH_PWOK 11 CL_RST#0 11

REV:B MODIFY REV:C MODIFY

R533 EV^0_4 R534 EV^0_4

CLK_MCH_OE# 2 MCH_ICH_SYNC# 11

Width : 20mil Length < 500mil

+1.8VSUS

DREFSSCLK# DREFSSCLK

R215

1K/F_4

R Value select For Calero : 80.6ohm For Cresstline:20ohm But check list use 80.6ohm

M_RCOMP#

R173 20/F_4

M_RCOMP

R180 20/F_4

R212

3.01K/F_4

R203 1K/F_4

RN31 EV^0_4P2R

4 3

C264 .01u/16V_4

C266 .01u/16V_4

REV:C MODIFY

DREFCLK# DREFCLK

<design guide> If no use DREFCLK PD and DREFCLK# PU

+3V

R242 IV^30K_4

+1.05V

RN32 EV^0_4P2R

+1.25V_CL_VREF

R246 10K_4 R237 10K_4

DFGT_VR_EN

REV:C MODIFY

R422 IV^22K_4

R222 IV^22K_4 R421 IV^22K_4 R423 IV^22K_4

4 3

EXTTS#0 EXTTS#1

R235 IV^100K_4

SM_RCOMP_VOH

SM_RCOMP_VOL

C319 .1u/16V_4

DFGT_VID_2

DFGT_VID_0 DFGT_VID_1 DFGT_VID_3

+1.8VSUS

C282

2.2u/6.3V_6

C277

2.2u/6.3V_6

+1.25V

R431 1K/F_4

R433 392/F_6

PROJECT : ZO1

Quanta Computer Inc.

Size Document Number Rev

GMCH DMI & STRAP

Date: Sheet

726Thursday, May 17, 2007

GM965 QN12 : AJ0QN120T04

SMA_MD[63..0]9

D D

C C

SMB_MD[63..0]9

B B

A A

SMA_MD0 SMA_MD1 SMA_MD2 SMA_MD3 SMA_MD4 SMA_MD5 SMA_MD6 SMA_MD7 SMA_MD8 SMA_MD9 SMA_MD10 SMA_MD11 SMA_MD12 SMA_MD13 SMA_MD14 SMA_MD15 SMA_MD16 SMA_MD17 SMA_MD18 SMA_MD19 SMA_MD20 SMA_MD21 SMA_MD22 SMA_MD23 SMA_MD24 SMA_MD25 SMA_MD26 SMA_MD27 SMA_MD28 SMA_MD29 SMA_MD30 SMA_MD31 SMA_MD32 SMA_MD33 SMA_MD34 SMA_MD35 SMA_MD36 SMA_MD37 SMA_MD38 SMA_MD39 SMA_MD40 SMA_MD41 SMA_MD42 SMA_MD43 SMA_MD44 SMA_MD45 SMA_MD46 SMA_MD47 SMA_MD48 SMA_MD49 SMA_MD50 SMA_MD51 SMA_MD52 SMA_MD53 SMA_MD54 SMA_MD55 SMA_MD56 SMA_MD57 SMA_MD58 SMA_MD59 SMA_MD60 SMA_MD61 SMA_MD62 SMA_MD63

SMB_MD0 SMB_MD1 SMB_MD2 SMB_MD3 SMB_MD4 SMB_MD5 SMB_MD6 SMB_MD7 SMB_MD8 SMB_MD9 SMB_MD10 SMB_MD11 SMB_MD12 SMB_MD13 SMB_MD14 SMB_MD15 SMB_MD16 SMB_MD17 SMB_MD18 SMB_MD19 SMB_MD20 SMB_MD21 SMB_MD22 SMB_MD23 SMB_MD24 SMB_MD25 SMB_MD26 SMB_MD27 SMB_MD28 SMB_MD29 SMB_MD30 SMB_MD31 SMB_MD32 SMB_MD33 SMB_MD34 SMB_MD35 SMB_MD36 SMB_MD37 SMB_MD38 SMB_MD39 SMB_MD40 SMB_MD41 SMB_MD42 SMB_MD43 SMB_MD44 SMB_MD45 SMB_MD46 SMB_MD47 SMB_MD48 SMB_MD49 SMB_MD50 SMB_MD51 SMB_MD52 SMB_MD53 SMB_MD54 SMB_MD55 SMB_MD56 SMB_MD57 SMB_MD58 SMB_MD59 SMB_MD60 SMB_MD61 SMB_MD62 SMB_MD63

PM965 QN14 : AJ0QN140T04

U22D

AR43

SA_DQ_0

AW44

SA_DQ_1

BA45

SA_DQ_2

AY46

SA_DQ_3

AR41

SA_DQ_4

AR45

SA_DQ_5

AT42

SA_DQ_6

AW47

SA_DQ_7

BB45

SA_DQ_8

BF48

SA_DQ_9

BG47

SA_DQ_10

BJ45

SA_DQ_11

BB47

SA_DQ_12

BG50

SA_DQ_13

BH49

SA_DQ_14

BE45

SA_DQ_15

AW43

SA_DQ_16

BE44

SA_DQ_17

BG42

SA_DQ_18

BE40

SA_DQ_19

BF44

SA_DQ_20

BH45

SA_DQ_21

BG40

SA_DQ_22

BF40

SA_DQ_23

AR40

SA_DQ_24

AW40

SA_DQ_25

AT39

SA_DQ_26

AW36

SA_DQ_27

AW41

SA_DQ_28

AY41

SA_DQ_29

AV38

SA_DQ_30

AT38

SA_DQ_31

AV13

SA_DQ_32

AT13

SA_DQ_33

AW11

SA_DQ_34

AV11

SA_DQ_35

AU15

SA_DQ_36

AT11

SA_DQ_37

BA13

SA_DQ_38

BA11

SA_DQ_39

BE10

SA_DQ_40

BD10

SA_DQ_41

BD8

SA_DQ_42

AY9

SA_DQ_43

BG10

SA_DQ_44

AW9

SA_DQ_45

BD7

SA_DQ_46

BB9

SA_DQ_47

BB5

SA_DQ_48

AY7

SA_DQ_49

AT5

SA_DQ_50

AT7

SA_DQ_51

AY6

SA_DQ_52

BB7

SA_DQ_53

AR5

SA_DQ_54

AR8

SA_DQ_55

AR9

SA_DQ_56

AN3

SA_DQ_57

AM8

SA_DQ_58

AN10

SA_DQ_59

AT9

SA_DQ_60

AN9

SA_DQ_61

AM9

SA_DQ_62

AN11

SA_DQ_63

CRESTLINE

U22E

AP49

SB_DQ_0

AR51

SB_DQ_1

AW50

SB_DQ_2

AW51

SB_DQ_3

AN51

SB_DQ_4

AN50

SB_DQ_5

AV50

SB_DQ_6

AV49

SB_DQ_7

BA50

SB_DQ_8

BB50

SB_DQ_9

BA49

SB_DQ_10

BE50

SB_DQ_11

BA51

SB_DQ_12

AY49

SB_DQ_13

BF50

SB_DQ_14

BF49

SB_DQ_15

BJ50

SB_DQ_16

BJ44

SB_DQ_17

BJ43

SB_DQ_18

BL43

SB_DQ_19

BK47

SB_DQ_20

BK49

SB_DQ_21

BK43

SB_DQ_22

BK42

SB_DQ_23

BJ41

SB_DQ_24

BL41

SB_DQ_25

BJ37

SB_DQ_26

BJ36

SB_DQ_27

BK41

SB_DQ_28

BJ40

SB_DQ_29

BL35

SB_DQ_30

BK37

SB_DQ_31

BK13

SB_DQ_32

BE11

SB_DQ_33

BK11

SB_DQ_34

BC11

SB_DQ_35

BC13

SB_DQ_36

BE12

SB_DQ_37

BC12

SB_DQ_38

BG12

SB_DQ_39

BJ10

SB_DQ_40

BL9

SB_DQ_41

BK5

SB_DQ_42

BL5

SB_DQ_43

BK9

SB_DQ_44

BK10

SB_DQ_45

BJ8

SB_DQ_46

BJ6

SB_DQ_47

BF4

SB_DQ_48

BH5

SB_DQ_49

BG1

SB_DQ_50

BC2

SB_DQ_51

BK3

SB_DQ_52

BE4

SB_DQ_53

BD3

SB_DQ_54

BJ2

SB_DQ_55

BA3

SB_DQ_56

BB3

SB_DQ_57

AR1

SB_DQ_58

AT3

SB_DQ_59

AY2

SB_DQ_60

AY3

SB_DQ_61

AU2

SB_DQ_62

AT2

SB_DQ_63

CRESTLINE

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS# SA_DM_0

SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

SB_BS_0

SB_BS_1

SB_BS_2

SB_CAS#

SB_DM_0

SB_DM_1

SB_DM_2

SB_DM_3

SB_DM_4

SB_DM_5

SB_DM_6

SB_DM_7 SB_DQS_0

SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0

SB_MA_1

SB_MA_2

SB_MA_3

SB_MA_4

SB_MA_5

SB_MA_6

SB_MA_7

SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

BB19 BK19 BF29

BL17 AT45

BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

AY17 BG18 BG36

BE17 AR50

BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

SMA_DM0 SMA_DM1 SMA_DM2 SMA_DM3 SMA_DM4 SMA_DM5 SMA_DM6 SMA_DM7

SMA_DQS0 SMA_DQS1 SMA_DQS2 SMA_DQS3 SMA_DQS4 SMA_DQS5 SMA_DQS6 SMA_DQS7 SMA_DQS0# SMA_DQS1# SMA_DQS2# SMA_DQS3# SMA_DQS4# SMA_DQS5# SMA_DQS6# SMA_DQS7#

SMA_MA0 SMA_MA1 SMA_MA2 SMA_MA3 SMA_MA4 SMA_MA5 SMA_MA6 SMA_MA7 SMA_MA8 SMA_MA9 SMA_MA10 SMA_MA11 SMA_MA12 SMA_MA13

SMB_DM0 SMB_DM1 SMB_DM2 SMB_DM3 SMB_DM4 SMB_DM5 SMB_DM6 SMB_DM7

SMB_DQS0 SMB_DQS1 SMB_DQS2 SMB_DQS3 SMB_DQS4 SMB_DQS5 SMB_DQS6 SMB_DQS7 SMB_DQS0# SMB_DQS1# SMB_DQS2# SMB_DQS3# SMB_DQS4# SMB_DQS5# SMB_DQS6# SMB_DQS7#

SMB_MA0 SMB_MA1 SMB_MA2 SMB_MA3 SMB_MA4 SMB_MA5 SMB_MA6 SMB_MA7 SMB_MA8 SMB_MA9 SMB_MA10 SMB_MA11 SMB_MA12 SMB_MA13

SMA_BA0 9 SMA_BA1 9 SMA_BA2 9

SMA_CAS# 9 SMA_DM0 9

SMA_DM1 9 SMA_DM2 9 SMA_DM3 9 SMA_DM4 9 SMA_DM5 9 SMA_DM6 9 SMA_DM7 9

SMA_DQS0 9 SMA_DQS1 9 SMA_DQS2 9 SMA_DQS3 9 SMA_DQS4 9 SMA_DQS5 9 SMA_DQS6 9 SMA_DQS7 9 SMA_DQS0# 9 SMA_DQS1# 9 SMA_DQS2# 9 SMA_DQS3# 9 SMA_DQS4# 9 SMA_DQS5# 9 SMA_DQS6# 9 SMA_DQS7# 9

SMA_MA[13..0] 9

SMA_RAS# 9

SMA_WE# 9

SMB_BA0 9 SMB_BA1 9 SMB_BA2 9

SMB_CAS# 9 SMB_DM0 9

SMB_DM1 9 SMB_DM2 9 SMB_DM3 9 SMB_DM4 9 SMB_DM5 9 SMB_DM6 9 SMB_DM7 9

SMB_DQS0 9 SMB_DQS1 9 SMB_DQS2 9 SMB_DQS3 9 SMB_DQS4 9 SMB_DQS5 9 SMB_DQS6 9 SMB_DQS7 9 SMB_DQS0# 9 SMB_DQS1# 9 SMB_DQS2# 9 SMB_DQS3# 9 SMB_DQS4# 9 SMB_DQS5# 9 SMB_DQS6# 9 SMB_DQS7# 9

SMB_MA[13..0] 9

SMB_RAS# 9

SMB_WE# 9

REV:C MODIFY

C334

330u/2.5V_7343

REV:B MODIFY

C271

10u/6.3V_8

C270

.22u/10V_4 C269

.22u/10V_4 C251

.1u/16V_4

REV:B MODIFY

C273

10u/6.3V_8

C208

.22u/10V_4 C186

.22u/10V_4 C183

.1u/16V_4 C287

.1u/16V_4 C222

.1u/16V_4

+1.05V

U22F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37 A3

VCC_NCTF_37 VSS_SCB1

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

+1.05V

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE

VSS NCTF

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

B2 C1 BL1 BL51 A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

+1.05V

AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13

AC39 AC43

AC47

AD21 AD26 AD29

AD41 AD45 AD49

AD50 AE10

AE14 AF20

AF23 AF24 AF31

AG38 AG43 AG47 AG50

AH40 AH41

AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM41 AM45

AN38 AN39 AN43

AP48 AP50 AR11

AR39 AR44 AR47

AT10 AT14 AT41 AT49

AU23 AU29

AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

AC3

AD1

AD3

AD5 AD8

AG2

AH3

AH7 AH9

AM3 AM4

AN1

AN5 AN7

AR2

AR7

AU1

AU3

A13 A15 A17 A24

AE6

AL1

AP4

U22I

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CRESTLINE

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

C46 C50

D13 D24

D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F40 F50

G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

H24 H28

H45 J11 J16

J24 J28 J33 J35 J39

K12 K47

L17 L20 L24 L28

L33

L49 M28 M42 M46 M49

M50 N11

N14 N17 N29 N32 N36 N39 N44 N49

P19 P23 P50

R49

T39

T43

T47 U41 U45 U50

K8 L1

M5 M9

N7 P2 P3

V2 V3

U22J

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243

VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286

CRESTLINE

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

PROJECT : ZO1

Size Document Number Rev

GMCH DDR & GND

Date: Sheet

Quanta Computer Inc.

REV:C MODIFY

826Thursday, May 17, 2007

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