Acer eMachines E520, eMachines E720 Schematics

1 1

Compal Confidential

2 2

KAWE0 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

3 3

2008-07-28

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

145Wednesday, July 30, 2008

Compal Confidential

Model Name : KAWE0

Fan Control

page 4

File Name : LA-4431P P/N : DA600009500 (RVE0)

1 1

P/N : DA600009510 (RVE1)

LCD Conn.

page 17

CRT Conn.

page 18

Intel Penryn Processor

uPGA-478 Package

(Socket P)

H_A#(3..35) H_D#(0..63)

667/800/1066MHz

page 4,5,6

FSB

Intel Cantiga

LVDS

uFCBGA-1329

page 7,8,9,10,11,12,13

Thermal Sensor

ADM7421ARMZ

page 4

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 533/667

Card Reader JMB385

page 24

port 0

PCI-Express

S-ATA

port 1

CDROM Conn.

page 23page 23

2 2

New Card Socket

MINI Card x1

WLAN

page 27page 28

LAN(GbE)

Realtek RTL8111C

page 25

SATA HDD

RJ45

page 26

Conn.

DMI

Intel ICH9-M

BGA-676

page 19,20,21,22

C-Link

USB conn x2

USB port 0, 2

page 28 page 17

3.3V 48MHz

3.3V 24.576MHz/48Mhz

USB

LPC BUS

3 3

RTC CKT.

page 20

Power On/Off CKT.

page 31

DC/DC Interface CKT.

page 34

LS-4391P

POWER/B Conn.

page 30

LS-4392P

LID SW/B Conn.

USB port 4

page 30

LS-4393P

LED/B Conn.

page 30

Touch Pad

ENE KB926

page 30

page 29

Int.KBD

page 30

BIOS

page 30

Clock Generator

ICS9LPRS387

page 16

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

Bluetooth Conn

page 28

MDC 1.5 Conn

page 31

HD Audio

page 14,15

CMOS Camera

HDA Codec

ALC268

page 32

Audio AMP

page 33

Phone Jack x3

page 33

Power Circuit DC/DC

4 4

page 35,36,37,38 39,40,41,42

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

245Wednesday, July 30, 2008

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+ +CPU_CORE +0.9VS 0.9V switched power rail for DDR terminator +1.05VS +1.25VS 1.25V switched power rail ON OFF OFF +1.5V 1.5V power rail for HDA ON ON OFF +1.5VS +1.8V +1.8VS 1.8V switched power rail +2.5VS +3VALW +3V +3V_LAN +3VS +5VALW +5VS +VSB VSB always on power rail ON ON* +RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V power rail for SB

3.3V power rail for LAN

3.3V switched power rail 5V always on power rail 5V switched power rail

S1 S3 S5

N/A N/A N/A

ON OFF ON OFF ON OFF OFF

ON OFF OFF ON ON ON ON ON ON ON ONXX ON ON

ON ON

N/AN/AN/A OFF OFF

OFF OFF

OFF

ON ON*

OFF

ON*

OFFON

OFF

ONON

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

OFF

AD_BID

ON ON

OFF

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

LOW

OFF

max

BOARD ID Table BTO Option Table

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

1.0 1A

BTO Item BOM Structure

EC SM Bus1 address

3 3

Device

Smart Battery EEPROM(24C16/02) GMT G781-1

Address Address

1010 000X b 1001 101X b

EC SM Bus2 address

Device

ADI ADT7421

1001 100X b0001 011X b

8111C 8111C@ 8102E 8102E@

ICH9M SM Bus address

Device

Clock Generator (ICS9LPRS387, SLG8SP556V)

DDR DIMM0 DDR DIMM2

4 4

Address

1101 001Xb

1001 000Xb 1001 010Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

345Wednesday, July 30, 2008

H_A#[3..35]<7>

H_REQ#[0..4]<7>

H_RS#[0..2]<7>

D D

C C

B B

BSEL2 BSEL1 BSEL0 BCLK

000266 010200

A A

H_A#[3..35] H_REQ#[0..4] H_RS#[0..2]

JCPU1A

AA4 AB2 AA3

D22

J4 L5 L4

J1 N3 P5 P2

L2 P4 P1 R1

K3 H2 K2

L1 Y2

U5 R3

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

V1 A6

A5 C4

D5 C6 B4 A3

N5 T2 V3 B2 D2

D3 F6

16601

JCPU1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

Penryn CONN@

CONN@

ADDR GROUP_0

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP_1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H_PROCHOT#

H1 E2 G5

H5 F21 E1

H_IERR#

D20 B3

H_RESET#

H_RS#0

H_RS#1

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6 AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

H_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25 C7

A22 A21

Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

+1.05VS

R39

R39 56_0402_5%

56_0402_5% @

3 1

Q2 MMBT3904_SOT23-3

MMBT3904_SOT23-3 @

H_ADS# <7> H_BNR# <7> H_BPRI# <7>

H_DEFER# <7> H_DRDY# <7> H_DBSY# <7>

H_BR0# <7>

H_INIT# <20> H_LOCK# <7> H_RESET# <7>

H_TRDY# <7> H_HIT# <7>

H_HITM# <7>

XDP_DBRESET# <21>

H_THERMTRIP# <8,20>

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

OCP# <21>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EN_DFAN1<29>

EN_DFAN1 VSET

2007/09/20 2008/09/20

1 2

R27 330_0402_5%R27 330_0402_5%

20080430 Add soft-start for +5VS drop issue

H_THERMDA

2200P_0402_50V7K

H_THERMDC

Compal Secret Data

+VCC_FAN1

C94

Deciphered Date

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15

H_ADSTB#0<7>

H_ADSTB#1<7>

H_A20M#<20>

H_FERR#<20>

H_IGNNE#<20>

H_STPCLK#<20>

H_INTR<20>

H_NMI<20>

H_SMI#<20>

H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

+5VS

C427

0.01U_0402_16V7K

XDP_TDI

XDP_TMS XDP_BPM#5

H_PROCHOT# H_IERR#

XDP_TRST#

XDP_TCK

+3VS

C10 10U_0805_10V4ZC10 10U_0805_10V4Z

1 2

VEN

VIN

VSET

G993P1UF_SOP8

Change to SA000022J00<RICHTEK> 20080227

FAN_SPEED1<29>

R17 54.9_0402_1%R17 54.9_0402_1%

1 2

R16 54.9_0402_1%R16 54.9_0402_1%

1 2

R8 54.9_0402_1%

1 2

R32 56_0402_5%R32 56_0402_5% R31 56_0402_5%R31 56_0402_5%

R13 54.9_0402_1%R13 54.9_0402_1% R7 54.9_0402_1%R7 54.9_0402_1%

1 2

C95

0.1U_0402_16V4Z

1 2

VDD

THERM#

EMC1402-1-ACZL-TR_MSOP8

FAN1 Conn

GND

+3VS

R299

R299 10K_0402_5%

10K_0402_5%

C393

C393 1000P_0402_50V7K

1000P_0402_50V7K

12 12

SMCLK

SMDATA

ALERT#

GND

+5VS

D2 1SS355_SOD323-2

1SS355_SOD323-2

1 2

BAS16_SOT23-3

BAS16_SOT23-3 C396

C396

10U_0805_10V4Z

1 2

C399

1000P_0402_50V7K

1 2

40mil

+VCC_FAN1

+1.05VS

JP12

1 2 3

ACES_85205-03001

ACES_85205-03001 CONN@

CONN@

left NC if no ITP 39Ohm

8 7 6 5

Title

Size Document Number Rev

Date: Sheet

1 2

R541

R541 10K_0402_5%

10K_0402_5%

401590

EC_SMB_CK2 <29> EC_SMB_DA2 <29>

+3VS

Compal Electronics, Inc.

SCHEMATICS, MB A4431

445Wednesday, July 30, 2008

H_D#[0..63]

JCPU1B

G22 G25

G24

H22

H23 H26

H25

N22

R23 M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

E22 F24 E26

F23 E25

E23 K24

J24 J23

F26 K22

J26

K25 P26

L23 L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

JCPU1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

Penryn CONN@

CONN@

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

DSTBN[2]#

DSTBP[2]#

DINV[2]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DSTBN[3]#

DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_D#0

PAD

PAD PAD

PAD

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTL_REF0

@ @

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

D D

H_DSTBN#0<7> H_DSTBN#2 <7> H_DSTBP#0<7> H_DSTBP#2

H_DINV#0<7>

C C

Trace Close CPU < 0.5'

Width=4 mil , Spacing: 15mil (55Ohm)

B B

R287

R287 1K_0402_1%

1K_0402_1%

R289

R289 2K_0402_1%

2K_0402_1%

+1.05VS

1 2

H_DSTBN#1<7> H_DSTBN#3 <7> H_DSTBP#1<7> H_DSTBP#3 <7>

H_DINV#1<7>

R317 1K_0402_5%@R317 1K_0402_5%@ R316 1K_0402_5%@R316 1K_0402_5%@

C381 0.1U_0402_16V4Z@C381 0.1U_0402_16V4Z@

1 2

12 12

T4 T2

T2 T13

T13

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_PWRGOOD H_CPUSLP#

R295 27.4_0402_1%R295 27.4_0402_1% R291 54.9_0402_1%R291 54.9_0402_1% R10 27.4_0402_1%R10 27.4_0402_1% R12 54.9_0402_1%R12 54.9_0402_1%

H_DINV#2 <7>

H_DINV#3 <7>

1 2 1 2 1 2 1 2

H_DPRSTP# <8,20,42> H_DPSLP# <20> H_DPWR# <7> H_PWRGOOD <20> H_CPUSLP# <7> PSI#

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

<42>

H_D#[0..63] <7>

<7>

+CPU_CORE

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A7 A9

B7 B9

E7 E9

F7 F9

JCPU1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

Penryn CONN@

CONN@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

+CPU_CORE

VCCSENSE

VSSSENSE

C85

<42>

0.01U_0402_16V7K

1 2

C85

CPU_VID0 <42> CPU_VID1 CPU_VID2 <42> CPU_VID3 <42> CPU_VID4 <42> CPU_VID5 <42> CPU_VID6 <42>

R286 100_0402_1%R286 100_0402_1%

R285 100_0402_1%R285 100_0402_1%

+1.05VS

20mils

C93

10U_0805_10V4Z

VCCSENSE <42>

VSSSENSE

+1.5VS

+CPU_CORE

<42>

A A

Security Classification

2007/09/20 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

401590

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

545Wednesday, July 30, 2008

+CPU_CORE +CPU_CORE

JCPU1D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

D D

C C

B B

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

Penryn CONN@

CONN@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

C378

C378 330U_D2E_2.5VM_R9@

330U_D2E_2.5VM_R9@

+CPU_CORE

C409

10U_0805_6.3V6M

+CPU_CORE

C21

10U_0805_6.3V6M

+CPU_CORE

C78

10U_0805_6.3V6M

+CPU_CORE

C395

10U_0805_6.3V6M

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

+1.05VS

C73

330U_D2E_2.5VM_R15

2 x 330uF(6mOhm/2) 2 x 330uF(6mOhm/2)

C98

330U_D2E_2.5VM_R9

C377

330U_D2E_2.5VM_R9

South Side Secondary North Side Secondary

C413

10U_0805_6.3V6M

C390

10U_0805_6.3V6M

C68

10U_0805_6.3V6M

C70

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

C64

(Place these capacitors on South side,Secondary Layer)

C20

10U_0805_6.3V6M

C19

10U_0805_6.3V6M

C18

10U_0805_6.3V6M

C17

10U_0805_6.3V6M

C394

10U_0805_6.3V6M

(Place these capacitors on North side,Secondary Layer)

C77

10U_0805_6.3V6M

C76

10U_0805_6.3V6M

C75

10U_0805_6.3V6M

C386

10U_0805_6.3V6M

C382

(Place these capacitors on South side,Primary Layer)

C391

10U_0805_6.3V6M

C384

10U_0805_6.3V6M

C385

10U_0805_6.3V6M

C410

10U_0805_6.3V6M

C383

10U_0805_6.3V6M

(Place these capacitors on North side,Primary Layer)

C,uF ESR, mohm ESL,nH 4X330uF 6m ohm/4 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32

C30

0.1U_0402_16V4Z

C16

C13

0.1U_0402_16V4Z

C31

0.1U_0402_16V4Z

C29

0.1U_0402_16V4Z

C61

10U_0805_6.3V6M@

C60

C403

C65

C411

C402

10U_0805_6.3V6M@

C69

10U_0805_6.3V6M@

C59

10U_0805_6.3V6M@

C412

10U_0805_6.3V6M@

A A

Security Classification

2007/09/20 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

645Wednesday, July 30, 2008

U31A

H_D#[0..63]<5>

D D

+1.05VS

R69

R69 221_0402_1%<BOM Structure>

221_0402_1%<BOM Structure>

H_SWING

width=10mil

C C

1 2

B B

width:spacing=10mil:20mil (<0.5")

R68

R68 100_0402_1%

100_0402_1%

H_RCOMP

R334

24.9_0402_1%

+1.05VS

C155

0.1U_0402_16V4Z

width=10mil

R77

R77 1K_0402_1%

1K_0402_1%

1 2 12

R74

R74 2K_0402_1%

2K_0402_1%

C161

C161 @

0.1U_0402_16V4Z

H_RESET#<4>

H_CPUSLP#<5>

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_RESET# H_CPUSLP#

H_AVREF

U31A

H_D#_0

H_D#_1

H_D#_2

H_D#_3

H_D#_4

H_D#_5

H_D#_6

H_D#_7

H_D#_8

H_D#_9

H_D#_10

M11

H_D#_11

H_D#_12

H_D#_13

N12

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

P13

H_D#_27

H_D#_28

H_D#_29

N10

H_D#_30

H_D#_31

H_D#_32

AD14

H_D#_33

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

H_D#_38

H_D#_39

AA8

H_D#_40

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

H_SWING

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[3..35] <4>

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#[0..4] <4>

H_RS#[0..2] <4>

U31

within 100mil to Ball A9,B9

A A

Security Classification

2007/09/20 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

GM45

GM@

745Wednesday, July 30, 2008

D D

All RSVD balls on GMCH should be left No Connect.

C C

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

PM_EXTTS#0

VGATE<16,21,42>

+1.05VS

R371

54.9_0402_1%

54.9_0402_1% R366

R366

1 2

330_0402_5%

1 2

R118 10K_0402_5%R118 10K_0402_5% R121 10K_0402_5%R121 10K_0402_5% R126 10K_0402_5%R126 10K_0402_5%

H_THERMTRIP#<4,20> PM_DPRSLPVR<21,42>

PM_EXTTS#1

1 2

MCH_CLKREQ#

1 2

Use VGATE for GMCH_PWROK

VGATE

1 2

R143 0_0402_5%@R143 0_0402_5%@

ICH_PWROK

1 2

R144 0_0402_5%R144 0_0402_5%

PM_SYNC#<21> H_DPRSTP#<5,20,42> PM_EXTTS#0<14> PM_EXTTS#1<15>

PLT_RST#<19,21,24,25,29>

R82 0_0402_5%R82 0_0402_5% R73 0_0402_5%R73 0_0402_5%

R75 100_0402_5%R75 100_0402_5% R85 0_0402_5%R85 0_0402_5% R80 0_0402_5%R80 0_0402_5%

+3VS

R202

R202 1K_0402_5%

1K_0402_5%

Q18

MMBT3904_SOT23-3

3 1

1 2 1 2

1 2 1 2 1 2

+3VS

GMCH_PWROK

R210

R210 1K_0402_5%

1K_0402_5%

Q21

Q21 MMBT3904_SOT23-3

MMBT3904_SOT23-3

3 1

+3VS

ICH_PWROK<21>

B B

A A

MCH_TSATN#

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_SYNC#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK MCH_RSTIN# THERMTRIP#_R DPRSLPVR_R

MCH_TSATN_EC# <29>

U31B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

RSVD16

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

NC_25

A47

NC_26

CANTIGA ES_FCBGA1329

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

Issued Date

SMRCOMP SMRCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_PWROK SM_REXT

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3

DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

ICH_PWROK CL_VREF

MCH_CLKREQ#

MCH_TSATN#

DDRA_CLK0 <14> DDRA_CLK1 <14> DDRB_CLK0 <15> DDRB_CLK1 <15>

DDRA_CLK0# <14> DDRA_CLK1# <14> DDRB_CLK0# <15> DDRB_CLK1# <15>

DDRA_CKE0 <14> DDRA_CKE1 <14> DDRB_CKE0 <15> DDRB_CKE1 <15>

DDRA_SCS0# <14> DDRA_SCS1# <14> DDRB_SCS0# <15> DDRB_SCS1# <15>

DDRA_ODT0 <14> DDRA_ODT1 <14> DDRB_ODT0 <15> DDRB_ODT1 <15>

R386 80.6_0402_1%R386 80.6_0402_1%

1 2

R383 80.6_0402_1%R383 80.6_0402_1%

1 2

SM_VREF

R125 0_0402_5% R125 0_0402_5%

1 2

R375 499_0402_1%R375 499_0402_1%

1 2

CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_ITX_MRX_N0 <21> DMI_ITX_MRX_N1 <21> DMI_ITX_MRX_N2 <21> DMI_ITX_MRX_N3 <21>

DMI_ITX_MRX_P0 <21> DMI_ITX_MRX_P1 <21> DMI_ITX_MRX_P2 <21> DMI_ITX_MRX_P3 <21>

DMI_MTX_IRX_N0 <21> DMI_MTX_IRX_N1 <21> DMI_MTX_IRX_N2 <21> DMI_MTX_IRX_N3 <21>

DMI_MTX_IRX_P0 <21> DMI_MTX_IRX_P1 <21> DMI_MTX_IRX_P2 <21> DMI_MTX_IRX_P3 <21>

CL_CLK0 <21> CL_DATA0 <21>

CL_RST#0 <21>

MCH_CLKREQ# <16> MCH_ICH_SYNC# <21>

Compal Secret Data

2007/09/20 2008/09/20

Compal Secret Data

SM_DRAMRST# would be needed for DDR3 only

For Cantiga 80 Ohm

+1.8V +1.8V

20mil

C212

0.1U_0402_16V4Z

C198

0.1U_0402_16V4Z

Deciphered Date

1 2

+1.05VS

R128

1K_0402_1%

1 2

R129

511_0402_1%

1 2

+1.8V

R392

R392 1K_0402_1%

1K_0402_1%

R390

3.01K_0402_1%

R389

R389 1K_0402_1%

1K_0402_1%

R146

1K_0402_1%

1 2

R147

R147 0_0402_5%

0_0402_5%

R145

1K_0402_1%

+DIMM_VREF

Strap Pin Table

CFG[2:0]

CFG5 CFG6 CFG9 CFG10

CFG[13:12]

CFG16 CFG19

CFG20

(PCIE/SDVO select)

SDVO_CTRLDATA L_DDC_DATA DDPC_CTRLDATA

SM_RCOMP_VOH

C491

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

C483

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

Title

Size Document Number Rev

Custom

Date: Sheet

C492

0.01U_0402_16V7K

SM_RCOMP_VOL

C482

0.01U_0402_16V7K

011 = FSB667 010 = FSB800 000 = FSB1067

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled

1 = iTPM Host Interface is Disabled 0 = Lane Reversal Enable

1 = Normal Operation (Default)

0 = PCIe Loopback Enable 1 = Disable

00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

0 = Normal Operation 1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

0 = No SDVO Card Present 1 = SDVO Card Present

0 = LFP Disable 1 = LFP Card Present; PCIE disable

0 = Digital DisplayPort Disable 1 = Digital DisplayPort Device Present

401590

(Default)

* *

(Default)

R110 2.21K_0402_1%@R110 2.21K_0402_1%@ R86 4.02K_0402_1%@R86 4.02K_0402_1%@ R92 2.21K_0402_1%@R92 2.21K_0402_1%@ R103 2.21K_0402_1%@R103 2.21K_0402_1%@ R98 2.21K_0402_1%@R98 2.21K_0402_1%@ R89 2.21K_0402_1%@R89 2.21K_0402_1%@ R90 2.21K_0402_1%@R90 2.21K_0402_1%@ R88 2.21K_0402_1%@R88 2.21K_0402_1%@

R96 4.02K_0402_1%@R96 4.02K_0402_1%@ R95 4.02K_0402_1%@R95 4.02K_0402_1%@

Compal Electronics, Inc.

SCHEMATICS, MB A4431

12 12 12 12 12 12 12 12

12 12

(Default)

* * *

(Default)

(Default) (Default) (Default)

+3VS

845Wednesday, July 30, 2008

DDRB_SDQ[0..63] DDRB_SDM[0..7] DDRB_SMA[0..14]

DDRA_SBS0# <14> DDRA_SBS1# <14> DDRA_SBS2# <14>

DDRA_SRAS# <14> DDRA_SCAS# <14> DDRA_SWE# <14>

DDRA_SDQS0 <14> DDRA_SDQS1 <14> DDRA_SDQS2 <14> DDRA_SDQS3 <14> DDRA_SDQS4 <14> DDRA_SDQS5 <14> DDRA_SDQS6 <14> DDRA_SDQS7 <14>

DDRA_SDQS0# <14> DDRA_SDQS1# <14> DDRA_SDQS2# <14> DDRA_SDQS3# <14> DDRA_SDQS4# <14> DDRA_SDQS5# <14> DDRA_SDQS6# <14> DDRA_SDQS7# <14>

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

AK47 AH46 AP47 AP46 AJ46 AJ48

AM48

AP48 AU47 AU46

BA48

AY48

AT47 AR47

BA47 BC47 BC46 BC44 BG43

BF43

BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5 BA1 BD3 AV2 AU3 AR3 AN2

AY2 AV1 AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

U31E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDRB_SDM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

CANTIGA ES_FCBGA1329

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7

DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7#

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14

DDRB_SBS0# <15> DDRB_SBS1# <15> DDRB_SBS2# <15>

DDRB_SRAS# <15> DDRB_SCAS# <15> DDRB_SWE# <15>

DDRB_SDQS0 <15> DDRB_SDQS1 <15> DDRB_SDQS2 <15> DDRB_SDQS3 <15> DDRB_SDQS4 <15> DDRB_SDQS5 <15> DDRB_SDQS6 <15> DDRB_SDQS7 <15>

DDRB_SDQS0# <15> DDRB_SDQS1# <15> DDRB_SDQS2# <15> DDRB_SDQS3# <15> DDRB_SDQS4# <15> DDRB_SDQS5# <15> DDRB_SDQS6# <15> DDRB_SDQS7# <15>

U31D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

DDRA_SDQ[0..63] DDRA_SDM[0..7] DDRA_SMA[0..14]

DDRB_SDQ[0..63]<15>

DDRB_SDM[0..7]<15>

DDRB_SMA[0..14]<15>

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

DDRA_SDM0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

CANTIGA ES_FCBGA1329

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7

DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7#

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14

DDRA_SDQ[0..63]<14>

D D

C C

B B

DDRA_SDM[0..7]<14>

DDRA_SMA[0..14]<14>

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

AJ38

AJ41 AN38 AM38

AJ36

AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6

AT5 AN10 AM11

AM5

AN12 AM13

AJ11 AJ12

AJ9 AJ8

A A

Security Classification

2007/09/20 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

945Wednesday, July 30, 2008

DPST_PWM<17>

ENBKL<29>

D D

C C

R104

75_0402_1%

GMCH_CRT_B<18> GMCH_CRT_G<18> GMCH_CRT_R<18>

B B

+3VS

R123 2.2K_0402_5%R123 2.2K_0402_5%

1 2

R122 2.2K_0402_5%R122 2.2K_0402_5%

1 2

R127 10K_0402_5%R127 10K_0402_5%

1 2

R120 10K_0402_5%R120 10K_0402_5%

1 2

R108 2.2K_0402_5%R108 2.2K_0402_5%

1 2

R100 2.2K_0402_5%R100 2.2K_0402_5%

1 2

Change to 0Ohm when use PM chip

R114 150_0402_1%R114 150_0402_1% R115 150_0402_1%R115 150_0402_1% R116 150_0402_1%R116 150_0402_1%

GMCH_CRT_HSYNC<18>

GMCH_CRT_VSYNC<18>

GMCH_LCD_CLK GMCH_LCD_DATA LCTLB_DATA LCTLA_CLK GMCH_CRT_CLK GMCH_CRT_DATA

1 2

R117 0_0402_5%R117 0_0402_5%

GMCH_LCD_CLK<17>

GMCH_LCD_DATA<17>

GMCH_ENVDD<17>

1 2

R402 2.37K_0402_1%R402 2.37K_0402_1%

GMCH_TXCLK-<17> GMCH_TXCLK+<17> GMCH_TZCLK-<17> GMCH_TZCLK+<17>

GMCH_TXOUT0-<17> GMCH_TXOUT1-<17> GMCH_TXOUT2-<17>

GMCH_TXOUT0+<17> GMCH_TXOUT1+<17> GMCH_TXOUT2+<17>

GMCH_TZOUT0-<17> GMCH_TZOUT1-<17> GMCH_TZOUT2-<17>

GMCH_TZOUT0+<17> GMCH_TZOUT1+<17> GMCH_TZOUT2+<17>

R93

R105

1 2

75_0402_1%

12 12 12

GMCH_CRT_CLK<18> GMCH_CRT_DATA<18>

U31C

L32

LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA

LVDS_IBG

R517

R517 0_0402_5%

0_0402_5%

1 2

GMCH_TXCLKGMCH_TXCLK+ GMCH_TZCLKGMCH_TZCLK+

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+

GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA

TV_DCONSEL_0 TV_DCONSEL_1

GMCH_CRT_CLK GMCH_CRT_DATA

CRT_IREF

R119

1.02K_0402_1%

1 2

G32 M32 M33 K33

M29 C44

B43 E37 E38

C41 C40 B37 A37

H47 E46 G40 A40

H48 D45

B40 A41

H38 G37

B42 G38

K37

H25 K25

H24

C31 E32

E28 G28

G29 H32

E29

J33

F40

J37

F37

F25

J28

J32 J29

L29

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL

LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF

CRT_VSYNC

PEG_COMP

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

CANTIGA ES_FCBGA1329

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

10mils

1 2

R130 49.9_0402_1%R130 49.9_0402_1%

+1.05VS

A A

R124 0_0402_5%R124 0_0402_5% R109 0_0402_5%R109 0_0402_5% R112 100K_0402_5%R112 100K_0402_5%

1 2

TV_DCONSEL_0 TV_DCONSEL_1 LBKLT_EN

Security Classification

2007/09/20 2008/09/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

10 45Wednesday, July 30, 2008

U31F

+1.8V

D D

Reference PILLAR_ROCK CRB Rev1.0

Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 board.

C C

B B

T10

T10 T9

A A

PAD

PAD PAD

PAD

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16

VCC_SM_AW16 VCC_SM_AT13

@ @

+1.05VS

VCC_AXG_SENSE VSS_AXG_SENSE

U31F

2600mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

CANTIGA ES_FCBGA1329

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+1.05VS

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C165

0.1U_0402_16V7K

Reference PILLAR_ROCK CRB Rev1.0

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_SM_AW16 VCC_SM_AT13

C158

C177

C159

0.1U_0402_16V7K

C177

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K 2

0.22U_0402_6.3V6K

Place close to the GMCH

VCC: 1930.4mA (GMCH), 1210.34mA (MCH)

+1.05VS

C122

220U_D2_4VM_R15

(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

C193

C194

C195

0.1U_0402_16V4Z

0.22U_0402_6.3V6K

10U_0805_10V4Z

0.1U_0402_16V4Z

0.22U_0402_6.3V6K

C192

+1.05VS

Cavity Capacitors

+1.05VS

VCC_AXG: 6326.84mA (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

C181

C180

0.47U_0603_16V4Z

0.47U_0603_16V4Z 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C172

10U_0805_10V4Z

C174

0.1U_0402_16V4Z

10U_0805_10V4Z

C171

C178

0.1U_0402_16V4Z

Cavity Capacitors

C118

330U_D2E_2.5VM_R15

Place close to the GMCH

VCC_SM: 2600mA

+1.8V

(330UF*1, 22UF*2, 0.1UF*1)

C205

330U_D2E_2.5VM_R15

C190

10U_0805_10V4Z

C191

10U_0805_10V4Z

C196

0.1U_0402_16V4Z

Place on the edge

C170

C169

0.1U_0402_16V7K

C199

1U_0402_6.3V4Z

C169 @

0.1U_0402_16V7K

C164

C164 @

0.1U_0402_16V7K

0.1U_0402_16V7K 2

C202

0.47U_0603_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C200

C200 @

0.1U_0402_16V7K

0.1U_0402_16V7K 2

Compal Secret Data

Deciphered Date

C185

C185 @

0.1U_0402_16V7K

C211

C211 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2007/09/20 2008/09/20

U31G

AG34

VCC_1

AC34

VCC_2

AB34

VCC_3

AA34

VCC_4

Y34

VCC_5

V34

VCC_6

U34

VCC_7

AM33

VCC_8

AK33

VCC_9

AJ33

VCC_10

AG33

VCC_11

AF33

VCC_12

AE33

VCC_13

AC33

VCC_14

AA33

VCC_15

Y33

VCC_16

W33

VCC_17

V33

VCC_18

U33

VCC_19

AH28

VCC_20

AF28

VCC_21

AC28

VCC_22

AA28

VCC_23

AJ26

VCC_24

AG26

VCC_25

AE26

VCC_26

AC26

VCC_27

AH25

VCC_28

AG25

VCC_29

AF25

VCC_30

AG24

VCC_31

AJ23

VCC_32

AH23

VCC_33

AF23

VCC_34

T32

VCC_35

CANTIGA ES_FCBGA1329

VCC CORE

POWER

+1.05VS

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29

VCC NCTF

VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

11 45Wednesday, July 30, 2008

L23

+1.05VS

VCCA_HPLL: 24mA

Please check Power source if want support IAMT

D D

(4.7UF*1, 0.1UF*1)

VCCA_MPLL: 139.2mA (22UF*1, 0.1UF*1)

1 2

MBK1608121YZF_0603

120Ohm@100MHz

1 2

MBK1608121YZF_0603

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

1 2

+3VS

L31

L31 MBK1608221YZF_0603

MBK1608221YZF_0603

C606

C606 220U_D2_4VM_R15

220U_D2_4VM_R15

C C

VCCA_DAC_BG: 2.6833333mA (0.1UF*1, 0.01UF*1)

1 2

+3VS

L30

L30 MBK1608221YZF_0603

MBK1608221YZF_0603

+1.05VS_HPLL

C434

4.7U_0805_10V4Z

4.7U_0805_10V4Z 2

+1.05VS_MPLL

R335

0.5_0603_1%

C437

C437 22U_0805_6.3V6M

22U_0805_6.3V6M

C495

C494

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.01U_0402_16V7K

Close to Ball A26, B27

C488

C489

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

0.01U_0402_16V7K

C441

0.1U_0402_16V4Z

Please check Power source if want support IAMT

C149

0.1U_0402_16V4Z

+3VS_CRTDAC

+1.05VS

Please check Power source if want support IAMT

+3VS_DACBG

C486

C486 @

10U_0805_6.3V6M

FOR EMI 20080226

+1.05VS

FOR EMI 20080226

R141

R141 0_0402_5%@

0_0402_5%@

1 2

+3VS

R140

R140 0_0402_5%

0_0402_5%

1 2

+1.5VS

Please check Power source if want support IAMT

+1.05VS

C233

10U_0805_6.3V6M

C435

C435 @

@ 220U_D2_4VM_R15

220U_D2_4VM_R15

+1.05VS

L32

1 2

MBK1608121YZF_0603

VCCA_DPLLA VCCA_DPLLB: 64.8mA (220UF*1, 0.1UF*1)

L10

1 2

MBK1608121YZF_0603

1 2 R97

R97 0_0805_5%

0_0805_5%

Please check Power source if want support IAMT

Close to Ball A25

VCCA_TV_DAC: 40mA (0.1UF*1,

+3VS

180Ohm@100MHz

+1.5VS

MBK1608221YZF_0603

180Ohm@100MHz

0.01UF*1 for each DAC)

L29

1 2

MBK1608221YZF_0603

VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1)

1 2

R83

R83 100_0603_1%

100_0603_1%

C478

0.1U_0402_16V4Z

C183

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

C179

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

C477

0.01U_0402_16V7K

+1.5VS_TVDAC

C184

Also power for internal Thermal Sensor

0.022U_0402_16V7K

C188

0.01U_0402_16V7K

+3VS_TVDAC

+1.5VS_QDAC

R91

R91 0_0402_5%

0_0402_5% @

Please check Power source if want support IAMT

B B

A A

+1.5VS

+1.05VS_DPLLA

C505

C505 220U_D2_4VM_R15

220U_D2_4VM_R15

+1.05VS_DPLLB

C263

C263 10U_0805_10V4Z

10U_0805_10V4Z

+1.8V_TX_LVDS

+VCCA_PEG_BG

C216

0.1U_0402_16V4Z

0.1U_0402_16V4Z 2

No CIS Symbol

1 2

MBK1608221YZF_0603

1 2

R142

R142 1_0402_1%

1_0402_1%

+1.05VS_A_SM

+1.05VS_A_SM_CK

1 2

R106

R106 0_0603_5%

0_0603_5%

2.2U_0603_6.3V6K

NO_STUFF

+1.05VS_HPLL

+1.8V

C513

0.1U_0402_16V4Z

C214

0.1U_0402_16V4Z

C213

C213 1000P_0402_50V7K

1000P_0402_50V7K

VCCA_SM: (22UF*2, 4.7UF*1, 1UF*1)

C173

22U_0805_6.3V6M

C182

C182 @

0_0402_5%

VCCA_LVDS: 13.2mA (1000PF*1)

VCCA_PEG_BG: 0.414mA (0.1UF*1)

+1.05VS_PEGPLL

C189

22U_0805_6.3V6M

VCCA_PEG_PLL: 50mA

C519

(0.1UF*1)

0.1U_0402_16V4Z

C168

4.7U_0805_10V4Z

4.7U_0805_10V4Z 2

VCCA_SM_CK: 24mA (22UF*1, 2.2UF*1, 0.1UF*1)

C186

0.1U_0402_16V4Z

+3VS_TVDAC

VCCD_HDA: 50mA (0.1UF*1)

R395

VCCD_HPLL: 157.2mA (0.1UF*1)

+1.05VS_PEGPLL

VCCD_PEG_PLL: 50mA (0.1UF*1)

1 2

R132

R132 0_0603_5%

0_0603_5%

C201

10U_0805_6.3V6M

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS_CRTDAC

+3VS_DACBG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL +1.05VS_MPLL

C176

1U_0402_6.3V4Z

+1.5VS_HDA

+1.5VS_TVDAC

+1.5VS_QDAC

+1.8V_LVDS

1U_0402_6.3V4Z

VCCD_LVDS: 60.311111mA (1UF*1)

Issued Date

AD48

AA48

AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16

AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25

AL25

AM24

AL24

AM23

AL23

M25

AF1

AA47

M38

C203

U31H

852mA

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.69mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

64.8mA

F47

VCCA_DPLLA

L48

VCCA_DPLLB

24mA

AD1

VCCA_HPLL

139.2mA

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

0.414mA

VCCA_PEG_BG

50mA

VCCA_PEG_PLL

480mA

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

24mA

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

87.79mA

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

50mA

A32

VCC_HDA

58.696mA

VCCD_TVDAC

48.363mA

L28

VCCD_QDAC

157.2mA

VCCD_HPLL

50mA

VCCD_PEG_PLL

60.31mA

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA ES_FCBGA1329

2007/09/20 2008/09/20

CRTPLLA LVDSA PEG

VTT

POWER

A SM

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

A CK

HDA

DMI PEG

VTTLF

LVDS D TV/CRT

Compal Secret Data

Deciphered Date

118.8mA

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

105.3mA

VCC_HV_1 VCC_HV_2 VCC_HV_3

1782mA

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

456mA

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

VCC_HV: 105.3mA

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

VCC_DMI: 456mA (0.1UF*1)

VTTLF_CAP1

VTTLF_CAP2

VTTLF_CAP3

AB2

0.47U_0603_16V4Z

VTT: 852mA

+1.05VS

(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

C127

C104

C104 220U_D2_4VM_R15

220U_D2_4VM_R15

C471

C471 @

10U_0805_6.3V6M

+1.8V_TX_LVDS: 118.8mA (22UF*1, 1000PF*1)

+3VS

C197

0.1U_0402_16V4Z

+1.05VS_PEG: 1782mA (220UF*1, 22UF*1, 4.7UF*1)

+1.05VS_DMI

C142

C438

0.47U_0603_16V4Z

+1.05VS +3VS

C127

4.7U_0805_10V4Z

VCC_AXF: 321.35mA

+1.05VS_AXF

(10UF*1, 1UF*1)

C470

1U_0402_6.3V4Z

+1.8V_SM_CK

C466

0.1U_0402_16V4Z

10U_0805_10V4Z

C452

0.47U_0603_16V4Z

0.47U_0603_16V4Z 2

D10

2 1

CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

1000P_0402_50V7K

C219

0.1U_0402_16V4Z

Date: Sheet

C116

2.2U_0603_6.3V6K

1 2

R376

R376 0_0603_5%

0_0603_5%

VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1)

1 2

R377

R377 1_0402_1%

1_0402_1%

+1.8V_TX_LVDS

C265

C261

10U_0805_10V4Z

+1.05VS_PEG

C258

C236

220U_D2_4VM_R15

1 2

R163

R163 0_0805_5%

0_0805_5%

R172

1 2

10_0603_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

C108

C100

0.47U_0603_16V4Z

Please check Power source if want support IAMT

+1.05VS

1uH 30%

1 2

L28

L28 MBK1608121YZF_0603

MBK1608121YZF_0603

0.1uH 20%

1 2

R178

R178 0_0603_5%

0_0603_5%

1 2

R174

R174 0_0805_5%

0_0805_5%

+1.05VS

1 2

C167

C167 10U_0805_6.3V6M

10U_0805_6.3V6M

+1.8V

Please check Power source if want support IAMT

+1.05VS

12 45Wednesday, July 30, 2008

U31I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

VSS_12

N47

VSS_13

L47

VSS_14

G47

VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21

V46

VSS_22

R46

VSS_23

P46

VSS_24

H46

VSS_25

F46

VSS_26 VSS_27 VSS_28 VSS_29 VSS_30

Y44

VSS_31

U44

VSS_32

T44

VSS_33

M44

VSS_34

F44

VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40

C43

VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

N42

VSS_48

L42

VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

Y41

VSS_56

U41

VSS_57

T41

VSS_58

M41

VSS_59

G41

VSS_60

B41

VSS_61 VSS_62 VSS_63 VSS_64 VSS_65

H40

VSS_66

E40

VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

N39

VSS_72

L39

VSS_73

B39

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

Y38

VSS_82

U38

VSS_83

T38

VSS_84

J38

VSS_85

F38

VSS_86

C38

VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93

H37

VSS_94

C37

VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

CANTIGA ES_FCBGA1329

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U31J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17 BA16 AU16

AN16

BG15 AC15

W15

BG14 AA14

BG13 BC13 BA13

AN13

AJ13

AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10 AV10 AT10

AJ10 AE10 AA10

N16 G16

C14

N13 G13

N11 G11 C11

M10 BF9 BC9 AN9 AM9 AD9

BH8 BB8 AV8 AT8

VSS_233 VSS_235 VSS_237

VSS_238 VSS_239

K16

VSS_240 VSS_241

E16

VSS_242 VSS_243 VSS_244 VSS_245

A15

VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258

L13

VSS_259 VSS_260

E13

VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266

J12

VSS_267

A12

VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

Y11

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290

VSS_291

VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

VSS

VSS NCTF

CANTIGA ES_FCBGA1329

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A4431

401590

13 45Wednesday, July 30, 2008

+1.8V +1.8V

JDIMM2

+DIMM_VREF

DDRA_SDQ0 DDRA_SDQ5 DDRA_SDQ1

DDRA_SDQS0#<9> DDRA_SDQS0<9>

D D

DDRA_SDQS1#<9> DDRA_SDQS1<9>

DDRA_SDQS2#<9> DDRA_SDQS2<9>

DDRA_CKE0<8>

C C

DDRA_SBS2#<9>

DDRA_SBS0#<9> DDRA_SWE#<9>

DDRA_SCAS#<9> DDRA_SCS1#<8>

DDRA_ODT1<8>

DDRA_SDQS4#<9> DDRA_SDQS4<9>

B B

DDRA_SDQS6#<9> DDRA_SDQS6<9>

D_CK_SDATA<15,16> D_CK_SCLK<15,16>

A A

+3VS

C32

2.2U_0603_6.3V6K

DDRA_SDQS0# DDRA_SDQS0

DDRA_SDQ2 DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ29

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_SBS2# DDRA_SMA12

DDRA_SMA9 DDRA_SMA8

DDRA_SMA5 DDRA_SMA3 DDRA_SMA1

DDRA_SMA10 DDRA_SBS0# DDRA_SWE#

DDRA_SCAS# DDRA_SCS1#

DDRA_ODT1 DDRA_SDQ32

DDRA_SDQ33 DDRA_SDQS4#

DDRA_SDQS4 DDRA_SDQ34

DDRA_SDQ35 DDRA_SDQ40

DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42

DDRA_SDQ43 DDRA_SDQ48

DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58

DDRA_SDQ59 D_CK_SDATA

D_CK_SCLK

+3VS

C57

0.1U_0402_16V4Z

DIMM0 REV H:5.2mm (BOT)

VREF

VSS

DQ0

DQ1

VSS

DQS0#

DQS0

VSS

DQ2

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

VSS

DQ18

DQ19

VSS

DQ24

DQ25

VSS

DM3

VSS

DQ26

DQ27

VSS

CKE0

VDD

BA2

VDD

A12

VDD

101

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_AS0A426-N2RN-7F

FOX_AS0A426-N2RN-7F CONN@

CONN@

DQ4 DQ5

DM0 DQ6

DQ7

DQ12 DQ13

DM1

CK0#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

VDD NC/A15 NC/A14

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

SAO

GND

VSS

VSS VSS

VSS

VSS VSS

CK0 VSS

VSS

BA1

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90

A11

96 98

100

102

104 106 108 110

S0#

112 114 116 118 120

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204

DDRA_SDQ4

DDRA_SDM0 DDRA_SDQ6

DDRA_SDQ7 DDRA_SDQ12

DDRA_SDQ13 DDRA_SDM1

DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ20 DDRA_SDQ21

DDRA_SDM2 DDRA_SDQ22

DDRA_SDQ23 DDRA_SDQ28

DDRA_SDQS3# DDRA_SDQS3

DDRA_SDQ30 DDRA_SDQ31

DDRA_CKE1DDRA_CKE0

DDRA_SMA14 DDRA_SMA11

DDRA_SMA7 DDRA_SMA6

DDRA_SMA4 DDRA_SMA2 DDRA_SMA0

DDRA_SBS1# DDRA_SRAS# DDRA_SCS0#

DDRA_ODT0 DDRA_SMA13

DDRA_SDQ36 DDRA_SDQ37

DDRA_SDM4 DDRA_SDQ38

DDRA_SDQ39 DDRA_SDQ44

DDRA_SDQ45 DDRA_SDQS5#

DDRA_SDQS5 DDRA_SDQ46

DDRA_SDQ47 DDRA_SDQ52

DDRA_SDQ53

DDRA_SDM6 DDRA_SDQ54

DDRA_SDQ55 DDRA_SDQ60DDRA_SDQ56

DDRA_SDQ61 DDRA_SDQS7#

DDRA_SDQS7 DDRA_SDQ62

DDRA_SDQ63

R25 10K_0402_5%R25 10K_0402_5%

1 2

R21 10K_0402_5%R21 10K_0402_5%

1 2

DDRA_CLK0 <8> DDRA_CLK0# <8>

PM_EXTTS#0 <8>

DDRA_SDQS3# <9> DDRA_SDQS3 <9>

DDRA_CKE1 <8>

DDRA_SBS1# <9> DDRA_SRAS# <9> DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_SDQS5# <9> DDRA_SDQS5 <9>

DDRA_CLK1 <8> DDRA_CLK1# <8>

DDRA_SDQS7# <9> DDRA_SDQS7 <9>

+DIMM_VREF

20mils

C206

0.1U_0402_16V4Z

DDRA_SMA[0..14]<9> DDRA_SDQ[0..63]<9>

DDRA_SDM[0..7]<9>

DDRA_CKE0 DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS#

DDRA_SCS1# DDRA_ODT1

DDRA_SMA11 DDRA_SMA14

DDRA_SMA6 DDRA_SMA7

DDRA_SMA2 DDRA_SMA4

DDRA_SBS1# DDRA_SMA0

DDRA_SCS0# DDRA_SRAS#

DDRA_SMA13 DDRA_ODT0

DDRA_CKE1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDRA_SMA[0..14] DDRA_SDQ[0..63] DDRA_SDM[0..7]

1 4 2 3

RP45 56_0404_4P2R_5%RP45 56_0404_4P2R_5%

1 4 2 3

RP40 56_0404_4P2R_5%RP40 56_0404_4P2R_5%

1 4 2 3

RP35 56_0404_4P2R_5%RP35 56_0404_4P2R_5%

1 4 2 3

RP31 56_0404_4P2R_5%RP31 56_0404_4P2R_5%

1 4 2 3

RP27 56_0404_4P2R_5%RP27 56_0404_4P2R_5%

1 4 2 3

RP23 56_0404_4P2R_5%RP23 56_0404_4P2R_5%

1 4 2 3

RP19 56_0404_4P2R_5%RP19 56_0404_4P2R_5%

1 4 2 3

RP41 56_0404_4P2R_5%RP41 56_0404_4P2R_5%

1 4 2 3

RP37 56_0404_4P2R_5%RP37 56_0404_4P2R_5%

1 4 2 3

RP32 56_0404_4P2R_5%RP32 56_0404_4P2R_5%

1 4 2 3

RP28 56_0404_4P2R_5%RP28 56_0404_4P2R_5%

1 4 2 3

RP24 56_0404_4P2R_5%RP24 56_0404_4P2R_5%

1 4 2 3

RP20 56_0404_4P2R_5%RP20 56_0404_4P2R_5%

1 2

R71 56_0402_5%R71 56_0402_5%

Compal Secret Data

2007/09/20 2008/09/20

Compal Secret Data

+1.8V

R138

R138 1K_0402_1%

1K_0402_1%

R136

R136 1K_0402_1%

1K_0402_1%

+0.9VS

Deciphered Date

C150

2.2U_0603_6.3V6K

C436

0.1U_0402_16V4Z

C101

0.1U_0402_16V4Z

C109

0.1U_0402_16V4Z

C141

0.1U_0402_16V4Z

20mils

+1.8V

+0.9VS

To SODIMM and GMCH

+DIMM_VREF

C136

C123

2.2U_0603_6.3V6K

C433

C442

0.1U_0402_16V4Z

C110

C103

0.1U_0402_16V4Z

C124

C115

0.1U_0402_16V4Z

C133

C151

0.1U_0402_16V4Z

C113

2.2U_0603_6.3V6K

C128

0.1U_0402_16V4Z

C143

0.1U_0402_16V4Z

401590

Compal Electronics, Inc.

SCHEMATICS, MB A4431

C102

2.2U_0603_6.3V6K

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0.1U_0402_16V4Z

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Title

Size Document Number Rev

Date: Sheet

14 45Wednesday, July 30, 2008

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