Acer Chromebook 15 CB3-531 Schematics

8
7
6
5
4
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1. Schematic Page Description :
1. Schematic Page Description :
1. Schematic Page Description :1. Schematic Page Description :
ZRU/Vichy Schematic Ver : 1.0
ZRU/Vichy Schematic Ver : 1.0
ZRU/Vichy Schematic Ver : 1.0ZRU/Vichy Schematic Ver : 1.0
D D
C C
01 -- Sch Page description 02 -- Block Diagram 03 -- Valley 1/9 (DDRA) 04 -- Valley 2/9 (DDRB) 05 -- Valley 3/9 (Display) 06 -- Valley 4/9 (SD/PCIE/SATA) 07 -- Valley 5/9 (SPI/GPIO/CLK) 08 -- Valley 6/9 (USB/LPC/I2C) 09 -- Valley 7/9 (Power 1) 10 -- Valley 8/9 (Power 2) 11 -- Valley 9/9 (GND) 12 -- BTM XDP & APS 13 -- DDR3L MEMORY DOWNx16 CHA 14 -- DDR3L MEMORY DOWNx16 CHB 15 -- Level Shfiter (SOC_EC) 16 -- Level Shfiter (SOC_DEV) 17 -- LCD/CCD/DMIC 18 -- Google Debug 19 -- HDMI 20 -- WIFI/BT(NGFF)
21 -- eMMC 22 -- TPM 23 -- DB /Thermal sensor/LID 24 -- Audio Codec/SPK/DMIC 25 -- Audio Headset Switch/HP 26 -- USB3/Hole 27 -- KB/TP/HW RST 28 -- KBC 29 -- Charger (BQ24717RGRR) 30 -- SYSTEM 5V/3V (TPS51225BR) 31 -- Load Switch 32 -- DDR 1.35V(TPS51216) 33 -- +1.05V/+1V(NB671GQ-Z) 34 -- +VCC_CORE(ISL95833) 35 -- 1.8V/1.35V LDO-1 (G9661) 36 -- 1.8V/1V/3.3V LDO-2 (G9661) 37 -- Thermal protect 38 -- Power Sequence 39 -- SMBUS/I2C 40 -- BTM PWR TREE
1
41 -- Change List
B B
I2C table
I2C table SMBus table
I2C tableI2C table
Function Touch pad Audio codec Light sensor
Function
PP3300_DSW
Channel
I2C0 I2C1 I2C4
Channel
0x42
Read
Write 0x67 0x21 0x20
SMBus table
SMBus tableSMBus table
Function Battery Thermal
Channel
SMB0 SMB2 0x4C
Address
PP5000 0x41 PP1350
A A
PP1050_PCH PP1000_PCH 0x47
8
0x49 0x43
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Date: Sheet of
7
6
5
4
3
Date: Sheet of
2
PROJECT :
Sch Page description
Sch Page description
Sch Page description
ZRU
ZRU
ZRU
1A
1A
1A
of
411
411
411
1
5
4
3
2
1
ZRU/Vichy
2
Intel Bay Trail-M Platform Block Diagram
D D
DDR3L 1600 Memory down
DDR3L
2 Channel 1Rx16
PAGE 12,13
C C
eMMC
16G/32G
MMC
PAGE 21
1.8V BIOS+TXE SPI ROM(64Mb)
W25Q64FWSSIG
SPI Interface
PAGE 7
B B
TPM
SLB9655TT1.2 FW4.32GOOG
TI KBC
TM4E1G31H6ZRB
SKUA DC N2830 AJSR1W4UT02 --CPU(1170P)N2830 2.16G SR1W4(FCBGA)STNBSQ
DDI 1
32.768KHz PAGE 6
X2 LANES
Intel Bay Trail-M
25 Mhz PAGE 6
Power : TDP 7.5 Watt
Package : FCBGA 1170
Size : 25 x 27 (mm)
Int
Audio Codec
MAX98090
PAGE 3~11
I2S+I2C(PORT1)
DDI 0
I2C Interface
USB 3.0 Interface
Port0
USB 2.0 Interface
PCIE Gen 2 x 1 LaneLPC Interface
Port1 Port0
NGFF
USB port3
Port3
Port0
USB3.0 Port x 1
PAGE 26
GL852G-OHG12
Port0
Port1
USB Hub
USB Hub -2
CardReader
LCD Conn
PAGE 17
HDMI Conn PAGE 19
Port1
Audio CodecTrack Pad
MAX98090
PAGE 27 PAGE 24
CCD
Port2
PAGE 17
USB Hub -1
BQ24717RGRR
Batery Charger
TPS51225
PP3300_DSW/PP5000
ISL95833HRTZ-T
+VCC_CORE/+VCC_GFX
WLAN / BT Combo
Package : TQFN-40
Size : 5 x 5 (mm)
PAGE 24
PCIE CLK PORT 0
PAGE 21
RTS5170
USB2.0 Port x 1
PAGE 22
Package : BGA-157
Size : 9.1 x 9.1 (mm)
PAGE 28
Daughter Board
Speaker
A A
Thermal IC
Hall Sensor
TMP432
PAGE 23
5
PAGE 23 PAGE 23
Keyboard
PAGE 27
MIC SW
TS3A225E
DMIC
4
PAGE 25
CCD Integrated
PAGE 24
Combo Jack Headphone + MIC
PAGE 24
PAGE 25
SD CON
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
3
2
Tuesday, March 31, 2015
TPS51216
PP1350
NB671GQ-Z
PP1000_PCH
Thermal Protection Discharger
BOM value option: SX@ => SOiX NSX@=>none SOiX HUB@=>USB HUB 3G@ => LTE GD@ =>Google debug
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Block Diagram
Block Diagram
Block Diagram
ZRU
ZRU
ZRU
1
1A
1A
1A
412
412
412
5
4
3
2
1
M_A_A[15:0][13]
D D
M_A_DM0[13] M_A_DM1[13] M_A_DM2[13] M_A_DM3[13] M_A_DM4[13] M_A_DM5[13] M_A_DM6[13] M_A_DM7[13]
M_A_RAS#[13] M_A_CAS#[13]
C C
PP1350
B B
R161
4.7K/F_4
R158
C120
4.7K/F_4
0.1U/16V_4
A A
5
M_A_WE#[13] M_A_BS0[13]
M_A_BS1[13] M_A_BS2[13]
M_A_CS#0[13]
M_A_CKE0[13]
M_A_ODT0[13]
M_A_CLKP0[13] M_A_CLKN0[13]
M_A_DRAMRST#[13]
R460 100K/F_4 R461 100K/F_4
R454 23.2/F_4 R456 29.4/F_4 R455 162/F_4
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_RAS# M_A_CAS# M_A_WE#
M_A_BS0 M_A_BS1 M_A_BS2
M_A_CS#0
M_A_CKE0
M_A_ODT0
M_A_CLKP0 M_A_CLKN0
M_A_DRAMRST#
CPU_VREF
ICLK_DRAM_TERMN_0 ICLK_DRAM_TERMN_1
SOC_DRAM_PWROK SOC_VCCA_PWROK
DRAM_RCOMP0 DRAM_RCOMP1 DRAM_RCOMP2
U12A
K45
DRAM0_MA_00
H47
DRAM0_MA_11
L41
DRAM0_MA_22
H44
DRAM0_MA_33
H50
DRAM0_MA_44
G53
DRAM0_MA_55
H49
DRAM0_MA_66
D50
DRAM0_MA_77
G52
DRAM0_MA_88
E52
DRAM0_MA_99
K48
DRAM0_MA_1010
E51
DRAM0_MA_1111
F47
DRAM0_MA_1212
J51
DRAM0_MA_1313
B49
DRAM0_MA_1414
B50
DRAM0_MA_1515
G36
DRAM0_DM_00
B36
DRAM0_DM_11
F38
DRAM0_DM_22
B42
DRAM0_DM_33
P51
DRAM0_DM_44
V42
DRAM0_DM_55
Y50
DRAM0_DM_66
Y52
DRAM0_DM_77
M45
DRAM0_RAS
M44
DRAM0_CAS
H51
DRAM0_WE
K47
DRAM0_BS_00
K44
DRAM0_BS_11
D52
DRAM0_BS_22
P44
DRAM0_CS_0
P45
DRAM0_CS_2
C47
DRAM0_CKE_00
D48
RESERVED_D48
F44
DRAM0_CKE_22
E46
RESERVED_E46
T41
DRAM0_ODT_0
P42
DRAM0_ODT_2
M50
DRAM0_CKP_0
M48
DRAM0_CKN_0
P50
DRAM0_CKP_2
P48
DRAM0_CKN_2
P41
DRAM0_DRAMRST
AF44
DRAM_VREF
AH42
ICLK_DRAM_TERMN
AF42
ICLK_DRAM_TERMN_AF42
AD42
DRAM_VDD_S4_PWROK
AB42
DRAM_CORE_PWROK
AD44
DRAM_RCOMP_00
AF45
DRAM_RCOMP_11
AD45
DRAM_RCOMP_22
AF40
RESERVED_AF40
AF41
RESERVED_AF41
AD40
RESERVED_AD40
AD41
RESERVED_AD41
VLV_M_D/BGA
4
+1.35V_SUS +1.35V_SUS
1 OF 13
DRAM0_DQ_00 DRAM0_DQ_11 DRAM0_DQ_22 DRAM0_DQ_33 DRAM0_DQ_44 DRAM0_DQ_55 DRAM0_DQ_66 DRAM0_DQ_77 DRAM0_DQ_88
DRAM0_DQ09_C32
DRAM0_DQ_1010 DRAM0_DQ_1111 DRAM0_DQ_1212 DRAM0_DQ_1313 DRAM0_DQ_1414 DRAM0_DQ_1515 DRAM0_DQ_1616 DRAM0_DQ_1717 DRAM0_DQ_1818 DRAM0_DQ_1919 DRAM0_DQ_2020 DRAM0_DQ_2121 DRAM0_DQ_2222 DRAM0_DQ_2323 DRAM0_DQ_2424 DRAM0_DQ_2525 DRAM0_DQ_2626 DRAM0_DQ_2727 DRAM0_DQ_2828 DRAM0_DQ_2929 DRAM0_DQ_3030 DRAM0_DQ_3131 DRAM0_DQ_3232 DRAM0_DQ_3333 DRAM0_DQ_3434 DRAM0_DQ_3535 DRAM0_DQ_3636 DRAM0_DQ_3737 DRAM0_DQ_3838 DRAM0_DQ_3939 DRAM0_DQ_4040 DRAM0_DQ_4141 DRAM0_DQ_4242 DRAM0_DQ_4343 DRAM0_DQ_4444 DRAM0_DQ_4545 DRAM0_DQ_4646 DRAM0_DQ_4747 DRAM0_DQ_4848 DRAM0_DQ_4949 DRAM0_DQ_5050 DRAM0_DQ_5151 DRAM0_DQ_5252 DRAM0_DQ_5353 DRAM0_DQ_5454 DRAM0_DQ_5555 DRAM0_DQ_5656 DRAM0_DQ_5757 DRAM0_DQ_5858 DRAM0_DQ_5959 DRAM0_DQ_6060 DRAM0_DQ_6161 DRAM0_DQ_6262 DRAM0_DQ_6363
DRAM0_DQSP_00 DRAM0_DQSN_00 DRAM0_DQSP_11 DRAM0_DQSN_11 DRAM0_DQSP_22 DRAM0_DQSN_22 DRAM0_DQSP_33 DRAM0_DQSN_33 DRAM0_DQSP_44 DRAM0_DQSN_44 DRAM0_DQSP_55 DRAM0_DQSN_55 DRAM0_DQSP_66 DRAM0_DQSN_66 DRAM0_DQSP_77 DRAM0_DQSN_77
3
M36
M_A_DQ0
J36
M_A_DQ1
P40
M_A_DQ2
M40
M_A_DQ3
P36
M_A_DQ4
N36
M_A_DQ5
K40
M_A_DQ6
K42
M_A_DQ7
B32
M_A_DQ8
C32
M_A_DQ9
C36
M_A_DQ10
A37
M_A_DQ11
C33
M_A_DQ12
A33
M_A_DQ13
C37
M_A_DQ14
B38
M_A_DQ15
F36
M_A_DQ16
G38
M_A_DQ17
F42
M_A_DQ18
J42
M_A_DQ19
G40
M_A_DQ20
C38
M_A_DQ21
G44
M_A_DQ22
D42
M_A_DQ23
A41
M_A_DQ24
C41
M_A_DQ25
A45
M_A_DQ26
B46
M_A_DQ27
C40
M_A_DQ28
B40
M_A_DQ29
B48
M_A_DQ30
B47
M_A_DQ31
K52
M_A_DQ32
K51
M_A_DQ33
T52
M_A_DQ34
T51
M_A_DQ35
L51
M_A_DQ36
L53
M_A_DQ37
R51
M_A_DQ38
R53
M_A_DQ39
T47
M_A_DQ40
T45
M_A_DQ41
Y40
M_A_DQ42
V41
M_A_DQ43
T48
M_A_DQ44
T50
M_A_DQ45
Y42
M_A_DQ46
AB40
M_A_DQ47
V45
M_A_DQ48
V47
M_A_DQ49
AD48
M_A_DQ50
AD50
M_A_DQ51
V48
M_A_DQ52
V50
M_A_DQ53
AB44
M_A_DQ54
Y45
M_A_DQ55
V52
M_A_DQ56
W51
M_A_DQ57
AC53
M_A_DQ58
AC51
M_A_DQ59
W53
M_A_DQ60
Y51
M_A_DQ61
AD52
M_A_DQ62
AD51
M_A_DQ63
J38
M_A_DQSP0
K38
M_A_DQSN0
C35
M_A_DQSP1
B34
M_A_DQSN1
D40
M_A_DQSP2
F40
M_A_DQSN2
B44
M_A_DQSP3
C43
M_A_DQSN3
N53
M_A_DQSP4
M52
M_A_DQSN4
T42
M_A_DQSP5
T44
M_A_DQSN5
Y47
M_A_DQSP6
Y48
M_A_DQSN6
AB52
M_A_DQSP7
AA51
M_A_DQSN7
?
M_A_DQ[63:0] [13]
SLP_S4#[7,12,15]
M_A_DQSP0 [13] M_A_DQSN0 [13] M_A_DQSP1 [13] M_A_DQSN1 [13] M_A_DQSP2 [13] M_A_DQSN2 [13] M_A_DQSP3 [13] M_A_DQSN3 [13] M_A_DQSP4 [13] M_A_DQSN4 [13] M_A_DQSP5 [13] M_A_DQSN5 [13] M_A_DQSP6 [13] M_A_DQSN6 [13] M_A_DQSP7 [13] M_A_DQSN7 [13]
PP1350PP3300_PCH_S5
R322
R315
4.7K_4
DRM_PWOK_C2
34
EC_PWROK[28]
5
Q29A PJ4N3KDW
10K_4
2
Q29B
PJ4N3KDW
61
SOC_VCCA_PWROK
C302
0.1U/16V_4
12/24 change C102 from 0.1u to 1u
PP1350PP3300_PCH_S5
R317
4.7K_4
DRM_PWOK_C1
34
5
Q30A PJ4N3KDW
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
R332 10K_4
DRAM_PWROK
61
2
Q30B PJ4N3KDW
Valley 1/9 (DDRA)
Valley 1/9 (DDRA)
Valley 1/9 (DDRA)
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
R343 *SHORT_4
PP1350_PGOOD[32]
SOC_DRAM_PWROK
R327 *SHORT_4
C253
0.1U/16V_4
ZRU
ZRU
ZRU
1
3
413
413
413
1A
1A
1A
5
4
3
2
1
M_B_DQ[63:0] [14]
4
M_B_DQSP0 [14] M_B_DQSN0 [14] M_B_DQSP1 [14] M_B_DQSN1 [14] M_B_DQSP2 [14] M_B_DQSN2 [14] M_B_DQSP3 [14] M_B_DQSN3 [14] M_B_DQSP4 [14] M_B_DQSN4 [14] M_B_DQSP5 [14] M_B_DQSN5 [14] M_B_DQSP6 [14] M_B_DQSN6 [14] M_B_DQSP7 [14] M_B_DQSN7 [14]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Date: Sheet of
Date: Sheet of
PROJECT :
Valley 2/9 (DDRB)
Valley 2/9 (DDRB)
Valley 2/9 (DDRB)
1
ZRU
ZRU
ZRU
of
414
414
414
1A
1A
1A
M_B_A[15:0][14]
D D
M_B_DM0[14] M_B_DM1[14] M_B_DM2[14] M_B_DM3[14] M_B_DM4[14] M_B_DM5[14] M_B_DM6[14] M_B_DM7[14]
M_B_RAS#[14] M_B_CAS#[14] M_B_WE#[14]
C C
B B
A A
5
M_B_BS0[14] M_B_BS1[14] M_B_BS2[14]
M_B_CS#0[14]
M_B_CKE0[14]
M_B_ODT0[14]
M_B_CLKP0[14] M_B_CLKN0[14]
M_B_DRAMRST#[14]
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
M_B_RAS# M_B_CAS# M_B_WE#
M_B_BS0 M_B_BS1 M_B_BS2
M_B_CS#0
M_B_CKE0
M_B_ODT0
M_B_CLKP0 M_B_CLKN0
M_B_DRAMRST#
4
AY45 BB47
AW41
BB44 BB50 BC53 BB49
BF50 BC52 BE52 AY48 BE51 BD47 BA51 BH49 BH50
BD38 BH36 BC36 BH42
AT51 AM42 AK50 AK52
AV45 AV44 BB51
AY47 AY44
BF52
AT44
AT45
BG47 BE46 BD44
BF48 AP41
AT42
AV50 AV48
AT50
AT48
AT41
U12B
DRAM1_MA_00 DRAM1_MA_11 DRAM1_MA_22 DRAM1_MA_33 DRAM1_MA_44 DRAM1_MA_55 DRAM1_MA_66 DRAM1_MA_77 DRAM1_MA_88 DRAM1_MA_99 DRAM1_MA_1010 DRAM1_MA_1111 DRAM1_MA_1212 DRAM1_MA_1313 DRAM1_MA_1414 DRAM1_MA_1515
DRAM1_DM_00 DRAM1_DM_11 DRAM1_DM_22 DRAM1_DM_33 DRAM1_DM_44 DRAM1_DM_55 DRAM1_DM_66 DRAM1_DM_77
DRAM1_RAS DRAM1_CAS DRAM1_WE
DRAM1_BS_00 DRAM1_BS_11 DRAM1_BS_22
DRAM1_CS_0 DRAM1_CS_2
DRAM1_CKE_00 RESERVED_BE46 DRAM1_CKE_22 RESERVED_BF48
DRAM1_ODT_0 DRAM1_ODT_2
DRAM1_CKP_0 DRAM1_CKN_0
DRAM1_CKP_2 DRAM1_CKN_2
DRAM1_DRAMRST
VLV_M_D/BGA
2 OF 13
3
DRAM1_DQ_00 DRAM1_DQ_11 DRAM1_DQ_22 DRAM1_DQ_33 DRAM1_DQ_44 DRAM1_DQ_55 DRAM1_DQ_66 DRAM1_DQ_77 DRAM1_DQ_88
DRAM1_DQ_99 DRAM1_DQ_1010 DRAM1_DQ_1111 DRAM1_DQ_1212 DRAM1_DQ_1313 DRAM1_DQ_1414 DRAM1_DQ_1515 DRAM1_DQ_1616 DRAM1_DQ_1717 DRAM1_DQ_1818 DRAM1_DQ_1919 DRAM1_DQ_2020 DRAM1_DQ_2121 DRAM1_DQ_2222 DRAM1_DQ_2323 DRAM1_DQ_2424 DRAM1_DQ_2525 DRAM1_DQ_2626 DRAM1_DQ_2727 DRAM1_DQ_2828 DRAM1_DQ_2929 DRAM1_DQ_3030 DRAM1_DQ_3131 DRAM1_DQ_3232 DRAM1_DQ_3333 DRAM1_DQ_3434 DRAM1_DQ_3535 DRAM1_DQ_3636 DRAM1_DQ_3737 DRAM1_DQ_3838 DRAM1_DQ_3939 DRAM1_DQ_4040 DRAM1_DQ_4141 DRAM1_DQ_4242 DRAM1_DQ_4343 DRAM1_DQ_4444 DRAM1_DQ_4545 DRAM1_DQ_4646 DRAM1_DQ_4747 DRAM1_DQ_4848 DRAM1_DQ_4949 DRAM1_DQ_5050 DRAM1_DQ_5151 DRAM1_DQ_5252 DRAM1_DQ_5353 DRAM1_DQ_5454 DRAM1_DQ_5555 DRAM1_DQ_5656 DRAM1_DQ_5757 DRAM1_DQ_5858 DRAM1_DQ_5959 DRAM1_DQ_6060 DRAM1_DQ_6161 DRAM1_DQ_6262 DRAM1_DQ_6363
DRAM1_DQSP_00 DRAM1_DQSN_00 DRAM1_DQSP_11 DRAM1_DQSN_11 DRAM1_DQSP_22 DRAM1_DQSN_22 DRAM1_DQSP_33 DRAM1_DQSN_33 DRAM1_DQSP_44 DRAM1_DQSN_44 DRAM1_DQSP_55 DRAM1_DQSN_55 DRAM1_DQSP_66 DRAM1_DQSN_66 DRAM1_DQSP_77 DRAM1_DQSN_77
?
BG38 BC40 BA42 BD42 BC38 BD36 BF42 BC44 BH32 BG32 BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51
BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
M_B_DQSP0 M_B_DQSN0 M_B_DQSP1 M_B_DQSN1 M_B_DQSP2 M_B_DQSN2 M_B_DQSP3 M_B_DQSN3 M_B_DQSP4 M_B_DQSN4 M_B_DQSP5 M_B_DQSN5 M_B_DQSP6 M_B_DQSN6 M_B_DQSP7 M_B_DQSN7
2
5
4
3
2
1
U12C
AK13 AK12 AM14 AM13
AM3 AM2
AB14
AV3 AV2 AT2 AT3 AR3 AR1 AP3 AP2
AL3 AL1
D27 C26
C28 B28
C27 B26
T2
T3 AB3 AB2
Y3
Y2
W3 W1
V2
V3
R3
R1 AD6 AD4 AB9 AB7
Y4
Y6
V4
V6 A29 C29
B30 C30
VLV_M_D/BGA
+1.0V_SX
DDI0_TXP_0
+1.0V_SX
DDI0_TXN_0
+1.0V_SX
DDI0_TXP_1
+1.0V_SX
DDI0_TXN_1
+1.0V_SX
DDI0_TXP_2
+1.0V_SX
DDI0_TXN_2
+1.0V_SX
DDI0_TXP_3
+1.0V_SX
DDI0_TXN_3
+1.0V_SX
DDI0_AUXP
+1.0V_SX
DDI0_AUXN
+1.8V
DDI0_HPD DDI0_DDCDATA
DDI0_DDCCLK DDI0_VDDEN
DDI0_BKLTEN DDI0_BKLTCTL
DDI0_RCOMP DDI0_RCOMP_P RESERVED_AM14 RESERVED_AM13 VSS_AM3 VSS_AM2
RESERVED_T2 RESERVED_T3 RESERVED_AB3 RESERVED_AB2 RESERVED_Y3 RESERVED_Y2 RESERVED_W3 RESERVED_W1 RESERVED_V2 RESERVED_V3 RESERVED_R3 RESERVED_R1 RESERVED_AD6 RESERVED_AD4 RESERVED_AB9 RESERVED_AB7 RESERVED_Y4 RESERVED_Y6 RESERVED_V4 RESERVED_V6 GPIO_S0_NC13 GPIO_S0_NC14_C29 RESERVED_AB14 GPIO_S0_NC12 RESERVED_C30
+1.8V +1.8V
+1.8V +1.8V +1.8V
3 OF 13
+1.0V_SX +1.0V_SX
+1.8V
+1.8V +1.8V
+1.8V +1.8V +1.8V
DDI1_DDCDATA
DDI1_DDCCLK
DDI1_BKLTEN
DDI1_BKLTCTL
RESERVED_AH14 RESERVED_AH13 RESERVED_AF14 RESERVED_AF13
VGA_DDCCLK
VGA_DDCDATA
RESERVED_T7
RESERVED_T9 RESERVED_AB13 RESERVED_AB12
RESERVED_Y12 RESERVED_Y13 RESERVED_V10
RESERVED_V9
RESERVED_T12 RESERVED_T10 RESERVED_V14 RESERVED_V13 RESERVED_T14 RESERVED_T13
RESERVED_T6
RESERVED_T4
RESERVED_P14
RESERVED_K34
GPIO_S0_NC26
GPIO_S0_NC25
GPIO_S0_NC24
GPIO_S0_NC23
GPIO_S0_NC22
GPIO_S0_NC21
GPIO_S0_NC20
GPIO_S0_NC18
GPIO_S0_NC17
GPIO_S0_NC16
GPIO_S0_NC15
Configuration Note
GPIO_S0_SC_56[8]
PP1800_PCH
I2S_LRCLK[6]
PP1800_PCH
SOC_OVERRIDE#[28]
R436 *SHORT_4
GPIO_S0_SC_56
R45 *10K_4
I2S_LRCLK
R130 10K_4
INT_HDMITX2P[19] INT_HDMITX2N[19] INT_HDMITX1P[19] INT_HDMITX1N[19] INT_HDMITX0P[19] INT_HDMITX0N[19] INT_HDMICLK+[19] INT_HDMICLK-[19]
D D
C C
INT_HDMI_HPD[19]
HDMI_DDCDATA_SW[19] HDMI_DDCCLK_SW[19]
R46 402/F_4
R335 *SHORT_4 R334 *SHORT_4
TP66 TP68
INT_HDMITX2P INT_HDMITX2N INT_HDMITX1P INT_HDMITX1N INT_HDMITX0P INT_HDMITX0N INT_HDMICLK+ INT_HDMICLK-
INT_HDMI_HPD HDMI_DDCDATA_SW
HDMI_DDCCLK_SW
SOC_DDIO_RCOMP SOC_DDIO_RCOMP_P
SOC_PIN_AM3 SOC_PIN_AM2
GPIO_NC13 GPIO_NC14
INTD_DSI_TE
BTM Strapping Table
B B
Pin Name Strap description
GPIO_SO_SC_56
Top Swap (A16 Override)
LPE_I2S2_FRM PWROKBIOS Boot Selection
GPIO_SO_SC_65 Security Flash Descriptors
Sampled
PWROK
PWROK
0 = Top address bit is unchanged
1 = Top address bit is inverted
0 = LPC
1 = SPI
0 = Override
1 = Normal operation
DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3
DDI1_AUXP DDI1_AUXN
DDI1_HPD
DDI1_VDDEN
VSS_AH3 VSS_AH2
VGA_RED
VGA_BLUE
VGA_GREEN
VGA_IREF VGA_IRTN
VGA_HSYNC VGA_VSYNC
I2S_DOUT[6]
AG3 AG1 AF3 AF2 AD3 AD2 AC3 AC1
AK3 AK2
K30 P30
G30 N30
J30 M30
AH14 AH13 AF14 AF13 AH3 AH2
BA3 AY2 BA1 AW1 AY3
BD2 BF2
BC1 BC2
T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14
K34 D32 N32 J34 K28 F28 F32 D34 J28 D28 M32 F34
?
R54 *10K_4
R124 *10K_4
I2S_DOUT
SOC_OVERRIDE_NM
EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1
EDP_AUXP EDP_AUXN
EDP_HPD_L DDI1_DDCDATA
SOC_DISP_ON_C SOC_EDP_BLON_C SOC_DPST_PWM_C
SOC_PIN_AH3 SOC_PIN_AH2
CRT_R CRT_B CRT_G SOC_VGA_IREF SOC_VGA_IRTN
CRT_HSYNC CRT_VSYNC
VGA_DDCCLK VGA_DDCDATA
XDP_GPIO_S0_NC19
XDP_GPIO_S0_NC23 XDP_GPIO_S0_NC22 XDP_GPIO_S0_NC21 XDP_GPIO_S0_NC20 XDP_GPIO_S0_NC18 XDP_GPIO_S0_NC17 XDP_GPIO_S0_NC16 XDP_GPIO_S0_NC15
3
2
2N7002K
1
EDP_TXP0 [17] EDP_TXN0 [17] EDP_TXP1 [17] EDP_TXN1 [17]
EDP_AUXP [17] EDP_AUXN [17]
SOC_DISP_ON_C [16] SOC_EDP_BLON_C [16] SOC_DPST_PWM_C [16]
R36 *SHORT_4 R34 *SHORT_4
TP57 TP56 TP55 TP59 TP58
TP2 TP1
R330 *SHORT_4 R331 *SHORT_4
XDP_GPIO_S0_NC19 [12]
XDP_GPIO_S0_NC23 [12] XDP_GPIO_S0_NC22 [12] XDP_GPIO_S0_NC21 [12] XDP_GPIO_S0_NC20 [12] XDP_GPIO_S0_NC18 [12] XDP_GPIO_S0_NC17 [12] XDP_GPIO_S0_NC16 [12] XDP_GPIO_S0_NC15 [12]
using SoC internal PU
using SoC internal PU
Q41
EDP_HPD_L
HPD output high SOC active Low
PP1800_PCH
3
1
R450 10K_4
2
Q42
2N7002K
EDP_HPD
R452 100K/F_4
5
EDP_HPD [17]
DDI0_DDCDATA DDI0 Detect
A A
DDI1_DDCDATA DDI1 Detect
PWROK
0 = DDI0 not detected
1 = DDI0 detected
0 = DDI0 not detected
1 = DDI0 detected
GPIO_SO_NC_13
5
4
Pull up +1.8V at HDMI sidePWROK
PP1800_PCH
PP1800_PCH
R106 2.2K_4
R409 *10K_4
3
HDMI_DDCDATA_SW
DDI1_DDCDATA
GPIO_NC13
R397 *10K_4
R101 *10K_4
R404 10K_4
using SoC internal PU
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
Tuesday, March 31, 2015
PROJECT :
Valley 3/9 (Display)
Valley 3/9 (Display)
Valley 3/9 (Display)
ZRU
ZRU
ZRU
415
415
1
415
1A
1A
1A
5
4
3
2
1
6
D D
SOC_KBC_SCI[15]
PP1800_PCH
C C
B B
A A
EMMC_CLK[21] EMMC_D0[21]
EMMC_D1[21] EMMC_D2[21] EMMC_D3[21] EMMC_D4[21] EMMC_D5[21] EMMC_D6[21] EMMC_D7[21]
EMMC_CMD[21] EMMC_RST#[21]
SD3_CD#[18,23]
R80 49.9/F_4
5
TP6 TP5
TP8 TP7
R38 *SHORT_4 R49 *SHORT_4
R22 *SHORT_4 R23 *10K_4 R337 *10K_4
R74 402/F_4
R65 49.9/F_4
R77 *0_4
TP17
SATA_TXP0_SSD SATA_TXN0_SSD
SATA_RXP0_SSD SATA_RXN0_SSD
ICLK_SATA_TERMP ICLK_SATA_TERMN
SATA_GP0 SATA_DEVSLP_C SATA_LED_R_N
SATA_RCOMP_DP SATA_RCOMP_DN
EMMC_CLK EMMC_D0
EMMC_D1 EMMC_D2 EMMC_D3 EMMC_D4 EMMC_D5 EMMC_D6 EMMC_D7
EMMC_CMD EMMC_RST#
EMMC_RCOMP
SD3_CD#_R
SDMMC3_1P8_EN
SDIO3_RCOMP
U12D
BF6
SATA_TXP_0
BG7
SATA_TXN_0
AU16
SATA_RXP_0
AV16
SATA_RXN_0
BD10
SATA_TXP1
BF10
SATA_TXN_1
AY16
SATA_RXP_1
BA16
SATA_RXN_1
BB10
ICLK_SATA_TERMP
BC10
ICLK_SATA_TERMN
BA12
SATA_GP0
AY14
SATA_GP1
AY12
SATA_LED
AU18
SATA_RCOMP_P_AU18
AT18
SATA_RCOMP_N_AT18
AT22
MMC1_CLK
AV20
MMC1_D0
AU22
MMC1_D1
AV22
MMC1_D2
AT20
MMC1_D3
AY24
MMC1_D4
AU26
MMC1_D5
AT26
MMC1_D6
AU20
MMC1_D7
AV26
MMC1_CMD
BA24
MMC1_RST
AY18
MMC1_RCOMP
BA18
SD2_CLK
AY20
SD2_D0
BD20
SD2_D1
BA20
SD2_D2
BD18
SD2_D3_CD
BC18
SD2_CMD
AY26
SD3_CLK
AT28
SD3_D0
BD26
SD3_D1
AU28
SD3_D2
BA26
SD3_D3
BC24
SD3_CD#
AV28
SD3_CMD
BF22
SD3_1P8EN
BD22
SD3_PWREN
BF26
SD3_RCOMP
VLV_M_D/BGA
4
+1.8V +1.8V +1.8V
+1.8V
+1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V +1.8V/+3.3V
+1.8V +1.8V
+1.0V +1.0V
+1.8V +1.8V +1.8V +1.8V
+1.8V
PCIE_RCOMP_P_AP14_AP14 PCIE_RCOMP_N_AP13_AP13
+1.8V/1.5V +1.8V/1.5V +1.8V/1.5V +1.8V/1.5V +1.8V/1.5V +1.8V/1.5V +1.8V/1.5V+1.8V/+3.3V +1.8V/1.5V
+1.8V
4 OF 13
PCIE_TXP_0 PCIE_TXN_0
PCIE_RXP_0 PCIE_RXN_0
PCIE_TXP_1 PCIE_TXN_1
PCIE_RXP_1 PCIE_RXN_1
PCIE_TXP_2 PCIE_TXN_2
PCIE_RXP_2 PCIE_RXN_2
PCIE_TXP_3 PCIE_TXN_3
PCIE_RXP_3 PCIE_RXN_3
VSS_BB7 VSS_BB5
PCIE_CLKREQ_0 PCIE_CLKREQ_1 PCIE_CLKREQ_2 PCIE_CLKREQ_3
SD3_WP_BD5
RESERVED_BB4 RESERVED_BB3
RESERVED_AV10
RESERVED_AV9
HDA_LPE_RCOMP
HDA_RST
HDA_SYNC
HDA_CLK
HDA_SDO HDA_SDI0 HDA_SDI1
HDA_DOCKRST
HDA_DOCKEN LPE_I2S2_CLK
LPE_I2S2_FRM
LPE_I2S2_DATAOUT
LPE_I2S2_DATAIN
RESERVED_P34 RESERVED_N34
RESERVED_AK9 RESERVED_AK7
+1.0V
PROCHOT
AY7 AY6
AT14 AT13
AV6 AV4
AT10 AT9
AT7 AT6
AP12 AP10
AP6 AP4
AP9 AP7
BB7 BB5
BG3 BD7 BG5 BE3 BD5
AP14 AP13
BB4 BB3 AV10 AV9
BF20 BG22 BH20 BJ21 BG20 BG19 BG21 BH18 BG18
BF28 BA30 BC30 BD28
P34 N34
AK9 AK7
C24
?
3
PCIE_TX0+_WLAN_C PCIE_TX0-_WLAN_C
PCIE_RX0+_WLAN PCIE_RX0-_WLAN
VSS_BB7 VSS_BB5
PCIE_CLKREQ_WLAN# PCIE_CLKREQ_IMAGE# PCIE_CLKREQ_WIMAX# PCIE_CLKREQ3#
SOC_PCIE_COMP SOC_PCIE_COMN
HDA_RCOMP ACZ_RST# ACZ_SYNC ACZ_BCLK ACZ_SDOUT PCH_AZ_CODEC_SDIN0
DET_TRIGGER HDA_DOCKEN#
I2S_BCLK I2S_LRCLK I2S_DOUT I2S_DIN
SOC_PROCHOT#
GND
0423 add C409 on PROCHOT# for ESD improvement
C7 0.1U/16V_4 C8 0.1U/16V_4
R31 *SHORT_4 R30 *SHORT_4
TP4 TP3
R56 402/F_4
R75 49.9/F_4
TP64 TP61 TP63 TP60 TP62
R378 *SHORT_4 R104 *SHORT_4
R121 *SHORT_4 R115 *SHORT_4 R111 *SHORT_4
R382 71.5/F_4 R370 *SHORT_4
C269
0.1U/16V_4
PCIE_TX0+_WLAN [20] PCIE_TX0-_WLAN [20]
PCIE_RX0+_WLAN [20] PCIE_RX0-_WLAN [20]
PCIE_CLKREQ_WLAN# [20]
DET_TRIGGER [24] AJACK_MICPRES_L [24,25]
I2S_BCLK_R [24] I2S_LRCLK_R [24] I2S_DOUT_R [24] I2S_DIN_R [24]
PP1000_PCH
H_PROCHOT#
R61 *SHORT_4 R55 *0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PCIE_CLKREQ_WLAN# PCIE_CLKREQ_IMAGE# I2S_DOUT
0 = LPC , 1 = SPI
I2S_LRCLK I2S_DOUT
Security Flash Descriptors 0 = Override 1 = Normal Operation
Need check to see if MOSFET isolation needed or not
H_PROCHOT# [18,28,34] IMVP7_PROCHOT# [29] ALERT# [23]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Valley 4/9 (SD/PCIE/SATA)
Valley 4/9 (SD/PCIE/SATA)
Valley 4/9 (SD/PCIE/SATA)
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
R336 10K_4 R346 10K_4 R418 *10K_4
I2S_LRCLK [5] I2S_DOUT [5]
ZRU
ZRU
ZRU
1
PP1800_PCH
416
416
416
1A
1A
1A
5
CRYSTAL 25MHZ
C252 12P/50V_4
Y2
25MHZ +10PPM
D D
C251 12P/50V_4
2nd BG625000121(HHE)
PP1800_PCH
R351 10K_4
PP1800_PCH_ME
R4 3.3K/F_4
PP1800_PCH_S5
R372 10K_4 R360 10K_4
C C
B B
R365 *10K_4 R321 10K_4 R368 10K_4 R362 10K_4 R358 10K_4
4
3
1
2
XTAL25_IN
R340 1M_4
XTAL25_OUT
KBD_IRQ#
SOC_SPI_CS#
PCH_WAKE# TRACKPAD_INT# SOC_JTAG2_TDO PCH_SPI_WP_D TOUCH_INT# LTE_WAKE# PMC_SUSCLK1
R39 4.02K/F_4 R42 47.5/F_4
CLK_PCIE_WLANN[20] CLK_PCIE_WLANP[20]
I2S_MCLK[24]
KBD_IRQ#[28] SRT_CRST#[12]
XDP_H_TCK[12] XDP_H_TRST#[12] XDP_H_TMS[12] XDP_H_TDI[12] XDP_H_TDO[12] XDP_H_PRDY#[12] XDP_H_PREQ#_C[12]
R373
PCH_WAKE_L[28]
TRACKPAD_INT#[27]
SOC_KBC_SMI[15]
MUX_AUD_INT1#[24] WIFI_DISABLE#[16]
R83 49.9/F_4
*SHORT_4
R58
*SHORT_4
4
XTAL25_IN XTAL25_OUT
ICLK_ICOMP ICLK_RCOMP
CLK_PCIE_WLANN CLK_PCIE_WLANP
I2S_MCLK
KBD_IRQ# SRT_CRST#
XDP_H_TCK XDP_H_TRST# XDP_H_TMS XDP_H_TDI XDP_H_TDO XDP_H_PRDY# XDP_H_PREQ#_C
SOC_SPI_CS# SOC_SPI_MISO
SOC_SPI_MOSI SOC_SPI_CLK
PCH_WAKE# TRACKPAD_INT# TOUCH_INT# LTE_WAKE# SOC_JTAG2_TDO PMC_SUSCLK1 PCH_SPI_WP_D SOC_GPOI7
MUX_AUD_INT1# WIFI_DISABLE#
SOC_GPIO_RCOMP
AH12 AH10
AD14 AD13
AD10 AD12
AM10
AT34
AD9
AF6 AF4
AF9 AF7
AK4 AK6
AM4 AM6
AM9
BH7 BH5 BH4 BH8 BH6
C12 D14
G12
G16 D18
C23 C21 B22 A21 C22
B18 B16 C18 A17 C17 C16 B14 C15
C13 A13 C19
N26
BJ9
F14 F12
F16
U12E
ICLK_OSCIN ICLK_OSCOUT
RESERVED_AD9 ICLK_ICOMP
ICLK_RCOMP RESERVED_AD10
RESERVED_AD12 PCIE_CLKN_00
PCIE_CLKP_00 PCIE_CLKN_11
PCIE_CLKP_11
PCIE_CLKN_22 PCIE_CLKP_22
PCIE_CLKN_33 PCIE_CLKP_33
RESERVED_AM10 RESERVED_AM9
PMC_PLT_CLK_00 PMC_PLT_CLK_11 PMC_PLT_CLK_22 PMC_PLT_CLK_33 PMC_PLT_CLK_44 PMC_PLT_CLK_55 ILB_RTC_RST
TAP_TCK TAP_TRST TAP_TMS TAP_TDI TAP_TDO TAP_PRDY TAP_PREQ RESERVED
PCU_SPI_CS_00 PCU_SPI_CS_11 PCU_SPI_MISO PCU_SPI_MOSI PCU_SPI_CLK
GPIO_S5_0 GPIO_S5_1 GPIO_S5_2 GPIO_S5_3 GPIO_S5_4 GPIO_S5_5 GPIO_S5_6 GPIO_S5_7
GPIO_S5_8 GPIO_S5_9 GPIO_S5_10
GPIO_RCOMP
VLV_M_D/BGA
3
+1.8V +1.8V +1.8V +1.8V
+1.8V +1.8V +1.8V +1.8V
+1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5 +1.8V +1.8V_S5
+1.8V_S5
5 OF 13
+3V_RTC
+3V_RTC +3V_RTC
+1.0V +1.0V
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
+1.8V +1.8V +1.8V +1.8V
+1.8V +1.8V +1.8V +1.8V +1.8V +1.8V
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.0V
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
SIO_UART1_RXD SIO_UART1_TXD SIO_UART1_RTS SIO_UART1_CTS
SIO_UART2_RXD SIO_UART2_TXD SIO_UART2_RTS SIO_UART2_CTS
PMC_SUSPWRDNACK
PMC_SUSCLK0_G24
PMC_SLP_S0IX
PMC_SLP_S4 PMC_SLP_S3
GPIO_S514_J20
PMC_ACPRESENT
PMC_WAKE_PCIE_0
PMC_BATLOW
PMC_PWRBTN
PMC_RSTBTN
PMC_PLTRST
GPIO_S517_J24
PMC_SUS_STAT
ILB_RTC_TEST
PMC_RSMRST
PMC_CORE_PWROK
ILB_RTC_X1 ILB_RTC_X2
ILB_RTC_EXTPAD
SVID_ALERT
SVID_DATA
SVID_CLK
SIO_PWM_00 SIO_PWM_11
GPIO_S5_22 GPIO_S5_23 GPIO_S5_24 GPIO_S5_25 GPIO_S5_26 GPIO_S5_27 GPIO_S5_28 GPIO_S5_29 GPIO_S5_30
SIO_SPI_CS SIO_SPI_MISO SIO_SPI_MOSI
SIO_SPI_CLK
AU34
ALS_INT#
AV34 BA34
TOUCH_INT_L_DX
AY34 BF34
SIO_UART2_RXD
BD34
SIO_UART2_TXD
BD32 BF32
D26
PMC_SUSPWRDNACK
G24
PMC_SUSCLK0
F18
SLP_S0IX#
F22
SLP_S4#
D22
SLP_S3#
J20 D20
ACPRESENT
F26
SOC_PMC_WAKE#
K26
PMC_BATLOW#
J26
SOC_PWRBTN#
BG9
SOC_REST_BTN#
F20
SOC_PLTRST#
J24 G18
PMC_SUS_STAT#
C11
SOC_RTEST#
B10
SOC_RSMRST#
B7
CORE_PWROK
C9
RTC_X1
A9
RTC_X2
B8
BRTC_EXTPAD
B24
SVID_ALERT#_SOC
A25
SVID_DATA_SOC
C25
SVID_CLK_SOC
AU32 AT32
SIO_PWM1
K24
XDP_GPIO_DFX0
N24
XDP_GPIO_DFX1
M20
XDP_GPIO_DFX2
J18
XDP_GPIO_DFX3
M18
XDP_GPIO_DFX4
K18
XDP_GPIO_DFX5
K20
XDP_GPIO_DFX6
M22
XDP_GPIO_DFX7
M24
XDP_GPIO_DFX8
AV32
SIO_SPI_CS#
BA28
SIO_SPI_MISO
AY28
SIO_SPI_MOSI
AY30
SIO_SPI_CLK
02/27 Change to TP for S3 leakage on PP1800_PCH issue.
?
TP31 TP27
SUS STAT OUTPUT PORT
R50 *SHORT_4
C254 0.1U/16V_4
R383 20/F_4 R387 16.9/F_4 R392 *SHORT_4
TP29
2
PMC_SUSPWRDNACK [15] PMC_SUSCLK0 [16] SLP_S0IX# [15] SLP_S4# [3,12,15] SLP_S3# [12,15]
ACPRESENT [16] SOC_PMC_WAKE# [16]
SOC_PWRBTN# [12,15] SOC_REST_BTN# [12,18] SOC_PLTRST# [12,15]
PMC_SUS_STAT# [15]
SOC_RTEST# [12]
SOC_RSMRST# [12,15] CORE_PWROK_R [12,28]
SPEC 512177 INPUT PORT
VR_SVID_ALERT# VR_SVID_DATA VR_SVID_CLK
XDP_GPIO_DFX0 [12] XDP_GPIO_DFX1 [12] XDP_GPIO_DFX2 [12] XDP_GPIO_DFX3 [12] XDP_GPIO_DFX4 [12] XDP_GPIO_DFX5 [12] XDP_GPIO_DFX6 [12] XDP_GPIO_DFX7 [12] XDP_GPIO_DFX8 [12]
TP23 TP24 TP20 TP26
0423 add C408 on CORE_PWROK for ESD improvement
CORE_PWROK
O_1.8VA
VR_SVID_ALERT# [34] VR_SVID_DATA [34] VR_SVID_CLK [34]
C18 0.1U/16V_4
PMC_SUSPWRDNACK ACPRESENT SOC_PMC_WAKE# PMC_BATLOW#
ALS_INT# TOUCH_INT_L_DX SOC_REST_BTN#
SOC_REST_BTN#
9/6 Add EC_REST_L for warm boot, EC side is OD type
RTC Clock 32.768KHz
RTC_X1
R347
10M_4
RTC_X2
ALERT Close to SOC
VR_SVID_ALERT#
VR_SVID_CLK VR_SVID_DATA
GND
R81 10K_4 R89 2.2K_4 R64 10K_4 R84 10K_4
R1 10K_4 R86 10K_4 R349 10K_4
R348 *SHORT_4
C259 15P/50V_4
12
Y3
32.768KHZ
C257 15P/50V_4
R386
73.2/F_4
1
PP1800_PCH_S5
PP1800_PCH
2nd BG332768453
PP1000_PCH
R410
73.2/F_4
7
EC_REST_L [28]
R408
73.2/F_4
DATA, CLK CLOSE TO VR
SPI_FLASHRTC Circuitry(RTC)
PP3300_PCH_S5
PP1800_PCH_ME
PP1800_PCH
R2
*0_6
30mils
+3V_RTC
R353
20K/F_4
PP3300_RTC
R361 *SHORT_6
A A
R352
20K/F_4
C262 1U/6.3V_4
5
SOC_RTEST#
C261 1U/6.3V_4
SRT_CRST#
C260 1U/6.3V_4
SPI_WP_ME
SPI_HOLD_ME
PP1800_PCH_S5
R12
*SHORT_6
SPI ROM needs power in S3/S5 for the TXE (Trusted execution engine).
near SPI ROM as possible
R345
*SHORT_4
R3
*SHORT_4
1
3
PCH_SPI_WP_D
Q31
PCH_SPI_WP_D connect to GPIO58 at GRB
2N7002K
2
SPI_WP_ME
4
GPIO_SPI_WP [18] SPI_HOLD#_BIOS [18]
SPI_WP_ME [26,28]
2
1
3
Q2
PJA138K
R17 *3.3K/F_4
R13 3.3K/F_4
To debug header
To PCH
From Screw/EC
3
C3 0.1U/16V_4
PP1800_PCH_ME
Default PD (pin3)
SPI_WP_ME_ROM
SPI_HOLD_ME
SPI_WP_ME
U11
8
SPI_SI
VCC
SPI_SO
3
R344
*SHORT_4
CS#
SPI_SCK
WP#
SPI_HOLD7GND
SPI_FLASH
soic8-7_9-1_27
AKE5EZN0N00
IC FLASH (8P) W25Q64FWSSIG (SOIC)
C2 0.1U/16V_4
3.3V
SPI_WP_ME_ROM_Q
LAYOUT CLOSE TO SPI ROM
5 2 1 6
4
PP1800_PCH_ME
U10
74LVC1G34
SOC_SPI_MOSI_R SOC_SPI_MISO_R SOC_SPI_CS#_R SOC_SPI_CLK_R
2 1
3 5
2
4
R26 22/F_4 R14 22/F_4 R5 22/F_4 R21 22/F_4
LAYOUT CLOSE TO SPI ROM
R25 *SHORT_4 R19 *SHORT_4 R24 *SHORT_4 R18 *SHORT_4
SPI NOR FLASH
SPI_WP_ME_ROM
R15 100K_4
SOC_SPI_MOSI SOC_SPI_MISO SOC_SPI_CS# SOC_SPI_CLKPP1800_PCH_ME_1
PCH_SPI_SI_R [18] PCH_SPI_SO_R [18] PCH_SPI_CS0#_R [18] PCH_SPI_CLK_R [18]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
Valley 5/9 (SPI/GPIO/CLK)
Valley 5/9 (SPI/GPIO/CLK)
Valley 5/9 (SPI/GPIO/CLK)
ZRU
ZRU
ZRU
417
417
1
417
1A
1A
1A
5
RAM_ID
Vender Freq.
Stage
C-2
3210 0x0000
Samsang AKD5PGST514 2GB 4K4B4G1646Q-HYK0 1600MHz Hynix
0x0010
Hynix H5TC4G63AFR-PBAAKD5JGETW04 Samsang K4B4G1646Q-HYK0AKD5PGST5140x0011
C-1
D D
0x0100 0x0101
Q P/N Mfr. PN
AKD5JGETW04 H5TC4G63AFR-PBA
H5TC4G63CFR-PBAAKD5PGSTW13Hynix
1600MHz0x0001 1600MHz 2GB 4 1600MHz 1600MHz
Size
4GBA-1
4GB 2GB 4GB1600MHz 8H5TC4G63CFR-PBAHynix AKD5PGSTW13
4
3
2
1
Pice
8
8
8 4
PP1800_PCH_S5
R342 10K_4
U12F
G2
02/14 Change RMID to 001.
RAM ID
RAM_ID0
R323 *1K_4 R324 1K_4 R329 *1K_4 R341 *1K_4
C C
PORT 1 USB CONN PORT 2
Cardreader HUB1 NA
PORT 3
NA
PORT 4
B B
PCLK_TPM[22]
CLK_PCI_EC[28] LPC_CLKRUN_L[28]
PP1800_PCH
R356 2.2K_4
A A
R355 2.2K_4 R350 2.2K_4
R319 1K_4
RAM_ID1
R320 *1K_4
RAM_ID2
R318 1K_4
RAM_ID3
R328 *1K_4
02/27 Reserve RAM_ID3 for memory BOM option.
MB USB3.0
CCD BT
USB_OC0#[15,26]
PP1800_PCH_S5
USB_OC1#[15,23]
R366 *0_4
R367 *SHORT_4
SMB_SOC_DATA SMB_SOC_CLK SMB_SOC_ALERTB
PP1800_PCH_S5
USBP0+[26] USBP0-[26]
USBP1+[23] USBP1-[23]
USBP2+[17] USBP2-[17]
USBP3+[20] USBP3-[20]
R53 1K/F_4 R59 1K/F_4
R379 10K_4 R339 10K_4
R41 45.3/F_4
R47 *0_4
R338 45.3/F_4 R67 49.9/F_4
LPC_LAD0[22,28] LPC_LAD1[22,28] LPC_LAD2[22,28] LPC_LAD3[22,28] LPC_LFRAME#[22,28]
CLK_PCI_EC_R SOC_CLKOUT_1 LPC_CLKRUN_L
SOC_SERIRQ[15]
R364 22/F_4 R359 22/F_4 R377 *SHORT_4
SMB_SOC_DATA[12] SMB_SOC_CLK[12]
ICLK_USB_TERMN_0 ICLK_USB_TERMN_1
USB_OC0# USB_OC1#
USB_RCOMP
SOC_CLKOUT_0
LTE_DISABLE#
RAM_ID1 RAM_ID2
RAM_ID3
USB_HSIC_RCOMP LPC_RCOMP
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#
SOC_CLKRUN# SOC_SERIRQ
SMB_SOC_DATA SMB_SOC_CLK SMB_SOC_ALERTB
0424 reserve R483 for CLKRUN# disable
GND
R369 *0_4
SOC_CLKRUN#
5
4
GPIO_S5_31
M3
GPIO_S5_32
L1
GPIO_S5_33
K2
GPIO_S5_34
K3
GPIO_S5_35
M2
GPIO_S5_36
N3
GPIO_S5_37
P2
GPIO_S5_38
L3
GPIO_S5_39
J3
GPIO_S5_40
P3
GPIO_S5_41
H3
GPIO_S5_42
B12
GPIO_S5_43
M16
USB_DP0
K16
USB_DN0
J14
USB_DP1
G14
USB_DN1
K12
USB_DP2
J12
USB_DN2
K10
USB_DP3
H10
USB_DN3
D10
ICLK_USB_TERMN_D10
F10
ICLK_USB_TERMN
C20
USB_OC_00
B20
USB_OC_11
D6
USB_RCOMPO
C7
USB_RCOMPI
M13
USB_PLL_MON
B4
USB_HSIC0_DATA
B5
USB_HSIC0_STROBE
E2
USB_HSIC1_DATA
D2
USB_HSIC1_STROBE
A7
USB_HSIC_RCOMP
BF18
LPC_RCOMP
BH16
ILB_LPC_AD_00
BJ17
ILB_LPC_AD_11
BJ13
ILB_LPC_AD_22
BG14
ILB_LPC_AD_33
BG17
ILB_LPC_FRAME
BG15
ILB_LPC_CLK_00
BH14
ILB_LPC_CLK_11
BG16
ILB_LPC_CLKRUN
BG13
ILB_LPC_SERIRQ
BG12
PCU_SMB_DATA
BH10
PCU_SMB_CLK
BG11
PCU_SMB_ALERT
VLV_M_D/BGA
+1.8V_S5 +1.8V_S5
+1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V/+3.3V +1.8V
+1.8V +1.8V +1.8V
6 OF 13
LTE_DISABLE#
+1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V
+1.8V
+1.8V +1.8V
+1.8V +1.8V
+1.8V +1.8V
+1.8V +1.8V
+1.8V +1.8V
+1.8V +1.8V
+1.8V +1.8V
3
RESERVED_M10
RESERVED_M9
RESERVED_P7 RESERVED_P6
RESERVED_M7
USB3_REXT0
RESERVED_P10 RESERVED_P12
RESERVED_M4 RESERVED_M6
USB3_RXP0 USB3_RXN0
USB3_TXP0 USB3_TXN0
RESERVED_H8 RESERVED_H7
RESERVED_H5 RESERVED_H4
GPIO_S0_SC_55 GPIO_S0_SC_56 GPIO_S0_SC_57 GPIO_S0_SC_58 GPIO_S0_SC_59 GPIO_S0_SC_60 GPIO_S0_SC_61
ILB_8254_SPKR
SIO_I2C0_DATA
SIO_I2C0_CLK
SIO_I2C1_DATA
SIO_I2C1_CLK
SIO_I2C2_DATA
SIO_I2C2_CLK
SIO_I2C3_DATA
SIO_I2C3_CLK
SIO_I2C4_DATA
SIO_I2C4_CLK
SIO_I2C5_DATA
SIO_I2C5_CLK
SIO_I2C6_DATA
SIO_I2C6_CLK
GPIO_S0_SC_092 GPIO_S0_SC_093
M10 M9
P7 P6
M7 M12
P10 P12
M4 M6
D4 E3
K6 K7
H8 H7
H5 H4
BD12 BC12 BD14 BC14 BF14 BD16 BC16
BH12
BH22 BG23
BG24 BH24
BG25 BJ25
BG26 BH26
BF27 BG27
BH28 BG28
BJ29 BG29
BH30 BG30
?
USB3_P0_REXTRAM_ID0
USB3_RXP0 USB3_RXN0
USB3_TXP0 USB3_TXN0
TRACKPAD_INT_DX GPIO_S0_SC_56 SOC_UART_TX SIM_DET_C EC_IN_RW_CUSB_PLL_MON
SOC_UART_RX
I2C_0_SDA_C I2C_0_SCL_C
I2C_1_SDA_C I2C_1_SCL_C
R43 1.24K/F_4
SOC_UART_TX SOC_UART_RX
R62
*0_4
Un-Stuff for Test Only
R388 22/F_4 R393 22/F_4
R400 22/F_4 R405 22/F_4
USB3_RXP0 [26]
USB3_RXN0 [26]
USB3_TXP0 [26] USB3_TXN0 [26]
2
TRACKPAD_INT_DX [27]
GPIO_S0_SC_56 [5] SOC_UART_TX [18]
EC_IN_RW_C [16] SOC_UART_RX [18]
I2C_0_SDA_R [16] I2C_0_SCL_R [16]
I2C_1_SDA_R [24] I2C_1_SCL_R [24]
Touch pad
TRACKPAD_INT_DX
SIM_DET_C
I2C_0_SDA_R I2C_0_SCL_R
I2C_1_SDA_R I2C_1_SCL_R
R60 10K_4
R63 10K_4
R389 4.7K_4 R394 4.7K_4
R401 4.7K_4 R406 4.7K_4
Audio Codec
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Tuesday, March 31, 2015
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
Tuesday, March 31, 2015
PROJECT :
Valley 6/9 (USB/LPC/I2C)
Valley 6/9 (USB/LPC/I2C)
Valley 6/9 (USB/LPC/I2C)
ZRU
ZRU
ZRU
1
PP1800_PCH
PP1800_PCH
of
1A
1A
1A
418
418
418
5
4
3
2
1
1031 for layout suggestion by intel, VSS_AXG_SENSE didn't connect to VSS_SENSE, will connect the GND via near VCC_AXG_SENSE
1031 for layout, add 0hm between
D D
+VCC_CORE+VCC_GFX
R116
R37
100/F_4
100/F_4
VCC_SENSE VCC_AXG_SENSE VSS_SENSE
R105
C C
B B
100/F_4
+VCC_CORE
GND and VSS_AXG_SENSE
VSS_AXG_SENSE[34]
VCC_SENSE[34] VCC_AXG_SENSE[34] VSS_SENSE[34]
PP1350
PP1350
C63 22U/6.3V_6 C62 10U/6.3V_4 C76 22U/6.3V_6 C73 10U/6.3V_4 C64 22U/6.3V_6 C81 22U/6.3V_8 C296 22U/6.3V_8 C77 22U/6.3V_8 C89 22U/6.3V_8 C289 22U/6.3V_8 C284 22U/6.3V_8 C282 22U/6.3V_8
R35 *SHORT_4
R169 *SHORT_4
C128 1U/6.3V_4 C104 1U/6.3V_4 C322 0.1U/16V_4
VCC_SENSE VCC_AXG_SENSE VSS_SENSE
PP1350_VSM
U12G
P28
CORE_VCC_SENSE_P28
BB8
UNCORE_VNN_SENSE
N28
CORE_VSS_SENSE_N28
AD38
DRAM_VDD_S4_AD38
AF38
DRAM_VDD_S4_AF38
A48
DRAM_VDD_S4
AK38
DRAM_VDD_S4_AK38
AM38
DRAM_VDD_S4_AM38
AV41
DRAM_VDD_S4_AV41
AV42
DRAM_VDD_S4_AV42
BB46
DRAM_VDD_S4_BB46
AA27
CORE_VCC_S0IX_AA27
AA29
CORE_VCC_S0IX_AA29
AA30
CORE_VCC_S0IX_AA30
AC27
CORE_VCC_S0IX_AC27
AC29
CORE_VCC_S0IX_AC29
AC30
CORE_VCC_S0IX_AC30
AD27
CORE_VCC_S0IX_AD27
AD29
CORE_VCC_S0IX_AD29
AD30
CORE_VCC_S0IX_AD30
AF27
CORE_VCC_S0IX_AF27
AF29
CORE_VCC_S0IX_AF29
AG27
CORE_VCC_S0IX_AG27
AG29
CORE_VCC_S0IX_AG29
AG30
CORE_VCC_S0IX_AG30
P26
CORE_VCC_S0IX_P26
P27
CORE_VCC_S0IX_P27
U27
CORE_VCC_S0IX_U27
U29
CORE_VCC_S0IX_U29
V27
CORE_VCC_S0IX_V27
V29
CORE_VCC_S0IX_V29
V30
CORE_VCC_S0IX_V30
Y27
CORE_VCC_S0IX_Y27
Y29
CORE_VCC_S0IX_Y29
Y30
CORE_VCC_S0IX_Y30
AF30
TP_CORE_V1P05_S4
VLV_M_D/BGA
7 OF 13
DRAM_VDD_S4_BD49 DRAM_VDD_S4_BD52 DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51
DRAM_VDD_S4_BJ48
DRAM_VDD_S4_C51 DRAM_VDD_S4_D44
DRAM_VDD_S4_F49 DRAM_VDD_S4_F52
DRAM_VDD_S4_F53 DRAM_VDD_S4_H46 DRAM_VDD_S4_M41 DRAM_VDD_S4_M42
DRAM_VDD_S4_V38
DRAM_VDD_S4_Y38
UNCORE_VNN_S3_AA24 UNCORE_VNN_S3_AC22 UNCORE_VNN_S3_AC24 UNCORE_VNN_S3_AD22 UNCORE_VNN_S3_AD24 UNCORE_VNN_S3_AF22 UNCORE_VNN_S3_AF24 UNCORE_VNN_S3_AG22 UNCORE_VNN_S3_AG24
UNCORE_VNN_S3_AJ22
UNCORE_VNN_S3_AJ24 UNCORE_VNN_S3_AK22 UNCORE_VNN_S3_AK24 UNCORE_VNN_S3_AK25 UNCORE_VNN_S3_AK27 UNCORE_VNN_S3_AK29 UNCORE_VNN_S3_AK30 UNCORE_VNN_S3_AK32 UNCORE_VNN_S3_AM22
TP2_CORE_VCC_S0IX
BD49 BD52 BD53 BF44 BG51 BJ48 C51 D44 F49 F52 F53 H46 M41 M42 V38 Y38
AA24 AC22 AC24 AD22 AD24 AF22 AF24 AG22 AG24 AJ22 AJ24 AK22 AK24 AK25 AK27 AK29 AK30 AK32 AM22
AA22
PP1350
+VCC_GFX
C113 1U/6.3V_4
C126 1U/6.3V_4
C118 1U/6.3V_4
C119 1U/6.3V_4
C124 1U/6.3V_4
C3204,C3205,C3217,C3218,C3231,C3238 footprint
C274 10U/6.3V_6
C264 22U/6.3V_8
C277 10U/6.3V_6
C263 22U/6.3V_8
C280 10U/6.3V_6
C268 22U/6.3V_8
C83 22U/6.3V_6
C50 10U/6.3V_4
+VCC_GFX
C272 22U/6.3V_8
Change netname for Layout
C125 1U/6.3V_4
󴣊󴣊󴣊󴣊󴥡󴥡󴥡󴥡󱻠󱻠󱻠󱻠󲒂󲒂󲒂󲒂󱘧󱘧󱘧󱘧
C49 10U/6.3V_4
CC0603_S
C52 22U/6.3V_6
9
C55 22U/6.3V_6
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
Valley 7/9 (Power 1)
Valley 7/9 (Power 1)
Valley 7/9 (Power 1)
ZRU
ZRU
ZRU
1A
1A
1A
of
419
419
1
419
5
4
3
2
1
C85 4.7U/6.3V_4 C105 4.7U/6.3V_4 C92 4.7U/6.3V_4 C107 4.7U/6.3V_4 C80 4.7U/6.3V_4
C37 1U/6.3V_4
D D
PP1000_PCH PP1000_PCH_SX
PP1000_PCH_SX
PP1000_PCH_SX
PP1000_PCH
C C
PP1000_PCH PP1000_PCH_SX
PP1000_PCH
PP1000_PCH_S5
PP1050_PCH PP1350_PCH_SX
B B
PP1350_PCH
PP1350_PCH
C28
A A
1U/6.3V_4
R114 *SHORT_4
R112 *SHORT_4 C96 4.7U/6.3V_4
C98 4.7U/6.3V_4 C99 4.7U/6.3V_4
R57 *SHORT_4 C43 4.7U/6.3V_4
C31 10U/6.3V_4 C24 10U/6.3V_4
R422 *SHORT_4
R33 *SHORT_4
R152 *SHORT_8 R127 *SHORT8
R333 *SHORT_6 C41 10U/6.3V_4
C20 1U/6.3V_4
USB3_V1P0_G3 VIS_V1P0_S0IX_PW
C34
0.01U/25V_4
C17 4.7U/6.3V_4
DARM_V1P0_S0IX_PWR_A
C97 4.7U/6.3V_4
DARM_V1P0_S0IX_PWR
DDI_V1P0_S0IX USB3_V1P0_G3 VIS_V1P0_S0IX_PW
C13 0.01U/25V_4 C30 10U/6.3V_4
C29 1U/6.3V_4 C58 10U/6.3V_4
CORE_V1P05 VIS_V1P0_S0IX_PW
C53 1U/6.3V_4 C56 10U/6.3V_4
C25 10U/6.3V_4 C67 1U/6.3V_4
USB3_V1P0_G3
C14 1U/6.3V_4 C19 1U/6.3V_4
CORE_V1P05
UNCORE_V1P35_S0IX
C87 4.7U/6.3V_4 C93 4.7U/6.3V_4
VGA_V1P35_S3
UNCORE_V1P35_S0IX
C38 4.7U/6.3V_4 C101 4.7U/6.3V_4
C9 10U/6.3V_4 C10 10U/6.3V_4
C293 22U/6.3V_8
C304 22U/6.3V_8
U12H
V32
SVID_V1P0_S3_V32
BJ6
VGA_V1P0_S3_BJ6
AD35
DRAM_V1P0_S0IX_AD35
AF35
DRAM_V1P0_S0IX_AF35
AF36
DRAM_V1P0_S0IX_AF36
AA36
DRAM_V1P0_S0IX_AA36
AJ36
DRAM_V1P0_S0IX_AJ36
AK35
DRAM_V1P0_S0IX_AK35
AK36
DRAM_V1P0_S0IX_AK36
Y35
DRAM_V1P0_S0IX_Y35
Y36
DRAM_V1P0_S0IX_Y36
AK19
DDI_V1P0_S0IX_AK19
AK21
DDI_V1P0_S0IX_AK21
AJ18
DDI_V1P0_S0IX_AJ18
AM16
DDI_V1P0_S0IX_AM16
U22
UNCORE_V1P0_G3_U22
V22
UNCORE_V1P0_G3_V22
AN29
VIS_V1P0_S0IX_AN29
AN30
VIS_V1P0_S0IX_AN30
AF16
UNCORE_V1P0_S3_AF16
AF18
UNCORE_V1P0_S3_AF18
Y18
UNCORE_V1P0_S3_Y18
G1
UNCORE_V1P0_S3_G1
AM21
PCIE_V1P0_S3_AM21
AN21
PCIE_V1P0_S3_AN21
AN18
PCIE_GBE_SATA_V1P0_S3_AN18
AN19
SATA_V1P0_S3_AN19
AA33
CORE_V1P05_S3_AA33
AF21
UNCORE_V1P0_S0IX_AF21
AG21
UNCORE_V1P0_S0IX_AG21
V24
VIS_V1P0_S0IX_V24
Y22
VIS_V1P0_S0IX_Y22
Y24
VIS_V1P0_S0IX_Y24
M14
USB_V1P0_S3_M14
U18
USB_V1P0_S3_U18
U19
USB_V1P0_S3_U19
AN25
GPIO_V1P0_S3_AN25
Y19
USB3_V1P0_G3_Y19
C3
USB3_V1P0_G3_C3
C5
UNCORE_V1P0_G3_C5
B6
UNCORE_V1P0_G3_B6
AC32
CORE_V1P05_S3_AC32
Y32
CORE_V1P05_S3_Y32
U36
UNCORE_V1P35_S0IX_F4_U36
AA25
UNCORE_V1P35_S0IX_F5_AA25
AG32
UNCORE_V1P35_S0IX_F2_AG32
V36
UNCORE_V1P35_S0IX_F3_V36
BD1
VGA_V1P35_S3_F1_BD1
AF19
UNCORE_V1P35_S0IX_F6
AG19
UNCORE_V1P35_S0IX_F1_AG19
AJ19
ICLK_V1P35_S3_F1_AJ19
AG18
ICLK_V1P35_S3_F2
AN16
VSSA_AN16
U16
USB_VSSA_U16
VLV_M_D/BGA
C299 22U/6.3V_8
8 OF 13
PP1000_PCH
C46 1U/6.3V_4
DRAM_V1P35_S0IX_F1_AD36
HDA_LPE_V1P5V1P8_S3_AM32
UNCORE_V1P8_S3_AM30
UNCORE_V1P8_S3_AN32
LPC_V1P8V3P3_S3_AM27
UNCORE_V1P8_G3_U24
USB_V3P3_G3_N18 USB_V3P3_G3_P18
UNCORE_V1P8_S3_U38
VGA_V3P3_S3_AN24
PCU_V1P8_G3_V25
3V_S5
PCU_V3P3_G3_N22
SD3_V1P8V3P3_S3_AN27
USB_HSIC_V1P24_G3_V18
UNCORE_V1P8_G3_AA18
C33 1U/6.3V_4
VSS_AD16 VSS_AD18
RTC_VCC_P22
USB_V1P8_G3_N20
PMU_V1P8_G3_U25 CORE_V1P05_S3_AF33 CORE_V1P05_S3_AG33 CORE_V1P05_S3_AG35
CORE_V1P05_S3_U33 CORE_V1P05_S3_U35 CORE_V1P05_S3_V33
VSS_A3_A3
VSS_A49_A49
VSS_A5_A5 VSS_A51_A51 VSS_A52_A52
VSS_A6_A6
VSS_B2_B2 VSS_B52_B52 VSS_B53_B53
VSS_BE1_BE1
VSS_BE53_BE53
VSS_BG1_BG1
VSS_BG53_BG53
VSS_BH1_BH1
VSS_BH2_BH2 VSS_BH52_BH52 VSS_BH53_BH53
VSS_BJ2_BJ2 VSS_BJ3_BJ3
VSS_BJ5_BJ5 VSS_BJ49_BJ49 VSS_BJ51_BJ51 VSS_BJ52_BJ52
VSS_C1_C1
VSS_C53_C53
VSS_E1_E1
VSS_E53_E53
RESERVED_F1 PCIE_V1P0_S3_AK18 PCIE_V1P0_S3_AM18
C35 1U/6.3V_4
AD36 AM32 AM30 AN32 AM27 U24 N18 P18 U38 AN24 V25 N22 AN27 AD16 AD18 V18 AA18 P22 N20 U25 AF33 AG33 AG35 U33 U35 V33 A3 A49 A5 A51 A52 A6 B2 B52 B53 BE1 BE53 BG1 BG53 BH1 BH2 BH52 BH53 BJ2 BJ3 BJ5 BJ49 BJ51 BJ52 C1 C53 E1 E53 F1 AK18 AM18
C39 1U/6.3V_4
UNCORE_V1P35_S0IX UNCORE_V1P8_AN32_PWR LPC_V3P3_PWR
V1P8_S5_PWR PCU_V3P3_G3_PWR
UNCORE_V1P8_AN32_PWR LPC_V3P3_PWR PCU_V1P8_G3_V25 PCU_V3P3_G3_PWR +VSDIO
VSS_AD18_AD16_PWR USB_HSIC_V1P24_G3 V1P8_AA18_PEW RTC_VCC_P22_PWR
V1P8_S5_PWR
CORE_V1P05
C51 1U/6.3V_4 C32 1U/6.3V_4
C79 1U/6.3V_4
C11 1U/6.3V_4
C106 1U/6.3V_4
R92 *SHORT_4 R99 *SHORT_4
R73 *SHORT_6 R82 *0_6
R78 *SHORT_4 R107 *SHORT_4
R29 *SHORT_4 R28 *SHORT_4 R32 *SHORT_4 R371 *SHORT_4
R87 *SHORT_4 C78 1U/6.3V_4
C82 4.7U/6.3V_4 C91 4.7U/6.3V_4 C86 4.7U/6.3V_4 C88 0.47U/6.3V_4
C36
0.01U/25V_4
PP1000_PCH
PP1800_PCH
PP3300_PCH
PP1800_PCH_S5 PP1800_PCH
PP3300_PCH_S5 PP3300_PCH
PP1000_PCH_S5 PP1800_PCH_S5 +3V_RTC
PP1800_PCH_S5
UNCORE_V1P8_AN32_PWR
V1P8_S5_PWR
PP1000_PCH
PP1000_PCH
LPC_V3P3_PWR
PCU_V3P3_G3_PWR
+VSDIO VSS_AD18_AD16_PWR
USB_HSIC_V1P24_G3 V1P8_AA18_PEW RTC_VCC_P22_PWR
C61 1U/6.3V_4
C68 1U/6.3V_4
C22
0.1U/16V_4
C42
0.1U/16V_4
C60 1U/6.3V_4
C65 1U/6.3V_4
C15
0.1U/16V_4
C4
0.1U/16V_4
10
C84 1U/6.3V_4
C45 0.1U/16V_4 C48 1U/6.3V_4
C94 1U/6.3V_4 C12 *1U/6.3V_4
C6 1U/6.3V_4 C16 1U/6.3V_4 C270 *1U/6.3V_4
C75 1U/6.3V_4
C74 1U/6.3V_4
C258
0.1U/16V_4
02/07 Add 7pcs
0.1U for EMI.
C26
0.1U/16V_4
C103 1U/6.3V_4
C70
0.01U/25V_4
C256
0.1U/16V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
Tuesday, March 31, 2015
Date: Sheet of
5
4
3
2
Tuesday, March 31, 2015
PROJECT :
Valley 8/9 (Power 2)
Valley 8/9 (Power 2)
Valley 8/9 (Power 2)
ZRU
ZRU
ZRU
1A
1A
1A
4110
4110
1
4110
5
4
3
2
1
11
D D
AG38
AH4 AH41 AH45
AH7
AH9
AJ1 AJ16 AJ21 AJ25 AJ27 AJ29
AJ3 AJ30 AJ32 AJ33 AJ35 AJ38 AJ53
AK10 AK14 AK16 AK33 AK41
AK44 AM12 AM19 AM24 AM25 AM29 AM33 AM35 AM36 AM40
M28
U12J
VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105
VLV_M_D/BGA
10 OF 13
VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140
AH47 AH48 AH50 AH51 AH6 AM44 AM51 AM7 AN1 AN11 AN12 AN14 AN22 AN3 AN33 AN35 AN36 AN38 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN5 AN51 AN53 AN6 AN8 AN9 AP40 AT12 AT16 AT19
U12I
A11
VSS1
A15
VSS2
A19
VSS3
A23
VSS4
A27
VSS5
A31
VSS6
A35
VSS7
A39
VSS8
A43
VSS9
A47
VSS10
AA1
VSS11
AA16
VSS12
C C
B B
AA19 AA21
AA3 AA32 AA35 AA38 AA53 AB10
AB4 AB41 AB45 AB47 AB48 AB50 AB51
AB6 AC16 AC18 AC19 AC21 AC25 AC33 AC35
VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35
VLV_M_D/BGA
9 OF 13
VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70
AC36 AC38 AD19 AD21 AD25 AD32 AD33 AD47 AD7 AE1 AE11 AE12 AE14 AE3 AE4 AE40 AE42 AE43 AE45 AE46 AE48 AE50 AE51 AE53 AE6 AE8 AE9 AF10 AF12 AF25 AF32 AF47 AG16 AG25 AG36
AT24 AT27 AT30 AT35 AT38
AT4 AT47 AT52
AU1
AU24
AU3 AU30 AU38 AU51 AV12 AV13 AV14 AV18 AV19 AV24 AV27 AV30 AV35 AV38 AV47 AV51
AV7 AW13 AW19 AW27
AW3
AW35
AY10 AY22 AY32
U12K
VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175
VLV_M_D/BGA
11 OF 13
VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210
AY36 AY4 AY50 AY9 BA14 BA19 BA22 BA27 BA32 BA35 BA40 BA53 BB19 BB27 BB35 BC20 BC22 BC26 BC28 BC32 BC34 BC42 BD19 BD24 BD27 BD30 BD35 BE19 BE2 BE35 BE8 BF12 BF16 BF24 BF38
BF30 BF36
BF4 BG31 BG34 BG39 BG42 BG45 BG49
BJ11 BJ15 BJ19 BJ23 BJ27 BJ31 BJ35 BJ39 BJ43 BJ47
BJ7 C14 C31 C34 C39 C42 C45 C49 D12 D16 D24 D30 D36 D38 E19 E35
U12L
VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245
VLV_M_D/BGA
12 OF 13
VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280
E8 F19 F2 F24 F27 F30 F35 F5 F7 G10 G20 G22 G26 G28 G32 G34 G42 H19 H27 H35 J1 J16 J19 J22 J27 J32 J35 J40 J53 K14 K22 K32 K36 K4 K50
M19 M26 M27 M34 M35 M38 M47 M51
N16 N38 N51 P13 P16 P19 P20 P24 P32 P35 P38
P47 P52
T40 U11
U12 U14 U21
L13 L19 L27 L35
K9
N1
P4
P9 U1
U12M
VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315
VLV_M_D/BGA
13 OF 13
VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350
U3 U30 U32 U40 U42 U43 U45 U46 U48 U49 U5 U51 U53 U6 U8 U9 V12 V16 V19 V21 V35 V40 V44 V51 V7 Y10 Y14 Y16 Y21 Y25 Y33 Y41 Y44 Y7 Y9
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
Valley 9/9 (GND)
Valley 9/9 (GND)
Valley 9/9 (GND)
1
ZRU
ZRU
ZRU
1A
1A
1A
of
4111
4111
4111
5
INTEL Debug Port
XDP_H_PRDY#[7] XDP_GPIO_DFX1[7]
D D
SOC_RSMRST#[7,15] PCH_PWRBTN_L[15,28]
CORE_PWROK_R[7,28]
SMB_SOC_DATA[8] SMB_SOC_CLK[8]
XDP_H_TCK[7]
C C
SOC_RSMRST# XDP_RSMRST#
XDP_GPIO_DFX2[7] XDP_GPIO_DFX3[7]
XDP_GPIO_DFX4[7]
XDP_GPIO_DFX5[7] XDP_GPIO_DFX6[7]
XDP_GPIO_DFX7[7] XDP_GPIO_DFX8[7]
R140 1K_4 R447 *SHORT_4
R137 1K_4 R151 *SHORT_4
R156 *SHORT_4 R159 *SHORT_4
4
XDP_H_PREQ# XDP_H_PRDY#
XDP_GPIO_DFX1 XDP_GPIO_DFX2
XDP_GPIO_DFX3 XDP_GPIO_DFX4
XDP_GPIO_DFX5 XDP_GPIO_DFX6
XDP_GPIO_DFX7 XDP_GPIO_DFX8
XDP_PMU_PWRBTN#PCH_PWRBTN_L XDP_COREPWROKCORE_PWROK_R
XDP_RTEST#XDP_RTEST_L SMB_XDP_SDASMB_SOC_DATA
SMB_XDP_SCLSMB_SOC_CLK XDP_H_TCK
PP1800_XDP_AB
C321 *0.1U/16V_4
CN2
GND
1
31
31
OBSFN_A0
3
32
32
OBSFN_A1
5
33
33
GND
7
34
34
OBSDATA_A_0
9
35
35
OBSDATA_A_1
11
36
36
13
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
GND
37
15
OBSDATA_A_2
38
17
OBSDATA_A_3
39
19
GND
40
21
OBSFN_B0
41
23
OBSFN_B1
42
25
GND
43
27
OBSDATA_B_0
44
29
OBSDATA_B_1
45
31
GND
46
33
OBSDATA_B_2
47
35
OBSDATA_B_3
48
37
GND
49
39
HOOK0
50
41
HOOK1
51
43
VCC_OBS_AB VCC_OBS_CD
52
45
HOOK2
53
47
HOOK3
54
49
GND
55
51
SDA
56
53
SCL
57
55
TCK1
58
57
TCK0
59
59
GND
60
*SEC_BSH-030-01-L-D-A-TR
3
GND OBSFN_C0 OBSFN_C1
GND
OBSDATA_C_0 OBSDATA_C_1
GND
OBSDATA_C_2 OBSDATA_C_3
GND
OBSFN_D_0 OBSFN_D_1
GND
OBSDATA_D_0 OBSDATA_D_1
GND
OBSDATA_D_2 OBSDATA_D_3
GND
ITPCLK/HOOK4
ITPCLK#/HOOK5
RESET#/HOOK6
DBR#/HOOK7
GND
TDO
TRSTn
TDI
GND_XDP_PRESENT
TMS
2
2
30
30
4
29
29
6
28
28
8
27
27
10
26
26
12
25
25
14
24
24
16
23
23
18
22
22
20
21
21
22
20
20
24
19
19
26
18
18
28
17
17
30
16
16
32
15
15
34
14
14
36
13
13
38
12
12
40
11
11
42
10
10
44
9
9
46
8
8
48
7
7
50
6
6
52
5
5
54
4
4
56
3
3
58
2
2
60
1
1
XDP_GPIO_S0_NC15 XDP_GPIO_DFX0
XDP_GPIO_S0_NC16 XDP_GPIO_S0_NC17
XDP_GPIO_S0_NC18 XDP_GPIO_S0_NC19
XDP_GPIO_S0_NC20 XDP_GPIO_S0_NC21
XDP_GPIO_S0_NC22 XDP_GPIO_S0_NC23
XDP_PMU_PLTRST# SOC_PLTRST# XDP_PMU_RSTBTN# SOC_REST_BTN#
XDP_H_TDO XDP_H_TRST# XDP_H_TDI XDP_H_TMS XDP_PRESENT_N
XDP_GPIO_S0_NC15 [5] XDP_GPIO_DFX0 [7]
XDP_GPIO_S0_NC16 [5] XDP_GPIO_S0_NC17 [5]
XDP_GPIO_S0_NC18 [5] XDP_GPIO_S0_NC19 [5]
XDP_GPIO_S0_NC20 [5] XDP_GPIO_S0_NC21 [5]
XDP_GPIO_S0_NC22 [5] XDP_GPIO_S0_NC23 [5]
R134 1K_4 R433 *SHORT_4
R136 *SHORT_4
PP1800_XDP_CD
1
C317 *0.1U/16V_4
SOC_PLTRST# [7,15] SOC_REST_BTN# [7,18]
XDP_H_TDO [7] XDP_H_TRST# [7] XDP_H_TDI [7] XDP_H_TMS [7]
12
XDP XDP
PP1800_PCH_S5
C320 *0.1U/16V_4
U16
*74AUP1G34GW
XDP_H_PREQ#_C[7]
B B
XDP_H_PREQ#_C
4
Buffer pin 1 NC
R444 *0_4
2 1
3 5
XDP_H_PREQ#
C323 *0.1U/16V_4
C117 0.1U/16V_4
PLACE C186 closed to XDP HOOK PIN 54
C319 0.1U/16V_4
PLACE C160 closed to XDP HOOK PIN48
APS
PP3300_PCH_S5
CN1
A A
*ACES_88511-180N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
APS1 PMC_SLP_S3#
ILB_RTC_RST# PMC_PWRBTN# PMC_RSTBTN#
5
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18
R11 *0_6 R10 *0_4
R9 *0_4
R8 *0_4 R7 *0_4 R6 *0_4
SLP_S3#
SLP_S4#PMC_SLP_S4#
SRT_CRST# SOC_PWRBTN# SOC_REST_BTN#
SLP_S3# [7,15]
SLP_S4# [3,7,15]
SRT_CRST# [7]
SOC_PWRBTN# [7,15]
4
XDP_RTEST#
XDP_PMU_RSTBTN#
PLACE R295 WITHIN 0.25" FROM XDP PIN
XDP_H_TDO
XDP_H_TMS XDP_H_TDI
PLACE R323 WITHIN 1.1" OF BUFFER PIN
XDP_H_PREQ#
XDP_H_TCK
PLACE R289 closed to XDP
XDP_H_TRST# XDP_PMU_PWRBTN#
3
R148 1K_4
R434 *1K_4
R440 51/F_4
R442 51/F_4 R441 51/F_4
R446 200/F_4
R160 51/F_4
R135 51/F_4 R445 *30K/F_4
PP3300_PCH_S5
PP1800_PCH
PP1800_XDP_AB
PP1800_PCH_S5
INTEL Debug Port Power
XDP Reset
XDP_RTEST_L
2
PP3300_PCH_S5
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Date: Sheet of
Date: Sheet of
PP1800_PCH PP1800_XDP_CD
R429 *SHORT_4
PP1800_PCH_S5 PP1800_XDP_ABPP1000_PCH_S5
R439 *SHORT_6 R435 *0_6
1
ZRU
ZRU
ZRU
SOC_RTEST# [7]
of
12 41
12 41
12 41
R133 *100K_4
3
*2N7002K
1
Q12
3
2
Q14
*2N7002K
1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CPU XDP / APS
CPU XDP / APS
CPU XDP / APS
1A
1A
1A
1
2
3
4
5
6
7
8
<DDR>
M_A_DQ43 [3] M_A_DQ44 [3] M_A_DQ42 [3] M_A_DQ40 [3] M_A_DQ47 [3] M_A_DQ45 [3] M_A_DQ46 [3] M_A_DQ41 [3]
M_A_DQ56 [3] M_A_DQ59 [3] M_A_DQ57 [3] M_A_DQ58 [3] M_A_DQ61 [3] M_A_DQ63 [3] M_A_DQ60 [3] M_A_DQ62 [3]
+DDR_VTT_RUN
+DDR_VTT_RUN
Vref_DQ
+SMDDR_VREF_DQ0
ZRU
ZRU
ZRU
8
13
C158
0.1U/16V_4
C150
0.047U/10V_4
13 41
13 41
13 41
1A
1A
1A
BYTE2_16-23
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD#B2 VDD#D9
VDD#G7
VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
VSSQ#B1
VSSQ#B9 VSSQ#D1 VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9 VSSQ#G1 VSSQ#G9
BYTE1_8-15
E3
M_A_DQ18
F7
M_A_DQ16
F2
M_A_DQ19
F8
M_A_DQ21
H3
M_A_DQ22
H8
M_A_DQ17
G2
M_A_DQ23
H7
M_A_DQ20
D7
M_A_DQ13
C3
M_A_DQ11
C8
M_A_DQ9
C2
M_A_DQ10
A7
M_A_DQ12
A2
M_A_DQ15
B8
M_A_DQ8
A3
M_A_DQ14
B2 D9 G7 K2 K8 N1 N9 R1 R9
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
M_A_DQ18 [3] M_A_DQ16 [3] M_A_DQ19 [3] M_A_DQ21 [3] M_A_DQ22 [3] M_A_DQ17 [3] M_A_DQ23 [3] M_A_DQ20 [3]
M_A_DQ13 [3] M_A_DQ11 [3] M_A_DQ9 [3] M_A_DQ10 [3] M_A_DQ12 [3] M_A_DQ15 [3] M_A_DQ8 [3] M_A_DQ14 [3]
M_A_DQSP0[3] M_A_DQSP3[3]
M_A_DM0[3] M_A_DM3[3]
M_A_DQSN0[3] M_A_DQSN3[3] M_A_DQSN4[3]
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_BS0 M_A_BS1 M_A_BS2
M_A_CLKP0 M_A_CLKN0 M_A_CKE0 M_A_CKE0 M_A_CKE0
M_A_ODT0 M_A_CS#0 M_A_CS#0 M_A_CS#0 M_A_RAS# M_A_CAS# M_A_WE#
M_A_DQSP0M_A_DQSP2 M_A_DQSP3 M_A_DQSP7
M_A_DQSN0M_A_DQSN2 M_A_DQSN3
M_A_DRAMRST# M_A_ZQ2
R191 240/F_4
U19
+SMDDR_VREF_DIMM
M_A_A[15:0][3]
A A
M_A_BS[2:0][3]
M_A_CLKP0[3] M_A_CLKN0[3] M_A_CKE0[3]
M_A_ODT0[3] M_A_CS#0[3] M_A_RAS#[3] M_A_CAS#[3] M_A_WE#[3]
M_A_DQSP2[3] M_A_DQSP1[3]
B B
M_A_DM2[3] M_A_DM1[3]
M_A_DQSN2[3] M_A_DQSN1[3]
M_A_DRAMRST#[3]
+SMDDR_VREF_DQ0
M8
VREFCA
H1
VREFDQ
N3
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_BS0 M_A_BS1 M_A_BS2
M_A_CLKP0 M_A_CLKN0 M_A_CKE0
M_A_ODT0 M_A_CS#0 M_A_RAS# M_A_CAS# M_A_WE#
M_A_DQSP1
M_A_DM2 M_A_DM0
M_A_DQSN1
M_A_DRAMRST# M_A_ZQ1
R187 240/F_4
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
100-BALL SDRAM DDR3
RAM _DDR3L
Hynix AKD5JGETW04--H5TC4G63AFR-PBA
M8
H1 N3
P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7
M7
M2
N8
M3
J7 K7 K9
K1 L2 J3 K3 L3
F3 C7
E7 D3
G3
B7
T2 L8
J1 L1 J9 L9
U20
VREFCA VREFDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
BA0 BA1 BA2
CK CK CKE
ODT CS RAS CAS WE
DQSL DQSU
DML DMU
DQSL DQSU
RESET ZQ
NC#J1 NC#L1 NC#J9 NC#L9
100-BALL SDRAM DDR3
RAM _DDR3L
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
VSS#A9 VSS#B3 VSS#E1
VSS#G8
VSS#J2
VSS#J8 VSS#M1 VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
BYTE0_0-7 BYTE3_24-31
E3
M_A_DQ3
F7
M_A_DQ5
F2
M_A_DQ2
F8
M_A_DQ0
H3
M_A_DQ7
H8
M_A_DQ4
G2
M_A_DQ6
H7
M_A_DQ1
D7
M_A_DQ29
C3
M_A_DQ27
C8
M_A_DQ28
C2
M_A_DQ26
A7
M_A_DQ25
A2
M_A_DQ30
B8
M_A_DQ24
A3
M_A_DQ31
B2 D9 G7 K2 K8 N1 N9 R1 R9
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
M_A_DQ3 [3] M_A_DQ5 [3] M_A_DQ2 [3] M_A_DQ0 [3] M_A_DQ7 [3] M_A_DQ4 [3] M_A_DQ6 [3] M_A_DQ1 [3]
M_A_DQ29 [3] M_A_DQ27 [3] M_A_DQ28 [3] M_A_DQ26 [3] M_A_DQ25 [3] M_A_DQ30 [3] M_A_DQ24 [3] M_A_DQ31 [3]
U21
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
M_A_DQSP6[3] M_A_DQSP4[3]
M_A_DM6[3] M_A_DM4[3]
M_A_DQSN6[3]
R467 240/F_4
M8
VREFCA
H1
VREFDQ
N3
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_BS0 M_A_BS1 M_A_BS2
M_A_CLKP0 M_A_CLKN0
M_A_ODT0 M_A_RAS#
M_A_CAS# M_A_WE#
M_A_DQSP6 M_A_DQSP4
M_A_DM6 M_A_DM5 M_A_DM4
M_A_DQSN6 M_A_DQSN4
M_A_DRAMRST# M_A_ZQ3
P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7
M2 N8 M3
J7 K7 K9
K1 L2
J3 K3 L3
F3 C7
E7 D3
G3 B7
T2 L8
J1 L1
J9 L9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
BA0 BA1 BA2
CK CK CKE
ODT CS RAS CAS WE
DQSL DQSU
DML DMU
DQSL DQSU
RESET ZQ
NC#J1 NC#L1 NC#J9 NC#L9
100-BALL SDRAM DDR3
RAM _DDR3L
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
VDDQ#A1
VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2
VDDQ#E9
VDDQ#F1 VDDQ#H2 VDDQ#H9
VSS#A9 VSS#B3 VSS#E1
VSS#G8
VSS#J2
VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9
VSS#T1
VSS#T9
VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
BYTE4_32-39 BYTE6_48-55
E3
M_A_DQ55
F7
M_A_DQ49
F2
M_A_DQ54
F8
M_A_DQ52
H3
M_A_DQ50
H8
M_A_DQ48
G2
M_A_DQ51
H7
M_A_DQ53
D7
M_A_DQ32
C3
M_A_DQ39
C8
M_A_DQ33
C2
M_A_DQ35
A7
M_A_DQ37
A2
M_A_DQ34
B8
M_A_DQ36
A3
M_A_DQ38
B2 D9 G7 K2 K8 N1 N9 R1 R9
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
M_A_DQ55 [3] M_A_DQ49 [3] M_A_DQ54 [3] M_A_DQ52 [3] M_A_DQ50 [3] M_A_DQ48 [3] M_A_DQ51 [3] M_A_DQ53 [3]
M_A_DQ32 [3] M_A_DQ39 [3] M_A_DQ33 [3] M_A_DQ35 [3] M_A_DQ37 [3] M_A_DQ34 [3] M_A_DQ36 [3] M_A_DQ38 [3]
M_A_DQSP5[3] M_A_DQSP7[3]
M_A_DM5[3] M_A_DM7[3]
M_A_DQSN5[3] M_A_DQSN7[3]
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_BS0 M_A_BS1 M_A_BS2
M_A_CLKP0 M_A_CLKN0
M_A_ODT0 M_A_RAS#
M_A_CAS# M_A_WE#
M_A_DQSP5
M_A_DM7M_A_DM3M_A_DM1
M_A_DQSN5 M_A_DQSN7
M_A_DRAMRST# M_A_ZQ4
R193 240/F_4
M8 H1
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3
L7 R7 N7 T3 T7 M7
M2 N8 M3
J7 K7 K9
K1
L2
J3 K3
L3
F3 C7
E7 D3
G3 B7
T2
L8
J1
L1
J9
L9
U22
VREFCA VREFDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15
BA0 BA1 BA2
CK CK CKE
ODT CS RAS CAS WE
DQSL DQSU
DML DMU
DQSL DQSU
RESET ZQ
NC#J1 NC#L1 NC#J9 NC#L9
100-BALL SDRAM DDR3
RAM _DDR3L
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD#B2 VDD#D9
VDD#G7
VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9
VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9
VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9
VSSQ#B1 VSSQ#B9
VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9
BYTE5_40-47 BYTE7_56-63
E3
M_A_DQ43
F7
M_A_DQ44
F2
M_A_DQ42
F8
M_A_DQ40
H3
M_A_DQ47
H8
M_A_DQ45
G2
M_A_DQ46
H7
M_A_DQ41
D7
M_A_DQ56
C3
M_A_DQ59
C8
M_A_DQ57
C2
M_A_DQ58
A7
M_A_DQ61
A2
M_A_DQ63
B8
M_A_DQ60
A3
M_A_DQ62
B2 D9 G7 K2 K8 N1 N9 R1 R9
A1 A8 C1 C9 D2 E9 F1 H2 H9
A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9 G1 G9
PP1350PP1350PP1350PP1350
P/NVendor
AKD5JGETW04 DDR3L 1600Mhz 4Gb
Hynix
AKD5JGST400
Elpida
C C
PP1350
Distributed around all DRAM devices (CHA and CHB)
C339 10U/6.3V_6
Place these Caps near each X16 Memory Down
C197 1U/6.3V_4
D D
C191 1U/6.3V_4
C170 1U/6.3V_4
C340 10U/6.3V_6
C159 1U/6.3V_4
C142 1U/6.3V_4
C199 1U/6.3V_4
C135 1U/6.3V_4
1
DDR3L 1333Mhz 4Gb
DDR3L 1600Mhz 4GbAKD5JGST404
C342
C341
10U/6.3V_6
10U/6.3V_6
C189
C141
1U/6.3V_4
1U/6.3V_4
C190
C168
1U/6.3V_4
1U/6.3V_4
C162
C169
1U/6.3V_4
1U/6.3V_4
C338 10U/6.3V_6
C198 1U/6.3V_4
C133 1U/6.3V_4
C134 1U/6.3V_4
C337 10U/6.3V_6
C167 1U/6.3V_4
C187 1U/6.3V_4
C144 1U/6.3V_4
2
C160 1U/6.3V_4
C161 1U/6.3V_4
C192 1U/6.3V_4
1205 add 0.1uFx2 on PP1350 for EMI request
C132 1U/6.3V_4
C143 1U/6.3V_4
C127
0.1U/16V_4
3
C175
0.1U/16V_4
+DDR_VTT_RUN
C209 1U/6.3V_4
C179
0.047U/10V_4
C148
0.047U/10V_4
C178 1U/6.3V_4
C211 1U/6.3V_4
Place these Caps near Memory Down CA & DQ pin
+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ0
4
1U/6.3V_4
C184
0.047U/10V_4
C155
0.047U/10V_4
1U/6.3V_4
C335
0.047U/10V_4
C154
0.047U/10V_4
C220
C206
C181
0.047U/10V_4
C152
0.047U/10V_4
5
C344 10U/6.3V_6
M_A_RAS# M_A_CAS# M_A_WE# M_A_BS0 M_A_BS1 M_A_BS2 M_A_CKE0 M_A_CS#0 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
R196 36/F_4 R199 36/F_4 R216 36/F_4 R218 36/F_4 R240 36/F_4 R203 36/F_4 R190 36/F_4 R206 36/F_4 R233 36/F_4 R232 36/F_4 R243 36/F_4 R234 36/F_4 R215 36/F_4 R224 36/F_4 R241 36/F_4 R252 36/F_4 R249 36/F_4 R239 36/F_4 R209 36/F_4 R237 36/F_4 R226 36/F_4 R251 36/F_4 R244 36/F_4 R211 36/F_4
6
+DDR_VTT_RUN
M1 solution
PP1350
R189
4.7K/F_4
R202
4.7K/F_4
7
M_A_ODT0
R197 36/F_4
M_A_CLKP0 M_A_CLKN0
R182 39/F_4 R183 39/F_4
C130 3.3P/50V_4
+DDR_VTT_RUN_A
M_A_CLKN0M_A_CLKP0
M1 solution
Vref_CA
+SMDDR_VREF_DIMM
C205
0.047U/10V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Tuesday, March 31, 2015
Tuesday, March 31, 2015
Tuesday, March 31, 2015
PP1350
R176
4.7K/F_4
R178
4.7K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
DDR3L MEMORY DOWNx16 A
DDR3L MEMORY DOWNx16 A
DDR3L MEMORY DOWNx16 A
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