Acer ASPIRE R3-471T Schematics

5

www.schematic-x.blogspot.com

4

3

2

1

ZQX_DDR3 BDW ULT SYSTEM BLOCK DIAGRAM

Dual Channel DDR III

D D

Memory Down

DDR3L-SODIMM

P15

2Rx16

Max. 4G

P14

SATA - HDD

P26

1066/1333/1600 MHZ

SATA0

Broadwell ULT 15W

MCP 1168pins

IMC

DC+GT3

40 mm X 24 mm

SATA

PCI-E x4 TX/RX

CLK

eDP

PCIE-5

EDP

GPU

N15S-GT N15V-GM

Display

P16~P21

X'TAL 27MHz

VRAM

DDR3

eDP Conn.

P23

P21

BOM

IV@ : iGPU EV@ : Optimus TDI@ : Touch pad I2C TSU@ : Touch screen USB TSI@ : Touch screen I2C SP@ : Special part TPM@ : TPM

01

TPMS@ : TPM IC OPTION

DDI1

DP

HDMI Conn.

P25

GT@ : N15S-GT GM@ : N15V-GM GMS@ : N15V-GM

USB2-0

CCD(Camera)

C C

Touch Screen(option)

P23

USB2-2

USB2-5

Integrated PCH

USB2.0

USB3.0/2.0

CLK

USB3-1

USB board

I/O Board Conn.USB2 IO

P28

USB2-1,2 ,7

PCI-E x1

X'TAL

32.768KHz

USB2 IO

X'TAL 24MHz

P8

Card Reader

BATTERY

Azalia

B B

RTC IHDA

LPC

P2~P13

CLK

SPI

SPI ROM

P8

Universal jack

PCIE-4 USB2-4

PCIE-3

USB3 Port MB side

P28

Mini CARD WLAN+BT

RTL8111GS

10/100/1G

P27

P24

X'TAL 25MHz

RJ45

P24

DMIC Array

Int. MIC

ALC283

AUDIO CODEC

P22

EC

IT8380

P30

TPM(option)

P26

Panel seosor board

Speaker*2

P22

A A

5

4

K/B Con.

P29

OCH1691WAD

HALL SENSOR

P23

Image Sensor

3

P32

Fan Driver

(PWM Type)

Gyro/eCompass/(Reserve) G sensor

P29

Light Sensor

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

PROJECT :

Block Diagram

ZQX

1 43Wednesday, September 03, 2014

1

1 43Wednesday, September 03, 2014

1B

5

4

3

2

1

SP@ : i3-4010U i3-4020U i5-4210U

D D

HDMI

C C

B B

INT_HDMITX2N[25]

INT_HDMITX2P[25]

INT_HDMITX1N[25]

INT_HDMITX1P[25]

INT_HDMITX0N[25]

INT_HDMITX0P[25] INT_HDMICLK-[25]

INT_HDMICLK+[25]

PCH_BRIGHT[23]

PCH_BLON[23]

EDP_VDD_EN[23]

TP94

BOARD_ID4[10] BOARD_ID1[10] BOARD_ID2[10]

PCH_BRIGHT PCH_BLON

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PME#

TPD_INT#_D DGPU_SELECT# BOARD_ID4 BOARD_ID1 BOARD_ID2

Haswell ULT (DISPLAY,eDP)

HSW_ULT_DDR3L

1 OF 19

HSW_ULT_DDR3L

9 OF 19

EDPDDI

DISPLAY

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN

DDPB_AUXP

DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

AD4

B8 A9 C6

U6 P4 N4 N2

U7

R5

L1 L3

L4

U28A

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

U28I

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

+3V +3V +3V +3V +3V

eDP SIDEBAND

+3V +3V +3V +3V +3V_S5

PCIE

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_AUXN EDP_AUXP

EDP_RCOMP

R537 100K_4

EDP_TXN0 [23] EDP_TXP0 [23] EDP_TXN1 [23] EDP_TXP1 [23]

EDP_AUXN [23] EDP_AUXP [23]

R229 24.9/F_4

R551 *0_4

R552 *0_4

HDMI_DDCCLK_SW [25] HDMI_DDCDATA_SW [25]

INT_HDMI_HPD [25] EDP_HPD [23]

02

eDP Panel

PCH_BRIGHTDP_UTIL

+VCCIOA_OUT

eDP_RCOMP Trace length < 100 mils Trace width = 20 mils Trace spacing = 25 mils

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

TPD_INT#_D

DGPU_SELECT#

R184 10K_4 R142 10K_4 R141 10K_4 R491 10K_4

R159 10K_4

R488 10K_4

DGPU_SELECT#,0=defalt,1=iGPU

+3V

A A

TPD_INT#[28,29]

Q19

5

4

3

2

2N7002K

1

TPD_INT#_D

Add 10/31

3

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

2

PROJECT :

Haswell 3/5 (DDI/eDP)

ZQX

2 43

1

1B

5

4

3

2

1

Change Data and DQS to interleave.

Haswell ULT (DDR3L) Haswell Processor (DDR3)

U28C

AH63

M_A_DQ0[14] M_A_DQ1[14] M_A_DQ2[14] M_A_DQ3[14] M_A_DQ4[14]

D D

C C

M_A_DQ5[14] M_A_DQ6[14] M_A_DQ7[14] M_A_DQ8[14]

M_A_DQ9[14] M_A_DQ10[14] M_A_DQ11[14] M_A_DQ12[14] M_A_DQ13[14] M_A_DQ14[14] M_A_DQ15[14]

M_B_DQ0[15]

M_B_DQ1[15]

M_B_DQ2[15]

M_B_DQ3[15]

M_B_DQ4[15]

M_B_DQ5[15]

M_B_DQ6[15]

M_B_DQ7[15]

M_B_DQ8[15]

M_B_DQ9[15] M_B_DQ10[15] M_B_DQ11[15] M_B_DQ12[15] M_B_DQ13[15] M_B_DQ14[15] M_B_DQ15[15] M_A_DQ16[14] M_A_DQ17[14] M_A_DQ18[14] M_A_DQ19[14] M_A_DQ20[14] M_A_DQ21[14] M_A_DQ22[14] M_A_DQ23[14] M_A_DQ24[14] M_A_DQ25[14] M_A_DQ26[14] M_A_DQ27[14] M_A_DQ28[14] M_A_DQ29[14] M_A_DQ30[14] M_A_DQ31[14] M_B_DQ16[15] M_B_DQ17[15] M_B_DQ18[15] M_B_DQ19[15] M_B_DQ20[15] M_B_DQ21[15] M_B_DQ22[15] M_B_DQ23[15] M_B_DQ24[15] M_B_DQ25[15] M_B_DQ26[15] M_B_DQ27[15] M_B_DQ28[15] M_B_DQ29[15] M_B_DQ30[15] M_B_DQ31[15]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8

M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15

M_B_DQ0

M_B_DQ1

M_B_DQ2

M_B_DQ3

M_B_DQ4

M_B_DQ5

M_B_DQ6

M_B_DQ7

M_B_DQ8

M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31

AH62

AK63

AK62 AH61 AH60

AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58 AR58 AM57

AK57

AL58

AK58 AR57 AN57

AP55 AR55 AM54

AK54

AL55

AK55 AR54 AN54

AY58 AW58

AY56 AW56

AV58 AU58

AV56 AU56

AY54 AW54

AY52 AW52

AV54 AU54

AV52 AU52

AK40

AK42 AM43 AM45

AK45

AK43 AM40 AM42 AM46

AK46 AM49

AK49 AM48

AK48 AM51

AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HSW_ULT_DDR3L

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1 SA_CKE0

SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32 AY34

AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#0 M_A_DQS#1 M_B_DQS#0 M_B_DQS#1 M_A_DQS#2 M_A_DQS#3 M_B_DQS#2 M_B_DQS#3

M_A_DQS0 M_A_DQS1 M_B_DQS0 M_B_DQS1 M_A_DQS2 M_A_DQS3 M_B_DQS2 M_B_DQS3

+VREF_CA_CPU +VREFDQ_SA_M3 +VREFDQ_SB_M3

M_A_CLK0# [14] M_A_CLK0 [14] M_A_CLK1# [14] M_A_CLK1 [14]

M_A_CKE0 [14] M_A_CKE1 [14]

M_A_CS#0 [14] M_A_CS#1 [14]

TP46

M_A_RAS# [14] M_A_WE# [14] M_A_CAS# [14]

M_A_BS#0 [14] M_A_BS#1 [14] M_A_BS#2 [14] M_A_A[15:0] [14]

M_A_DQS#0 [14] M_A_DQS#1 [14] M_B_DQS#0 [15] M_B_DQS#1 [15] M_A_DQS#2 [14] M_A_DQS#3 [14] M_B_DQS#2 [15] M_B_DQS#3 [15]

M_A_DQS0 [14] M_A_DQS1 [14] M_B_DQS0 [15] M_B_DQS1 [15] M_A_DQS2 [14] M_A_DQS3 [14] M_B_DQS2 [15] M_B_DQS3 [15]

U28D

AY31

M_A_DQ32[14] M_A_DQ33[14] M_A_DQ34[14] M_A_DQ35[14] M_A_DQ36[14] M_A_DQ37[14] M_A_DQ38[14] M_A_DQ39[14] M_A_DQ40[14] M_A_DQ41[14] M_A_DQ42[14] M_A_DQ43[14] M_A_DQ44[14] M_A_DQ45[14] M_A_DQ46[14] M_A_DQ47[14] M_B_DQ32[15] M_B_DQ33[15] M_B_DQ34[15] M_B_DQ35[15] M_B_DQ36[15] M_B_DQ37[15] M_B_DQ38[15] M_B_DQ39[15] M_B_DQ40[15] M_B_DQ41[15] M_B_DQ42[15] M_B_DQ43[15] M_B_DQ44[15] M_B_DQ45[15] M_B_DQ46[15] M_B_DQ47[15] M_A_DQ48[14] M_A_DQ49[14] M_A_DQ50[14] M_A_DQ51[14] M_A_DQ52[14] M_A_DQ53[14] M_A_DQ54[14] M_A_DQ55[14] M_A_DQ56[14] M_A_DQ57[14] M_A_DQ58[14] M_A_DQ59[14] M_A_DQ60[14] M_A_DQ61[14] M_A_DQ62[14] M_A_DQ63[14] M_B_DQ48[15] M_B_DQ49[15] M_B_DQ50[15] M_B_DQ51[15] M_B_DQ52[15] M_B_DQ53[15] M_B_DQ54[15] M_B_DQ55[15] M_B_DQ56[15] M_B_DQ57[15] M_B_DQ58[15] M_B_DQ59[15] M_B_DQ60[15] M_B_DQ61[15] M_B_DQ62[15] M_B_DQ63[15]

M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23 AW23

AY21 AW21

AV23 AU23

AV21 AU21

AY19 AW19

AY17 AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HSW_ULT_DDR3L

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32 AM35

AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

M_B_ODT0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_A_DQS#4 M_A_DQS#5 M_B_DQS#4 M_B_DQS#5 M_A_DQS#6 M_A_DQS#7 M_B_DQS#6 M_B_DQS#7

M_A_DQS4 M_A_DQS5 M_B_DQS4 M_B_DQS5 M_A_DQS6 M_A_DQS7 M_B_DQS6 M_B_DQS7

03

M_B_CLK0# [15] M_B_CLK0 [15] M_B_CLK1# [15] M_B_CLK1 [15]

M_B_CKE0 [15] M_B_CKE1 [15]

M_B_CS#0 [15] M_B_CS#1 [15]

TP45

M_B_RAS# [15] M_B_WE# [15] M_B_CAS# [15]

M_B_BS#0 [15] M_B_BS#1 [15] M_B_BS#2 [15] M_B_A[15:0] [15]

M_A_DQS#4 [14] M_A_DQS#5 [14] M_B_DQS#4 [15] M_B_DQS#5 [15] M_A_DQS#6 [14] M_A_DQS#7 [14] M_B_DQS#6 [15] M_B_DQS#7 [15]

M_A_DQS4 [14] M_A_DQS5 [14] M_B_DQS4 [15] M_B_DQS5 [15] M_A_DQS6 [14] M_A_DQS7 [14] M_B_DQS6 [15] M_B_DQS7 [15]

B B

+VREF_CA_CPU +VREFDQ_SA_M3 +VREFDQ_SB_M3

3 OF 19

+VREF_CA_CPU [14] +VREFDQ_SA_M3 [14] +VREFDQ_SB_M3 [15]

4 OF 19

Power tracking

A A

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

5

4

3

2

Wednesday, September 03, 2014

PROJECT :

Haswell 2/5 (DDR3 I/F)

ZQX

1B

3 43

1

3 43

1B

5

4

3

2

1

04

H_PECI (50ohm) Route on microstrip only

D D

C C

Spacing >18 mils Trace Length: 0.4~6.125 iches

H_PWRGOOD (50ohm) Trace Length: 1~11.25 inches

CPU_PLTRST# (50ohm) Trace Length: 10~17 inches

H_PECI[29] XDP_PRDY# [13]

H_PROCHOT#[29,30,34]

TP116 TP49

R569 56_4

SM_RCOMP[0:2] Trace length < 500 mils Trace width = 12~15 mils Trace spacing = 20 mils

PROC_DETECT CATERR# H_PECI

H_PROCHOT#_RH_PROCHOT#

H_PWRGOOD_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

DDR_PG_CTRL

Haswell ULT (SIDEBAND)

HSW_ULT_DDR3L

MISC

THERMAL

PWR

DDR3L

DSW

JTAG

2 OF 19

+1.05V_VCCST [5,10] +1.35V_SUS [5,14,15,32] +VCCIO_OUT [5] +5V_S5 [8,27,31,32,34,36]

D61 K61 N62

K63

C61

AU60

AV60

AU61

AV15 AV61

U28B

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

+1.05V_VCCST +1.35V_SUS +VCCIO_OUT +5V_S5

PRDY PREQ

PROC_TCK

PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J62

XDP_PRDY#

K62

XDP_PREQ#

E60

XDP_TCK0

E61

XDP_TMS_CPU

E59

XDP_TRST#

F63

XDP_TDI_CPU

F62

XDP_TDO_CPU

J60

XDP_BPM#0

H60

XDP_BPM#1

H61

XDP_BPM#2

H62

XDP_BPM#3

K59

XDP_BPM#4

H63

XDP_BPM#5

K60

XDP_BPM#6

J61

XDP_BPM#7CPU_DRAMRST#

XDP_PREQ# [13] XDP_TCK0 [8,13] XDP_TMS_CPU [13] XDP_TRST# [8,13] XDP_TDI_CPU [13] XDP_TDO_CPU [13]

XDP_BPM#0 [13]

XDP_BPM#1 [13]

TP114 TP113 TP55 TP117 TP58 TP56

TCK,TMS Trace Length < 9000mils

BPM#[0:7] Trace Length 1~6 inches Length match < 300 mils

Power tracking

B B

DRAM COMP

R249 200/F_4 U33

R250 120/F_4

R248 100/F_4

PU/PD of CPU

H_PROCHOT#

A A

H_PWRGOOD_R

R579 *62_4

R578 62_4

R565 10K_4

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

5

+VCCIO_OUT

+1.05V_VCCST

DRAMRST

CPU DRAM

CPU_DRAMRST#

+1.35V_SUS

12

4

XDP_TDO_CPU

XDP_TCK0 XDP_TRST#

R220 470_4

R568 51_4

R269 51_4 R262 *51_4

R217 *short_4

+1.05V_VCCST

12

C154

*0.1u/10V_4

DDR3_DRAMRST# [14,15]

3

DDR3L ODT GENERATIONXDP PU/PD

+3VSUS

12

R645 *220K/F_4

DDR_VTTT_PG_CTRL[32]

2

+5V_S5

12

R573 220K/F_4

+1.35V_SUS

2

R651 *2M/F_4

+1.35V_SUS

5

12

C545

0.1u/10V_4

3

Q41 2N7002K

1

Size Document Number Rev

Date: Sheet of

VCC

4

Y

74AUP1G07GW

R544 66.5/F_4 R542 66.5/F_4

Haswell 1/5 (PEG/DMI/FDI)

Wednesday, September 03, 2014

1

NC

2

3

R572 *short_4

M_B_ODT0_DIMM [15] M_B_ODT1_DIMM [15]

ZQX

4 43

1

A

GND

Quanta Computer Inc.

PROJECT :

DDR_PG_CTRL

1B

5

4

3

2

1

VDDQ Output Decoupling Recommendations

C217 10u/6.3V_6

TP61 TP68

TP47

TP44 TP48 TP64

TP51 TP52 TP50 TP62 TP70 TP69 TP59 TP66 TP65 TP60 TP53 TP63 TP67

+3V +1.05V +1.35V_SUS +1.05V_VCCST +VCCIN

Power tracking

TP57 TP54

ULT_RVSD_63 ULT_RVSD_64

VCC_SENSE_R ULT_RVSD_65

ULT_RVSD_66 ULT_RVSD_67 ULT_RVSD_68

H_CPU_SVIDART# H_CPU_SVIDCLK H_CPU_SVIDDAT VCCST_PWRGD VRON_CPU IMVP_PWRGD

ULT_RVSD_69 ULT_RVSD_70 ULT_RVSD_71 ULT_RVSD_72 ULT_RVSD_73 ULT_RVSD_74 ULT_RVSD_75 ULT_RVSD_76 ULT_RVSD_77 ULT_RVSD_78 ULT_RVSD_79 ULT_RVSD_80 ULT_RVSD_81

+1.05V_VCCST

+VCCIN

ULT_RVSD_61 ULT_RVSD_62

PWR_DEBUG_R

+3V [2,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36] +1.05V [11,13,30,33,34,35] +1.35V_SUS [4,14,15,32] +1.05V_VCCST [4,10] +VCCIN [34]

Haswell ULT (POWER)

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

L59

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59 AC22

AE22 AE23

AB57 AD57 AG57

C24

C28

C32

J58

U28L

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

+

C521 *330u_2.5V_3528

C236 22u/6.3V_8

C238 22u/6.3V_8

C282 22u/6.3V_8

C237 22u/6.3V_8

C242 *22u/6.3V_8

VCC Output Decoupling Recommendations

470uFx4 7343 22uFx8 22uFx11 10uFx11

C257 22u/6.3V_8

C254 22u/6.3V_8

C260 22u/6.3V_8

C250 22u/6.3V_8

C247 *22u/6.3V_8

C269 22u/6.3V_8

C252 22u/6.3V_8

C262 22u/6.3V_8

C245 22u/6.3V_8

C248 *22u/6.3V_8

TOP socket side 4 on TOP, 4 on BOT near socket edge

0805 0805

TOP, inside socket cavity

0805

BOT, inside socket cavity

C285 22u/6.3V_8

C274 22u/6.3V_8

C264 22u/6.3V_8

C271 22u/6.3V_8

C243 *22u/6.3V_8

SVID

+VCCIO_OUT

H_CPU_SVIDDAT

Place PU resistor close to CPU

H_CPU_SVIDART#

+VCCIN 32A

C267 22u/6.3V_8

C235 22u/6.3V_8

C265 22u/6.3V_8

C253 22u/6.3V_8

C266 *22u/6.3V_8

R260 *130/F_4

+VCCIN

C255 22u/6.3V_8C220

C523 22u/6.3V_8

C259 22u/6.3V_8

C256 22u/6.3V_8

C268 *22u/6.3V_8

+1.05V_VCCST

R259 130/F_4

R258 *short_4

R263 43_4

05

+VCCIO_OUT+1.05V

R555 *0_8

C528 *4.7u/6.3V_6

Layout note: need routing together and ALERT need between CLK and DATA.

VR_SVID_DATA [34]

R265 75_4

+VCCIO_OUT

R266 *75_4

VR_SVID_ALERT# [34]

+1.05V_VCCST

330uFx2 7343 22uFx11 10uFx10

+1.35V_SUS

D D

R231 0_1206 R239 0_1206

BOT socket side 5 onTOP, 6 on BOT inside socket cavity

0805

5 onTOP, 5 on BOT inside socket cavity

0805

+1.35V_CPU 1.4A

+1.35V_CPU

C219 10u/6.3V_6

C215

2.2u/6.3V_6

R566 100/F_4 R582 *short_4

300mA 300mA

VCCST_PWRGD[13]

R277 *short_4 R570 150_6

C240 *4.7u/6.3V_6

C278

2.2u/6.3V_6

VRON_CPU[34]

IMVP_PWRGD[10,34]

C276 10u/6.3V_6

C218

2.2u/6.3V_6

+VCCIO_OUT

+VCCIOA_OUT

+VCCIN

C494

2.2u/6.3V_6

+VCCIN

VCC_SENSE[34]

PWR_DEBUG[13]

+1.05V_VCCST

R564 *10K_4 R580 10K_4

+1.05V_VCCST+1.05V

C277 10u/6.3V_6

C216

10u/6.3V_6

+

C470 *470u/2V_7343

C C

B B

10u/6.3V_6

+1.05V_VCCST

VRON_CPU IMVP_PWRGD

R235 *short_8

+3V

HWPG_1.05V for DDR=1.5V

+1.05V

A A

R556 *4.7K_4

C535 *1000p/50V_4

2

Q38

1 3

*MMBT3904-7-F

5

+3V

R558 *4.7K_4

C534 *1000p/50V_4

2

10/30 reserve DDR=1.5V ,This block POP

R559 *4.7K_4

R557 *100K/F_4

Q40

1 3

*DTC144EU

HWPG_1.05V [29]

4

VCCST PWRGD

+1.05V_VCCST

10K_4

VCCST_PWRGD

C558 *0.1u/10V_4

R588 *short_4

+3V_S5

C573

0.1u/10V_4

VCCST_PWRGD_R

3

U37

5

VCC

4

Y

74AUP1G07GW

NC

GND

1

2

A

3

VCCST_PWRGD_EN

H_CPU_SVIDCLK

R612 *0_4 R613 *0_4R587 R604 *short_4

2

R268 *short_4

HWPG_1.05V_S5 [13,29,33] APWORK [7,29] PCH_PW ROK [7,29]

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

VR_SVID_CLK [34]

Quanta Computer Inc.

PROJECT :

Haswell 4/5 (POWER)

ZQX

1

5 43

1B

5

4

3

2

1

Haswell ULT (CFG,RSVD)

U28S

D D

NOA_STBN_0[13] NOA_STBN_1[13] NOA_STBP_0[13] NOA_STBP_1[13]

C C

R254 49.9/F_4

CFG0[13] CFG1[13] CFG2[13] CFG3[13] CFG4[8,13] CFG5[13] CFG6[13] CFG7[13] CFG8[13]

CFG9[13] CFG10[13] CFG11[13] CFG12[13] CFG13[13] CFG14[13] CFG15[13]

TP103

R541 8.2K_4

NOA_STBN_0 NOA_STBN_1 NOA_STBP_0 NOA_STBP_1

CFG_RCOMP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

TD_IREF

AC60 AC62 AC63 AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62 V63

J20 H18 B12

A5 E1

D1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP RSVD RSVD

RSVD RSVD RSVD TD_IREF

HSW_ULT_DDR3L

RESERVED

19 OF 19

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD

PROC_OPI_RCOMP

RSVD

RSVD RSVD

VSS VSS

RSVD RSVD

AV63 AU63

C63 C62 B43

A51 B51

L60 N60 W23

Y22 AY15

AV62 D58

P22 N21

P20 R20

OPI_COMP1

R224 49.9/F_4

06

Processor Strapping

1 0

CFG0 EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKED CFG1 PCH/ PCH LESS MODE SELECTION

(DEFAULT) NORMAL OPERATION; NO STALL

(DEFAULT) NORMAL OPERATION

STALL

PCH-LESS MODE

CFG0

CFG1

R270 *1K_4

R264 *1K_4

B B

CFG3 PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

CFG 8 ALLOW THE USE OF NOA ON LOCKED UNITS

CFG9 NO SVID PROTOCOL CAPABLE VR CONNECTED

CFG10 SAFE MODE BOOT

A A

5

DISABLED NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

DISABLED(DEFAULT); IN THIS CASE, NOA WILL BE DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS

VRS SUPPORTING SVID PROTOCOL ARE PRESENT

POWER FEATURES ACTIVATED DURING RESET

4

ENABLED AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT

ENABLED; NOA WILL BE AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT

NO VR SUPPORTING SVID IS PRESENT. THE CHIP WILL NOT GENERATE (OR RESPOND TO) SVID ACTIVITY

POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED

3

CFG3

CFG8

CFG9

CFG10

R561 *1K_4

R577 *1K_4

R560 *1K_4

R308 *1K_4

2

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

PROJECT :

Haswell 5/5 (CFG/GND)

ZQX

6 43

1

1B

5

4

3

2

1

Haswell ULT PCH (PM)

PCH_SUSACK#[29]

SYS_RESET#[13]

D D

SYS_PWROK EC_PWROK

PCH_SUSPWARN#[29]

PCH_SLP_S0#[13]

RSMRST#[29]

DNBSWON#[29]

ACPRESENT[30]

PCH_SUSPWRACK

R602 *short_4 R598 *0_4 R608 *0_4

R467 *0_4 R468 *0_4

C571 *1u/6.3V_4

R601 *0_4 R605 *0_4

R511 *short_4 R445 *0_4 R128 *short_4 R139 *short_4

TP38

SUSACK#_R

SYS_RESET#

SYS_PWROK_R EC_PWROK_R APWROK_R PCI_PLTRST#

PCH_RSMRST# PCH_SUSPWRACK PCH_PWRBTN# PCH_ACPRESENT PCH_BATLOW# PCH_SLP_S0# PCH_SLP_WLAN#

U28H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

AW6

AV4 AL7 AJ8

AN4

AF3

AM5

+3V_S5

PLTRST

RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

+3V +3V_S5 +3V_S5 DSW

DSW DSW DSW +3V_S5 DSW

+3V_S5

8 OF 19

DSWVRMEN

DPWROK

DSW

CLKRUN/GPIO32

SUS_STAT/GPIO61

DSW DSW DSW DSW DSW

WAKE

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4 SLP_S3

SLP_A SLP_SUS SLP_LAN

AW7

DSWVREN

AV5

DPWROK_R

AJ5

PCIE_LAN_WAKE#

V5

CLKRUN#

AG4

LPCPD#

AE6

PCH_SUSCLK

AP5

PCH_SLP_S5#

AJ6

SUSC#

AT4

SUSB#

AL5

PCH_SLP_A#

AP4

PCH_SLP_SUS#

AJ7

PCH_SLP_LAN#

Deep Sx

R479 *0_4

TP20

TP31

DSWVREN [8] DPWROK [29] PCIE_LAN_WAKE# [24,26]

CLKRUN# [21,29] LPCPD# [21]

PCH_SLP_S5# [13]

SUSC# [13,29] SUSB# [13,29] PCH_SLP_A# [13] PCH_SLP_SUS# [29]

07

C C

Power Sequence

PCH_PWROK[5,29]

R519

100K_4

R518 *short_4

EC_PWROK SYS_PWROK_R

R606 *0_4

EC_PWROK_R

DPWROK_RRSMRST#

APWORK[5,29]

R614 *short_4

Speed up 250ms to boot up for EC power on 250 ms

APWROK_R

R615 10K_4R482 *short_4

Non Deep Sx

PCH PM PU/PD

+3V

CLKRUN# SYS_RESET#

B B

A A

PCH_RSMRST# SYS_PWROK DPWROK_R

PCH_SUSPWRACK

PCH_ACPRESENT PCH_BATLOW# PCIE_LAN_WAKE# PCH_PWRBTN#

R160 8.2K_4 R499 10K_4

R510 10K_4 R596 *10K_4 R478 100K/F_4

+3V_S5

R453 *10K_4

+3V_S5

R165 10K_4 R505 8.2K_4 R193 1K_4 R137 *10K_4

+3VPCU

R134 *10K_4 R471 *8.2K_4 R169 *1K_4 R145 *10K_4

5

DSW PU

PLTRST# Buffer Deep Sx Circuit

+3V

PCI_PLTRST#

2 1

C127 0.1u/10V_4

4

U9

3 5

TC7SH08FU

R94 100K_4

PLTRST# [13,16,21,24,26,29]

+3V_S5 +3VCC_S5

C157 *0.33u/10V_6

SYSPWOK

+3V_S5

C561 *0.1u/10V_4

2

SYS_PWROK[13]

4

SYS_PWROK

4

U38 TC7SH08FU

R607 *0_4

3 5

EC_PWROK

1

3

EC_PWROK [29] IMVP_PWRGD_3V [10]

R616 10K_4

Size Document Number Rev

Date: Sheet of

2

PCH_SLP_SUS#

Wednesday, September 03, 2014

Non Deep Sx

R204 *Short_6

2

3

1

Q20 *AO3413

R136 *0_6

Q15 *2N7002K

ZQX

3

1

R151 *100K_4

2

Quanta Computer Inc.

PROJECT :

LPT 1/6 (DMI/FDI/VGA)

7 43

1B

5

[2,5,7,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36]

Haswell ULT PCH (RTC/HDA/SATA/SPI)

U28E

RTC_X1 RTC_X2

+3VPCU

20MIL

SM_INTRUDER# PCH_INTVRMEN SRTC_RST# RTC_RST#

HDA_BCLK_R HDA_SYNC_R HDA_RST#_R

HDA_SDO_R

XDP_TCK1 XDP_TDI PCH_JTAG_TDO

PCH_JTAGX

+3V_RTC_[0:2] Trace width = 20 mils

R481 1M_4

+3V_RTC

D D

C C

B B

RTC_RST#[13]

PCH_AZ_CODEC_SDIN0[22]

XDP_TRST#[4,13]

XDP_TCK1[13]

XDP_TDI[13] XDP_TDO[13] XDP_TMS[13]

XDP_TCK0[4,13]

RTC Circuitry (RTC)

VCCRTC_2

1 3

VCCRTC_3 VCCRTC_4

Q39 MMBT3904

2

12

BT6

R303 0_4

R571 0_4

R563 4.7K_4

RTC Clock 32.768KHz (RTC)

C437 18p/50V_4

C438 18p/50V_4

HDA

A A

PCH JTAG

JTAG_TCK,JTAG_TMS Trace Length < 9000mils

PCH_AZ_CODEC_RST#[22] PCH_AZ_CODEC_SDOUT[22] PCH_AZ_CODEC_BITCLK[22]

PCH_AZ_CODEC_SYNC[22]

23

XDP_TMS XDP_TDI PCH_JTAG_TDO PCH_JTAGX

XDP_TCK1

Y7

32.768KHZ

4 1

MP remove(Intel)

R272 51_4 R273 51_4 R271 51_4 R562 *1K_4

R276 *51_4

5

C448 *10p/50V_4

AW5

AW8

AV11 AY10

AU12 AU11

AW10

AV10

AU62 AE62 AD61 AE61 AD62 AL11

AE63

R516 *Short_6 R509 1K_4

R574 4.7K_4

RTC_X1

R508 10M_4

RTC_X2

R530 33_4 R536 33_4 R529 33_4

R532 33_4 C450 *10p/50V_4

+1.05V_S5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD

AC4

RSVD JTAGX

AV2

RSVD

+3V_RTC_2 +3V_RTC_1

+5V_S5

R576

68.1K/F_4

R575 150K/F_4

HDA_RST#_R HDA_SDO_R HDA_BCLK_R

HDA_SYNC_R

RTC

AUDIO SATA

JTAG

+3V_RTC Trace width = 30 mils

+3V_RTC

D29

R517

20K/F_4

BAT54C

R524

20K/F_4

C436 1u/6.3V_4

ULT Strapping Table

Pin Name Strap description

GPIO81(SPKR)

HDA_SDO

INTVRMEN

GPIO66

GPIO86

GPIO15

CFG4

DSWVREN

HSW_ULT_DDR3L

5 OF 19

C152 1u/6.3V_4

C161 1u/6.3V_4

4

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

+3V

SATA0GP/GPIO34

+3V

SATA1GP/GPIO35

+3V

SATA2GP/GPIO36

+3V

SATA3GP/GPIO37

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

RTC_RST#

12

J6 *JUMP

SRTC_RST#

12

J7 *JUMP

No reboot on TCO Timer expiration

Flash Descriptor Security Override / Intel ME Debug Mode

SPI_CS0#_UR_ME[29]

PCH_SPI_SO_EC[29]

Integrated 1.05V VRM enable ALWAYS

Top-Block Swap override

Boot BIOS Strap Bit

TLS(Transport layer security)

DP presence strap

Deep Sx well on die VR enable

4

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1

VGPU_EN

U1

SYS_COM_REQ

V6

GPIO36

AC1

GPIO37

A12

SATA_IREF

L11 K10 C12

SATA_RCOMP

U3

SATA_LED#

SATA_RCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils

PCH Quad SPI ROM(8M)

+3V_PCH_ME

R416 10K_4

PCH_SPI_SO

reserve for SPI fast read

SATA_RXN0 [21] SATA_RXP0 [21] SATA_TXN0 [21] SATA_TXP0 [21]

TP35 TP36 TP41 TP40

VGPU_EN [36]

R539 0_4

R538 3.01K/F_4 R455 10K_4

R415 *short_4 R430 15_4 R429 15_4

+3V_PCH_ME

R419 *1K_4

Sampled

PWROK

3

Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)

U28G

PCH_SPI_CLK

PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3

8 7 6 5

PCH_SPI_IO2

SPI_HOLD_IO3_ME

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

R421 *Short_6

SPI_HOLD_IO3_ME

R425 15_4 R427 15_4

PCH_SPI_CLK_R

PCH_SPI_SI_R

+3V_RTC

+3V_S5

+3V_RTC

LPC_LAD0[21,26,29] LPC_LAD1[21,26,29] LPC_LAD2[21,26,29] LPC_LAD3[21,26,29]

LPC_LFRAME#[21,26,29]

HDD

trace width 12~15mil

+V1.05S_ASATA3PLL

trace width 12~15mil

+V1.05S_ASATA3PLL +3V

(Default for WIN8)

U24

PCH_SPI_CS0# PCH_SPI_SO_R

0 = Default enable (iPD 20K)

1 =Disable No-Reboot mode

0 = Default can program ME (iPD 20K)

1 =can't program ME

1=Should be always pull-up 0 = Default disable (iPD 20K)

1 = Enable TBS function

0 = Default SPI (iPD 20K)

1 =LPC

0 = Default enable w/o confidentiality(iPD 20K)

1 =Default enable with confidentiality

0 = Enable an external display port is connected to the eDP

1 =disable

1=Should be always pull-up

1

CS#

2

IO1/DO

3

IO2/WP#

4

GND

W25Q64FVSSIQ -- 8MB

VCC

IO3/HOLD#

CLK

IO0/DI

change PN 11/15

SPI_WP_IO2_ME PCH_SPI_IO3

R423 15_4

R422 15_4 R98 0_4

Configuration note

3

2

HSW_ULT_DDR3L

+3V_S5

SMBUS

+3V_S5 +3V_S5 +3V_S5

C-LINKSPI

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

SML1ALERT/PCHHOT/GPIO73

LPC

SMBus

+3V_S5

R501 10K_4 R485 10K_4 R470 10K_4

R123 2.2K_4 R124 2.2K_4 R500 2.2K_4 R503 2.2K_4

+3V_PCH_ME+3V_S5

+3V_PCH_ME

C420 0.1u/10V_4

R418 *1K_4

PCH_SPI_CLK

PCH_SPI_SI

C430 *22p/50V_4

reserve for SPI fast read

R426 15_4 R428 15_4

3.3K is original and for no support fast read function

R448 *1K_4

+3V

HDA_SDO_R

GPIO66[10]

+3V

GPIO86[10]

+3V

GPIO15[10]

DSWVREN[7]

R535 0_4

R526 330K_4 R525 *330K_4

R520 *1K_4

R202 *1K_4

R161 8.2K_4

CFG4[6,13]

R513 330K_4

PCH_INTVRMEN

GPIO66

GPIO86

GPIO15

CFG4

DSWVREN

2

SMB0ALERT# SMB1ALERT# SMBALERT#

SMB_PCH_CLK SMB_PCH_DAT

SMBDATA0 SMBCLK0

PCH_SPI_CLK_EC [29] PCH_SPI_SI_EC [29]

SPKR

SMBALERT/GPIO11

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_DATA

7 OF 19

SPKR [10,22]

ME_WR# [29]

R527 *1K_4

R200 *1K_4

R186 *1K_4

R255 1K_4

R514 *330K_4

1

SYS_COM_REQ GPIO36 GPIO37

08

R495 10K_4 R185 10K_4 R498 10K_4

VGPU_EN

SMBCLK

CL_CLK CL_RST

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB0ALERT# SMBCLK0 SMBDATA0 SMB1ALERT# SMB_ME1_CLK SMB_ME1_DAT

CL_CLKPCH_SPI_CS0# CL_DAT CL_RST#

TP98 TP96 TP97

R465 *10K_4

SMBus(PCH)

+3V

R104

4.7K_4

R117

4.7K_4

SMB_PCH_DAT

SMB_PCH_CLK

Q17

5

2 6

2N7002DW

43

1

PCH_XDP_WLAN/S5 DDR_TP/S0

SMBus(EC)

2ND_MBCLK[19,29]

2ND_MBDATA[19,29]

EC/S5 PCH/S5

+3V_S5

Q14

5

2 6

*2N7002DW

2ND_MBCLK 2ND_MBDATA

+3VPCU +3V_S5 +3V +1.05V_S5 +V1.05S_ASATA3PLL

Power tracking

Size Document Number Rev

Date: Sheet of

LPT 2/6 (SATA/HDA/SPI)

Wednesday, September 03, 2014

R97 *2.2K_4

43

1

SMB_ME1_CLK SMB_ME1_DAT

R92 0_4

+3VPCU [7,11,13,21,22,23,28,29,30,31,35,36,37] +3V_S5 [5,7,9,10,11,13,21,24,27,28,29,31,34,36] +3V +1.05V_S5 [11,13,33,37] +V1.05S_ASATA3PLL [11]

Quanta Computer Inc.

PROJECT :

ZQX

1

+3V

R447 10K_4

CLK_SDATA [13,14,15,26]

CLK_SCLK [13,14,15,26]

R91 *2.2K_4

SMB_ME1_CLK

SMB_ME1_DAT

8 43

1B

5

4

3

2

1

Haswell ULT PCH (PCIE,USB3.0,USB2.0)

PCIE USB

+3V_S5 +3V_S5

HSW_ULT_DDR3L

11 OF 19

+3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5

DSW

USB2N0

DSW

USB2P0

DSW

USB2N1

DSW

USB2P1

DSW

USB2N2

DSW

USB2P2

DSW

USB2N3

DSW

USB2P3

DSW

USB2N4

DSW

USB2P4

DSW

USB2N5

DSW

USB2P5

DSW

USB2N6

DSW

USB2P6

DSW

USB2N7

DSW

USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

RSVD RSVD

AN8

USBP1- [27]

AM8 AR7

AT7 AR8

AP8 AR10

AT10 AM15

AL15 AM13

AN13 AP11

AN11 AR13

AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

MB USB3.0

USBP1+ [27] USBP2- [27]

DB USB2.0

USBP2+ [27]

TP37 TP39

USBP3- [27]

DB USB2.0

USBP3+ [27] USBP4- [26]

BT

USBP4+ [26] USBP5- [23]

Touch screen

USBP5+ [23] USBP6- [23]

CCD

USBP6+ [23] USBP7- [27]

Card reader

USBP7+ [27] PCLK_TPM [21]

USB3_RXN0 [27] USB3_RXP0 [27]

USB3_TXN0 [27] USB3_TXP0 [27]

R222 22.6/F_4

USB_OC0# [27] USB_OC1# [27]

MB USB3.0

USBCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils

MB U3

DB U2

WLAN LAN

VGA

CLK_PCIE_LANN[24] CLK_PCIE_LANP[24]

CLK_PCIE_LAN_REQ#[24]

CLK_PCIE_WLANN[26]

CLK_PCIE_WLANP[26]

PCIE_CLKREQ_WLAN#[26]

CLK_PCIE_VGA#[16]

CLK_PCIE_VGA[16]

CLK_PEGA_REQ#[16]

USB Overcurrent

USB_OC3# USB_OC1#

USB_OC0#

Swap for layou 11/14

U28K

PEG_RX#0[16]

D D

PEG x4

C C

WLAN LAN

B B

PEG_RX0[16]

PEG_TX#0[16]

PEG_TX0[16]

PEG_RX#1[16]

PEG_RX1[16]

PEG_TX#1[16]

PEG_TX1[16]

PEG_RX#2[16]

PEG_RX2[16]

PEG_TX#2[16]

PEG_TX2[16]

PEG_RX#3[16]

PEG_RX3[16]

PEG_TX#3[16]

PEG_TX3[16]

PCIE_RX3-_LAN[24] PCIE_RX3+_LAN[24]

PCIE_TX3-_LAN[24]

PCIE_TX3+_LAN[24]

PCIE_RX4-_WLAN[26]

PCIE_RX4+_WLAN[26]

PCIE_TX4-_WLAN[26]

PCIE_TX4+_WLAN[26]

+V1.05S_AUSB3PLL

C478 EV@0.22u/10V_4 C476 EV@0.22u/10V_4

C481 EV@0.22u/10V_4 C480 EV@0.22u/10V_4

C467 EV@0.22u/10V_4 C463 EV@0.22u/10V_4

C474 EV@0.22u/10V_4 C468 EV@0.22u/10V_4

C497 0.1u/10V_4 C506 0.1u/10V_4

C491 0.1u/10V_4 C493 0.1u/10V_4

TP42 TP43

TP105 TP104

R232 3.01K/F_4 R233 *short_4

PCIE_RCOMP PCIE_IREF

F10

PERN5_L0

E10

PERP5_L0

C23

R_PEG_TX#0 R_PEG_TX0

R_PEG_TX#1 R_PEG_TX1

R_PEG_TX#2 R_PEG_TX2

R_PEG_TX#3 R_PEG_TX3

PCIE_TX3PCIE_TX3+

PCIE_TX4PCIE_TX4+

PCIE_RXN1 PCIE_RXP1

PCIE_TXN1 PCIE_TXP1 USBCOMP

C22

F8 E8

B23 A23

H10 G10

B21 C21

E6 F6

B22 A21

G11

F11

C29 B30

F13

G13 B29

A29 G17

F17

C30 C31

F15

G15 B31

A31

E15 E13 A27 B27

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

PERN3 PERP3

PETN3 PETP3

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

Haswell ULT PCH (CLOCK)

U28F

TP108 TP106 TP92

TP22

R450 *short_4

R462 *short_4

R125 *short_4

+3V_S5

10

9 8 7 4

RP6

10K_10P8R

CLK_PCIE_N0 CLK_PCIE_P0 CLK_PCIE_REQ0#

CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

CLK_PCIE_REQ5#

1 2 3

56

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

HSW_ULT_DDR3L

+3V

CLK_PCIE_REQ0# CLK_PCIE_REQ1# CLK_PCIE_REQ2# CLK_PCIE_REQ3# CLK_PCIE_REQ5#

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8USB_OC2#

CLK_PCIE_REQ4#

CLOCK

SIGNALS

6 OF 19

R474 10K_4 R143 10K_4 R451 10K_4 R490 10K_4 R477 10K_4

R550 10K_4 R549 10K_4 R218 10K_4 R219 10K_4

R158 10K_4 R183 *1K_4

XTAL24_IN

XTAL24_OUT

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

+3V

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

R545 1M_4

C490 12p/50V_4

2 4

1 3

C489 12p/50V_4

XTAL24_IN XTAL24_OUT

ICLK_BIAS TESTLOW_C35

TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLK_PCH_PCI3 CLK_PCH_PCI4

Y8 24MHz

R546 3.01K/F_4

R228 TPM@22_4 R227 22_4 R225 22_4

C205 *18p/50V_4

CLK_PCI_LPCCLK_PCI_EC

09

+V1.05S_AXCK_LCPLL

CLK_PCI_LPC [26] CLK_PCI_EC [29]

CLK_PCIE_XDPN [13] CLK_PCIE_XDPP [13]

C210 *18p/50V_4

+V1.05S_AUSB3PLL +3V_S5 +3V +V1.05S_AXCK_LCPLL

+V1.05S_AUSB3PLL [11] +3V_S5 [5,7,8,10,11,13,21,24,27,28,29,31,34,36] +3V [2,5,7,8,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36] +V1.05S_AXCK_LCPLL [11]

Power tracking

A A

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

5

4

3

2

Wednesday, September 03, 2014

PROJECT :

LPT 3/6 (PCIE/USB/CLK)

ZQX

9 43

1

9 43

1B

5

4

3

2

1

PCH GPIO PU/PD

Haswell ULT PCH (GPIO,CPU/MISC,NCTF)

High Low

GPIO8

D D

C C

DEVSLP0 for HDD DEVSLP1 for mSATA

touch panel No Touch panel

GPIO8[23]

GPIO15[8]

DGPU_PWROK[17]

DGPU_HOLD_RST#[16]

DGPU_PWR_EN[37]

MODPHY_EN[33]

Sensor_INT[27,29]

G_sen_INT[27,29]

DEVSLP0[21]

TP93

SPKR[8,22]

R484 *short_4

TP21 TP33 TP29 TP95

TP27 TP18 TP19 TP34 TP30 TP26

DGPU_HOLD_RST# DGPU_PWR_EN

MODPHY_EN

TP25

R138 *short_4

DEVSLP0

SPKR

BOARD_ID0 LAN_DISABLE#

GPIO15 SKU_ID0 DGPU_PWROK GPIO24 WK_GPIO27 GPIO28 ODD_PRSNT#

GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47

DGPU_PW_CTRL# RAM_ID0

RAM_ID3 GPIO25

GPIO45

RAM_ID1 RAM_ID2

BOARD_ID3 DEVSLP1 SKU_ID1

Board ID

+3V

R492 10K_4

R181 10K_4

B B

R178 10K_4 R534 NTPM@10K_4

R489 10K_4

BOARD_ID0

BOARD_ID1[2]

BOARD_ID1

BOARD_ID2[2]

BOARD_ID2

BOARD_ID3

BOARD_ID4[2]

BOARD_ID4

R463 *10K_4

R156 *10K_4

R154 *10K_4 R533 TPM@10K_4

R461 *10K_4

U28J

P1

BMBUSY/GPIO76

AU2

AM7

AD6

AD5 AN5 AD7 AN3

AG6

AP1

AL4

AT5

AK4

AB6

AT3

AH4 AM4 AG5 AG3

AM3 AM2

Y1 T3

U4 Y3 P3 Y2

P2 C4 L2 N5 V2

+3V_S5

GPIO8 LAN_PHY_PWR_CTRL/GPIO12

+3V_S5

GPIO15

+3V

GPIO16

+3V

GPIO17

+3V_S5

GPIO24

DSW

GPIO27

+3V_S5

GPIO28

+3V_S5

GPIO26

+3V_S5

GPIO56

+3V_S5

GPIO57

+3V_S5

GPIO58

+3V_S5

GPIO59

+3V_S5

GPIO44

+3V_S5

GPIO47

+3V

GPIO48

+3V

GPIO49

+3V

GPIO50 HSIOPC/GPIO71

+3V_S5

GPIO13

+3V_S5

GPIO14

DSW

GPIO25

+3V_S5

GPIO45

+3V_S5

GPIO46

+3V_S5

GPIO9

+3V_S5

GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81

RAM ID

R506 SP@10K_4 R191 SP@10K_4 R502 SP@10K_4 R188 10K_4

RAM_IDVender Freq.

Hynix

Elpida 0010 AKD5JGST407 EDJ4216EFBG-GN-LF 1600MHz

MICRON 0100 MT41K256M16HA-125 1600MHzAKD5JGSTL08 Kingston 0101

0000 0001

1234

SKU ID

UMA Only

dGPU Only

Switchable (Mux)

Optimize (Muxless)

R497 IV@10K_4 R179 IV@10K_4

Low

BOARD_ID0

BOARD_ID1

A A

BOARD_ID2

BOARD_ID3

BOARD_ID4

Reserved (Default)

Enable on board memory

Default(LOW)

No DTPM

Reserved (Default)

5

High

Reserved

Disable on board memory

DTPM

Reserved

HSW_ULT_DDR3L

+3V

+3V +3V

GPIO

+3V

DSW

10 OF 19

RAM_ID0 RAM_ID1 RAM_ID2 RAM_ID3

+3V

CPU/

PCH_OPI_RCOMP

MISC

+3V

GSPI0_CS/GPIO83

+3V

GSPI0_CLK/GPIO84

+3V

GSPI0_MISO/GPIO85

+3V

GSPI0_MOSI/GPIO86

+3V

GSPI1_CS/GPIO87

+3V

GSPI1_CLK/GPIO88

+3V

GSPI1_MISO/GPIO89

+3V

GSPI_MOSI/GPIO90

+3V

UART0_RXD/GPIO91

+3V

UART0_TXD/GPIO92

+3V

UART0_RTS/GPIO93

SERIAL IO

+3V

UART0_CTS/GPIO94

+3V

UART1_RXD/GPIO0

+3V

UART1_TXD/GPIO1

+3V

UART1_RST/GPIO2

+3V

UART1_CTS/GPIO3

+3V

I2C0_SDA/GPIO4

+3V +3V +3V +3V +3V +3V +3V +3V +3V

R472 SP@10K_4 R167 SP@10K_4 R469 SP@10K_4 R163 *10K_4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

Q PN Mfr. PN

AKD5JGETW04 H5TC4G63AFR-PRBA(A) 1600MHz

H5TC4G63MFR-PBA(M) 1600MHzHynix 0011 AKD5PGSTW03

SKU_ID0 SKU_ID1

SKU_ID1 SKU_ID0 VGA H/W

0

1

0

1

0

1

4

R466 EV@10K_4 R155 EV@10K_4

Setup

Signal

Menu

UMA

Hidden

UMA boot

GPU

Hidden

GPU boot

UMA+GPU dGPU/SG UMA boot

UMA

UMA/SG

UMA boot

THRMTRIP

RCIN/GPIO82

SERIRQ

RSVD RSVD

+3V_S5

4 3 2 1

+3V

D60

THRMTRIP#

V4

SIO_RCIN#

T4

IRQ_SERIRQ

AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

OPI_COMP2

TP_INT_PCH GPIO84 GPIO85 GPIO86 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 SIO_EXT_SMI# SIO_EXT_SCI# DGPU_EVENT# GC6_FB_EN

GPIO64 GPIO65 GPIO66 GPIO67 GPIO68 GPIO69

R223 49.9/F_4

CPU thermal trip

IMVP_PWRGD_3V

+1.05V_VCCST

THRMTRIP#

IMVP_PWRGD[5,34]

3

I2C0 connect to Sensor HUB, I2C1 connect touchpanle and touchpad for Acer request 11/08

R203 *short_4 R210 *short_4

20130926 chnge GPIO port

+1.05V_VCCST

3

2

R627 1K_4

Q43 FDV301N

1

R628 1K_4

2

1 3

Q42 MMBT3904-7-F

U39

NC1VCC

2

A

GND3Y

74AUP1G07GW

SIO_RCIN# [29] IRQ_SERIRQ [21,29]

TP_INT_PCH [23]

GPIO86 [8]

SIO_EXT_SMI# [29] SIO_EXT_SCI# [29] DGPU_EVENT# [19] GC6_FB_EN [17,19] Sensor_PCH_DAT [29] Sensor_PCH_CLK [29] I2C1_SDA_GPIO6 [23,28] I2C1_SCL_GPIO7 [23,28]

GPIO66 [8]

SYS_SHDN# [21,31,35]

+1.05V_VCCST

5

C579

0.1u/10V_4

4

IRQ_SERIRQ DEVSLP0 DEVSLP1 SIO_RCIN# SIO_EXT_SMI# SIO_EXT_SCI#

GPIO85 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO64 GPIO65 TP_INT_PCH GPIO84 Sensor_PCH_DAT Sensor_PCH_CLK I2C1_SDA_GPIO6 I2C1_SCL_GPIO7 GPIO67 GPIO68 GPIO69

R475 *100K_4

R493 EV@100K_4 R494 *10K_4

+3V

12

R623 10K_4

IMVP_PWRGD_3V [7]

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

2

Wednesday, September 03, 2014

DGPU_PWR_EN

DGPU_HOLD_RST#

high UMA Only

GPU power is control by PCH

low

GPIO (Discrete, SG or Optimize)

ODD_PRSNT# GPIO8

GPIO24 GPIO28 GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO45 G_sen_INT

LAN_DISABLE# GPIO25

WK_GPIO27

GPIO27 : If not used then use

8.2-kΩ to 10-kΩ pull-down to GND.

Quanta Computer Inc.

PROJECT :

LPT 4/6 (GPIO/MISC)

R182 10K_4 R476 10K_4 R460 10K_4 R412 10K_4 R177 10K_4 R458 10K_4

R180 10K_4 R170 10K_4 R152 10K_4 R140 10K_4 R459 10K_4 R454 10K_4 R153 10K_4 R487 10K_4 R486 10K_4 R201 10K_4 R205 10K_4 R157 10K_4 R176 10K_4 R442 2.2K_4 R444 2.2K_4 R483 2.2K_4 R512 2.2K_4 R206 10K_4 R531 10K_4 R515 10K_4

R449 10K_4 R496 10K_4

DGPU_PW_CTRL# DGPU_PWROK

R504 10K_4 R473 10K_4

R187 10K_4 R162 10K_4 R189 10K_4 R207 10K_4 R190 10K_4 R211 10K_4 R166 10K_4 R144 10K_4 R164 10K_4 R452 10K_4

R209 10K_4 R147 10K_4 R168 10K_4 R192 *10K_4

1

ZQX

10

+3V

I2C PULL HIGH

R464 IV@1K_4

+3V_S5

10 43

+3V

1B

5

[2,5,7,8,9,10,13,14,15,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36]

C182 *1u/6.3V_4 C190 1u/6.3V_4 C191 1u/6.3V_4

+1.05V

25mA

C232 1u/6.3V_4

R212 *short_8

Deep Sx

+3VPCU

+3V_S5

D D

R238 *0_6

+1.05V_S5

Non Deep Sx

+3V

C C

+1.05V

WW15 4/10 Intel VCCDSW3 G3 can't boot issue.

C181

+PCH_VCCDSW+VCCPDSW

0.47u/25V_6

+1.05V_MODPHY

R208 *0_6

+1.05V_S5

+1.05V_DCPSUS2

R171 *0_6 R194 *Short_6

R523 *short_8

C201 1u/6.3V_4

+3VCC_S5

1.741A

C176 *1u/6.3V_4

C168

10u/6.3V_6

+V1.05S_AIDLE

10mA

C172

1u/6.3V_4

+V3.3DX_1.5DX_1.8DX_AUDIO

0.114A

+3VCC_S5

C163 1u/6.3V_4

41mA

C446 22u/6.3V_8

+1.05V

63mA

PCH VCCHSIO Power

B B

4

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

+V1.05S_APLLOPI

+1.05V_DCPSUS3

C202 22u/6.3V_8

+VCCPDSW

+V3.3S_VCCPCORE

+V1.05S_AXCK_DCB +V1.05S_AXCK_LCPLL

C204 1u/6.3V_4

1.838A

AA21

W21

AH14

AH13

AC9 AA9

AH10

K19

R21 K18

M20

AE20 AE21

K9

L10

M9

N8

P9 B18 B11

Y20

J13

V8

W9

J18 A20

J17 T21

V21

3

Haswell ULT PCH (Power)

HSIO

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

OPI

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

13 OF 19

U28M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

AH11 AG10 AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

+VCCRTCEXT

+V3.3M_PSPI

+1.05V_DCPSUS1

PCH_VCC_1_1_21

+V1.05S_CORE_PCH

0.109A

R237 *0_6

C231 1u/6.3V_4

+V3.3S_VCCSDIO +1.05V_DCPSUS4

+V1.05S_VCCUSBCORE

18mA

+PCH_VCCDSW

+V1.05M_VCCASW

2

R221 *Short_6

+V1.05M_VCCASW

+1.05V_S5

3mA 1mA

17mA

R236 *0_6

C230 1u/6.3V_4

R230 *short_8

C229 1u/6.3V_4

C193

0.1u/10V_4

C200 1u/6.3V_4

0.658A

C174 1u/6.3V_4

+V1.5S_VCCATS +V3.3S_VCCPTS

+1.05V_S5

C203 1u/6.3V_4

C171

0.1u/10V_4

+1.05V +1.05V

+1.05V

C170

0.1u/10V_4

R521 *Short_6 R522 *0_6

C192

0.1u/10V_4

C186 1u/6.3V_4

C195 1u/6.3V_4

R214 *short_8

C166 22u/6.3V_8

R540 *Short_6 R226 *Short_6

C208 1u/6.3V_4

R175 *Short_6

C160 1u/6.3V_4

+3VCC_S5

+3V_RTC

C447 1u/6.3V_4

R215 *short_8

C185 10u/6.3V_6

+1.05V

+3V_S5 +1.5V +3V +1.05V +3V_RTC +3VCC_S5 +1.05V_S5 +V1.05S_AUSB3PLL +V1.05S_ASATA3PLL +V1.05S_AXCK_LCPLL

Power tracking

+3V_S5 +3V

+1.5V +3V

+3V

1

11

+1.05V

+3V_S5 [5,7,8,9,10,13,21,24,27,28,29,31,34,36] +1.5V [22,26,35] +3V +1.05V [5,13,30,33,34,35] +3V_RTC [8,29] +3VCC_S5 [7,13] +1.05V_S5 [8,13,33,37] +V1.05S_AUSB3PLL [9] +V1.05S_ASATA3PLL [8] +V1.05S_AXCK_LCPLL [9]

7/2 remove LDO instead of MOS switch

L9 2.2uH/210mA_8

C196

*47u/6.3V_8

+1.05V_MODPHY +V1.05S_AUSB3PLL +1.05V_MODPHY +V1.05S_ASATA3PLL

A A

L11 2.2uH/210mA_8

C197

47u/6.3V_8

5

C198 47u/6.3V_8

C199 1u/6.3V_4

L18 2.2uH/210mA_8

C454

47u/6.3V_8

4

42mA41mA

C455 47u/6.3V_8

C457 1u/6.3V_4

PCH HDA Power

+3V_S5

R216 *Short_6

3

11mA

+V3.3DX_1.5DX_1.8DX_AUDIO

C189

0.1u/10V_4

Place close to ball

57mA

C184 *47u/6.3V_8

+V1.05S_APLLOPI+1.05V

C206 1u/6.3V_4

2

VCCAPLL power

+1.05V +V1.05S_AXCK_DCB

L10 2.2uH/210mA_8

C180

47u/6.3V_8

+1.05V +V1.05S_AXCK_LCPLL

L19 2.2uH/210mA_8

C460

47u/6.3V_8

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

0.2A

C179 47u/6.3V_8

C188 1u/6.3V_4

31mA

C461 47u/6.3V_8

Quanta Computer Inc.

PROJECT :

LPT 5/6 (POWER)

C462 1u/6.3V_4

1

ZQX

11 43

1B

5

4

3

2

1

Haswell ULT (GND)

HSW_ULT_DDR3L

18 OF 19

VSS_SENSE [34]

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U28O

HSW_ULT_DDR3L

15 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D50 D51 D53 D54 D55 D57 D59 D62

E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

H13

HSW_ULT_DDR3L

U28P

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

D5

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D8

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS VSS

16 OF 19

VSS_SENSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

VSS_SENSE_R

U28R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

R581 0_4 R567 100/F_4

HSW_ULT_DDR3L

AA1 AA58 AB10 AB20 AB22

AB7

AC61 AD21

AD3

AD63

AE10

AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18

AG1

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U28N

14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14

AV16 AV20 AV24 AV28

AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

D D

C C

B B

12

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

U28Q

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 TP_DC_TEST_AY60

TP111

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_B2

A A

5

TP99

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

4

HSW_ULT_DDR3L

17 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

3

A3

DC_TEST_A3_B3

A4

TP_DC_TEST_A4

A60

TP_DC_TEST_A60

A61

DC_TEST_A61_B61

A62

TP_DC_TEST_A62

AV1

TP_DC_TEST_AV1

AW1

TP_DC_TEST_AW 1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

TP_DC_TEST_AW 63

TP101 TP110 TP115

TP24 TP100

TP112

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

2

Wednesday, September 03, 2014

PROJECT :

LPT 6/6 (GND)

1

ZQX

12 43

1B

5

H_SYS_PWROK_XDP

R594 *1K_4

+3V_S5

4

3

2

1

13

+3V

D D

C C

B B

A A

XDP_DBRESET_N NOA_STBP_0

5

R619 *1K_4

TP23 TP14 TP83 TP32 TP13 TP16

TP102 TP119 TP120 TP17

HWPG_1.05V_S5[5,29,33]

SYS_PWROK[7]

SYS_RESET#

+3VCC_S5

R620 *1K_4

R595 *0_4

SUSB# [7,29] PCH_SLP_S5# [7]

SUSC# [7,29] PCH_SLP_A# [7]

RTC_RST# [8] NBSWON# [27,29] SYS_RESET# [7] PCH_SLP_S0# [7]

4

PWR_DEBUG[5]

XDP_PREQ#[4] XDP_PRDY#[4]

CFG0[6] CFG1[6]

CFG2[6] CFG3[6]

XDP_BPM#0[4] XDP_BPM#1[4]

CFG4[6,8] CFG5[6]

CFG6[6] CFG7[6]

CLK_SDATA[8,14,15,26]

CLK_SCLK[8,14,15,26] XDP_TCK1[8] XDP_TCK0[4,8]

+3VPCU

VCCST_PWRGD[5]

CFG0 CFG1

CFG2 CFG3

CFG4 CFG5

CFG6 CFG7

VCCST_PWRGD_XDP NBSWON#

H_SYS_PWROK_XDP

U31

NC1VCC

2

A

GND3Y

*74AUP1G07GW

CN6

31

31 323229 333328 343427 353526 363625 373724 383823 393922 404021 414120 424219 434318 444417 454516 464615 474714 484813 494912 505011 515110

52

53

54

55

56

57

58

59

60

*SEC_BSH-030-01-L-D-A-TR

5

*0.1u/10V_4

4

3

C536

30

9 8 7 6 5 4 3 2 1

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

XDP_TDO[8]

XDP_TDI[8]

XDP_TMS[8]

+1.05V

12

+3V

NOA_STBN_0 CFG8

CFG9 CFG10

CFG11 NOA_STBP_1

NOA_STBN_1 CFG12

CFG13 CFG14

CFG15 CK_XDP_P_R

CK_XDP_N_R XDP_RST_R_N

XDP_DBRESET_N XDP_TDO

XDP_TRST_N XDP_TDI XDP_TMS

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST_N

R247 *10K_4

R548 *0_4 R547 *0_4

R312 *1K_4 R609 *0_4

R261 *51_4

+3V

C287 *0.1u/10V_4

NOA_STBP_0 [6] NOA_STBN_0 [6]

CFG8 [6] CFG9 [6]

CFG10 [6] CFG11 [6]

NOA_STBP_1 [6] NOA_STBN_1 [6]

CFG12 [6] CFG13 [6]

CFG14 [6] CFG15 [6]

U16

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

*74CBTLV3126

2

CLK_PCIE_XDPP [9] CLK_PCIE_XDPN [9]

SYS_RESET#

DPAD

GND

Size Document Number Rev

Date: Sheet of

CPU/PCH XDP

Wednesday, September 03, 2014

PLTRST# [7,16,21,24,26,29]

+1.05V_S5

3

1B

6

2B

8

3B

11

4B

15 7

Quanta Computer Inc.

PROJECT :

XDP_TDO_CPU [4]

XDP_TDI_CPU [4]

XDP_TMS_CPU [4]

XDP_TRST# [4,8]

ZQX

13 43

1

1B

1

<DDR>

A A

Hynix

Elpida

B B

+1.35V_SUS +DDR_VTT_RUN +SMDDR_VREF_DIMM

C C

+VREF_CA_CPU +VREFDQ_SA_M3

Power tracking

+1.35V_SUS

D D

+DDR_VTT_RUN

M_A_DQS#[7:0][3]

M_A_DQS[7:0][3] M_A_DQ[63:0][3]

M_A_A[15:0][3]

SO-DIMMB SPD Ad dress is 0XA4 SO-DIMMB TS Add ress is 0X34

M_A_BS#[2:0][3]

M_A_CLK0[3] M_A_CLK0#[3] M_A_CKE0[3]

M_A_CS#0[3] M_A_RAS#[3] M_A_CAS#[3] M_A_WE#[3]

DDR3_DRAMRST#[4,15]

P/NVendor

AKD5JGST400

DDR3L 1333Mhz 4 Gb

DDR3L 1600Mhz 4 GbAKD5 JGST404

SO-DIMMB SPD Ad dress is 0XA4 SO-DIMMB TS Add ress is 0X34

M_A_CLK1[3]

M_A_CLK1#[3]

M_A_CKE1[3]

M_A_CS#1[3]

+1.35V_SUS [4,5,15,32] +DDR_VTT_RUN [15,32] +SMDDR_VREF_DIMM [15]

+VREF_CA_CPU [3] +VREFDQ_SA_M3 [3]

Place these Caps near Memory Down

C459

C298

10u/6.3V_6

C183 *1u/6.3V_4

C222 1u/6.3V_4

C209 1u/6.3V_4

C505 1u/6.3V_4

C445 *0.1u/10V_4

C554 *0.1u/10V_4

C138 1u/6.3V_4

C144 1u/6.3V_4

C511

10u/6.3V_6

*10u/6.3V_6

C435

C517

*1u/6.3V_4

1u/6.3V_4

C502

C310

*1u/6.3V_4

C485

C314

*1u/6.3V_4

C453

C433

*1u/6.3V_4

1u/6.3V_4

C169

C487

*0.1u/10V_4

C156

C516

*0.1u/10V_4

C131

C425

1u/6.3V_4

C148

C136

1u/6.3V_4

1

2

BYTE1_8-15

U15

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

100-BALL SDRAM DDR3

ESP@RAM _DDR3L

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#M1 VSS#M9 VSS#P1 VSS#P9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2

VSS#J2

J8

VSS#J8

M1 M9 P1 P9 T1

VSS#T1

T9

VSS#T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M8

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

H1

+SMDDR_VREF_DQ0

N3

M_A_A0

P7

M_A_A1

P3

M_A_A2

N2

M_A_A3

P8

M_A_A4

P2

M_A_A5

R8

M_A_A6

R2

M_A_A7

T8

M_A_A8

R3

M_A_A9

L7

M_A_A10

R7

M_A_A11

N7

M_A_A12

T3

M_A_A13

T7

M_A_A14

M7

M_A_A15

M2

M_A_BS#0

N8

M_A_BS#1

M3

M_A_BS#2

J7 K7 K9

K1

M_A_ODT0

L2 J3 K3 L3

F3

M_A_DQS0

C7

M_A_DQS1

E7 D3

G3

M_A_DQS#0

B7

M_A_DQS#1

T2 L8

R242 240/F_4

J1

1 2

L1 J9 L9

3

M_A_DQ0 M_A_DQ2 M_A_DQ4 M_A_DQ6 M_A_DQ47 M_A_DQ1 M_A_DQ3 M_A_DQ5 M_A_DQ7 M_A_DQ43

M_A_DQ14 M_A_DQ13 M_A_DQ10 M_A_DQ8 M_A_DQ15 M_A_DQ9 M_A_DQ11 M_A_DQ12

+1.35V_SUS +1.35V_SUS +1.35V_SUS +1.35V_SUS

+SMDDR_VREF_DQ0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK0 M_A_CLK0# M_A_CKE0

M_A_ODT0 M_A_CS#0 M_A_RAS# M_A_CAS# M_A_WE#

M_A_DQS2 M_A_DQS3

M_A_DQS#2 M_A_DQS#3

DDR3_DRAMRST#

M_A_ZQ2M_A_ZQ1

R234 240/F_4

1 2

BYTE0_0-7 BYTE5_40-47

U32

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

100-BALL SDRAM DDR3

ESP@RAM _DDR3L

C458 *10u/6.3V_6

C249 1u/6.3V_4

C316 *1u/6.3V_4

C469 *1u/6.3V_4

C241 *1u/6.3V_4

C519 *0.1u/10V_4

C488 *0.1u/10V_4

2

E3

M_A_DQ2

DQL0

F7

M_A_DQ0

DQL1

F2

M_A_DQ6 M_A_DQ47

DQL2

F8

M_A_DQ4

DQL3

H3

M_A_DQ7 M_A_DQ43

DQL4

H8

M_A_DQ5

DQL5

G2

DQL6

H7

M_A_DQ1

DQL7

D7

M_A_DQ13

DQU0

C3

M_A_DQ14

DQU1

C8

M_A_DQ8

DQU2

C2

M_A_DQ10

DQU3

A7

M_A_DQ9

DQU4

A2

M_A_DQ11

DQU5

B8

M_A_DQ12

DQU6

A3

M_A_DQ15

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

C440

C233 *10u/6.3V_6

C178 *1u/6.3V_4

C273 *1u/6.3V_4

C284 *1u/6.3V_4

C444 *1u/6.3V_4

C524 *0.1u/10V_4

C317 *0.1u/10V_4

10u/6.3V_6

C538 1u/6.3V_4

C251 *1u/6.3V_4

C477 *1u/6.3V_4

C211 1u/6.3V_4

C529 *0.1u/10V_4

C475 *0.1u/10V_4

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ0

12

C244 *10u/6.3V_6

C293 *1u/6.3V_4

C212 1u/6.3V_4

C315 *1u/6.3V_4

C173 *1u/6.3V_4

C486 *0.1u/10V_4

C512 *0.1u/10V_4

C175

0.047u/25V_4

C239

0.047u/25V_4

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK1 M_A_CLK1# M_A_CKE1

M_A_ODT0 M_A_CS#1 M_A_RAS# M_A_CAS# M_A_WE#

M_A_DQS2 M_A_DQS5

M_A_DQS#2 M_A_DQS#3

DDR3_DRAMRST# DDR3_DRAMRST#

M_A_ZQ6

R553 240/F_4

1 2

C158

C479

10u/6.3V_6

*10u/6.3V_6

C456

C167

*1u/6.3V_4

C452

C556

*1u/6.3V_4

C501

C509

*1u/6.3V_4

C141

C227

*1u/6.3V_4

1u/6.3V_4

C533

C439

*0.1u/10V_4

C520

C286

*0.1u/10V_4

12

C527

C555

0.047u/25V_4

Place these Caps near Memory Down CA & DQ pin

12

C224

C451

0.047u/25V_4

3

M8

+SMDDR_VREF_DIMM

H1

+SMDDR_VREF_DQ0

N3

M_A_A0

P7

M_A_A1

P3

M_A_A2

N2

M_A_A3

P8

M_A_A4

P2

M_A_A5

R8

M_A_A6

R2

M_A_A7

T8

M_A_A8

R3

M_A_A9

L7

M_A_A10

R7

M_A_A11

N7

M_A_A12

T3

M_A_A13

T7

M_A_A14

M7

M_A_A15

M2

M_A_BS#0

N8

M_A_BS#1

M3

M_A_BS#2

J7 K7 K9

K1

M_A_ODT0

L2 J3

M_A_RAS#

K3

M_A_CAS#

L3

M_A_WE#

F3

M_A_DQS0

C7

M_A_DQS1 M_A _DQS3

E7 D3

G3

M_A_DQS#0

B7

M_A_DQS#1

T2

DDR3_DRAMRST#

L8

M_A_ZQ5

R586 240/F_4

J1

1 2

L1 J9 L9

SP : ELPIDA DRAM P/N : AKD5JG ST400 HYNIX DRAM P/N : AKD5JGQ TW01

C543

C194

10u/6.3V_6

C484

C275

1u/6.3V_4

C499

C213

1u/6.3V_4

C515

C258

*1u/6.3V_4

C540

C557

*1u/6.3V_4

C504

C522

*0.1u/10V_4

C261

C225

*0.1u/10V_4

C426 1u/6.3V_4

C130 10u/6.3V_6

C429

C137

1u/6.3V_4

10u/6.3V_6

4

BYTE2_16-23BYTE0_0-7

U14

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

100-BALL SDRAM DDR3

ESP@RAM _DDR3L

VDDQ#A1

VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSSQ#B1 VSSQ#B9

VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

M_A_DQ16

DQL0

F7

M_A_DQ18

DQL1

F2

M_A_DQ21

DQL2

F8

M_A_DQ22

DQL3

H3

M_A_DQ17

DQL4

H8

M_A_DQ23

DQL5

G2

M_A_DQ20

DQL6

H7

M_A_DQ19

DQL7

D7

M_A_DQ26

DQU0

C3

M_A_DQ25

DQU1

C8

M_A_DQ27

DQU2

C2

M_A_DQ29

DQU3

A7

M_A_DQ30

DQU4

A2

M_A_DQ28

DQU5

B8

M_A_DQ31

DQU6

A3

M_A_DQ24

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

J1 L1 J9 L9

BYTE2_16-23 BYTE7_56-63

U29

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

100-BALL SDRAM DDR3

ESP@RAM _DDR3L

C214 10u/6.3V_6

C270 *1u/6.3V_4

C207 1u/6.3V_4

C140 *1u/6.3V_4

C143 1u/6.3V_4

C465 *0.1u/10V_4

C165 *0.1u/10V_4

12

C234

0.047u/25V_4

12

C432

0.047u/25V_4

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

12

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

C280 *10u/6.3V_6

C297 *1u/6.3V_4

C318 *1u/6.3V_4

C503 1u/6.3V_4

C500 1u/6.3V_4

C442 *0.1u/10V_4

C539 *0.1u/10V_4

C162

0.047u/25V_4

C279

0.047u/25V_4

E3

M_A_DQ18

DQL0

F7

M_A_DQ16

DQL1

F2

M_A_DQ22

DQL2

F8

M_A_DQ21

DQL3

H3

M_A_DQ19

DQL4

H8

M_A_DQ20

DQL5

G2

M_A_DQ23M_A_DQ3

DQL6

H7

M_A_DQ17

DQL7

D7

M_A_DQ25

C3

M_A_DQ26

C8

M_A_DQ29

C2

M_A_DQ27

A7

M_A_DQ28

A2

M_A_DQ31

B8

M_A_DQ24

A3

M_A_DQ30

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

C498

C526

10u/6.3V_6

*10u/6.3V_6

C263

C313

*1u/6.3V_4

1u/6.3V_4

C246

C272

1u/6.3V_4

C221

C142

1u/6.3V_4

*1u/6.3V_4

C472

C483

1u/6.3V_4

*1u/6.3V_4

C542

C164

*0.1u/10V_4

C311 *0.1u/10V_4

*0.1u/10V_4

12

C177

C308

0.047u/25V_4

12

C312

C326

0.047u/25V_4

4

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

J1 L1 J9 L9

C187 *10u/6.3V_6

C228 *1u/6.3V_4

C296 1u/6.3V_4

C291 *1u/6.3V_4

C434 *1u/6.3V_4

C530 *0.1u/10V_4

C443 *0.1u/10V_4

12

C226

0.047u/25V_4

12

C449

0.047u/25V_4

5

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK0 M_A_CLK0# M_A_CKE0

M_A_ODT0 M_A_CS#0 M_A_RAS# M_A_CAS# M_A_WE#

M_A_DQS5 M_A_DQS4

M_A_DQS#5 M_A_DQS#4

DDR3_DRAMRST#

M_A_ZQ3

R213 240/F_4

1 2

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK1 M_A_CLK1# M_A_CKE1

M_A_ODT0 M_A_CS#1 M_A_RAS# M_A_CAS# M_A_WE#

M_A_DQS4

M_A_DQS#5 M_A_DQS#4

DDR3_DRAMRST#

M_A_ZQ7

R543 240/F_4

1 2

+VREF_CA_CPU

+VREFDQ_SA_M3

5

U13

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

ESP@RAM _DDR3L

U27

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

ESP@RAM _DDR3L

R279 *Short_6

M3 solution

R282 *Short_6

M3 solution

6

BYTE4_32-39BYTE3_24-31

E3

M_A_DQ44

DQL0

F7

M_A_DQ46

DQL1

F2

M_A_DQ45

DQL2

F8

DQL3

H3

M_A_DQ40

DQL4

H8

M_A_DQ42

DQL5

G2

M_A_DQ41

DQL6

H7

DQL7

D7

M_A_DQ38

DQU0

C3

M_A_DQ37

DQU1

C8

M_A_DQ34

DQU2

C2

M_A_DQ33

DQU3

A7

M_A_DQ35

DQU4

A2

M_A_DQ36

DQU5

B8

M_A_DQ39

DQU6

A3

M_A_DQ32

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

100-BALL SDRAM DDR3

BYTE4_32-39BYTE1_8-15 BYTE3_24-31 BYTE6_48-55

E3

M_A_DQ46

DQL0

F7

M_A_DQ44

DQL1

F2

DQL2

F8

M_A_DQ45

DQL3

H3

DQL4

H8

M_A_DQ41

DQL5

G2

M_A_DQ42

DQL6

H7

M_A_DQ40

DQL7

D7

M_A_DQ37

DQU0

C3

M_A_DQ38

DQU1

C8

M_A_DQ33

DQU2

C2

M_A_DQ34

DQU3

A7

M_A_DQ32

DQU4

A2

M_A_DQ39

DQU5

B8

M_A_DQ36

DQU6

A3

M_A_DQ35

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

100-BALL SDRAM DDR3

M1 solution

+1.35V_SUS

Vref_CA

R275

1.8K/F_4

R281

1.8K/F_4

M1 solution

+1.35V_SUS

R290

1.8K/F_4

R288

1.8K/F_4

+SMDDR_VREF_DIMM

Vref_DQ

+SMDDR_VREF_DQ0

R280 2/F_6

C304

0.022u/16V_4

1 2

R274

24.9/F_4

R283 5.1/F_6

C327

0.022u/16V_4

1 2

R289

24.9/F_4

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

DDR3_DRAMRST#

1 2

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

1 2

C525 470p/50V_4

C281 470p/50V_4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK0 M_A_CLK0# M_A_CKE0

M_A_ODT0 M_A_CS#0 M_A_RAS# M_A_CAS# M_A_WE#

M_A_DQS7 M_A_DQS6

M_A_DQS#7 M_A_DQS#6

M_A_ZQ4

R113 240/F_4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK1 M_A_CLK1# M_A_CKE1

M_A_ODT0 M_A_CS#1 M_A_RAS# M_A_CAS# M_A_WE#

M_A_DQS7 M_A_DQS6

M_A_DQS#7 M_A_DQS#6

M_A_ZQ8

R528 240/F_4

CLK_SCLK[8,13,15,26]

CLK_SDATA[8,13,15,26]

WP =1 : WRITE DISABLE

M_A_ODT0

7

U12

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

ESP@RAM _DDR3L

U26

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

ESP@RAM _DDR3L

100-BALL SDRAM DDR3

R133 *0_4 R126 *0_4

+3V

R120 30/F_4

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1

VSSQ#B9

VSSQ#D1

VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9

VSSQ#G1

VSSQ#G9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1

VSSQ#B9

VSSQ#D1

VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9

VSSQ#G1

VSSQ#G9

SPD_CLK_SCLK SPD_CLK_SDATA

R146 *1K_4

Change to 36 ohm Modify connection on 10/25

+DDR_VTT_RUN

R112 36/F_4

M_A_WE# M_A_CAS# M_A_RAS# M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CKE0 M_A_CS#0 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_CKE1 M_A_CS#1

R435 36/F_4 R443 36/F_4C223 R438 36/F_4 R111 36/F_4 R439 36/F_4 R109 36/F_4 R108 36/F_4 R114 36/F_4 R441 36/F_4 R440 36/F_4 R110 36/F_4 R135 36/F_4 R148 36/F_4 R150 36/F_4 R507 36/F_4 R480 36/F_4 R122 36/F_4 R437 36/F_4 R118 36/F_4 R115 36/F_4 R457 36/F_4 R127 36/F_4 R436 36/F_4

R107 36/F_4 R116 36/F_4

6

M_A_CLK0

C553

3.3P/50V_4

M_A_CLK0#

R434 30/F_4

Size Document Number Rev

Date: Sheet of

7

BYTE7_56-63BYTE5_40-47 BYTE6_48-55

E3

M_A_DQ60

F7

M_A_DQ58

F2

M_A_DQ56

F8

M_A_DQ59

H3

M_A_DQ57

H8

M_A_DQ63

G2

M_A_DQ61

H7

M_A_DQ62

D7

M_A_DQ50

C3

M_A_DQ49

C8

M_A_DQ54

C2

M_A_DQ53

A7

M_A_DQ51

A2

M_A_DQ48

B8

M_A_DQ55

A3

M_A_DQ52

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

E3

M_A_DQ58

F7

M_A_DQ60

F2

M_A_DQ59

F8

M_A_DQ56

H3

M_A_DQ62

H8

M_A_DQ61

G2

M_A_DQ63

H7

M_A_DQ57

D7

M_A_DQ49

C3

M_A_DQ50

C8

M_A_DQ53

C2

M_A_DQ54

A7

M_A_DQ52

A2

M_A_DQ55

B8

M_A_DQ48

A3

M_A_DQ51

+1.35V_SUS+1.35V_SUS+1.35V_SUS +1.35V_SUS

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

SPD_A0

R174 *1K_4

SPD_A1

R173 *1K_4

SPD_A2

R172 *1K_4

U10

6

A0

SCL

5

A1

SDA

A2

7

VCC

WP

GND

*M24C02-WMN6TP

R149 *1K_4

SPD address:A2

+1.35V_SUS

change to 3.3p 10/28

M_A_CLK1

M_A_CLK1#

R433 30/F_4

C428

0.1u/10V_4

Quanta Computer Inc.

PROJECT :

DDR3 ME MORY DOWNx 16 A

Wednesday, September 03, 2014

8

R199 *1K_4 R198 *1K_4 R197 *1K_4

1

SPD_A0

2

SPD_A1

3

SPD_A2

8 4

3.3P/50V_4

R432 30/F_4

ZQX

8

C552

14

+3V

R431 30/F_4

C427

0.1u/10V_4

14 43

C153 *0.1u/10V_4

1B

5

4

3

2

1

M_B_A[15:0][3]

D D

M_B_BS#0[3] M_B_BS#1[3] M_B_BS#2[3] M_B_CS#0[3] M_B_CS#1[3] M_B_CLK0[3] M_B_CLK0#[3] M_B_CLK1[3] M_B_CLK1#[3] M_B_CKE0[3] M_B_CKE1[3] M_B_CAS#[3] M_B_RAS#[3]

R456 10K_4 R446 10K_4

+3V

C C

B B

M_B_WE#[3]

CLK_SCLK[8,13,14,26]

CLK_SDATA[8,13,14,26]

M_B_ODT0_DIMM[4] M_B_ODT1_DIMM[4]

M_B_DQS2[3] M_B_DQS0[3] M_B_DQS1[3] M_B_DQS3[3] M_B_DQS4[3] M_B_DQS5[3] M_B_DQS6[3]

M_B_DQS7[3] M_B_DQS#2[3] M_B_DQS#0[3] M_B_DQS#1[3] M_B_DQS#3[3] M_B_DQS#4[3] M_B_DQS#5[3] M_B_DQS#6[3] M_B_DQS#7[3]

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

DIMM1_SA0 DIMM1_SA1

M_B_DQS2 M_B_DQS0 M_B_DQS1 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#2 M_B_DQS#0 M_B_DQS#1 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

JDIM6A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM1_H=5.2_STD

PC2100 DDR3 SDRAM SO-DIMM

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

(204P)

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

M_B_DQ17 M_B_DQ16 M_B_DQ21 M_B_DQ18 M_B_DQ23 M_B_DQ22 M_B_DQ19 M_B_DQ20 M_B_DQ2 M_B_DQ3 M_B_DQ0 M_B_DQ1 M_B_DQ5 M_B_DQ4 M_B_DQ7 M_B_DQ6 M_B_DQ8 M_B_DQ12 M_B_DQ10 M_B_DQ15 M_B_DQ9 M_B_DQ14 M_B_DQ11 M_B_DQ13 M_B_DQ27 M_B_DQ31 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ26 M_B_DQ25 M_B_DQ24 M_B_DQ34 M_B_DQ35 M_B_DQ39 M_B_DQ38 M_B_DQ32 M_B_DQ33 M_B_DQ36 M_B_DQ37 M_B_DQ44 M_B_DQ40 M_B_DQ46 M_B_DQ42 M_B_DQ41 M_B_DQ45 M_B_DQ43 M_B_DQ47 M_B_DQ51 M_B_DQ55 M_B_DQ53 M_B_DQ48 M_B_DQ52 M_B_DQ49 M_B_DQ50 M_B_DQ54 M_B_DQ57 M_B_DQ56 M_B_DQ58 M_B_DQ59 M_B_DQ62 M_B_DQ63 M_B_DQ61 M_B_DQ60

M_B_DQ[63:0] [3]

+VREFDQ_SB_M3 +1.05V +SMDDR_VREF_DIMM +DDR_VTT_RUN +3V

Power tracking

R121 *10K_4

DDR3_DRAMRST#[4,14]

+VREFDQ_SB_M3 [3] +1.05V [5,11,13,30,33,34,35] +SMDDR_VREF_DIMM [14] +DDR_VTT_RUN [14,32] +3V [2,5,7,8,9,10,11,13,14,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36]

+3V

+SMDDR_VREF_DQ1

+SMDDR_VREF_DIMM

+1.35V_SUS

2.48A

+3V

PM_EXTTS#1

C537 *0.1u/10V_4

+SMDDR_VREF_DQ1

JDIM6B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=5.2_STD

M1 solution

+1.35V_SUS

PC2100 DDR3 SDRAM SO-DIMM

(204P)

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT1 VTT2

GND GND

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

15

+DDR_VTT_RUN

+1.35V_SUS

A A

+DDR_VTT_RUN +SMDDR_VREF_DQ1

Place these Caps near SO-DIMM

C496 10u/6.3V_6

C441 1u/6.3V_4

C492 10u/6.3V_6

C128 1u/6.3V_4

5

C510 10u/6.3V_6

C129 1u/6.3V_4

C514 10u/6.3V_6

C135 1u/6.3V_4

C507 10u/6.3V_6

C133

4.7u/6.3V_6

C495

0.1u/10V_4

+

C471 330u/2V_7343

+3V

3

C147

2.2u/6.3V_6

C146

0.1u/10V_4

C466

0.1u/10V_4

C482

0.1u/10V_4

C464

2.2u/6.3V_6

C508

0.1u/10V_4

+SMDDR_VREF_DIMM

C134

4.7u/6.3V_6

4

C513

0.1u/10V_4

C518 10u/6.3V_6 C321

C132

4.7u/6.3V_6

C473

0.1u/10V_4

+VREFDQ_SB_M3

M3 solution

C334

0.1u/10V_4

R278 *Short_6

C332

2.2u/6.3V_6

2

R285 2/F_6

0.022u/16V_4

1 2

R284

24.9/F_4

Size Document Number Rev

Date: Sheet of

R286

1.8K/F_4

R295

1.8K/F_4

Quanta Computer Inc.

PROJECT :

DDRIII SO-DIMM-1

Vref_DQ

+SMDDR_VREF_DQ1

C333 470p/50V_4

ZQX

15 43Wednesday, September 03, 2014

1

1B

1

+1.05V_GFX

A A

PEX_IOVDD + PEX_IOVDDQ = 1.042A

+1.05V_GFX

PEX_PLL_HVDD + PEX_SVDD_3V3 = 143mA

B B

+3V_GFX

C C

+1.05V_GFX

D D

Near GPU

C107 EV@22U/6.3VS_6 C90 EV@22U/6.3VS_6 C91 EV@10U/6.3V_6 C100 EV@10U/6.3V_6 C88 EV@4.7U/6.3V_6

C104 EV@1U/6.3V_4 C106 EV@1U/6.3V_4

Under GPU

C99 EV@22U/6.3VS_6 C89 EV@22U/6.3VS_6 C97 EV@10U/6.3VS_6 C103 EV@10U/6.3VS_6 C98 EV@4.7U/6.3V_6

Near GPU

C105 EV@1U/6.3V_4 C102 EV@1U/6.3V_4

Under GPU

C92 EV@0.1U/10V_4 C96 EV@4.7U/6.3V_6 C95 EV@4.7U/6.3V_6

Near GPU

8mils width (0.2MM)

VGA_VCCSENSE[36]

VGA_VSSSENSE[36]

R410 *200/F_4

CX300T30001 Change to 0ohm

R80 EV@0_4

Near GPU

C101 EV@4.7U/6.3V_6 C86 EV@1U/6.3V_4

C85 EV@0.1U/10V_4

PEX_PLLVDD = 130mA

R409 EV@10K/F_4

R86 EV@2.49K/F_4

1

PEX_TSTCLK PEX_TSTCLK#

PEX_PLLVDD

Under GPU

TESTMODE

PEX_TERMP

AA22 AB23 AC24 AD25 AE26 AE27

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AF22 AE22

AA14 AA15

AF25

AA8 AA9

AB8

AD9

F2

F1

2

U20A

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT PEX_TSTCLK_OUT

PEX_PLLVDD PEX_PLLVDD

TESTMODE

PEX_TERMP

ESP@N14P-GV2

2

NC NC

1/14 PCI_EXPRESS

PEX_WAKE

PEX_RST

PEX_CLKREQ

PEX_REFCLK PEX_REFCLK

PEX_TX0 PEX_TX0

PEX_RX0 PEX_RX0

PEX_TX1 PEX_TX1

PEX_RX1 PEX_RX1

PEX_TX2 PEX_TX2

PEX_RX2 PEX_RX2

PEX_TX3 PEX_TX3

PEX_RX3 PEX_RX3

PEX_TX4 PEX_TX4

PEX_RX4 PEX_RX4

PEX_TX5 PEX_TX5

PEX_RX5 PEX_RX5

PEX_TX6 PEX_TX6

PEX_RX6 PEX_RX6

PEX_TX7 PEX_TX7

PEX_RX7 PEX_RX7

PEX_TX8 PEX_TX8

PEX_RX8 PEX_RX8

PEX_TX9 PEX_TX9

PEX_RX9 PEX_RX9

PEX_TX10 PEX_TX10

PEX_RX10 PEX_RX10

PEX_TX11 PEX_TX11

PEX_RX11 PEX_RX11

PEX_TX12 PEX_TX12

PEX_RX12 PEX_RX12

PEX_TX13 PEX_TX13

PEX_RX13 PEX_RX13

PEX_TX14 PEX_TX14

PEX_RX14 PEX_RX14

PEX_TX15 PEX_TX15

PEX_RX15 PEX_RX15

GF119GF117

3

AB6

AC7 AC6 AE8

AD8 AC9

AB9 AG6

AG7 AB10

AC10 AF7

AE7 AD11

AC11 AE9

AF9 AC12

AB12 AG9

AG10 AB13

AC13 AF10

AE10 AD14

AC14 AE12

AF12 AC15

AB15 AG12

AG13 AB16

AC16 AF13

AE13 AD17

AC17 AE15

AF15 AC18

AB18 AG15

AG16 AB19

AC19 AF16

AE16 AD20

AC20 AE18

AF18 AC21

AB21 AG18

AG19 AD23

AE23 AF19

AE19 AF24

AE24 AE21

AF21 AG24

AG25 AG21

AG22

3

PEX_CLKREQ#

PEG_RX0_C PEG_RX0#_C

PEG_RX1_C PEG_RX1#_C

PEG_RX2_C PEG_RX2#_C

PEG_RX3_C PEG_RX3#_C

C119 EV@0.22U/10V_4 C118 EV@0.22U/10V_4

C116 EV@0.22U/10V_4 C117 EV@0.22U/10V_4

C115 EV@0.22U/10V_4 C114 EV@0.22U/10V_4

C113 EV@0.22U/10V_4 C112 EV@0.22U/10V_4

AD10

AD7

B19

F11

V5 V6

G1 G2 G3 G4 G5 G6 G7

V1 V2

W1 W2 W3 W4

4

PEGX_RST# [19]

CLK_PCIE_VGA [9] CLK_PCIE_VGA# [9]

PEG_RX0 [9] PEG_RX#0 [9]

PEG_TX0 [9] PEG_TX#0 [9]

PEG_RX1 [9] PEG_RX#1 [9]

PEG_TX1 [9] PEG_TX#1 [9]

PEG_RX2 [9] PEG_RX#2 [9]

PEG_TX2 [9] PEG_TX#2 [9]

PEG_RX3 [9] PEG_RX#3 [9]

PEG_TX3 [9] PEG_TX#3 [9]

U20C

14/14 XVDD/VDD33

NC NC NC

3V3AUX_NC

FERMI_RSVD1_NC FERMI_RSVD2_NC

CONFIGURABLE POWER CHANNELS * nc on substrate

XPWR_G1 XPWR_G2 XPWR_G3 XPWR_G4 XPWR_G5 XPWR_G6 XPWR_G7

XPWR_V1 XPWR_V2

XPWR_W1 XPWR_W2 XPWR_W3 XPWR_W4

ESP@N14P-GV2

4

GPU_PEX_RST_HOLD#[19]

VDD33 = 56mA

VDD33 VDD33 VDD33 VDD33

PEX_CLKREQ#

G10 G12 G8 G9

C39 EV@4.7U/6.3V_6 C38 EV@1U/10V_6

C26 EV@0.1U/10V_4 C25 EV@0.1U/10V_4

5

+3V_GFX +3V_GFX

R81 EV@10K/F_4

1

R83 *0_4

SYS_PEX_RST_MON#

R397 *0_4

PLTRST#[7,13,21,24,26,29]

DGPU_HOLD_RST#[10]

Un-stuff Sys_PEX_RST_MON# , stuff PEGX_RST# for not GC6 stuff Sys_PEX_RST_MON# for GC6

+3V_GFX

Near GPU

C37 EV@4.7U/6.3V_6 C94 EV@1U/10V_6

C24 EV@0.1U/10V_4

Under GPU

+3V_MAIN

Under GPU

5

Follow Z09 to isolate CLK_REQ#

2

3

Q12

EV@2N7002K

C416 EV@0.1U/10V_4

+3V

2 1

3 5

+3V

2 1

3 5

CLK_PEGA_REQ# [9]

PU at page 9

C417 *0.1U/10V_4

4

U22 *MC74VHC1G08DFT2G

4

U23 EV@MC74VHC1G08DFT2G

6

PEGX_RST#

R398 EV@0_4

Power down sequence

6

R399 EV@100K/F_4

SYS_PEX_RST_MON# [19]

7

NVDD = 32.22 ~ 26.66 A

Under GPU

C70 EV@1U/6.3V_4 C79 EV@1U/6.3V_4 C55 EV@1U/6.3V_4 C67 EV@1U/6.3V_4 C43 EV@4.7U/6.3V_6 C46 EV@4.7U/6.3V_6 C44 EV@4.7U/6.3V_6 C73 EV@4.7U/6.3V_6 C47 EV@4.7U/6.3V_6 C74 EV@4.7U/6.3V_6 C76 EV@4.7U/6.3V_6 C59 EV@4.7U/6.3V_6 C62 EV@4.7U/6.3V_6 C60 EV@4.7U/6.3V_6

12

+

C395

EV@330u_2.5V_3528

C77 EV@22U/6.3V_8 C75 EV@10U/6.3VS_6

C61 EV@4.7U/6.3VS_6 C58 EV@4.7U/6.3VS_6 C45 EV@4.7U/6.3VS_6 C42 EV@4.7U/6.3VS_6 C72 EV@4.7U/6.3VS_6

Near GPU

VDD33 +3V_GFX/ +3V_MAIN

NVDD +VGPU_CORE

PXE_VDD +1.05V_GFX

FBVDDQ +1.35_GFX

+VGPU_CORE

K10 K12 K14 K16 K18 L11 L13 L15

L17 M10 M12 M14 M16 M18

N11

N13

N15

N17

P10

P12

P14

P16

P18

R11

R13

R15

R17

T10

T12

T14

T16

T18

U11

U13

U15

U17

V10

V12

V14

V16

V18

t>0

U20E

ESP@N14P-GV2

11/14 NVVDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

8

16

N15x Power on sequance

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

7

PROJECT :

N14M-GS (PCIE I/F) /NVDD

ZQX

8

16 43Wednesday, September 03, 2014

1B

1

EC_FB_CLAMP

R50 *0_4

R43 EV@10K/F_4

For GC6 2.0 and 1.0 no stuff GC6_FB_EN

PV modify

A A

FBA_ODT_L FBA_ODT_H FBA_RST# FBA_CKE_L FBA_CKE_H

TP78

B B

TP11

TP79

C C

+1.05V_GFX

FBA_CMD2 FBA_CMD18 FBA_CMD5 FBA_CMD3 FBA_CMD19

FBA_CMD1

FBA_CMD17

FBA_CMD31

FB_PLLAVDD = 55mA

L8 EV@BLM15PX331SN1D

C69 EV@22U/6.3VS_6 C64 EV@0.1U/10V_4

D D

C22 EV@0.1U/10V_4 C34 EV@0.1U/10V_4

R45 EV@10K/F_4 R385 EV@10K/F_4 R56 EV@10K/F_4 R41 EV@10K/F_4 R82 EV@10K/F_4

+1.5V_GFX

VMA_CLK0[20]

VMA_CLK0#[20]

VMA_CLK1[20]

VMA_CLK1#[20]

FBA_CMD0[20] FBA_CMD2[20]

FBA_CMD3[20] FBA_CMD4[20] FBA_CMD5[20] FBA_CMD6[20] FBA_CMD7[20] FBA_CMD8[20]

FBA_CMD9[20] FBA_CMD10[20] FBA_CMD11[20] FBA_CMD12[20] FBA_CMD13[20] FBA_CMD14[20] FBA_CMD15[20] FBA_CMD16[20]

FBA_CMD18[20] FBA_CMD19[20] FBA_CMD20[20] FBA_CMD21[20] FBA_CMD22[20] FBA_CMD23[20] FBA_CMD24[20] FBA_CMD25[20] FBA_CMD26[20] FBA_CMD27[20] FBA_CMD28[20] FBA_CMD29[20] FBA_CMD30[20]

R53 *60.4_4 R58 *60.4_4

+FB_PLLAVDD

FB_DLLAVDD = 15mA

1

FB_CLAMP

2

U20B

F3

FB_CLAMP

C27

FBA_CMD0

C26

FBA_CMD1

E24

FBA_CMD2

F24

FBA_CMD3

D27

FBA_CMD4

D26

FBA_CMD5

F25

FBA_CMD6

F26

FBA_CMD7

F23

FBA_CMD8

G22

FBA_CMD9

G23

FBA_CMD10

G24

FBA_CMD11

F27

FBA_CMD12

G25

FBA_CMD13

G27

FBA_CMD14

G26

FBA_CMD15

M24

FBA_CMD16

M23

FBA_CMD17

K24

FBA_CMD18

K23

FBA_CMD19

M27

FBA_CMD20

M26

FBA_CMD21

M25

FBA_CMD22

K26

FBA_CMD23

K22

FBA_CMD24

J23

FBA_CMD25

J25

FBA_CMD26

J24

FBA_CMD27

K27

FBA_CMD28

K25

FBA_CMD29

J27

FBA_CMD30

J26

FBA_CMD31

F22

FBA_DEBUG0

J22

FBA_DEBUG1

D24

FBA_CLK0

D25

FBA_CLK0

N22

FBA_CLK1

M22

FBA_CLK1

D18

FBA_WCK01

C18

FBA_WCK01

D17

FBA_WCK23

D16

FBA_WCK23

T24

FBA_WCK45

U24

FBA_WCK45

V24

FBA_WCK67

V25

FBA_WCK67

F16

FB_PLLAVDD

P22

FB_PLLAVDD

H22

FB_DLLAVDD

INT

ESP@N14P-GV2

2

GF119NC

GF117

GF119

GF117FB_PLLAVDD

3

2/14 FBA

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FB_VREF_PROBE

4

E18

VMA_DQ0

F18

VMA_DQ1

E16

VMA_DQ2

F17

VMA_DQ3

D20

VMA_DQ4

D21

VMA_DQ5

F20

VMA_DQ6

E21

VMA_DQ7

E15

VMA_DQ8

D15

VMA_DQ9

F15

VMA_DQ10

F13

VMA_DQ11

C13

VMA_DQ12

B13

VMA_DQ13

E13

VMA_DQ14

D13

VMA_DQ15

B15

VMA_DQ16

C16

VMA_DQ17

A13

VMA_DQ18

A15

VMA_DQ19

B18

VMA_DQ20

A18

VMA_DQ21

A19

VMA_DQ22

C19

VMA_DQ23

B24

VMA_DQ24

C23

VMA_DQ25

A25

VMA_DQ26

A24

VMA_DQ27

A21

VMA_DQ28

B21

VMA_DQ29

C20

VMA_DQ30

C21

VMA_DQ31

R22

VMA_DQ32

R24

VMA_DQ33

T22

VMA_DQ34

R23

VMA_DQ35

N25

VMA_DQ36

N26

VMA_DQ37

N23

VMA_DQ38

N24

VMA_DQ39

V23

VMA_DQ40

V22

VMA_DQ41

T23

VMA_DQ42

U22

VMA_DQ43

Y24

VMA_DQ44

AA24

VMA_DQ45

Y22

VMA_DQ46

AA23

VMA_DQ47

AD27

VMA_DQ48

AB25

VMA_DQ49

AD26

VMA_DQ50

AC25

VMA_DQ51

AA27

VMA_DQ52

AA26

VMA_DQ53

W26

VMA_DQ54

Y25

VMA_DQ55

R26

VMA_DQ56

T25

VMA_DQ57

N27

VMA_DQ58

R27

VMA_DQ59

V26

VMA_DQ60

V27

VMA_DQ61

W27

VMA_DQ62

W25

VMA_DQ63

D19

VMA_DM0

D14

VMA_DM1

C17

VMA_DM2

C22

VMA_DM3

P24

VMA_DM4

W24

VMA_DM5

AA25

VMA_DM6

U25

VMA_DM7

E19

VMA_WDQS0

C15

VMA_WDQS1

B16

VMA_WDQS2

B22

VMA_WDQS3

R25

VMA_WDQS4

W23

VMA_WDQS5

AB26

VMA_WDQS6

T26

VMA_WDQS7

F19

VMA_RDQS0

C14

VMA_RDQS1

A16

VMA_RDQS2

A22

VMA_RDQS3

P25

VMA_RDQS4

W22

VMA_RDQS5

AB27

VMA_RDQS6

T27

VMA_RDQS7

GPU_PWR_GD ,PD at GPU power side

GPU_PWR_GD[36]

D23

GC6_FB_EN[10,19]

EC_FB_CLAMP[19,29]

stuff EC_FB_CLAMP for not GC6

stuff GC6_FB_EN for GC6

4

VMA_DQ[63:0]

VMA_DQ[63:0] [20]

FBVDDQ + FBVDD = 3.116A

C29 EV@0.1U/10V_4 C52 EV@0.1U/10V_4

C48 EV@1U/10V_6 C54 EV@1U/10V_6 C35 EV@4.7U/6.3V_6 C93 EV@10U/6.3V_6 C83 EV@22U/6.3VS_6 C36 EV@4.7U/6.3V_6

VMA_DM[7:0] [20]

VMA_WDQS[7:0] [20]

VMA_RDQS[7:0] [20]

C375 *0.1u/10V_4

R337 EV@0_4 R348 EV@0_4 R342 *0_4

For support GC6

5

+1.5V_GFX

2 1

5

U20D

12/14 FBVDDQ

B26

FBVDDQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

H24

FBVDDQ

H26

FBVDDQ

J21

FBVDDQ

K21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W21

FBVDDQ

ESP@N14P-GV2

HWPG_1.5VGFX[37]

+3V

C377 EV@0.1U/10V_4

5

U19

3

EV@SN74AHC1G32DCKR

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

R364 EV@4.7K_4

4

6

D22

C24

B25

R346 EV@100K/F_4

6

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

DGPU_POK4

C383 *1000P/50V_4

FBVDDQ_EN [37]

R44 EV@40.2/F_4

R32 EV@42.2/F_4

R29 EV@51.1/F_4

DGPU_PGOK-1

2

Q32 EV@METR3904-G

1 3

+1.5V_GFX

7

U20F

13/14 GND

A2 AB17 AB20 AB24

AC2 AC22 AC26

AC5

AC8 AD12 AD13

AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20 AB11

AF1

AF11 AF14 AF17 AF20 AF23

AF5

AF8

AG2 AG26 AB14

H23

H25

M11

GND GND GND GND GND GND GND GND GND GND GND

A26

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND GND GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

L10

GND

L12

GND

L14

GND

L16

GND

L18

GND

L2

GND

L23

GND

L25

GND

L5

GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND

ESP@N14P-GV2

+3V_GFX

+3V

R347 EV@4.7K_4

C378 EV@1000P/50V_4

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

7

R358 EV@4.7K_4

2

Q31 EV@DTC144EUA

R349 EV@100K/F_4

1 3

PROJECT :U82

Quanta Computer Inc.

N14M-GS (MEMORY/GND)

8

17

M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5

AA7 AB7

DGPU_PWROK [10]

17 43Wednesday, September 03, 2014

8

1B

GF119

ESP@N14P-GV2

GF119

1

GF117

NC NC

NC

DVI/HDMI DP

NC NC

NC

GF117GF119

GF117

NC

GF117

NC

NC NC

NC

U20G

4/14 IFPAB

AA6

IFPAB_RSET

V7

IFPAB_PLLVDD

W7

IFPAB_PLLVDD

A A

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

B B

IFPAB

U20H

5/14 IFPC

T6

IFPC_RSET

M7

IFPC_PLLVDD

N7

IFPC_PLLVDD

C C

P6

IFPC_IOVDD

ESP@N14P-GV2

U20I

6/14 IFPD

GF119

U6

IFPD_RSET

T7

IFPD_PLLVDD

R7

IFPD_PLLVDD

IFPD

D D

R6

IFPD_IOVDD

GF117

NC

GF119 GF117

NC

GF117

NC NC

NC

ESP@N14P-GV2

1

GF119

IFPA_TXC IFPA_TXC

IFPA_TXD0 IFPA_TXD0

IFPA_TXD1 IFPA_TXD1

IFPA_TXD2 IFPA_TXD2

IFPA_TXD3 IFPA_TXD3

IFPB_TXC IFPB_TXC

IFPB_TXD4 IFPB_TXD4

IFPB_TXD5 IFPB_TXD5

IFPB_TXD6 IFPB_TXD6

IFPB_TXD7 IFPB_TXD7

I2CW_SDA I2CW_SCL

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

I2CX_SDA I2CX_SCL

TXC TXC

GPIO14

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

2

AC4 AC3

Y3 Y4

AA2 AA3

AA1 AB1

AA5 AA4

AB4 AB5

AB2 AB3

AD2 AD3

AD1 AE1

AD5 AD4

J7

K7

K6

H6

J6

U20J

7/14 IFPEF

IFPEF_PLLVDD

IFPEF_RSET

IFPE_IOVDD

IFPF_IOVDD

GF119

B3

IFPC

GF119GF117

N5 N4

N3 N2

R3 R2

R1 T1

T3 T2

C3

P4 P3

R5 R4

T5 T4

U4 U3

V4 V3

D4

ESP@N14P-GV2

GF119

2

IFPC_AUX IFPC_AUX

IFPC_L3 IFPC_L3

IFPC_L2 IFPC_L2

IFPC_L1 IFPC_L1

IFPC_L0 IFPC_L0

GPIO15

DPDVI/HDMI

IFPD_AUX IFPD_AUX

IFPD_L3 IFPD_L3

IFPD_L2 IFPD_L2

IFPD_L1 IFPD_L1

IFPD_L0 IFPD_L0

GPIO17

GF119

IFPE

IFPF

3V_MAIN_EN[19]

+3V_MAIN

3

GF117

NC

GF117

NC

GF117

NC

R381 EV@4.7K_4

3

NC NC

NC

+3V_GFX

DVI-DL

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_ENC

DVI-DL

TXD3 TXD3

TXD4 TXD4

TXD5 TXD5

R363 EV@10K_4

C398 *1000p/50V_4

+3V_GFX

2

GF119

DVI-SL/HDMI

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_E

GF119

DVI-SL/HDMI

I2CZ_SDA I2CZ_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_F

3V MAIN POWER

R367 *10K_4

R368 *200K_4

3

Q33 *2N7002K

1

2

Q36

1 3

EV@MMBT3904-7-F

4

DP

J3

IFPE_AUX

J2

IFPE_AUX

J1

IFPE_L3

K1

IFPE_L3

K3

IFPE_L2

K2

IFPE_L2

M3

IFPE_L1

M2

IFPE_L1

M1

IFPE_L0

N1

IFPE_L0

GPIO18

C2

DP

H4

IFPF_AUX

H3

IFPF_AUX

J5

IFPF_L3

J4

IFPF_L3

K5

IFPF_L2

K4

IFPF_L2

L4

IFPF_L1

L3

IFPF_L1

M5

IFPF_L0

M4

IFPF_L0

GPIO19

F7

+1.05V_GFX

5

AE2 AF2

W5

U20K

3/14 DACA

DACA_VDD

DACA_VREF

DACA_RSET

ESP@N14P-GV2

PLLVDD = 38mA

L6 EV@BLM15PX331SN1D

C51 EV@0.1U/10V_4 C49 EV@22U/6.3VS_6

SP_PLLVDD = 17mA

L7 EV@BLM15PX181SN1D

C56 EV@0.1U/10V_4 C57 EV@0.1U/10V_4 C66 EV@4.7U/6.3V_6 C65 EV@22U/6.3VS_6

VID_PLLVDD = 41mA

R350 EV@10K/F_4

6

GF119

GF117

NC

TSEN_VREF

NC

GF117

GF119 NC NC

NC NC

NC

NC NC

I2CA_SCL I2CA_SDA

DACA_HSYNC DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

NV_PLLVDD

U20M

SP_PLLVDD

XTAL_SSIN

27M_XTAL_IN_R 27M_XTAL_OUT

M6

A10

C11

L6

N6

9/14 XTAL_PLL

PLLVDD SP_PLLVDD

VID_PLLVDD

XTALSSIN

XTALIN

GF119

NC

GF117

B7 A7

AE3 AE4

AG3 AF4 AF3

I2CA_SCL I2CA_SDA

7

R352 EV@2.2K_4 R357 EV@2.2K_4

27M_XTAL_IN_R 27M_XTAL_OUT

XTALOUTBUFF

EV@10p/50V_4

XTALOUT

C381

C10

B10

18

BXTALOUT

ESP@N14P-GV2

8

Y6

1 3 2 4

EV@27MHZ

R356 EV@10K/F_4

C380 EV@10p/50V_4

+3V_GFX

60mil

C390 *0.022U/25V_4

C389 *0.022U/25V_4

+3V

R383 EV@4.7K_4

C402 EV@1000p/50V_4

4

1

2

Q34 *AO3413

3

R376 EV@0_8

+3V_MAIN

60mil

1A-7 2013/10/21 add R5331 for not GC6 support.

+3V_GFX

2

1 3

N15V stuff not support GC6.

R401 EV@4.7K_4

3V_MAIN_PWGD

R386 *100K/F_4

Q37 EV@DTC144EU

3V_MAIN_PWGD [36,37]

+1.05V_GFX and GPU core power EN

5

PROJECT :U82

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

6

Date: Sheet of

7

N14M-GS (DISPLAY)

18 43Wednesday, September 03, 2014

8

1B

1

TP8

E12 F12

U20N

8/14 MISC1

THERMDN

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST

ESP@N14P-GV2

1

TP10

R52 GT@40.2K/F_4

R3

2

3

Q9

EV@2N7002K

For N15S-GT sku N15S-GT device ID=0x0FE4 R3=40.3k pull down.

1.ROM_SCLK =4.99K pull down

A A

2.ROM_SO = 4.99K pull down

3.ROM_SI= Memory strap setting

3.STRAP0 = 50k Pull pu.

4.Strap4~1 = reserve Pull pu and Pull down

For N15V-GL-B and N15V-GM-B sku Board_ID0= H=N15V-GM,L=N15V-GL Device ID=0x1140 R3= N.C.

1.ROM_SCLK =10K pull down.

2.ROM_SI= 10k pull down

3.ROM_SO= 10k pull down

4.Strap3~0 = RVL memory binary mode setting.

5.Strap4 =10k pull down

B B

TP9 TP7

TP87 TP86

TP85

C C

PEGX_RST#[16]

D D

THERMTHERM+

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#

AE5 AD6 AE6 AF6 AG4

R57 EV@0_4

1

E10 F10

D1

STRAP0

D2

STRAP1

E4

STRAP2

E3

STRAP3

D3

STRAP4

C1

dGPU_OTP# [29]

2

U20L

10/14 MISC2

VMON_IN0 VMON_IN1

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

GF119

STRAP5_NC

F6

MULTISTRAP_REF0_GND

F4

MULTISTRAP_REF1_GND

F5

MULTISTRAP_REF2_GND

ESP@N14P-GV2

GF117

NC NC

GF117

NC NC NC

2

GF119

I2CS_SCL

I2CS_SDA

I2CC_SCL I2CC_SDA

I2CB_SCL

I2CB_SDA

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13

GF119

GPIO16 GPIO20 GPIO21

GF117

NC

D9

GPUT_CLK_L

D8

GPUT_DATA_L

A9

DGPU_EDIDCLK

B9

DGPU_EDIDDATA

C9

N12E_SCL

C8

N12E_SDA

C6

FB_CLAMP_M0N

B2 D6 C7 F9 A3

3V_MAIN_EN

A4

FB_CLAMP_REQ#_R

B6 A6

VGA_OVT#

F8

R644 EV@10K/F_4

C5 E7 D7

GPIO12_ACIN

B4

DGPU_PSI

D5 E6 C4

GPU_PEX_RST_HOLD#

GF117

NC

GPIO12_ACIN

3

ROM_CS

ROM_SI

ROM_SO

ROM_SCLK

BUFRST

PGOOD

CEC

R351 EV@2.2K_4 R24 EV@2.2K_4

R25 EV@2.2K_4 R26 EV@2.2K_4 R345 EV@0_4

1

Q29

2

*2N7002K

+3V_GFX

3V_MAIN_EN [18]

PWM-VID [36] DGPU_PSI [36]

GPU_PEX_RST_HOLD# [16]

1

2

+3V_GFX

3

D12

ROM_CS

B12

ROM_SI

A12

ROM_SO

C12

ROM_SCLK

D11 D10

R14 *10K/F_4

E9

SYS_PEX_RST_MON#

R338 *0_4

3

R341 EV@0_4TP88

R339 EV@10K/F_4

dGPU_OPP# = EC control

3

EV@2N7002K

4

R23 EV@10K_4

R61 EV@10K/F_4

dGPU_OPP# [29]

GPIO12 AC detect AC high DC low

+3V_GFX

ROM_SI ROM_SO ROM_SCLK

+3V_GFX

SYS_PEX_RST_MON# [16]

2ND_MBCLK[8,29]

2ND_MBDATA[8,29]

R64 *0_4

1

Q11 *2N7002K

2

+3V_GFX

N15S -> GPIO0 un-stuff Q24 and EC_FB_CLAMP. GPIO6 Unstuff Q26\R70 and FB_CLAMP_REQ#.

EC/S5 VGA/VGA

EC_FB_CLAMP [17,29]

GC6_FB_EN [10,17]

+3V_GFX

R62 *10K/F_4

3

4

R361 *4.99K/F_4

R355 GMS@4.99K/F_4

N15S Based on RVL. N15V pull down10k.

Pull Down 4.99k for N15S-GT. Pull Down 10k for N15V.

+3V_MAIN

Q30

5

2 6

EV@2N7002DW

R75 *0_4 R74 *0_4

R360 *4.99K/F_4

R354 GMS@4.99K/F_4

R343 EV@4.7K_4

43

1

GPIO12_ACIN

DGPU_PSI

VGA_OVT#VGA_OVT#

GPU_PEX_RST_HOLD#

3V_MAIN_EN

JTAG_TRST#

5

6

Default: HYNIX

+3V_GFX

R359 *4.99K/F_4

R353 GMS@4.99K/F_4

R344 EV@4.7K_4

GPUT_CLK_L

GPUT_DATA_L

4H DM 9S 0 0 1 1(0=R36 1=R20) 1 0 0 0 2 1 1 0 3 0 1 1(0=R37 1=R21)

N15S-GT STRAP1---> 50k PU N15V-GM\GL STRAP4---> 10k PD

4.99k CS24992FB26 10k CS31002FB26 15k CS31502FB24 20k CS32002FB29

24.9k CS32492FB16

30.1k CS33012FB18

34.8k CS33482FB22

45.3k CS34532FB18

R20 SP@49.9K/F_4

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

R36 SP@10K/F_4

N15S Strap0 pull up 50k, strap1~4 reverve only. N15V Strap4 pull down 10k, strap0~3 based on RVL binary setting.

VRAM Configuration Table

DESCRIPTION

0000

DDR3(L) 256MBx16x4, 64bit,1000MHz(

DDR3(L) 256MBx16x4, 64bit,,1000MHz(900MHz)

0010(0101) SAMSUNG 0110(1001) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz)

FB_CLAMP_REQ# [29]

DGPU_EVENT# [10]

Strap [3:0]

0100

1100 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) 0001 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO 1101 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO

R51 EV@10K/F_4

R16 *10K/F_4

R54 EV@10K/F_4

R15 EV@10K/F_4Q7

R362 *10K/F_4

R85 EV@10K/F_4

0111(1010) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz)

DDR3(L) 128MBx16x4, 64bit,,1000MHz(900MHz) SAMSUNG

1000(1011)

DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz)0001(0100)

DESCRIPTION

DDR3(L) 256MBx16x4, 64bit,1000MHz(900MHz)

+3V_GFX

GPIO

0 1

3 4 5 6 7 8

9 10 11 12 13

Vendor Vendor P/N

HYNIX HYNIX

I/O IN

OUT OUT OUT2LCD_VCC OUT OUT OUT OUT I/O I/O OUT OUT IN OUT

GPIO ASSIGNMENTS

5

6

R19 *4.99K/F_4

R35 GM@10K/F_4

7

R17 SP@10K/F_4

R33 SP@10K/F_4

R21 SP@10K/F_4

R37 SP@10K/F_4

+3V_GFX+3V_MAIN

R18 *10K/F_4

R34 GM@10K/F_4

8

Logical Strap Bit Mapping

PU-VDD PD

4.99K

1000 0000

10K

1001 0001 15K 20K

24.9K

30.1K

34.8K

45.3K

1011 0011

1100

1101

1110 0110

1111

Vendor

HYNIX

HYNIX MICRO

MICRO

00101010

0100 0101

0111

Vendor P/NROM_SI

H5TC4G63AFR-11C

K4W4G1646D-BC1A H5TC2G63FFR-11C MT41J128M16JT-093G:K K4W2G1646Q-BC1A

MT41J256M16HA-093G:E

AKD5PGWTW05 AKD5PGWTW13

QCI P/N

H5TC4G63AFR-11C H5TC2G63FFR-11C MT41J128M16JT-093G:K

MT41J256M16HA-093G:E

FB_CLAMP_MON MEM_VDD_CTL LCD_BL_PWM

USAGE FB Clamp monitor

Memory VDD VID Panel Backlight PWM

PANEL POWER ENABLE LCD_BLEN Reserved FB_CLAMP_TGL_REQ 3D VISION OVERT ALERT MEM VREF_CTL

PANEL BACKLIGHT ENABLE

--

Active low FB Clamp toggle request

3D VISION LEFT/RIGHT signal

ACTIVE LOW THERMAL OVER TEMP

ACTIVE LOW THERMAL ALERT

MEMMORY VREF CONTROL PWR_VID GPU CORE_VDD PWM Control signal PWR_LEVEL

AC Power detect or power supply overdraw input PSI Phase Shedding

PROJECT :U82

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

N14M-GS (GPIO/STRAPS)

Date: Sheet of

7

Date: Sheet of

8

Note

19 43Wednesday, September 03, 2014

19

STN P/NQCI P/N

1B

5

VMA_DQ[63..0][17]

VMA_DM[7..0][17]

VMA_WDQS[7..0][17]

VRAM6

VREFC_VMA1 VREFD_VMA1

D D

C C

B B

FBA_CMD9[17]

FBA_CMD11[17]

FBA_CMD8[17] FBA_CMD25[17] FBA_CMD10[17] FBA_CMD24[17] FBA_CMD22[17]

FBA_CMD7[17] FBA_CMD21[17]

FBA_CMD6[17] FBA_CMD29[17] FBA_CMD23[17] FBA_CMD28[17] FBA_CMD20[17]

FBA_CMD4[17] FBA_CMD14[17]

FBA_CMD12[17] FBA_CMD27[17] FBA_CMD26[17]

VMA_CLK0[17]

VMA_CLK0#[17]

FBA_CMD3[17]

FBA_CMD2[17]

FBA_CMD0[17] FBA_CMD30[17] FBA_CMD15[17] FBA_CMD13[17]

FBA_CMD5[17]

Should be 240 Ohms +-1%

VMA_WDQS1 VMA_RDQS1

VMA_DM1 VMA_DM0

VMA_WDQS0 VMA_RDQS0

VMA_ZQ1

R55 EV@243/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL SDRAM DDR3

ESP@VRAM _DDR3_HYNIX_256MX16

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7

VDD#K2

VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1

VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2

VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1 VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

VMA_DQ13 VMA_DQ11 VMA_DQ12 VMA_DQ9 VMA_DQ14 VMA_DQ10 VMA_DQ15 VMA_DQ8

VMA_DQ7 VMA_DQ0

VMA_DQ5

VMA_DQ3 VMA_DQ4 VMA_DQ2 VMA_DQ6 VMA_DQ1

+1.5V_GFX

VMA_RDQS[7..0][17]

Should be 240 Ohms +-1%

4

CHANNEL A: 256MB/512MB DDR3

VRAM8

VREFC_VMA1 VREFD_VMA1

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14

FBA_CMD12 FBA_CMD27 FBA_CMD26

VMA_CLK0 VMA_CLK0# FBA_CMD3

FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13

VMA_WDQS2 VMA_RDQS2

VMA_DM2 VMA_DM3

VMA_WDQS3 VMA_RDQS3

FBA_CMD5

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

VMA_ZQ2 VMA_ZQ3 VMA_ZQ4

R365 EV@243/F_4

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL SDRAM DDR3

ESP@VRAM _DDR3_HYNIX_256MX16

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1

VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2

VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

VMA_DQ21

F7

VMA_DQ16

F2

VMA_DQ20

F8

VMA_DQ18

H3

VMA_DQ23

H8

VMA_DQ19

G2

VMA_DQ22

H7

VMA_DQ17

D7

VMA_DQ31

C3

VMA_DQ24

C8

VMA_DQ30

C2

VMA_DQ26

A7

VMA_DQ28

A2

VMA_DQ27

B8

VMA_DQ29

A3

VMA_DQ25

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5V_GFX

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

3

VMA_CLK1[17]

VMA_CLK1#[17]

FBA_CMD19[17]

FBA_CMD18[17] FBA_CMD16[17]

Should be 240 Ohms +-1%

2

HYU 256Mx16, PN HYU 128Mx16, PN

SAM 256Mx16, PN SAM 128Mx16, PN

VRAM7

R79 EV@243/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

ESP@VRAM _DDR3_HYNIX_256MX16

96-BALL SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9

VDD#G7

VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9

VSS#T1 VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

VREFC_VMA3 VREFD_VMA3

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14

FBA_CMD12 FBA_CMD27 FBA_CMD26

FBA_CMD30 FBA_CMD15 FBA_CMD13

VMA_WDQS5 VMA_RDQS5

VMA_DM5 VMA_DM4

VMA_WDQS4 VMA_RDQS4

FBA_CMD5 FBA_CMD5

󶁪󶁪󶁪󶁪

AKD5PGWTW08---AKD5PGWTW07

󶁪󶁪󶁪󶁪

AKD5MZDTW03---AKD5MZDTW02

QBC TOP B/S

󶁪󶁪󶁪󶁪

AKD5PZDT501---AKD5PZDT500

󶁪󶁪󶁪󶁪

AKD5MGGT535---AKD5MGGT534

E3

VMA_DQ41

F7

VMA_DQ45

F2

VMA_DQ40

F8

VMA_DQ46

H3

VMA_DQ43

H8

VMA_DQ47

G2

VMA_DQ42

H7

VMA_DQ44

D7

VMA_DQ33

C3

VMA_DQ37

C8

VMA_DQ34

C2

VMA_DQ39

A7

VMA_DQ35

A2

VMA_DQ36

B8

VMA_DQ32

A3

VMA_DQ38

B2

+1.5V_GFX

D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Should be 240 Ohms +-1%

VREFC_VMA3 VREFD_VMA3

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14

FBA_CMD12 FBA_CMD27 FBA_CMD26

VMA_CLK1 VMA_CLK1# FBA_CMD19

FBA_CMD18 FBA_CMD16 FBA_CMD30 FBA_CMD15 FBA_CMD13

VMA_WDQS7 VMA_RDQS7

VMA_DM7 VMA_DM6

VMA_WDQS6 VMA_RDQS6

R384 EV@243/F_4

VRAM9

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

ESP@VRAM _DDR3_HYNIX_256MX16

VDDQ#C1 VDDQ#C9 VDDQ#D2

VDDQ#H2 VDDQ#H9

96-BALL SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8

VDDQ#E9 VDDQ#F1

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

20

VMA_DQ61 VMA_DQ56 VMA_DQ63 VMA_DQ59 VMA_DQ62 VMA_DQ57 VMA_DQ60 VMA_DQ58

VMA_DQ54 VMA_DQ48 VMA_DQ55 VMA_DQ50 VMA_DQ53 VMA_DQ51 VMA_DQ52 VMA_DQ49

+1.5V_GFX

VMA_CLK0

R31 EV@162/F_4

VMA_CLK0#

A A

+1.5V_GFX

C30 EV@1U/6.3V_4 C41 EV@1U/6.3V_4 C27 EV@1U/6.3V_4

5

+1.5V_GFX

C379 EV@10U/6.3V_6 C50 EV@1U/6.3V_4 C401 EV@1U/6.3V_4C403 EV@1U/6.3V_4 C385 EV@0.1U/10V_4C413 EV@1U/6.3V_4 C418 EV@1U/6.3V_4 C384 EV@1U/6.3V_4 C399 EV@1U/6.3V_4

R374 EV@1.33K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA3 VREFD_VMA3

R372 EV@1.33K/F_4

+1.5V_GFX

4

C388 EV@0.1U/10V_4

C111 EV@10U/6.3V_6 C397 EV@1U/6.3V_4

C121 EV@1U/6.3V_4 C53 EV@1U/6.3V_4

C68 EV@1U/6.3V_4 C400 EV@1U/6.3V_4

R8 EV@1.33K/F_4

R13 EV@1.33K/F_4

C14 EV@0.1U/10V_4

+1.5V_GFX

C109 EV@10U/6.3V_6 C63 EV@10U/6.3V_6 C387 EV@0.1U/10V_4

C382 EV@0.1U/10V_4

C414 EV@0.1U/10V_4 C78 EV@0.1U/10V_4

VMA_CLK1

R84 EV@162/F_4

VMA_CLK1#

+1.5V_GFX

C396 EV@10U/6.3V_6 C410 EV@10U/6.3V_6

C120 EV@0.1U/10V_4 C386 EV@0.1U/10V_4C71 EV@1U/6.3V_4 C108 EV@0.1U/10V_4

3

2

+1.5V_GFX+1.5V_GFX

R76 EV@1.33K/F_4

R73 EV@1.33K/F_4

+1.5V_GFX

R402 EV@1.33K/F_4

C87 EV@0.1U/10V_4

R387 EV@1.33K/F_4

PROJECT :U82

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

DGPU Memory (DDR3)

C406 EV@0.1U/10V_4

1

1B

20 43Wednesday, September 03, 2014

1B

1

2

3

4

LED(UIF)

FFC SATA HDD

CN13

10

12

9

11

A A

SATA_CONN

8 7 6 5 4 3 2 1

SATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C DEVSLP0_R

Layout Notes: Place decoupling CAPs close to Connector

C559 0.01u/16V_4 C560 0.01u/16V_4

C563 0.01u/16V_4 C564 0.01u/16V_4 R603 *0_4 R600 *0_4 R599 0_4

C342

0.01u/16V_4

C341

0.01u/16V_4

C343

SATA_TXP0 [8] SATA_TXN0 [8]

SATA_RXN0 [8] SATA_RXP0 [8]

DEVSLP0 [10] HDD protect [27]

C344 *0.1u/10V_4

+5V_HDD

C335 10u/6.3V_6

R296 *short_8

C562

+

*100u/6.3V_3528*0.1u/10V_4

+5V

PWRLED#[29]

SUSLED#[29] BATLED0#[29] BATLED1#[29]

PWRLED#

SUSLED# BATLED0# BATLED1#

+3VPCU+3V_S5

1

2

3

4

5

6

7

8

88511-0801

CN16

9

10

Change CN6 PN for ME request

9

21

10

120mil

B B

+3VPCU +3V_S5 +3V +5V

+3VPCU [7,8,11,13,22,23,28,29,30,31,35,36,37] +3V_S5 [5,7,8,9,10,11,13,24,27,28,29,31,34,36] +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,22,23,24,25,26,27,28,29,31,32,33,34,35,36] +5V [22,23,25,28,31,35]

3/5VPCU reset switch (CLG)

SW6 SWITCH_1.5

TP75

2

5

3

14

6

TP76

C376 D28

0.1u/10V_4

12

*14V/100p_4

SYS_SHDN# [10,31,35]

Power tracking

TPM (TPM)

U8

C C

TPM_VDD

1 2

R95 *20K_4 R93 TPMI@4.7K_4 R96 *4.7K_4

TPM_GPIO

TP121

TPM_PP

FAE : install R80 4K7, PIN7 wo interanl PD

TP122

D D

6

GPIO

2

NC2

7

PP

13

NC13

14

NC14

8

NC8

12

NC12

3

NC3

1

NC1

TPM SLB9655

GND[1]4GND[2]11GND[3]18GND[4]

25

TPMS@NPCT620/650_TSSOP28

VDD[3] VDD[4]

VDD[2] VDD[1]

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

NC28

LRESET#[1] LRESET#[2]

SERIRQ

NC15

R648 TPMI@0_4

5

R649 TPMN@0_4

10 24 19

21 22

17 20 23 26

28 16

9 27

15

LPC_LFRAME# LPC_LAD3

LPC_LAD2 LPC_LAD1 LPC_LAD0

R650 TPMN@0_4

TPM_RST_R SERIRQ_R

FAE : a 0ohm between pin9 to LRESET signals

TPM_VDD TPM_VSB

near pin 21 as possible

C110 *10p/50V_4

PCLK_TPM [9]

LPC_LFRAME# [8,26,29]

LPC_LAD3 [8,26,29] LPC_LAD2 [8,26,29] LPC_LAD1 [8,26,29] LPC_LAD0 [8,26,29]

PLTRST#

R90 TPMI@0_4 R100 TPM@0_4

R758 TPMN@0_4

TPM_VDD

C125 TPM@0.1U/10V_4

LPCPD# [7]

PLTRST# [7,13,16,24,26,29]

IRQ_SERIRQ [10,29]

CLKRUN# [7,29]

4 x100nF (place close to device VDD/GND pins)

C126 TPM@0.1U/10V_4

C122 TPM@0.1U/10V_4

C124 TPM@0.1U/10V_4

+3V

R88 TPM@2.2_6

C123 TPM@10u/6.3V_6

TPM_VSB +3VSUS+3V_S5

R647 TPMN@0_4 R646 *0_4

C584 TPM@0.1U/10V_4

C587 TPM@10u/6.3V_6

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

1

2

3

Date: Sheet of

PROJECT :

SATA-HDD/ TPM

4

ZQX

1B

21 43Wednesday, September 03, 2014

5

4

3

2

1

Codec(ADO)

HPR HPL LINE1L-VREFO LINE1R-VREFO MIC2-VREFO

31

LINE1-VREFO-L

30

LINE1-VREFO-R

C322 10u/6.3V_4

29

CODEC_VREF

INT_AMIC-VREFO

25

26

27

28

VREF

AVDD1

LDO1-CAP

MIC2-VREFO

MIC1-CAP

MIC2-R/SLEEVE

MIC2-L/RING2

MONO-OUT

12

PCH_AZ_CODEC_RST#

ACZ_SDIN

R287 33_4

C320 *22p/50V_4

U17

AVSS1

LINE2-L

LINE2-R

LINE1-L

LINE1-R

NC

JDREF

Sense B

Sense A

PCBEEP BEEP_1

D D

+1.5VA

C301 10u/6.3V_4

ADOGND

Place next to pin 40

Analog

Digital

Add for FAE suggest

C C

+5V

C288

10u/6.3V_6

+5V

C302

0.1u/10V_4

C289

10u/6.3V_6

C546

0.1u/10V_4

Low is power down amplifier output

near Codec

placed close to codec

ADOGND

C294 10u/6.3V_4

C290

0.1u/10V_4

near Codec

TP72

L_SPK+ L_SPKR_SPKR_SPK+

PD#

C303 1u/10V_4

+AZA_VDD

37 38 39 40 41 42 43 44 45 46 47 48

49

C30710u/6.3V_4

C3231u/10V_4

32

33

34

35

36

CBN

CPVEE

CPVDD CBP AVSS2 LDO2-CAP AVDD2 PVDD1 SPK-L+ SPK-LSPK-RSPK-R+ PVDD2 PDB SPDIFO/GPIO2

DGND

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BIT-CLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESETB11PCBEEP

HP-OUT-L

HP-OUT-R

ALC283

Add for FAE suggest

C299

0.1u/10V_4

+AZA_VDD

C300 10u/6.3V_4

DMIC_DAT_L

DMIC_CLK_L

R267 *short_6

+3V

Place next to pin 1

DMIC_DAT_L DMIC_CLK_L

C693

B B

C692 27pf/50V_4

27pf/50V_4

DMIC_DAT_L[27]

DMIC_CLK_L[27]

LINE1L-VREFO [27] LINE1R-VREFO [27]

MIC2-VREFO [27]

C340 2.2U/6.3V_4 C349 10u/6.3V_4

24 23 22

LINE1L_R

21

LINE1R_R

20 19 18

SLEEVE

17

RING2

16 15

CODEC_JDREF

14 13

1.6Vrms

C339 1u/10V_4

HPR [27]

HPL [27]

ADOGND ADOGND

0.1u/10V_4

C347

+5VA

C348 10u/6.3V_4

Place next to pin 26

ADOGND

LINE1L_R [27] LINE1R_R [27]

C346 10u/6.3V_4

R318 20K/F_4

R304 39.2K/F_4

Placement near Audio Codec

C338 100p/50V_4

PCH_AZ_CODEC_RST# [8] PCH_AZ_CODEC_SYNC [8]

PCH_AZ_CODEC_SDIN0 [8] PCH_AZ_CODEC_BITCLK [8]

PCH_AZ_CODEC_SDOUT [8]

R299 47K_4

R300

4.7K_4

DVDD_IO

Add by FAE suggest 10/31

INT_AMIC-VREFO

MIC2-VREFO

Add by FAE suggest 10/24

ADOGND

HP_JD#SENSEA

D17 RB500V-40 D18 RB500V-40

R294 *short_4

R292 *0_4

C331

0.1u/10V_4

Place next to pin 9

ADOGND

HP_JD# [27]

Analog

Digital

C330 10u/6.3V_4

R309 100K_4

R297 100K_4

SPKR [8,10] PCBEEP_EC [29]

+3V +1.5V

Grounding circuit(ADO)

PIN1, PIN4, PIN3, PIN6 are ANALOG

+5V

+3V

Power tracking

ADOGND

Q26

1

4 3

R310 *short_4 R246 *short_4 R554 *short_4 R251 *short_4 R245 *short_4 R253 *short_4

C531 *1000p/50V_4 C532 *1000p/50V_4

6

SLEEVE

2

RING2

5

2N7002DW

+5V [21,23,25,28,31,35]

+3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,23,24,25,26,27,28,29,31,32,33,34,35,36]

+3VPCU

R311

100K_4

SLEEVE [27]

RING2 [27]

TBC

3

2N7002K

1

22

+3V

R316

*100K_4

2

R313 10K_4

Q22

C345 *1u/10V_4

PCH_AZ_CODEC_RST#

C568

*68p/50V_4

+AZA_VDD

R256 *1K_4

R257 *10K_4

Change D25,D49 to RB500V-40

D15RB500V-40

D16RB500V-40

C566

C567

*68p/50V_4

3

C565

*68p/50V_4

PCH_AZ_CODEC_RST#PD#

R_SPK+_1 R_SPK-_1

AMP_MUTE# [29]

CN15

1 2 345

6

SPK_CONN_4P

Codec PWR 3V/1.5V(ADO)

+1.5V

C295

1U/6.3V_4

2

+1.5VA

ANALOG DIGITAL

R252 *short_4

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

ALC283/HP/SPK

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

PROJECT :

1

ZQX

1B

4322

Mute(ADO)Codec PWR 5V(ADO)

ANALOG DIGITAL

+5V

C358

C352

*10u/6.3V_6

A A

*0.1u/10V_4

L12 HCB2012KF220T60/6A/22ohm_8

U18

3 2 1

*G923-330T1UF

R315 *0_4

IN GND SHDN

4

OUT

5

ADOGND

R322 *29.4K/F_4

R320 *10K/F_4

SET

C730, C787 close U37 pin3 and L65

5

C360 *10u/6.3V_6

+5VA

ADOGND

C357 *0.1u/10V_4

Internal Speaker

40mil for each signal

R_SPK+

R592 *Short_6

R_SPK-

R591 *Short_6

L_SPK+ L_SPK+_1

R589 *Short_6

L_SPK- L_SPK-_1

R590 *Short_6

Swap LSPK+,LSPK- 11/01

4

1

2

3

4

5

6

7

8

LCD CONNECTOR

VIN

C7

C6

1000p/50V_4

A A

VIN

+3VPCU +3V

VIN [28,30,31,32,33,34,35,36,37]

+3VPCU [7,8,11,13,21,22,28,29,30,31,35,36,37] +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,24,25,26,27,28,29,31,32,33,34,35,36]

4.7u/25V_8

Power tracking

+3V

R38 100K_4

B B

R42 *100K_4

EDP_AUX_C EDP_AUX#_C

TP_RST#

R369 *100K_4 R370 100K_4

R366 10K_4

Add 10/31

eDP only one channel

C C

Touch Panel interrupt

TP_INT_PCH[10]

Del TP_PWR 5V, Add pin31 connect to TP_PWR

eDP

CCD-USB

Touch Panel

3

PCH_BRIGHT[2]

EDP_AUXP[2] EDP_AUXN[2]

EDP_TXP1[2] EDP_TXN1[2]

EDP_TXP0[2] EDP_TXN0[2]

+3V

2

*2N7002K

R382 *0_4

EDP_HPD[2]

USBP6+[9] USBP6-[9]

USBP5+[9] USBP5-[9]

TS_EN[29]

GPIO8[10]

R371 *10K_4

1

Q35

TP_INT

C18

LCDVCC

+3V

+5V +3V

PCH_BRIGHT

C16 .1U/16V_4 C21 .1U/16V_4

C391 .1U/16V_4 C392 .1U/16V_4

C393 .1U/16V_4 C394 .1U/16V_4

R377 *short_4 R378 *short_4

R379 *short_4 R380 *short_4

R375 *short_4

TP_INT

R373 *0_4

TP_PWR CCD_PWR

C12

C11

0.1u/10V_4_X7R 1000p/50V_4

VIN

MAX 1.5A

R27 *Short_6 R28 *Short_6

C17

*1u/6.3V_4

R6 *Short_6

R22 *Short_6 R129 *0_6

I2C1_SCL_GPIO7_CONN I2C1_SDA_GPIO6_CONN

40pins: lvd-a40sfyg-40p-r

*1u/6.3V_4

V_BLIGHT

CCD_PWR

TP_PWR

BL_ON EDP_HPD

EDP_AUX_C EDP_AUX#_C

EDP_TX1_C EDP_TX1#_C

EDP_TX0_C EDP_TX0#_C

USBP6+_R USBP6-_R

USBP5+_R USBP5-_R

TP_RST#

GS12401-1011P-7H

C13

0.1u/10V_4_X7R

CN7

G_5

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

G_0

C10

1000p/50V_4

G_4

G_1

Swap Cn22 pin7,8 follow ZQ0

LID

+3VPCU

R7 *100K_4

D6 *VPORT_6

D D

1

R12 *Short_6

21

2

1

C9

4.7u/6.3V_6

1st󶁪AL009249000 -- BCD 2nd󶁪AL001691000 -- OCS

2

3

MR6 AH9249NTR-G1

21

LID#

D7 *VPORT_6

3

4

5

LCD Power

+3V

C82

1u/6.3V_4

EDP_VDD_EN_R

EDP_VDD_EN[2]

R77 *short_4

R78

100K_4

Touch screen level shift I2C(reserve)

I2C1_SDA_GPIO6[10,28]

I2C1_SCL_GPIO7[10,28]

Backlight Control

PCH_BLON_R

PCH_BLON[2]

PCH_BLON_EC[29]

2013/11/28 Add BLON pin from PCH to lison.

R68 *short_4

R69 0_4

6

U6

6

IN

4

IN

3

ON/OFF

G5243AT11U

R67 100K_4

Q10

2N7002DW

OUT GND GND

R47 *0_4

Q6

1

4 3

*2N7002DW

R46 *0_4

+3VPCU

R65 10K_4

BL#

5

4 3

1 2

C31 *0.1u/10V_4

R40 *2.2K_4

BL_ON

1 3

C81 *2.2u/10V_8

+3V

R39 *2.2K_4

I2C1_SDA_GPIO6_CONN

I2C1_SCL_GPIO7_CONN

+3VPCU

R49 *100K_4

LID#

LID591#,EC intrnal PU

D8 *1N4148W S

2

Q8 DTC144EUA

Quanta Computer Inc.

PROJECT :

CRT/LVDS/CAMERA/LID

5

6 2

+3V

5

+3V

R48 10K_4

6

2

1

Size Document Number Rev

Date: Sheet of

7

C32

0.1u/10V_4

LCDVCC

C33

0.01u/25V_4

LID# [29]

EC_FPBACK# [29]

ZQX

8

23 43Wednesday, September 03, 2014

23

C80

22u/6.3V_8

1B

5

LAN

D D

LANVCC

R584 *Short_6

C C

LANVCC

40 mils (Iout=1A)

C550

0.1U/10V_4

For RTL8111GS * Place 0.1uF CAP close to each VDD33 pin-- 11, 32

B B

Tramsformer

C351

0.1U/10V_4

LANVCC+3V_S5

40 mils (Iout=1A)40 mils (Iout=1A)

C350

0.1U/10V_4

C1 C2

C544

4.7U/6.3V_6

For surge improvement, place C1 and C2 close to each VDD33 pin11,32(optional)

C541

4.7U/6.3V_6

C337 10U/6.3V_6

change 1 ohm to to shortpad for FAE suggest

MDI_3+ MDI_3-

U34

1

MDI_0+

IO1

IO4

2

MDI_1-

MDI_2+ MDI_3-

A A

REF5GND

IO23IO3

*CM1293A-04SO

U35

1

IO1

IO4

2

REF5GND

IO23IO3

*CM1293A-04SO

Reserve for Surge Line to GND TVS

LANVCC

6

MDI_0-

4

MDI_1+

LANVCC

6

MDI_2-

4

MDI_3+

MDI_2+ MDI_2- LAN_MX2-

MDI_1+ MDI_1-

MDI_0+ MDI_0-

C292

0.01U/50V/X7R_4

LANVCC

VDD10

LANVCC

R585 *SHORT_8

40 mils (Iout=1A)

4

LAN_XTALI

VDD10

U36

33

GND

1

MDIP0

2

MDIN0

3

AVDD10(NC)

4

MDIP1

5

MDIN1

6

MDIP2(NC)

7

MDIN2(NC)

8

AVDD10

VDDREG/VDD33

RSET

10 mils

C551

4.7U/6.3V_6

32

31

AVDD33

RTL8111GS-CG

10

R583 2.49K/F_4

MDI_0+ MDI_0-

MDI_1+ MDI_1MDI_2+ MDI_2- GPP_TX2N_LAN

MDI_3+ MDI_3-

C309

0.1U/10V_4

RSET

30

AVDD10

AVDD33(NC)11MDIP3(NC)9MDIN3(NC)

28

CKXTAL229CKXTAL1

HSIP13HSIN14REFCLK_P15REFCLK_N

CLKREQB

12

27

25

26

LED0

LED1/GPO

LED2(LED1)

VDDREG(VDD33)

16

PCIE_REQ_LAN#_R

C305 *10P/50V/COG_4

TP71 TP73 TP118

C547 *10P/50V/COG_4

24

REGOUT

23 22

DVDD10(NC)

21

LANWAKEB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

REGOUT

40 mils (Iout=1A) 40 mils (Iout=1A)

LAN_XTAL2

REGOUT VDDREG/VDD33 VDD10

ISOLATEB

GPP_TX2P_LAN

ISOLATEB

L20 4.7uH

Remove For Not Using SWR mode

C824,C825 close to Pin23.

U30

10 11 12

1 2 3

4 5 6

7 8 9

TD1+ TD1TCT1

TCT2 TD2+ TD2-

TD3+ TD3TCT3

TCT4 TD4+ TD4-

NS692417

MX1+ MX1MCT1

MCT2 MX2+

MX3+

MCT3

MCT4 MX4+

MX2-

MX3-

MX4-

24

LAN_MX3+

23

LAN_MX3-

22

21 20 19

18 17 16

15 14 13

LAN_MX2+

LAN_MX1+ LAN_MX1-

LAN_MX0+ LAN_MX0-

R652 75/F_6

R653 75/F_6

R654 75/F_6

R655 75/F_6

6/30 separate 75ohm

LANCT3

3

C549 12p/50V_4

1

2

Y9

25MHZ +-30PPM

4

3

C548 12p/50V_4

PCIE_LAN_WAKE#_R

C574 0.1U/10V_4 C575 0.1U/10V_4

+3V

R293 1K_4

R597 15K_4

CLK_PCIE_LANN [9] CLK_PCIE_LANP [9]

PCIE_TX3-_LAN [9]

PCIE_TX3+_LAN [9]

RTL8111GS (SWR mode) support

C319

4.7U/6.3V_6

C283 10p/3KV_1808

C324

0.1U/10V_4

PLTRST# [7,13,16,21,26,29] PCIE_RX3-_LAN [9] PCIE_RX3+_LAN [9]

For RTL8111G(S) * Place 1uF CAP close to each VDD10 pin-- 22 (reserve)

For RTL8111G(S) * Place 0.1uF CAP close to each VDD10 pin-- 3, 8, 22, 30

R241 *1M_8

C336

0.1U/10V_4

2

Power trace tracking

C328

0.1U/10V_4

C306

0.1U/10V_4

RJ45 Connector

Add 11/14

R240 *Short_6

1

24

change to LANCC and add PU res for FAE suggest

LANVCC

S5

R302 *10K/J_4

2

C570 1U/6.3V_4

CN12

1 2 3 4 5 6 7 8

RJ45

3

R593 *0_4

+3V_S5[5,7,8,9,10,11,13,21,27,28,29,31,34,36]

0+ 01+ 2+ 213+ 3-

CLK_PCIE_LAN_REQ#[9]

PCIE_LAN_WAKE#[7,26]

C329

0.1U/10V_4

LAN_MX0+ LAN_MX0LAN_MX1+ LAN_MX2+ LAN_MX2LAN_MX1LAN_MX3+ LAN_MX3-

R622 *0/J_4

LANVCC

R291 *10K/J_4

2

+3V[2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,25,26,27,28,29,31,32,33,34,35,36]

VDD10

C325

0.1U/10V_4

GND GND GND GND

1

Q25 2N7002K

Q21 DTC144EUA

13

9 10 11 12

LGND

PCIE_REQ_LAN#_R

PCIE_LAN_WAKE#_R

delete shortpad for layout 11/05

LGNDLGND

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

5

4

3

2

Wednesday, September 03, 2014

Quanta Computer Inc.

PROJECT :

LAN (RTL8111GS)

ZQX

1

1B

4424

5

4

3

2

1

HDMI Cost Reduced level shift (HDM) HDMI connector (HDM)

CN18

C359

*1000p/50V_4

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

59075-01942-001

12

R637 470_4

INT_HDMITX2N_C INT_HDMITX2P_C

INT_HDMITX1N_C INT_HDMITX1P_C

12

R641

R640

470_4

12

R639

R638

470_4

12

R642

R643

470_4

+5V

Q27

3

IN

AP2331SA-7

OUT

GND

1 2

C356 *220p/50V_4

HDMI_MB_HP

D20 *14V/100p_4

INT_HDMITX2N[2] INT_HDMITX2P[2]

INT_HDMITX1N[2] INT_HDMITX1P[2]

D D

INT_HDMITX0N[2] INT_HDMITX0P[2]

INT_HDMICLK+[2] INT_HDMICLK-[2]

Layout Notes: Place decoupling CAPs close to Connector

C C

C367 0.1u/10V_4 C368 0.1u/10V_4

C363 0.1u/10V_4 C364 0.1u/10V_4

C365 0.1u/10V_4 C366 0.1u/10V_4

C362 0.1u/10V_4 C361 0.1u/10V_4

*100K/F_4

+3V

R633

INT_HDMITX0N_C INT_HDMITX0P_C

INT_HDMICLK+_C INT_HDMICLK-_C

12

R636 470_4

3

2

1

Q45

2N7002K

INT_HDMITX2P_C INT_HDMITX2N_C

INT_HDMITX1P_C INT_HDMITX1N_C

INT_HDMITX0P_C INT_HDMITX0N_C

INT_HDMICLK+_C INT_HDMICLK-_C

HDMI_DDCCLK_MB HDMI_DDCDATA_MB

HDMI_5V

R305 *short_4

RV6

*5V/0.2p_4

12

HP_DET_CN

C353

*1000p/50V_4

SHELL1 SHELL3

SHELL4 SHELL2

20 22

23 21

25

HDMI DDC (HDM)

+3V

R307

2.2K_4

R319

2.2K_4

B B

HDMI_DDCCLK_SW[2]

A A

HDMI_DDCDATA_SW[2]

5

R314 *short_4

R317 *short_4

HDMI_DDCCLK_COM HDMI_DDCCLK_MB

+3V

Q24

2

BSN20

1

+3V

Q28

2

BSN20

1

4

+5V

D19

RB500V-40

R321

3

RB500V-40

3

2.2K_4

Follow CRB 1.0 change to 2.2K

+5V

D21

R323

2.2K_4

Follow CRB 1.0 change to 2.2K

HDMI_DDCDATA_MBHDMI_DDCDATA_COM

EMI (EMC) HDMI-detect (HDM)

INT_HDMITX2P_C

R327 *100/F_4

INT_HDMITX2N_C

INT_HDMITX1P_C

INT_HDMITX0P_C

INT_HDMICLK+_C

3

R325 *100/F_4

INT_HDMITX1N_C

R326 *100/F_4

INT_HDMITX0N_C

R324 *100/F_4

INT_HDMICLK-_C

+3V +5V

Power tracking

INT_HDMI_HPD[2]

+3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,26,27,28,29,31,32,33,34,35,36] +5V [21,22,23,28,31,35]

2

+3V+3V

R301 1M_4

Size Document Number Rev

Date: Sheet of

2

1

3

HDMI_MB_HP

12

Q23 2N7002K

Quanta Computer Inc.

PROJECT :

HDMI (PS8101)

1

R306 20K_4

ZQX

25 43Wednesday, September 03, 2014

1B

1

2

3

4

5

6

7

8

MINI-CARD WLAN(MPC)

+3.3V: 1000mA +3.3Vaux:330mA +1.5V:500mA

A A

BT_POWERON[29]

TP74

PLTRST#[7,13,16,21,24,29]

CLK_PCI_LPC[9]

PCIE_TX4+_WLAN[9] PCIE_TX4-_WLAN[9]

PCIE_RX4+_WLAN[9]

PCIE_RX4-_WLAN[9]

B B

CLK_PCIE_WLANP[9] CLK_PCIE_WLANN[9]

CLK_PCIE_WLAN_REQ#_R

PCIE_WAKE#_R

R336 *short_4 R334

CL_RST1#_WLAN

R335 *0_4 R9 *0_4

+WL_VDD

H=5.2mm

CN8

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

53

+3.3V

GND

+1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

W_DISABLE#

GND

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V

GND

+3.3V

GND54GND

MINI-CARD1

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18

16 14 12 10 8 6 4 2

WLAN#

WLAN_CLK_SDATA WLAN_CLK_SCLK

+WL_VDD +1.5V_MINI1_VDD

+1.5V_MINI1_VDD +WL_VDD

RF_EN [29]

A_LFRAME#_R

A_LAD3_R A_LAD2_R A_LAD1_R A_LAD0_R

+1.5V_MINI1_VDD +WL_VDD

+WL_VDD

TP6

R10 *0_4 R11 *0_4

R1

R340 *short_4

Debug

R60 *short_4 R63 *short_4 R66 *short_4 R71 *short_4 R72 *short_4

*4.7K_4

USBP4+ [9] USBP4- [9]

CLK_SDATA [8,13,14,15] CLK_SCLK [8,13,14,15]

PLTRST#

R3

LPC_LFRAME# [8,21,29] LPC_LAD3 [8,21,29] LPC_LAD2 [8,21,29] LPC_LAD1 [8,21,29] LPC_LAD0 [8,21,29]

C15

*0.1u/10V_4

+WL_VDD

C19

*0.1u/10V_4

500mA for +1.5V

C84

0.1u/10V_4

C28 *1000p/50V_4

C20

10u/6.3V_6

+1.5V_MINI1_VDD

C23 *0.1u/10V_4

R30 *short_8

R59 *0_8

C40 *10u/6.3V_6

+3V

+1.5V

26

2

1

Q13 *2N7002K

6

CLK_PCIE_WLAN_REQ#_R

R89 *4.7K_4

PCIE_WAKE#_R

Size Document Number Rev

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Date: Sheet of

Wednesday, September 03, 2014

Quanta Computer Inc.

PROJECT :

Mini Card/mSATA

7

ZQX

1B

4427

8

PCIE_CLKREQ_WLAN#[9]

+3VPCU +1.5V +3V_S5

C C

D D

Power tracking

1

+3VPCU [7,8,11,13,21,22,23,28,29,30,31,35,36,37] +1.5V [11,22,35] +3V_S5 [5,7,8,9,10,11,13,21,24,27,28,29,31,34,36]

2

PCIE_LAN_WAKE#[7,24]

3

4

5

R70 *short_4

+3V

3

5

4

3

2

1

USB3.0

+5VPCU

C580 1u/6.3V_4

U40

2

IN1 IN23OUT2

D D

USB_BC_ON[29]

USB_OC0#[9]

USBP1-[9]

USBP1+[9]

USB3_RXN0[9]

USB3_RXP0[9] USB3_TXN0[9]

USB3_TXP0[9]

4

EN#

1

GND

UP7534ARA8-15

C370 0.1u/10V_4 C369 0.1u/10V_4

OUT3 OUT1

OC#

8 7 6

5

USB3_TXN0_C USB3_TXP0_C

USBPWR1

12

C582

100u/6.3V_1206

R330 *short_4 R331 *short_4

R333 *short_4 R332 *short_4

R329 *short_4 R328 *short_4

Active High: 1st: AL007534001 (Promate) 2nd: AL000547006 (GMT) 3rd: AL002511002 (DDS)

C581 1000p/50V_4

USBP1-_R USBP1+_R

USB3_RXN0_R USB3_RXP0_R

USB3_TXN0_R USB3_TXP0_R

USB 3.0 Connector

CN19

1

VBUS

1

2

D-

2

3

D+

3

4

GND

5

SSRX-

5

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

9

USB3.0 CONN

12

11111010131312

G Sensor

SENSOR_EN[29]

+3V_S5

SENSOR_EN

1

R782 *100K_4

R780 *0_4

+3V +3V3_SER

R781 0_8

3

Q54

2

*AO3413

C715 *1000p/50V_4

C717 *1u/6.3V_4

C716 *0.1u/10V_4

27

C C

USB3_TXN0_R USB3_TXP0_R USB3_RXN0 USB3_RXP0

C372 *1.6p/50V_4 C371 *1.6p/50V_4 C374 *1.6p/50V_4 C373 *1.6p/50V_4

USBP1-_R USBP1+_R USB3_RXN0_R USB3_RXP0_R USB3_TXN0_R USB3_TXP0_R

D24 *5V/0.2p_4

1 2 1 2

D25 *5V/0.2p_4 D27 *5V/0.2p_4

1 2 1 2

D26 *5V/0.2p_4

1 2

D23 *5V/0.2p_4 D22 *5V/0.2p_4

1 2

USB2.0 I/O board For Universal Audio jack Function

+3V

+5V_S5

B B

NBSWON#[13,29]

USBON#[29]

USB_OC1#[9]

USBP2+[9]

USBP2-[9]

USBP3+[9]

USBP3-[9]

USBP7+[9]

USBP7-[9]

HP_JD#[22]

HPL[22]

HPR[22]

SLEEVE[22]

MIC2-VREFO[22]

A A

RING2[22]

LINE1L_R[22]

LINE1L-VREFO[22]

LINE1R_R[22]

LINE1R-VREFO[22]

5

NBSWON# USBON# USB_OC1#

USBP2+ USBP2-

USBP3+ USBP3-

USBP7+ USBP7-

HP_JD#

R630 56_4

HPL HPR

R631 56_4

SLEEVE MIC2-VREFO

RING2

C355 4.7u/6.3V_6 R629 4.7K_4

C354 4.7u/6.3V_6 R632 4.7K_4

HPL_C HPR_C

CN11

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 293031

32

Sub_CONN

ADOGND ADOGND

4

+3V3_SER

+5VPCU +3V +5V_S5

Power tracking

R400 0_4

Sensor board

C694 *27pf/50V_4

+5VPCU [31,32,33] +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,28,29,31,32,33,34,35,36] +5V_S5 [4,8,31,32,34,36]

3

C411

0.1u/10V_4

SDA_TO_EC

C695 *27pf/50V_4

C408

0.1u/10V_4

U21

7

VDD

3

VDDIO

11

PS

8

GNDIO

9

GND

ADDR:0X18

DMIC_CLK_L[22] DMIC_DAT_L[22]

G_INT

CN9

10 9 8 7 6 5 4 3 2

12

1

11

Subboard_CONN

R406 *short_4 R405 0_4 R407 0_4 R404 0_4

+3V

5

2 1

U7

3

*SN74AHC1G32DCKR

Quanta Computer Inc.

PROJECT :

INT&EXT USB

SDA_TO_EC [29] SCL_TO_EC [29] G_sen_INT [10,29]

C8 1000p/50V_4

4

1

HDD protect [21]

ZQX

27 43Wednesday, September 03, 2014

1B

1

SDO

2

SDA_TO_EC_R

SDX

12

SCL_TO_EC_R

SCX

5

INT1

6

INT2

NC

CSB

4

10

BMA250E

Sensor_INT[10,29]

+3V3_SER

+3V

SCL_TO_EC SDA_TO_ECSCL_TO_EC

DMIC_DAT_L

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

5

K/B (KBC) TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay)

CN14

26

MY0[29] MY1[29] MY2[29] MY3[29] MY4[29] MY5[29]

D D

C C

MY6[29] MY7[29] MY8[29] MY9[29] MY10[29] MY11[29] MY12[29] MY13[29] MY14[29] MY15[29] MY16[29] MY17[29] MX7[29] MX6[29] MX5[29] MX4[29] MX3[29] MX2[29] MX1[29] MX0[29]

MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 MX7 MX6 MX5 MX4 MX3 MX2 MX1 MX0

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

KB_CONN

28 27

4

7 8 5

6

3

4

1

2

CP10 *100p/50Vx4

7 8 5

6

3

4

1

2

CP11 *100p/50Vx4

7 8 5

6

3

4

1

2

CP6 *100p/50Vx4

7 8 5

6

3

4

1

2

CP7 *100p/50Vx4

7 8 5

6

3

4

1

2

CP8 *100p/50Vx4

7 8 5

6

3

4

1

2

CP9 *100p/50Vx4 C572 *100p/50V_4

C569 *100p/50V_4

+3VPCU

RP7

10

9

MX7

8

MX6

7 4

MX5 MX4

*10K_10P8R

3

MY16 MY17 MX7 MX6

MX5 MX4 MX3 MX2

MY0 MY1 MY2 MY3

MY4 MY5 MY6 MY7

MY8 MY9 MY10 MY11

MY12 MY13 MY14 MY15

MX1 MX0

1 2

MX1

3

MX2 MX3

56

Modify on 11/08, add touchpad i2c PU RES

I2C1_SDA_GPIO6[10,23]

I2C1_SCL_GPIO7[10,23]

I2C_TP_SDA_R I2C_TP_SCL_R

+TPVDD

R625

2.2K_4

R626 *0_4

1

4 3

2N7002DW

R634 *0_4

+TPVDD

TPD_ENMX0

R635

2.2K_4

Q44

6 2

5

+3V

R621 *10K_4

I2C_TP_SDA_R I2C_TP_SCL_R

TPCLK[29]

TPDATA[29]

2

+3V_S5 +3V +3VSUS

+TPVDD

R610

R611

10K_4

R618 *short_4 R617 *short_4

L23 *0_6 L21 *0_6 L22 2.2_6

PTP_PWR_EN#[29]

1

R776 0_6

2

Q53 *AO3413

3

C713 *1000p/50V_4

TPD_INT#[2,29]

TPD_EN[29]

+

C712

0.22u/25V_6

+TPVDD TPCLK_R TPDATA_R

I2C_TP_SDA_R I2C_TP_SCL_R

+TPVDD_R +TPVDD

C576

0.1u/10V_4

C578 *0.1u/10V_4

1

R775 *10K/J_4

C577

*0.1u/10V_4

50mil

C714

0.1u/10V_4

28

CN17

1 2 3 4 5 6 789

TP CN

10

CPU FAN (THM)

+3V

+5V

+3V

+5V

R119

2

1 3

Q16 MMBT3904-7-F

C583 1000p/50V_4

1K_4

+3VPCU +3V +5V

+3VPCU [7,8,11,13,21,22,23,29,30,31,35,36,37] +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,29,31,32,33,34,35,36] +5V [21,22,23,25,31,35]

FAN1_PWM[29]

Power tracking

B B

HOLE

HOLE17

*HG-C315D118P2

8 9

123

HOLE9 *H-C146D146N

1

A A

67 5 4

HOLE13 *H-C146D146N

HOLE14

*HG-C315D158P2

8 9

1

123

HOLE11 *H-C146D146N

5

67 5 4

1

HOLE12

*HG-C315D118P2

8 9

123

LGND

HOLE15

*HG-C315D118P2

8 9

123

67 5 4

*HG-C315D118P2

8 9

67 5 4

HOLE16

123

67 5 4

HOLE10

*HG-C315D146P2

8 9

123

HOLE8 EV@H-C236D140P2

1

67 5 4

4

HOLE6 EV@H-C236D140P2

1

HOLE7

*HG-C276D118P2

67 5

8

4

9

123

EMI

VIN +1.35Vsus_Src +Vin_Gpu_Core +Vgpu_Core +1V_Src

3

R102 10K_4

C585 1000p/50V_4

FANSIG[29]

FAN_PWM_CN1

30mil

C586 1000p/50V_4

R103 10K_4

C588 1000p/50V_4

R101 *short_8

+5V_FAN1

2

CN10

C589 1000p/50V_4

345 2 1

FAN1

6

CPU

Quanta Computer Inc.

ZQX

PROJECT :

Size Document Number Rev

Date: Sheet of

PROJECT :

KB/TP/FAN

ZQX

28 43Wednesday, September 03, 2014

1

28 43Wednesday, September 03, 2014

1B

5

EC(KBC)

R413 2.2_6

+3VPCU

+3VPCU_EC and +3V_RTC minimum trace width 12mils.

D D

+3VPCU

D14

R106

SDMK0340L-7-F

100K_4

1 2

2 1

WRST#

C139 1u/6.3V_4

C C

B B

CLK_PCI_EC

R420 *22_4

C422 *10p/50V_4

Please do not place any pull-up resistor on GPG0, GPG2, and GPG6 (Reserved hardware strapping).

L17 BLM15AG121SN1D/0.5A/120ohm_4

12 mils

C405

0.1u/10V_4

LPC_LAD0[8,21,26] LPC_LAD1[8,21,26] LPC_LAD2[8,21,26] LPC_LAD3[8,21,26]

PLTRST#[7,13,16,21,24,26]

TPD_INT#[2,28]

MAINON[32,35]

TPD_EN[28]

FAN1_PWM[28]

ME_WR#[8]

C404

0.1u/10V_4

+3V

TP80

SUSON[31,32]

TP81

ACIN[30]

TS_EN[23]

D/C#[30]

MY16[28] MY17[28]

S5_ON[31,33,35]

MY0[28] MY1[28] MY2[28] MY3[28] MY4[28] MY5[28] MY6[28] MY7[28] MY8[28]

MY9[28] MY10[28] MY11[28] MY12[28] MY13[28] MY14[28] MY15[28]

C409

0.1u/10V_4

PCH_SPI_CLK_EC[8] SPI_CS0#_UR_ME[8]

CLK_PCI_EC[9]

LPC_LFRAME#[8,21,26]

IRQ_SERIRQ[10,21]

SIO_EXT_SMI#[10]

SIO_EXT_SCI#[10]

SIO_RCIN#[10]

PCH_BLON_EC[23]

BT_POWERON[26]

EC_PWROK[7]

SENSOR_EN[27] Sensor_INT[10,27]

AMP_MUTE#[22]

PCH_SLP_SUS#[7]

TEMP_MBAT[30] PCBEEP_EC[22] SDA_TO_EC[27]

SCL_TO_EC[27]

PCH_SPI_SI_EC[8]

PCH_SPI_SO_EC[8]

C145

0.1u/10V_4

R414 2.2_6

PLTRST#

PROCHOT_EC SIO_A20GATE

BT_POWERON SENSOR_EN

Sensor_INT E51_TXD

PCBEEP_EC SDA_TO_EC

SCL_TO_EC

S5_ON

C424

0.1u/10V_4

ECAGND

+3VPCU_EC

C415

0.1u/10V_4

+3V_EC

C419

0.1u/10V_4

10

9 8

7 22 13

6 17

126

5 15 23 14

4 16

119 123

80

104

33 88 81 87

109 108

71 72 73 35 34

107

95 94

105 101 102 103

56 57 32

100 106

36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55

MX0[28] MX1[28] MX2[28] MX3[28] MX4[28] MX5[28] MX6[28] MX7[28]

4

+A3VPCU

12 mils

+3V_RTC

C431

0.1u/10V_4

U25

LAD0/GPM0(X) LAD1/GPM1(X) LAD2/GPM2(X) LAD3/GPM3(X) LPCRST#/WUI4/GPD2(Up) LPCCLK/GPM4(X) LFRAME#/GPM5(X)

LPCPD#/WUI6/GPE6(Dn) GA20/GPB5(X)

SERIRQ/GPM6(X) ECSMI#/GPD4(Up) ECSCI#/GPD3(Up) WRST# KBRST#/GPB6(X) PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT

CRX0/GPC0(Dn) CTX0/TMA0/GPB2(Dn)

DAC4/DCD0#/GPJ4(X) DSR0#/GPG6(X) GINT/CTS0#/GPD5(Up) PS2DAT1/RTS0#/GPF3(Up) DAC5/RIG0#/GPJ5(X) PS2CLK1/DTR0#/GPF2(Up) TXD/SOUT0/GPB1(Up) RXD/SIN0/GPB0(Up)

ADC5/DCD1#/WUI29/GPI5(X) ADC6/DSR1#/WUI30/GPI6(X) ADC7/CTS1#/WUI31/GPI7(X) RTS1#/WUI5/GPE5(Dn) PWM7/RIG1#/GPA7(Up) DTR1#/SBUSY/GPG1/ID7(Dn) CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn) CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)

FSCK/GPG7 FSCE#/GPG3 FMOSI/GPG4 FMISO/GPG5

KSO16/SMOSI/GPC3(Dn) KSO17/SMISO/GPC5(Dn) PWM6/SSCK/GPA6(Up)

SSCE0#/GPG2(X) SSCE1#/GPG0(X)

KSO0/PD0 KSO1/PD1 KSO2/PD2 KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15

C412

0.1u/10V_4

11

114

VCC

VSTBY26VSTBY50VSTBY92VSTBY

LPC

CIR

EXTERNAL SERIAL FLASH

SPI ENABLE

KBMX

KSI0/STB#58KSI1/AFD#59KSI2/INIT#60KSI3/SLIN#61KSI462KSI563KSI664KSI7

127

121

3

74

VBAT

AVCC

VSTBY

IT8380

UART port

1

65

L16 BLM15AG121SN1D/0.5A/120ohm_4

+3VPCU_ECPLL

84

VSTBY

VSS

L15 BLM15AG121SN1D/0.5A/120ohm_4

C407

0.1u/10V_4

82

EGAD/WUI25/GPE1(Dn)

EGCS#/WUI26/GPE2(Dn)83EGCLK/WUI27/GPE3(Dn)

20

19

L80HLAT/BAO/WUI24/GPE0(Dn)

L80LLAT/WUI7/GPE7(Up)

GPIO

(For PLL Power)

HWPG

R403 0_4

USB_BC_ON

97

93

WUI41/GPH5/ID5(Dn)98WUI42/GPH6/ID6(Dn)99WUI19/GPH3/ID3(Dn)96WUI40/GPH4/ID4(Dn)

WAKE UP

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn)

VSS27VSS49VSS

VSS

91

113

VCORE

VSS

AVSS

12

75

122

C421

0.1u/10V_4

ECAGND

SUSC# [7,13] SUSB# [7,13]

TP90

PTP_PWR_EN# [28]

TP84 TP82

G_sen_INT [10,27] USB_BC_ON [27]

CLKRUN# [7,21]

SMCLK0/GPB3(X) SMDAT0/GPB4(X) SMCLK1/GPC1(X) SMDAT1/GPC2(X)

PECI/SMCLK2/WUI22/GPF6(Up)

SMDAT2/WUI23/GPF7(Up)

PS2CLK0/TMB0/CEC/GPF0(Up)

PS2DAT0/TMB1/GPF1(Up)

SM BUS

PS2CLK2/WUI20/GPF4(Up) PS2DAT2/WUI21/GPF5(Up)

CLKRUN#/WUI16/GPH0/ID0(Dn)

PS/2

PWM0/GPA0(Up) PWM1/GPA1(Up) PWM2/GPA2(Up) PWM3/GPA3(Up) PWM4/GPA4(Up) PWM5/GPA5(Up)

PWM

TACH0A/GPD6(Dn)

TACH1A/TMA1/GPD7(Dn)

TMRI0/WUI2/GPC4(Dn) TMRI1/WUI3/GPC6(Dn)

PWRSW/GPE4(Up) RI1#/WUI0/GPD0(Up) RI2#/WUI1/GPD1(Up)

ADC0/GPI0(X) ADC1/GPI1(X) ADC2/GPI2(X) ADC3/GPI3(X)

ADC4/WUI28/GPI4(X)

A/D D/A

TACH2/GPJ0(X)

DAC2/TACH0B/GPJ2(X) DAC3/TACH1B/GPJ3(X)

CK32KE/GPJ7

CLOCK

CK32K/GPJ6

IT8380E-192/CX

3

GPJ1(X)

+3VPCU_EC

110 111 115 116 117 118

85 86 89 90

24 25 28 29 30 31

47 48

120 124

125 18 21

112

66 67 68 69 70

76 77 78 79

MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA EC_PECR_R

AC_Protect

SUSLED#

FAN2SIG

NBSWON# dGPU_OPP#

ICMNT

C423 10u/6.3V_6

FB_CLAMP_REQ#

EC_FB_CLAMP

MBCLK [30] MBDATA [30] 2ND_MBCLK [8,19] 2ND_MBDATA [8,19]

R392 43_4

AC_Protect [30] LID# [23] TPCLK [28] TPDATA [28]

PWRLED# [21] BATLED1# [21] SUSLED# [21] BATLED0# [21] Sensor_PCH_CLK [10] Sensor_PCH_DAT [10]

TP15

DNBSWON# [7] DPWROK [7]

NBSWON# [13,27] dGPU_OPP# [19] SB_ACDC [30]

RSMRST# [7]

RF_EN [26] ICMNT [30]

ECAGND

APWORK [5,7] VRON [34] FB_CLAMP_REQ# [19]

dGPU_OTP# [19] EC_FB_CLAMP [17,19] PCH_PWROK [5,7] USBON# [27]

EC_FPBACK# [23]

SWAP for EC request

2 128

PCH_SUSACK# [7] PCH_SUSPWARN# [7]

SM BUS ARRANGEMENT TABLE

SM Bus 1

Battery

SM Bus 2

PCH/VGA

N/A

SM Bus 3

SM Bus 4

H_PECI [4]

6/30 add AC_protect for power request

FANSIG [28]

2

S5_ON

dGPU_OPP#

MAINON SUSON VRON PCH_SPI_SI_EC

PCH_SPI_SO_EC

R394 10K_4

R424 *10K_4

R417 100K_4 R393 100K_4 R99 100K_4 R395 *10K_4

R396 *10K_4

1

+3VPCU

29

+3V_GFX

SM BUS PU(KBC)

+3VPCU

+3V_S5

+3V

H_PROCHOT# [4,30,34]

+3V

R87 10K_4

HWPG

PROCHOT_EC

HWPG(KBC)

MBCLK MBDATA

2ND_MBCLK 2ND_MBDATA

SCL_TO_EC SDA_TO_EC

R105 100K_4

DDR=1.5V, D1 DNP and D2 POP DDR=1.35V, D1 POP and D2 DNP

HWPG_1.5V[35]

HWPG_1.05V[5]

HWPG_VDDR[32]

HWPG_1.05V_S5[5,13,33]

SYS_HWPG[31]

R388 4.7K_4 R389 4.7K_4

R390 4.7K_4 R391 4.7K_4

R411 *4.7K_4 R408 *4.7K_4

3

2

1

D1 D2

Q18

2N7002K

D12 RB500V-40 D11 *RB500V-40 D13 *RB500V-40 D10 RB500V-40 D9 RB500V-40

For test only

A A

5

TP109

3 5

6

Power Switch

SW7

2

NBSWON#

14

TP107

4

iRST

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

KBC IT8380

ZQX

1B

29 43Wednesday, September 03, 2014

1

29 43Wednesday, September 03, 2014

1B

5

PJ6

1 2 3 4

Power conn

D D

VIN

C C

ACIN[29]

ACPRESENT[7]

SB_ACDC[29]

B B

PJ7

89 7 6 5 4 3

50458-00801-V01

2 1

10

A A

PU18 *IP4223-CZ6

1

CH1

CH4

2

VN CH23CH3

Add ESD diode base on EC FAE suggestion

PR221 *short 0_4

*100p/50V_4

6 5

VP

4

5

PC26

0.1u/50V_6

PC194

0.1u/50V_6

PC61

PR142 *short 0_4

PR140 100_4

*47p/50V_4

PR143 100_4

MBDATA

+3VPCU

MBCLKTEMP_MBAT

PC74

PC25

2200p/50V_6

+3VPCU

PR220 *10K_4

PR227 *0_4

6

1

Delete Bat_EN

TEMP_MBAT

PR141 1M_4

PC73 *47p/50V_4

PR139 100_4

MBCLK [29]

MBDATA [29]

Delete SW6 for ACER request No system power cut off mechanism

PR233 100K_4

2

PC189

PR229

0.1u/25V_4

100K_4

5

PQ53 2N7002DW

4 3

TEMP_MBAT [29]

+3VPCU

4

VA1

PC136

0.1u/50V_6

PD7 1N4148WS

recommend 200mA at least.

PR125 *short 0_6

MBDATA

+3VPCU

24737_BM#

4

PR213 10K_4

PR218

316K/F_4

MBCLK

PR232 10K_4

PR214 *100K_4

3

2

PQ31 *2N7002K

1

CS41332FB06

65W-DIS

CS34022FB15

40W-UMA 40.2K

PD11 SMAJ20A

2 1

PR127

63.4K/F_4

PR131 10K/F_4

PR136 20_1206

PR226 *short 0_4

PR222 *short 0_4

24737_BM#

24737_CMPOUT

24737_ILIM

PR215

PC173

100K/F_4

0.01u/25V_4

ICMNT[29]

PR135 Value

133K

24737_ACDET

24737_VCC

PC188

0.47u/25V_6

24737_CMPIN

PR230 100K/F_4

PC28

0.1u/50V_6

PC68

0.1u/50V_6

6

ACDET

20

VCC

5

ACOK#

8

SDA

9

SCL

11

BM#

3

CMPOUT

10

ILIM

4

CMPIN

PR135 SP@133K/F_4

AC_Protect[29]

3

PR59 220K_4

PR62 220K_4

0.1u/50V_6

2

BQ24737RGRR

IOUT

7

PC186 100p/50V_4

3

PC192

ACP

PU17

21

1

ACN

GND

GND22GND24GND23GND

24737_CMPOUT

1 3

1 6 2 3

PQ24

IMD2AT108

24737_ACP

24737_ACN

PC65

0.1u/50V_6

REGN

BTST

HIDRV

PHASE

LCDRV

PGND

SRP

SRN

25

PR231

*0_4

PR242

*short 0_4

2

PQ47 AOL1413

4

5 4

16

24737_REGN

17

24737_BST

18

24737_DH

19

24707_LX

15

14

PR212 10_6

13

PR210 7.5_6

12

PR138

*100K_4

52

+1.05V

2

VA2

PD12

SBR1045SP5-13

1 2

PR61 *short 0_4

PR224 *short 0_6

24737_SRP

24737_SRN

3

PQ33 2N7002K

1

PC177 1u/16V_6

PD13 RB500V-40

PC184 47n/50V_6

2014/06/18 modify

PR185

0.02/F_0612

3

1 2

D/C# [29]

PC58

0.1u/25V_4

PC54

0.1u/25V_4

PC171

0.1u/25V_4

H_PROCHOT# [4,29,34]

Limit set on 65W(DIS)/40W(UMA)

2

1

2/10 MODIFY

PR186 *short 0_4

24737_ACN

24737_ACP

PR187 *short 0_4

PC182

1

PQ51 MDV1528

PQ50 MDV1528

2200p/50V_6

PR122 *4.7_6

PC53 *680p/50V_6

6.8uH_7X7X3

52

4

3

52

4

3

PL15

PC191

0.1u/50V_6

24737_SRPBAT-V 24737_SRN

VIN

PR211 *short 0_4

PC187

4.7u/25V_8

1 2

PC193 2200p/50V_6

VIN

PR208

0.01/F_0612

PR209 *short 0_4

1 3

PR234 33K/F_4

PQ52 2N7002K

PC71

0.1u/25V_4

Add 11/14

PC169

2200p/50V_6

PQ32 AOL1413

2

PC72

0.1u/25V_4

52

4

PR235 10K_4

3

1

PC170

10u/25V_1206

30

BAT-V24737_DL

PC168

10u/25V_1206

REGN MAX voltage 6.5V V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr =0.793V for 3.965A current limit

Pin10 ILIM=0.793V Rsr = 0.01ohm

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

PROJECT :

Charger(BQ24737RGRR)

ZQX

1B

30 43Wednesday, September 03, 2014

1

30 43Wednesday, September 03, 2014

1B

5

SYS_SHDN#

MAIND

D D

SYS_HWP G[29 ]

C C

B B

A A

SYS_SHDN#

SYS_SHDN# [10,21,35]

MAIND [3 3,35]

SYS_HWP G

PR153 10K/F_4

LDO(MAX)=100mA

+15V

+3VPCU

PR13

100K/F_4

+3V_LDO

PR147 22_8

PR217 *short 0_4

PR225 *short 0_4

PC63

*0.1U/10V _4

SYS_SHDN#

PR24 *short 0_4

PR21 *499K/F_4

PC110 *0.1U/10V _4 PC195

13

670_EN

PR7 *short 0 _4

PR25 *0_4

PC93 10u/6.3V _6

PD8

1PS302

670PG

670_ENLDO

PC83

0.1u/50V _6

PD9

3

1PS302

1

2

PC82

0.1u/50V _6

PC76

0.1u/50V _6

PR228 *499K/F_4

671_EN 671_ SW 671PGSYS_HWPG

PR219 *short 0_4

EN

4

PG

3

LP#

12

ENLDO

6

LDO

14

AGND

670_CLK

PC87

0.1u/50V _6

PD10

3

1PS302

1

2

PC88

0.1u/50V _6

1

VIN

13

EN

4

PG

3

LP#

PU16

5

NB671

NC1

6

NC2

14

AGND

VCC

11

VL

1

10

VIN

PU10

NB670GQ-Z

CLK5VCC

11

PC86

0.1u/50V _6

3

1

2

671_BST 671_BST1

10

BST

SW1 SW2 SW3 SW4

VOUT

PGND

FB

12

PC181 1u/6.3V_ 4

670_BST 670_BST1

5VPCU_VIN

671_FB

4

3VPCU_VIN

PR163 1/F_6

0.1u/50V _6

BST

8

670_SW

SW1

9

SW2

15

SW3

16

SW4

7

VOUT

2

PGND

PC111 1u/6.3V_ 4

PR216 1/F_6

PC175

0.1u/50V _6

8 9 15 16 7 2

PC178

0.1u/16V _4

VREF=0.604V

PC109

PC7

*0.1u/16V_4

PC190 2200p/50V_6

PR123 *4.7_6

PC59 *680p/50 V_6

PR129

11K/F_4

PC112 2200p/50V_6

PL7

3.3uH_7X 7X3

PR11 *4.7_6

PC8 *680p/50 V_6

PC70 4.7u/25V_8

PL14

3.3uH_7X 7X3

PC98 4.7u/25V_8

PC66 4.7u/25V_8

PR126 82K/F_4

PC104 4.7u/25V_8

PC105 0.1u/50V_6

PR14

*short 0_6

PC185 4.7u/25V_8

3

1/13 Adding +3VSUS power for touch pad (By acer request)

JP11 *short 0.001/F_3720

1 2

PC97 4.7u/25V_8

PC117 4.7u/25V_8

1 2

*short 0.001/F_3720

+

PC127

PC16 22u/6.3V_8

JP18 *short 0.001/F_3720

1 2

PC57 22u/6.3V_8

PC179 22u/6.3V_8

220u/6.3V_6X4.2

+

PC51 22u/6.3V_8

PC14 22u/6.3V_8

PC13 22u/6.3V_8

PC64 4.7u/25V_8

PC172 0.1u/50V_6

JP6

PC166

12

+

*220u/6.3V_6X4.2

+3VPCU

PC167 33U/25V_ 6x4.5

1 2

JP15 *short 0.001/F_3720

VIN

+3VPCU

3.3 Volt +/- 5% TDC : 4.3A PEAK : 5.8A Width : 180mil

VIN

+5VPCU

S5_ON[29,33,35]

+5VPCU 5 Volt +/- 5% TDC : 5.5A PEAK : 7.4A OCP : 9A Width : 220mil

2

PQ30

DTC144EU

SUSON[29,32]

DTC144EU

PR121 1M_6

1 3

PR118 1M_6

2

1

31

+15VVIN

PR239 1M_6

3

PQ64

2N7002K

1

52

4

3

TDC : 3A PEAK : 4A Width : 120mil

+5VPCU

52

4

3

TDC : 2.41A PEAK : 3.21A Width : 100mil

VIN +3VPCU

PR240

1

*1M_6

*2.2n/50V_4

MDV1528Q

3

2

SUSD

PQ67 AO3404

1

+3VSUS

TDC : 0.038A PEAK : 0.05A Width : 20mil

+3VPCU

3

PQ25

+5V_S5 +3V_S5

PQ26

+5V

2

1

TDC : 0.6A PEAK : 0.81A Width : 40mil

+3VPCU

3

2

1

TDC : 0.62A PEAK : 0.83A Width : 40mil

PQ11 AO3404

PQ10 AO3404

+3V

+3VSUS

PR238 1M_6

2

PR237

1 3

PR56 22_8

PQ21 2N7002K

1M_6

+5V_S5+3V_S5

PR117 22_8

3

2

PQ29 2N7002K

1

PQ66

3

2

1

PR236 22_8

3

2

1

+15VVIN

3

2

1

2

PQ65 2N7002K

VIN +5VPCU

PR119

PR120

*1M_6

1M_6

S5D S5D

PQ28

2N7002K

PC52 *2.2n/50V_4

MAIND MAIND

PR132

*short 0_6

Size Docum ent Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Quanta Computer Inc.

PROJECT :

SYSTEM 5V/3V (TPS51225)

1

ZQX

31 43Wednesday, S eptember 03, 2014

1B

5

4

3

2

1

TDC : 0.75A PEAK : 1A Width : 40mil

D D

TDC : 0.38A PEAK : 0.5A

DDR_VTTREF

Width : 20mil

PC36

0.22u/10V_4

+3V

PR76

100K/F_4

PC34

20

17

16

19

18

26

51216_REF

PR68 10K/F_4

C C

HWPG_VDDR[29]

MAINON[29,35]

SUSON[29,31]

PR69

*0_4

PR67

*short 0_4 PR72

200K/F_4 PR71

82K/F_4

51216_S3

51216_S5

51216_MODE

51216_TRIP

VREF=1.8V

B B

51216_S551216_S3

PR188 *0_4

51216_S3

PR70 *short 0_4

DDR_VTTT_PG_CTRL [4]

0.1u/10V_4

PGOOD

S3

S5

MODE

TRIP

PAD

+DDR_VTT_RUN

PC38 10u/6.3V_6

21

22

PAD

REF

8

6

51216_REFIN

5

PAD

TPS51216RUKR

REFIN

9

32

PC37 10u/6.3V_6

Close to IC

Greater than or equal 40mil

+5V_S5

PR66 *SHORT_4

PC145

12

14

15

13

11

10

10u/6.3V_6

51216_DRVH

51216_VBST

51216_SW

51216_DRVL

PR64 2/F_6

2

3

1

4

VTT

VTTREF

VDDQSNS

PU6

VTTSNS

VTTGND

PAD24PAD

25

VLDOIN

V5IN

DRVH

VBST

SW

DRVL

PGND

GND

PAD

7

23

PR190 *short 0_6

PR65 *0_4

PC32 1u/10V_4

PC31

0.1u/50V_6

4

RDSon=2.2mohm

+5VPCU

VIN

52

PC140 2200p/50V_4

PQ48 MDV1528

3

1

52

PQ49

PR63

MDV1595S

*4.7_6

3

1

PC29 *680p/50V_6

PC139

4.7u/25V_8

PL11

2.2uH_7X7X3

+1.35VSUS_SRC

PC137

0.1u/50V_6

JP14 *short 0.001/F_3720

1 2

+

PC138 330u/2.5V_6X4.2

+1.35V_SUS

1.35 Volt +/- 5% TDC : 4.8A PEAK : 6.4A OCP : 8A Width : 200mil

+1.35V_SUS

+1.35V_SUS [4,5,14,15]

Close to output cap

PR189

30.1K/F_4

PC33

0.01u/25V_4

Mode Frequency Discharge mode

200K 400K Tracking Discharge

OCP=8A L ripple current =(19-1.35)*1.35/(2.2u*400k*19)

A A

=1.425A Vtrip=8-(1.425/2)*14mohm =102.024mV Rlimit=102.024mV/10uA*8=81.62Kohm

5

DDR=1.35V PR84=10K/F_4 PR86=30.1K/F_4

4

100K 300K Tracking Discharge

S3 S5

S0

S3 (mainon off)

S4/S5

1 0

1 1

3

ON ON ON OFF

VTTREF+1.35VSUS

ON ON

OFF

OFF OFF0 0

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

PROJECT :

DDR 1.35V(TPS51216)

ZQX

1B

32 43Wednesday, September 03, 2014

1

5

4

3

2

1

JP7 *short 0.001/F_3720

1 2

D D

+3V

PR172 100K/F_4

HWPG_1.05V_S5[5,13,29]

S5_ON[29,31,35]

C C

PR34 *short 0_4

PR174 *100K/F_4

PR173 82K/F_4 PR175 464K/F_4

51211V_EN 51211V_VBST 51211V_TRIP 51211V_TST

1 3 2 5

12

PGOOD EN TRIP

TPS51211DSCR

TST GND

GND13GND14GND15GND

7

PU12

V5IN

DRVH

VBST

DRVL

GND

4

16

+5VPCU

PC129 1u/10V_4

51211V_DRVH

9 10 8

SW

FB

51211V_SW +1V_SRC

6

51211V_DRVL

11

51211V_FB

PR176 *short 0_6

PC130

0.1u/50V_6

PQ41

MDV1595S

52

PQ40

4

MDV1528

3

1

52

3

1

PC132 2200p/50V_6

PL10

2.2uH_7X7X3

PR45 *4.7_6

PC21 *680p/50V_6

PC133

4.7u/25V_8

PR37

5.1K/F_4

PR35 10K/F_4

PC128

0.1u/50V_6

VIN

+1V_SRC

+

PC131 330u/2.5V_6X4.2

1 2

JP13 *short 0.001/F_3720

+1.05V_S5

+1.05V

1.05 Volt +/- 5% TDC : 4.7A PEAK : 6.3A OCP : 8A

33

Width : 200mil

OCP=8A L ripple current =(19-1.05)*1.05/(2.2u*290k*19) =1.555A Vtrip=8-(1.555/2)*14mohm

B B

=101.12mV Rlimit=101.12mV/10uA*8=80.89Kohm

VFB=0.7V

+1.05V_S5

52

4

MAIND[31,35]

VIN

PR47 *1M_4

A A

MODPHY_EN[10]

PR49 *0_4

PC22 *1u/10V_4

12

2

PR48 *100K_4

PQ14 *PDTC143TT

1 3

PR46 *1M_4

PR184 *22_8

3

2

PQ46 *2N7002K

1

+15V+1.05V_MODPHY

PR58 *1M_4

MODPHY_D

3

2

PQ15 *2N7002K

1

PC27 *2.2n/50V_4

+1.05V_S5

2

3

PQ23 *AO3404

1

+1.05V_MODPHY

+1.05V_MODPHY +1.05V

PR60 *short 0_8

+1.05V_MODPHY TDC : 1.43A PEAK : 1.9A

MAIND

Width : 80mil

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

PQ42 MDV1528Q

3

1

+1.05V

TDC : 2.31A PEAK : 3.08A Width : 100mil

Quanta Computer Inc.

PROJECT :

+1.05V_S5 (TPS51211)

ZQX

33 43Wednesday, September 03, 2014

1

1B

5

IMON offset

+VIN_VCCIN

H_PROCHOT#[4,29,30] VR_SVID_CLK[5]

IMVP_PWRGD[5,10]

VRON[29]

VRON_CPU[5]

CS35622FB10 CS44122FB00PR79

PR87 2M/F_4

PR89 2M/F_4

PR80 30K/F_4

PC164

VR_SVID_CLK VR_SVID_ALERT# VR_SVID_DATA

PR103 *short 0_4

PR94 *0_4

PR82 *short 0_4

VCC_SENSE[5] VSS_SENSE[12]

Parallel

5

51624_OCP-I

PR113

130/F_4

0.1u/10V_4

PR205

*100K/F_4

15W

Value CS22262FB05 CS31692FB11 CS46652FB10 CS24992FB26 CS33902FB16 CS43652FB10

51624_VRON

PR83 100K/F_4

+1.05V

56_4

PR115

PR114

*75/F_4

+3V

PR91

PR202

*100K/F_4

+VCCIN

PR104 *10_4

PR97 *10_4

Close to the CPU side.

D D

C C

VR_SVID_ALERT#[5] VR_SVID_DATA[5]

B B

BW-U 28W 1 phase

Location Value

PR63 CS22212FB11

A A

PR191 CS32262FB15 PR67 CS45232FB00 PR95 CS24752FB12 PR70

+3V_S5 51624_VREF +5V_S5

1_6

PR105

PC47

1u/6.3V_4

PC158

0.33u/6.3V_4

Close to VR

*56_4

PR206

PR107 *short 0_4 PR108 *short 0_4 PR109 *short 0_4

+3V+3V

PC44 *330p/50V_4

PC43 *0.01u/50V_4

51624_CLK 51624_ALERT# 51624_DATA

51624_SKIP# 51624_VRON

51624_VFB

51624_GFB

51624_VREF

PR102 *short 0_4

PR100 *short 0_4

BW-U 28W 2 phase

Location Value PL7



PL8 0.24uH_7X7X4

PR63 1.82K/F_4

PR191



PR194 *22.6K/F_4

PR182 2.67K/F_4

PC144



PC148

0.15u/10V_4

PR67 294K/F_4

4

Place NTC close to the VCORE Hot-Spot.

PR77

PR78

36.5K/F_4

20K/F_4

PR84

51624_VDD

2

30

VR_HOT

31

VCLK

32

ALERT

1

VDIO

3

PGOOD

7

SKIP

8

VR_ON

24

VFB

23

GFB

26

51624_COMP

PC50

PR111

10K/F_4

*100p/50V_4

PR106 4.7K/F_4

PR112

PC46

4.75K/F_4

*90.9K/F_4

PR86

PR85

100K/F_4

150K/F_4

51624_O-USR

51624_F-IMAX

51624_B-RAMP

9

VREF

DROOP25COMP

51624_OCP-I

10

O-USR

TPS51624RSM

OCP-I12IMON

13

51624_IMON

51624_SLEWA

11

15

F-IMAX

SLEWA

B-RAMP

PU7

PAD

GND29PAD34PAD35PAD36PAD37PAD38PAD39PAD40PAD41PAD

33

PR90

365K/F_4

PR81

39K/F_4

51624_VREF

27

VDD

51624_DROOP

1500p/50V_4

PR79

665K/F_4

Location Value PR75 56.2K/F_4

PR203

PR200

*39.2K/F_4

100K/F_4_4250NTC

39K/F_4

PR199

51624_THERM 51624_V5A 51624_VBAT

28

14

16

V5A

THERM

PC41

4700p/25V_4

VBAT

PWM1 PWM2 MODE

CSP1 CSN1 CSN2 CSP2

1n/50V_4

PC149

PR198

9.09K/F_4

6 5 4 17 18 19 20 21

NC

22

N/C

42

PR193 *short 0_8

51624_PWM1 51624_PWM2 51624_MODE 51624_CSP1 51624_CSN1 51624_CSN2 51624_CSP2

PR110

51624_CSP2

51624_PWM2

51624_CSN2

PR95 2.37K/F_4 PR101 10K/F_4 PR79 150K/F_4

PR84



PC142 PC147

 

PR87

PC145 PC149

*0_4

*0.1u/25V_4

StuffBlock 1.

4

20/F_6

PC159

2.2u/10V_6

PR101 150K/F_4

PR95 0_4

PR88

10K/F_4

+3V_S5

3

+5V_S5

PC144 1u/10V_4

51624_PWM1

PR196 *SHORT_4

PR197

2.2/F_6

51624_SKIP# 51624_PWM1_R CS_BSTR1

1

SKIP#

8

PWM

6

BOOT_R

7

CS_BST1

BOOT

PC148

0.22u/25V_6

Add 11 GND VIAs for thermal pad

BW-U 15W(1 phase)

Icc TDC PL2󶁪14A Icc Max󶁪32A OCP󶁪37A Fsw󶁪1.2MHz

VCORE L/L󶁪󶁪󶁪󶁪

R_DC_LL󶁪- 2.0mV/A

Rmode

R_AC_LL󶁪- 7.0mV/A

For BW-U 28W 2 phase

+5V_S5

PC154 *1u/10V_4

51624_SKIP# 51624_PWM2

CS_BSTR2

PR98 0_4

PR99 *0_4

3

PR207 *2.2/F_6

Block 1.

1

SKIP#

8

PWM

6

BOOT_R

7

CS_BST2

BOOT

PC165 *0.22u/25V_6

Add 11 GND VIAs for thermal pad

2

VDD

VIN

VSW

PGND

PAD

PU14

CSD97374CQ4M

51624_CSP1

PC151 *0.1u/25V_4

51624_CSN1

PC153 *0.1u/25V_4

2

VDD

VIN

VSW

PGND

PAD

PU15

*CSD97374CQ4M

51624_CSP2

PC157 *0.1u/25V_4

51624_CSN2

PC155 *0.1u/25V_4

2

+VIN_VCCIN

5 4

CS_SW1

3 9

PC152

Close to the VR side.

100K Ohm

150K OhmONON

+VIN_VCCIN

5 4

CS_SW2

3 9

PC156

Close to the VR side.

2

PC150

PC147

2200p/50V_4

0.1u/50V_6

PR73

2.2_6

PC35

1000p/50V_6

PR191

2.94K/F_4

0.12u/10V_4

PR192

10K/F_4_3435KNTC

Close with phase1 inductor

PS3 OSR

PC161

PC160

*2200p/50V_4

*0.1u/50V_6

PR96

*2.2_6

PC42

*1000p/50V_6

PR194

*2.67K/F_4

*0.15u/10V_4

PR195

*10K/F_4_3435KNTC

Close with phase1 inductor

PC40

PL12

0.15uH_7X7X4

1 2

3

4

PR74 2.26K/F_4

PR201

16.9K/F_4

ON

OFF

PC45

PL13

*0.24uH_7X7X4

1 2

3

4

PR92 *1.82K/F_4

PR204

*22.6K/F_4

1

JP16 *short 0.001/F_3720

4.7u/25V_8

PR75 *short 0_4

1 2

PC39

4.7u/25V_8

DCR= 1mOhm

PC30

PC141

0.1u/10V_4

+

PC142

22u/6.3V_8

VIN

12

PC143

33U/25V_6x4.5

+VCCIN

+

PC146

*330u/2V_7343

BW-U 28W(1 phase)

Icc TDC PL2󶁪19A Icc Max󶁪40A OCP󶁪47A Fsw󶁪800KHz

VCORE L/L󶁪󶁪󶁪󶁪

R_DC_LL󶁪- 2.0mV/A R_AC_LL󶁪- 7.0mV/A

PC48

*4.7u/25V_8

DCR= 1mOhm

PC49

PC162

*0.1u/10V_4

PR93 *0_4

Size Document Number Rev

Date: Sheet of

PC163

*22u/6.3V_8

Quanta Computer Inc.

PROJECT :

+VCCIN(TPS51624)

+VCCIN

ZQX

34 43Wednesday, September 03, 2014

1

34 43Wednesday, September 03, 2014

34

1B

1

2

3

4

5

+3VPCU

1 2

+3V

JP8 *short 0.001/F_3720

PR130

MAINON

100K/F_4

PR133 *short 0_4

1000p/50V_4

PC183

*100p/50V_4

A A

HWPG_1.5V[29]

PC62

PC69

10u/6.3V_6

8.06K/F_4

PC180

1500p/50V_4

PR223

PC67

0.1u/25V_6

PR128 121K/F_4

PU8 TPS54318RTER

16

VIN

1

VIN

2

VIN

14

PWRGD

15

EN

7

COMP

8

RT/CLK

9

SS

PC60

0.01u/25V_4

10

PH

11

PH

12

PH

13

BOOT

VSNS

GND GND

AGND

PAD17PAD18PAD19PAD20PAD21PAD

22

PR124 *short 0_6

6 3 4 5

PC56

0.1u/50V_6

1.5V_VSNS

VFB=0.8V

PL16

1uH_7X7X3

R1

R2

+1.5V

1.5Volt +/- 5% TDC : 0.56A PEAK : 0.75A Width : 40mil

PR134 100K/F_4

PR137 113K/F_4

PC176

0.1u/10V_4

PC174

10u/6.3V_6

+1.5V

12

PC55 10u/6.3V_6

JP17 *short 0.001/F_3720

35

V0=0.8*(R1+R2)/R2

B B

VIN

Thermal protection

PD6

3 2

1 3

84

+

-

DA2J10100L

PR53 1M_6

2

PC23

0.1u/50V_6

1

PU13A AS393MTR-E1

1

3

PQ18 AO3409

PR52 *short 0_6

PR51 200K_6

PC134

0.1u/50V_6

VIN

PR39 1M_4

MAINON_ON_G

2

PR31 *100K/F_6

PQ6 DTC144EU

1 3

MAINON[29,32]

SYS_SHDN# [10,21,31]

3

2

PQ43 2N7002K

1

PR38 1M_4

PR33 22_8

3

2

PQ38 2N7002K

1

3

2

1

PR116 22_8

PQ27 2N7002K

+1.05V

PR50 22_8

3

2

PQ16 2N7002K

1

+15V+5V+3V

PR40 1M_4

MAIND

3

2

PQ7 2N7002K

1

PC18 *2200p/50V_4

MAIND [31,33]

Need fine tune for thermal protect point

Note placement position TEMP=85C

2

PR179

1.58K/F_4

VLVL

S5_ON

DTC144EU

PR178 200K/F_4

2.469V

PR177 200K/F_4PQ17

PQ19

S5_ON[29,31,33]

C C

change PR164 to 1.47k for power request 11/07 (85c)

PR180

S5_ON

10K/F_4_3435NTC

3

2

2N7002K

1

LM393_PIN2

D D

For EC control thermal protection (output 3.3V)

1

5 6

+

-

7

PU13B AS393MTR-E1

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

2

3

4

Date: Sheet of

PROJECT :

+1.5V/Thermal Protect

ZQX

1B

35 43Wednesday, September 03, 2014

5

35 43Wednesday, September 03, 2014

1B

5

4

3

2

1

SP@ : GT@ GM@ UMA@

D D

PR29 *1/F_4 PR155 *short_4 PR156 *0_4

PR157 *short_4

PR158 *short_4

R1

PR161

SP@20K/F_4

PC100

SP@2700P/50V_4

2

12

PR22 EV@10K/F_4

PC12 *0.01U/25V_4

1 2

PR26 *499K/F_4

1 2

PC107 EV@1U/10V_4

SP@20K/F_4

12

SP@2K/F_4

SP@18.2K/F_4

PR16 *5.1K/F_4

3

PQ35 *2N7002K

1

PR20

PR15

PR17

PR18

SP@0_4

3V_MAIN_PWGD

PR8 EV@100K/F_4

3V_MAIN_PWGD[18,37]

VGPU_EN[8]

DGPU_PSI[19]

PWM-VID[19]

C C

DGPU_PSI

PR6 EV@10K_4

PR9

*0_4

+3V_S5

PR12

*10K_4

1 2

1658R-VREF

+VIN_GPU_CORE

VGPU_EN

DGPU_PSI

PWM-VID

+3VPCU

1 2

Phase Number of Operation

B B

Standby Function

TP77

VGA_STBY

PR159 *82.5/F_4

12

*1U/10V_4

PC95

PR23 EV@20K/F_4

1658R-OCS/CB

1658R-EN

1658R-PSI

1658R-VID

1658R-VREF

1658R-REFADJ

R2

1658R-REFIN

R3

R4

R5

+VGPU_CORE

PC103

12

PU11

9

OCS/CB

3

EN

4

PSI

EV@UP1658RQKF

5

VID

8

VREF

6

REFADJ

7

REFIN

FB

*0.01U/25V_4

11

1658R-FB

PC114

PR166

*22P/50V_4

+5V_S5

*short_4

PC101

PC102

PC122

EV@4.7u/25V_8

EV@10u/6.3V_8

PC77

EV@4.7u/25V_8

EV@10u/6.3V_8

JP12

*short_3720

1 2

+

PC119

EV@330u/2V_7343

+

PC90

EV@330u/2V_7343

PR27 *short_6

PR160

12

PC9

GND

BOOT1

UGATE1

PHASE1 LGATE1

BOOT2

UGATE2

PHASE2 LGATE2

PGOOD

COMP

FBRTN

EV@1U/10V_4

1

1658R-BOOT1

2

1658R-UGATE1

20

1658R-PHASE1

19

1658R-LGATE1

15

1658R-BOOT2

14

1658R-UGATE2

16

1658R-PHASE2

17

1658R-LGATE2

13

1658R-PG

12

1658R-COMP

10

1658R-FBRTN

PR165

PR169 EV@10K_4

1 2

PR28 *short_4

12

PC115

12

EV@4700P/25V_4

PC116

PR171

EV@16K/F_6

*short_4

EV@22P/50V_4

+3V

GPU_PWR_GD [17]

1658R-PVCC

18

PVCC

21

1658R-BOOT1

EV@0.22u/25V_6

1658R-UGATE1

1658R-PHASE1

1658R-LGATE1

1658R-BOOT2

1658R-UGATE2

1658R-PHASE2

1658R-LGATE2

EV@2.2/F_6

PC99

PR170

EV@2.2/F_6

PC113

EV@0.22u/25V_6

4

PQ36 EV@AON6752

4

PQ37 EV@AON6752

5

213

5

213

5

213

PQ39 EV@AON6414AL

5

213

+VIN_GPU_CORE

PQ34 EV@AON6414AL

PR10 EV@2.2/F_6

PC6 EV@1000p/50V_6

+VIN_GPU_CORE

PR30 EV@2.2/F_6

PC11 EV@1000p/50V_6

PC20

EV@2200p/50V_4

PC92

EV@2200p/50V_4

PC126

EV@0.1u/50V_6

PL6

EV@0.24uH_7X7X3

PC91

EV@0.1u/50V_6

PL9

EV@0.24uH_7X7X3

PC121

EV@4.7u/25V_8

DCR=1.1m ohm

PC17

EV@0.1u/10V_4

PC78

EV@4.7u/25V_8

DCR=1.1m ohm

PC123

EV@0.1u/10V_4

+

PC108

EV@330u/2.5V_6X4.2

36

12

+

PC106

EV@33U/25V_6x4.5

+VGPU_CORE

VIN

PR168 *short_4

VGA_VCCSENSE[16]

VGA_VSSSENSE[16]

A A

5

Parallel

PR167 *short_4

PR164 *short_4

4

PR162 *short_4

N15S-GT(840M)

Location Value

PR161 CS32002FB29 PR20 CS32002FB29 PR15 CS22002FB19 PR17 CS31822FB16 PR18

3

QCI P/N QCI P/N

20K 20K 2K 18K

CS00002JB38 CH22706KB14PC100

0

2.7N

N15V-GM(820M)

Value CS32702FB16 CS27502FB11 CS00002JB38 CS26202FB17 CS21742FB00 CH25604KB18

27K

7.5K 0

6.2K

1.74K

5.6N

2

Size Document Number Rev

Date: Sheet of

N15V-GM

+VGPU_CORE Countinue current:A Peak current:43A OCP:64A FSW:300KHz L/L=0mV/A

Quanta Computer Inc.

PROJECT :

+VGPU_CORE(UP1642PQAG)

ZQX

36 43Wednesday, September 03, 2014

1

36 43Wednesday, September 03, 2014

1B

5

+1.05V_GFX[16,17,18] +1.5V_GFX[17,20]

+3V_GFX[16,17,18,19,29]

D D

4

3

2013/12/19 Change to converter

1.5VGFX_VIN

2

JP9

*short_3720

1 2

1

37

VIN

PR144

2014/06/12 modify

PR148 EV@100K/F_4

HWPG_1.5VGFX[17]

FBVDDQ_EN[17]

C C

PR241 EV@200K/F_4

NB671_VCC

PR150 *short_4

PR149 *short_4

PR146

*short_6

*0.1U/10V_4

PC84

*499K/F_4

1

EN PG LP# NC1 NC2 AGND

VIN

PU9 EV@NB671

VCC

11

PC89 EV@1u/6.3V_4

1.5VGFX_EN 1.5VGFX_SW

1.5VGFX_PG

13

4 3 5 6

14

PR145

*short_4

NB671_VCC

PR154 EV@1/F_6

1.5VGFX_BST 1.5VGFX_BST1

10

12

BST

VOUT

PGND

FB

SW1 SW2 SW3 SW4

EV@0.1u/50V_6

8 9 15 16 7 2

1.5VGFX_FB

PC96

PC94

EV@0.1u/16V_4

VREF=0.604V

PC85 EV@2200p/50V_6

PR19 *4.7_6

PC10 *680p/50V_6

PC75 EV@4.7u/25V_8

PC80 EV@4.7u/25V_8

PL8

EV@3.3uH_7X7X3

PR152 EV@82K/F_4

PR151 EV@64.9K/F_4

PC79 EV@4.7u/25V_8

PC81 EV@4.7u/25V_8

+1.5V_GFX

1 2

+1.5V_GFX

1.5 Volt +/- 5% TDC : 3.2A PEAK : 4.3A

JP10

*short_3720

PC118 EV@0.1u/50V_6

PC125 EV@22u/6.3V_8

PC124 EV@22u/6.3V_8

PC120 EV@22u/6.3V_8

QCI P/N

CS35492FB1454.9K/F_4

Width : 130mil

64.9K/F_4 CS36492FB17

VIN

PR55 EV@1M_4

B B

PR182

3V_MAIN_PWGD[18,36]

*short_4

PC135

*1u/10V_4

12

PR183 EV@100K_4

2

PQ44

1 3

EV@PDTC143TT

PR57 EV@1M_4

PR181 EV@22_8

3

2

PQ45 EV@2N7002K

1

+15V+1.05V_GFX

PR54 EV@1M_4

dGPU_D1

3

2

PQ22 EV@2N7002K

1

PC24 *2.2n/50V_4

+1.05V_S5

2

3

1

PQ20 EV@AO3404

+1.05V_GFX

+1.05V_GFX TDC : 1.72A PEAK : 2.29A Width : 80mil

VIN

PR43 EV@1M_4

A A

DGPU_PWR_EN[10]

5

PR36 *short_4

PC15

*1u/10V_4

12

PR32 EV@100K_4

2

PQ8

1 3

EV@PDTC143TT

4

PR42 EV@1M_4

PR44 EV@22_8

3

2

PQ12 EV@2N7002K

1

+15V+3V_GFX

PR41 EV@1M_4

dGPU_D

3

2

PQ13 EV@2N7002K

1

3

PC19 *2.2n/50V_4

2

+3VPCU

3

1

PQ9 EV@AO3404

+3V_GFX

+3V_GFX TDC : 0.26A PEAK : 0.35A Width : 20mil

2

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

PROJECT :

+1.5V_GFX/+1.05V_GFX/+3V_GFX

ZQX

37 43Wednesday, September 03, 2014

1

1B

1

2

3

4

5

6

7

8

+3V_S5

+3V

38

SDRAM

2.2K2.2K

AP2

SMB_PCH_CLK

AH1

A A

SMB_PCH_DAT

+3V

2N7002DW Level shift

CLK_SCLK CLK_SDATA

4.7K4.7K

Touch PAD

+3V

XDP

WLAN

Haswell ULT

+3V_S5

+3V

2N7002DW Level shift

4.7K 4.7K

WLAN_CLK_SCLK WLAN_CLK_SDATA

2.2K2.2K

AN1

SMB_ME0_CLK

AK1

SMB_ME0_DAT

B B

+3V_S5

*2.2K*2.2K

AU3

SMB_ME1_CLK

AH3

SMB_ME1_DAT

+3V_S5

*2N7002DW Level shift

+3V_GFX

4.7K4.7K

2ND_MBDATA

116

2ND_MBCLK

C C

SIO

ITE8380

115

110

MBCLK

111 MBDATA

+3VPCU

100

10K10K

100

+3V_GFX

2N7002DW Level shift

Battery

Charger

10K10K

dGPU

+3V

19 20

LIGHT_SCL LIGHT_SDA

4.7K 4.7K

Light sensor

+3V

D D

94

SCL_TO_EC

95

SDA_TO_EC

1

2

4.7K 4.7K

3

4

G-sensor

Gyro/Accelerometer

Ecompass

5

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

6

Date: Sheet of

7

PROJECT :

Block Diagram

ZQX

8

1B

38 43Wednesday, September 03, 2014

1B

1

2

3

4

5

6

7

8

VGA power up sequence

39

+3VPCU

A A

PCH +3V_GFX

dGPU_PWR_EN

MOSFET

VGA_VID

VIN

VGPU_EN

PWM

VGPU_PWRGD

EC_FB_CLAMP

+VGPU_CORE

VIN

OR Gate

FBVDDQ_EN

PWM

+1.5V_GFX

HWPG_1.5VGFX VGPU_PWRGD

+1.05V_S5

1.05V_GFX_EN

MOSFET +1.05V_GFX

DGPU_PWROK

EC

B B

VGA Reset

PCH

PLTRST#

DGPU_HOLD_RST#

PEX_RST timing

I/O 3.3V

PEX_RST

C C

D D

Trise >= 1uS Tfail <=500nS

PEGX_RST#

Power States

POWER PLANE

VIN +3V_RTC +3VPCU +5VPCU +15V

+5V_S5 +5V

+1.35VSUS +DDR_VTT_RUN LCDVCC +1.5V +1.05V +VCCIN +VGPU_CORE S0VGPU_ENExternal GPU POWER +3V_GFX External GPU POWER dGPU_PWR_EN S0 +1.5V_GFX +1.05V_GFX

VOLTAGE

+10V~+19V +3V~+3.3V +3.3V +5V +15V +3.3V +5V +5V +3.3V +1.35V +0.675V +3.3V +1.5V +1.05V variation variation +3.3V +1.5V +1.05V

DESCRIPTION

RTC POWER EC POWER USB CHARGE POWER CHARGE PUMP POWER LAN/BT POWER USB POWER HDD/SPK/HDMI POWER PCH/GPU/Peripheral component POWER+3V CPU/SODIMM/MD POWER SODIMM/MD Termination POWER LCD POWER MINI CARD/NEW CARD POWER PCH CORE VCCST POWER MAINON CPU CORE POWER

External GPU POWER External GPU POWER

CONTROL SIGNAL

ALWAYSMAIN POWER ALWAYS ALWAYS ALWAYS

S5_ON+3V_S5 S5_ON MAINON MAINON SUSON MAINON LVDS_VDDEN MAINON

VRON

FBVDDQ_EN

1.05V_GFX_ENS0S0

ACTIVE IN

ALWAYS ALWAYS ALWAYS ALWAYS ALWAYSALWAYS S0-S5 S0-S5 S0 S0 S0-S3 S0 S0 S0 S0 S0

Thermal Follow Chart

CPU CORE PWR

GPU NTC Thermal Protection

GPU CORE PWR

H_PROCHOT#

dGPU_OPP#

GPU_THAL#

H/W Throttling

GPIO12_ACIN

CPU NTC Thermal Protection

HSW ULT

SM-Bus1

EC

dGPU_ALT#

dGPU_OTP#

dGPU

PM_THRMTRIP# SYS_SHDN#

SM-Bus1

FAN1_PWM

FAN2_PWM

WIRE-AND

GPIO12 HW throttle over power protect

CPU FAN

GPU FAN

3V/5 V SYS PWR

Quanta Computer Inc.

PROJECT :

dGPU_OPP# EC notify HW throttle over power protect dGPU_ALT# for ADPS circuit to infrom EC NV dGPU VPS Alert dGPU_OTP# VGA thrmtrip# => inform EC over temperature protect

1

2

3

4

5

6

Size Document Number Rev

PWR Status & GPU PWR CRL & THRM

Date: Sheet of

7

PROJECT :

ZQX

39 43Wednesday, September 03, 2014

8

1B

5

Battery Mode

Support Deep Sx

MAINON

+5V

+3V

+1.05V

MAINON

9

8

21

22

21

?

17

21

11

10

12

21

8

18

19

23

24

28

27

25

24

12

2929

HWPG_VDDR

HWPG_1.05V

HWPG_1.5V

+5VPCU

3

+3VPCU

D D

3

S5 PWR

VIN

1

DDR VDDQ VR

S3

S5

C C

+3VPCU

3

1.5V VR

EN

+5V_S5

+3V_S5

S5_ON

+1.35V_SUS

DDR_VTTREF

+DDR_VTT_RUN

HWPG_VDDR

PG

DDR_PG_CTRL

MAINON

+0.75V_ON

SUSON

26

+1.5V

HWPG_1.5V

PG

RUN PWR

B B

A A

3

9

+5VPCU

+3VPCU

+1.05V_S5

PCH

MOS1 MOS2

MOS3

G

VIN

1

+1.05V_S5

VR

EN

S5_ON

MAINON

5

PG

+1.05V_S5

HWPG_1.05V

4

VIN

3V/5V

VR

EN2

1

VL

+15V

EN1

NBSWON#

3 3

+3VPCU +5VPCU

3V_LDO

2

PWR BTN

7

30

HWPG

+0.75V_ON

EC_PWROK

HWPG_1.05V_EC#

?

+1.05V

VIN

1

IMVP

0 ohm

+1.05V_VCCST

+VCCIN

33

VR

34

32a

32b

37

SVID

IMVP_PWRGD

PG

EN

VRON_CPU

VRON

CPU

4

3

+3VPCU

3

2

depend on A measure

+3.3V_DSW

result to implement

EC

VRON

MAINON

for B test

5a

13 14 15

S5_ON

SUSON

DSW_ON

6

DPWROK RSMRST#

SB_ACDC DNBSWON# SUSC# SUSB#

PCH_SUSACK# PCH_SUSPWARN# PCH_SLP_SUS#

34

16 20

31

35 38

IMVP_PWRGD

4

2

+3.3V_DSW

EN

Delay DSW power well 10ms

EC_PWROK PCH_CLK PLTRST#

5b

SYS_PWROK

1

CHARGER

DPWROK

RSMRST#

ACPRESENT PWRBTN# SLP_S4# SLP_S3# SUSACK SUSWRAN SLP_SUS#

APWROK PCH_PWROK

PLTRST#

SYS_PWROK

1

BAT-VVIN

Battery

DSW PWR

PCH

3

SUS PWR

ASW PWR

SPI PWR

HSIO PWR

PLL PWR

CORE PWR

SDIO PWR

HDA PWR

+3VPCU or +3.3V_DSW

40

+3VCC_S5

+1.05V

+3V_S5

+V1.05DX_MODPHY

+1.05V

+3V

+3V_S5

36

31

12

31

36

HWPG_1.05V_EC#

30a

HWPG+1ms

EC_PWROK

HWPG_1.05V

EC_PWROK

SYS_PWROK

10K ohm

VCCST_PWRGD_EN

2

32b30a

8172131

3

38

PLTRST#

CORE PWR

CPU

RESET#

PROCPWRGD

SVID

37

Size Document Number Rev

Date: Sheet of

VDDQ PWR

VCCST PWR

VR_ENVRON_CPU

SM_PG_CNTL1

DDR_PG_CTRL

22

VR_READY

VCCST_PWRGD

IMVP_PWRGD

VCCST_PWRGD_EN

32a

34

Quanta Computer Inc.

PROJECT :

Power Sequence

1

+VCCIN

+1.35V_SUS

+1.05V_VCCST

ZQX

40 43Wednesday, September 03, 2014

1B

󱬯󱬯󱬯󱬯󳴣󳴣󳴣󳴣󴞱󴞱󴞱󴞱defult

5

󴖤󴖤󴖤󴖤󳴣󳴣󳴣󳴣󴞱󴞱󴞱󴞱reserve

SYS_HWPG

1

D D

PWR

3V_LDO

1

EN!

EN2

PWRGD3V_LDO

3V/5V

TPS51225

Vin

S5_Vout

S3_Vout

VIN

C C

HWPG_1.05V

PWRGD

S5_ON

MAINON

Vin

+1.05V_S5

TPS51211

EN

Vout

HWPG_1.5VGFX

10

VGPU_PWRGD

9

+1.05V_S5

VIN

2

EC

B B

4

EC

4

+5VPCU

+3VPCU

AND Gate

PCH

MAIND

4

1.05V_GFX_EN

S5D

2

MAIND

4

S5D

2

MAIND

4

dGPU_PWR_EN

MDV1528Q

AO3404

+1.05V

+1.05V_GFX

3

+5V_S5

+5V

+3V_S5

+3V

+3V_GFX

EC

VIN

7

EC_FB_CLAMP

VGPU_PWRGD

9

VGPU_EN

7

VRON_CPU

VRON

2

VIN

PCH

Vin

VGPU_EN

VIN

OR Gate

PWRGD

CPU VCCIN

TPS51622 EN

Vin

FBVDDQ_EN

IMVP_PWRGD

Vout

PWRGD

VGPU Core

uP1642 EN

PWRGD

+1.5V_GFX

Vin

TPS51211

VGPU_PWRGD

Vout

HWPG_1.5VGFX

EN

+VCCIN

Vout

1

41

9

+VGPU_CORE

10

+1.5V_GFX

HWPG_VDDR

3

EC

DDR_VTTT_PG_CTRL

PCH

A A

EC

MAINON

4

+0.75V_ON

S5 EN

S3 EN

PWRGDSUSON

+1.35V_SUS

TPS51216

Vin

S5_Vout

S3_Vout

+1.35V_SUS DDR_VTTREF

+DDR_VTT_RUN

+3VPCU

Vin

MAINON

VIN

5

4

3

2

PWRGD

+1.5V

TPS54318

EN

HWPG_1.5V

Vout

+1.5V

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

PROJECT :

ULT PWR CONTROL

ZQX

41 43Wednesday, September 03, 2014

1

41 43Wednesday, September 03, 2014

1B

5

Version

Model

ZQX

D D

C C

B B

1. Add TPM function. (page26)

1A

2. Modify Audio L/R connection. (page28)

3. Add 100k on MIC2-VREFO to AGND for FAE suggest (page22)

4. update CN31 footprint and PN (page29)

5. Add 0805 0 ohm on +1.35V_SUS. (page5)

6. Modify VCCST_PWRGD_EN connection. (page5)

7. Add LPCPD# for TPM function (page7)

8. Change SPI damping R fform 15 to 0 ohm (page8)

9. change USB2.0 mapping port (page9)

10. change GPIO0~7 mapping port (page10)

10/24

11. Add pull high res for GPIO pin (page10)

12. unmunt page13 debug item (page13)

13. Change +DDR_VTT_RUN res from 34.8 to 36 ohm

14. Change Q63 type (page19)

15. Reserve +3V for TP_PWR (page23)

16. Add 1.6P cap on USB3.0 for RF (page28)

17. reserver 0 ohm for Light_sensor I2C (page28)

18. Modify M_A_CLK0,M_A_CLK1 connection. (page14)

19. Modify Block diagram (page1)

20. Change PC134,PC139 PN (page37)

21. Change TPM module to SLB9655 (page26)

22. Change G-sensor to BMA250E (page 29)

10/25

23. Add CN2 pin31 AGND

24. Add GPIO25 PU res (page10)

25. Change DGPU_SELECT# to PU10K (page2)

26. Modify BMA250E CSB pin for FAE suggestion. (page29)

27. Change USB3.0 mapping for WHCK (page9)

28. Change HDD conn type to FFC (page26)

10/28

29. Change C301,C9009 to 3.3p (page14)

30. Change Q5045 SW power to +3v (page29)

31. Modify LineL\R connection (page29)

10/29

32. Remove IOAC function (page24,page27,page30)

33. Add Mos for leakage (page27)

34. Change to LANCC and add PU res for FAE suggest (page24)

35. Change MDI0~MDI3 Res form 1 ohm to shortpad for FAE suggest (page24)

10/30

36. Swap GND and HP_JD# for FAE suggest (page28)

37. Add 10u Cap on +5v codec for FAE suggest (page22)

38. Modify USB port mapping (page10)

39. Swap DDR Data,DQS for layout request. (page14,15)

40. Swap Vram Data,DQS for layout request.(page21)

10/31

41. Add 100K on INT_AMIC-VREFO for FAE suggest (page22)

42. Reserve 0805 Res between +3V_MAIN and +3V_GFX for non GC6 function (page20)

43. SWAP PCH_SUSACK# and PCH_SUSPWARN# for EC request. (page30)

44. Change TP_INT_PCH port to GPIO83 (page10)

45. Add TPD_EN,TPD_INT# (page2,page29)

46. Modify EC GPIO pin, detail please see page30 mark (page30)

47. Mount PR183,unmount PR184 for power request (page37)

48. Change +1.35_SUS o ohm 0805 to1206

49. Add TP_RST# PU RES (page23)

50. Swap LSPK+,LSPK- 11/01 (page14,15)

51. Swap I2C port 0 and port1 (page10)

11/01

52. Swap USB2,3,7 +- for layout (page28)

53. Del TP_PWR 5V,Add pin31 connect to TP_PWR (page 23) 54 Change +3V to +WL_VDD Q5043 (page27)

55. Remove SMB_PCH_CLK and SMB_PCH_DAT (page30)

56. Reverse CN25 HDD(page26)

57. Modify screw hole type (page29,31)

11/04

58. Swap Rin2,Sleeve,HPL_C,HPR_C (page28)

59. Modify surge sch follow ZQSA (page24)

60. Modify CN23 gnd and surge component PN.

61. Delete shortpad for layout 11/05 (page24)

11/05

62. Use MOS replace U40, +1.05V_MODPHY (page11)

63. Delete SW6 for ACER request No system power cut off mechanism.(page31)

64. Change CN6 PN for ME request (page26)

65. Add powe net name SP_PLLVDD (page18)

11/06

66. Add TP, update EC PN (page30)

67. Modify surge sch (page24)

68. Modify SMB_PCH_CLK/DAT for EC (page30)

69. Add sensor_INT (page10,30)

70. Chage pr164 to 1.47k for power request (page36)

11/07

71. Change Hole2 type (page29)

72. Use GPIO46 to be G-sen_INT (page10,29)

73. I2C0 connect to Sensor HUB,I2C1 connect touchpanle and touchpad for Acer request 11/08 (page10,30)

11/08

74. Modify on 11/08, add touchpad i2c PU RES(page29)

75. Change power cap 22u PN from CH6221M9A03 toCH6221M9A00

76. Reserve 0ohm on Sensor_PCH I2C (page10)

77. Change L45,L46,L47 PN for EOL issue (page30)

78. Change D25,D49 to RB500V-40 (page22)

11/11

79. Change L15,L19 to CX300T10000, L20 to CX5PX181000 For EOD issue( page15,page17)

80. Change power net 3V_MAIN_PWGD PL 100k for power request (page37)

81. Mount Q26,R227 unmount R226 for leakage issue (page19)

82. Change PC79,PC147,PC132 PN for EOD issue (page35,page37)

83. Change Hole7 type (page29)

11/12

84. Change L20 footprint (page18)

11/14 85. update power +VCCIN(TPS51624) sch (page35)

86. Swap net for layout request (DDR Dim,keyboard and usb filter) (page9,page15,page23)

87. Delete Hole10 (page29)

88. Add 0ohm between LAND and GND (page24)

89. Add 0.1u cap on VIn (page31)

90. Delete 2 pcs 0.1u cap on VIN (page31)

91. Rename.

92. update titleblock; power description (page35)

11/15 93. Change power discription (page38)

94. Change PU4 PN for +1.5V_GFX for peak current to 4.3A(page38)

95. Change Rom PN to AKE3EFP0N07 (3.3V type) (page8)

96. Modify GC6 mount part (page17,19,20)

11/18

97. change PU4 PN to AL054318000 (page38)

4

CHANGE LIST

3

2

1

A A

PROJECT MODEL

DOC NO.

: PART NUMBER: DRAWING BY: REVISON:

5

ZQX APPROV ED BY:

4

DATE:

3

2

Quanta Computer Inc.

PROJECT :

ZQX

PROJECT :

ZQX

PROJECT :

Change li st-1

ZQX

42 43Wednesd ay, September 03, 2 014

1

Size Document Number Rev

Date: Sheet of

1A

5

Version

Model

1B

ZQX

D D

C C

Change Item Reason for Change

1. Add HDD protect function. example : U7 (page28)

2. Change Sensor board conn. (CN9) from 16 to 10 pin Remove Gyro/Accelerometer & eCompass function (page27)

3. Add DEVSLP0_R & HDD protect to CN13.4 (page21)

4. Add RTC charge circuit (page 8)

5. Q13.2 connect change from +3V+S5 to +3V (page26)

6. Q44.2 & 5 connect change from +3V to +TPVDD (page28)

7. R65 connect change from +3V to +3VPCU (page23)

8. R22 connect change from +3V to +5V (page23)

9. Connect SWAP PCIE CLKOUT 2 & 3 (page28)

10.TP_INT connect to CN7.5 & 6 (page23)

11. Add BLON pin (PCH_BLON_EC) to EC. (page23)

12. Change GPU from 29*29 to 23*23 Modify GPU circuit . Cahnge VRAM circuit.(page16 ~20)

1. Add C583 C585 C586 C588 C589 C692 C693 C694 C695

2A

Modify C8 from 0.1UF to 1000PF for EMI request

2. Change TPM circuit Add. C584 C587 D35 R645 R646 R647 R649 R758 TP121 TP122 & R648 Remove T28

3. Modify TP circuit Add. L23

4. Change +3VSUS circuit Add PQ66 PQ65 PQ64 P Q67 PR238 PR237 PR236 PR239 PR240 & PC195

5. Add R644 for NV

6. R631 & R630 change from 56 to 47 ohm for vender request

1. Add R651 & R645 for glitch of DDR_VTTT_PG_CTR

2B

Modify C8 from 0.1UF to 1000PF for EMI request

2. Change TPM circuit Add. C584 C587 D35 R645 R646 R647 R649 R758 TP121 TP122 & R648 Remove T28

3. Modify TP circuit Add. L23

4. Change +3VSUS circuit Add PQ66 PQ65 PQ64 P Q67 PR238 PR237 PR236 PR239 PR240 & PC195

5. Add R644 for NV

6. R631 & R630 change from 56 to 47 ohm for vender request

4

3

2

1

CHANGE LIST

1. Reserve for HDD protect in machine rotate condition

2. Remove sensors which aren't using on feature list

3. Reserve for HDD protect in machine rotate condition

4. Cause of placement and PE requirement, ZQX need to use small size of RTC(1220) with charging circuit

5. Remove IOAC function

6. Match touch pad support S5 power well

7. Ite load code time to long, cause backlight has flicker when AC in.

8. Touch screen voltgae change to 5V

9. PCIE clock request mapping issue

10. Reserve for touch screen interrupt control signal

11. Fn+F6 function

12. Acer feature change

B B

A A

PROJECT MODEL

DOC NO.

: PART NUMBER: DRAWING BY: REVISON:

5

ZRQ APPROVED BY:

4

DATE:

3

2

Quanta Computer Inc.

PROJECT :

ZQX

PROJECT :

ZQX

PROJECT :

Change li st-2

ZQX

43 43Thurs day, September 04, 2 014

1

Size Document Number Rev

Date: Sheet of

1A

Acer ASPIRE R3-471T Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual