Acer Aspire One AOD257 Schematics
1
2
3
4
5
6
7
8
01
ZE6 Block Diagram
A A
CK505
Graphics Interfaces
PCI-E
INT_LVDS
CRT
PCI-Express(Port1~4)
Pineview
DDRIII-SODIMM
B B
SATA - HDD
667 MT/s
P3
N570 1.66G: AJSLBXEVT05
N475 1.83G: AJSLBX5UT08
N455 1.66G: AJSLBX9VT05
SATA 0
P19
SATA
CPU
P4,5,6,7
DDR SYSTEM MEMORY
DMI
DMI(x2)
DMI
Tigerpoint
USB port*3
CCD
C C
Bluetooth module
3G
WLAN
USB-0,1,3
P17
USB-2
P14
USB-6
P15
USB-5
P20
USB-7
P20
USB 2.0 (Port0~7)
BATTERY
P11
Intel High Definit ion Audio
USB
RTC
IHDA
SB
P8,9,10,11,12,13
PN : AJSLGXX0T14
LPC
10.1 "Panel
Up to 1280*800 or 1366*768
CRT
PCIE-4
USB-5
PCIE-2
USB-7
PCIE-1
PCIE-3
P14
P14
3G/WiMAX
WLAN/WiMAX
LAN
RTL8105TA
Card Reader
RTS5209-GR
Charger
+3VPCU
+5VPCU
SIM Card
USB-4
P20
P20
P18
P20
+3V_S5
+5V_S5
+3VSUS
+3V
+5V
VCC_CORE
+1.5VSUS
+SMDDR_VREF
+0.75V_DDR_VTT
+1.5V
+1.05V
P21
+1.5V
Discharge
VCCGFX
P2
P27
P28
P29
P30
P31
P32
LPC
K/B Con.
EC
Touch Pad /B
Con.
4
NPCE791L
SPI Flash
P22P15 P15
5
Charger
P22
P24
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
6
Date: Sheet
7
PROJECT :
Block Diagram
Block Diagram
Block Diagram
ZE6
ZE6
ZE6
1B
1B
1B
of
135Friday, March 11, 2011
of
135Friday, March 11, 2011
of
135Friday, March 11, 2011
8
Audio Codec
D D
Int. SPK
CONN
1
Realtek ALC271X
Int. AMIC
CONN
2
MIC
Jack
Combo
Jack
P16
3
CLK GEN (CLK)
5
L21
L21
1 = Pin 43/44 as CPU_ITP
0 = Pin 43/44 as SRC_1
1 = Pin 11 as 33MHz
0= Pin 11 as 25MHz
5
L20
L20
C178
C178
4.7U/10V/8
4.7U/10V/8
VDD_CLK_3.3V
C185
C185
4.7U/10V/8
4.7U/10V/8
CLKUSB_48[8]
14M_ICH[11]
PCLK_ICH[10]
LCLK_EC[22]
PCLK_DEBUG[20]
C157
C157
C188
C188
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
0.1uF near every po wer pin
VDD_CLKIO_1.05V
C162
C162
C145
C145
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
0.1uF near every po wer pin
SMBDT1[3,20]
SMBCK1[3,20]
CLK_BSEL1_FSB FSB
R217 1K_4R217 1K_4
R218 33/J_4R218 33/J_4
R191 33/J_4R191 33/J_4
CLK_BSEL2_FSC
R190 10K_4R190 10K_4
R205 22/J_4R205 22/J_4
R204 22/J_4R204 22/J_4
R219 33/J_4R219 33/J_4
FSC FSB Frequency
0 0 133MHz
0 1 166MHz
1 1 200MHz
1 0 100MHz
C163
C163
.1U/10V_4
.1U/10V_4
C171
C171
.1U/10V_4
.1U/10V_4
+3V
PBY160808T-301Y-N/2A/300ohm_6
VDD_IO can be ranging
from 1.05V to 3.3V.
+1.05V
R209 0_6R209 0_6
Place close to L18
CL=20p
PBY160808T-301Y-N/2A/300ohm_6
PBY160808T-301Y-N/2A/300ohm_6
PBY160808T-301Y-N/2A/300ohm_6
C154
C154
33P/50V_4
33P/50V_4
CG_XIN
21
Y2
14.318MHZY214.318MHZ
C152
C152
33P/50V_4
33P/50V_4
CG_XOUT
Place close to L8
D D
C C
<Layout note>
Crystal place within 500mil of CK505
Follow Silegro schematic
B B
R206 *10K/J_4R206 *10K/J_4
+3V
R207 10K/J_4R207 10K/J_4
A A
0221 : follow vendor's suggestion, change from 10K to 4.7K
R208 4.7K/J_4R208 4.7K/J_4
+3V
R197 *10K/J_4R197 *10K/J_4
ITP_EN
pin 10 has internal pull down resistor.
33M_SEL
4
U9
U9
5
VDD_REF_3.3
9
VDD_PCI_3.3
14
VDD_48M_3.3
30
VDD_SRC_IO_1.05
35
VDD_SRC_IO_1.05
48
VDD_CPU_IO_1.05
1
NC
2
NC
13
NC
54
NC
CG_XOUT
3
XTAL_OUT
CG_XIN
4
XTAL_IN
SMBDT1
7
SDA
SMBCK1
8
SCL
15
USB48_1/FSB
USB_48M
17
USB48_2
FSC
6
REF/FSC
ITP_EN
10
PCIF/ITP_EN
33M_SEL
11
25MHz/PCI_2/SEL_33MHz
12
VSS_PCI
16
VSS_48M
22
VSS_LCD
24
VSS_SATA
39
VSS_SRC
51
VSS_CPU
56
VSS_REF
57
Thermal Pad
SLG8LV631V
SLG8LV631V
no connect FSA to CPU, due to there is no FSA PIN for CPU.
need to check check how to handle it in CPU CLK_BESEL0
CPU_BSEL1[4]
CPU_BSEL2[4]
+1.05V
+1.05V
R215 *1K_4R215 *1K_4
CLK_BSEL1_FSB
R214 0_4R214 0_4
R216 *0_4R216 *0_4
R188 *1K_4R188 *1K_4
CLK_BSEL2_FSC
R187 0_4R187 0_4
R189 *0_4R189 *0_4
4
VDD_CORE_1.5
VDD_CORE_1.5
PCI_STOP#
CPU_STOP#
CPU_0
CPU_0#
CPU_1
CPU_1#
SRC_1/CPU_ITP
SRC_1/CPU_ITP#
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
SRC_4#
SRC_5
SRC_5#
SRC_6
SRC_6#
DOT96/SRC7
DOT96#/SRC7#
LCD_CLK
LCD_CLK#
SATA#
CLKREQ_A#
CLKREQ_B#
CLKREQ_C#
CKPWRGD/PD#
3
2
1
02
VDD_CLK_1.5V
C191
C191
C146
C146
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
0.1uF near every power pin
23
45
PM_STPPCI#_R
PM_STPCPU#_R
DREFCLK
DREFCLK#
CLKREQ_LAN#_R
CLKREQ_MPC#_R
CLKREQ_MNC#_R
R164 *0/J_4R164 *0/J_4
R157 *0/short_J_4R157 *0/short_J_4
R141 475/F_4R141 475/F_4
R142 475/F_4R142 475/F_4
R201 475/F_4R201 475/F_4
36
42
53
52
50
49
44
43
41
40
38
37
34
33
32
31
28
27
18
19
20
21
26
SATA
25
47
46
29
55
R212 2.2/J_6R212 2.2/J_6
1 2
C195
C195
<20100819_FAE Poyueh> Add 2.2ohm resis tor for noise suppr ess
4.7U/10V/8
4.7U/10V/8
Place close to L 13
1/19 : 439549_439549_CorbettPark_Schm_Rev0.5: If this pin is
used as PCI_STOP#, it is required to provide a 10-k pull-up to
Vcc3_3. It is not recommended to connect this signal to the
Tiger Point(NM10) as it may cause unexpected system behavior.
PM_STPPCI# [11]
PM_STPCPU# [11]
CLK_CPU_BCLK [4]
CLK_CPU_BCLK# [4]
CLK_MCH_BCLK [4]
CLK_MCH_BCLK# [4]
CLK_PCIE_LANP [18]
CLK_PCIE_LANN [18]
PE4CLK+ [20]
PE4CLK- [20]
PE2CLK+ [20]
PE2CLK- [20]
CLK_PCIE_DMIP [4]
CLK_PCIE_DMIN [4]
CLK_CARDREADER [21]
CLK_CARDREADER# [21]
CLK_PCIE_ICH [8]
CLK_PCIE_ICH# [8]
DREFCLK [4]
DREFCLK# [4]
DREFSSCLK [4]
DREFSSCLK# [4]
CLK_PCIE_SATA [9]
CLK_PCIE_SATA# [9]
CLKREQ_LAN# [18]
CLKREQ_WLAN# [20]
CLKREQ_CARD# [21]
VR_PWRGD_CK410 [11]
To CPU (Core CLK)
To CPU (Host CLK)
To Mini Card 2 (3G/Wimax)
<20100819> Add 475 ohm for current leakage
VR PWRGD
VR_PWRGD_CK410#[23,26]
1
<20090721(B2A)>
Change Q3,Q5,Q6 from BAM700200F6 to BAM70020002 (with ESD protection function)
3
2
2N7002KQ92N7002K
Q9
R146 *10K_4R146 *10K_4
R147 10K_4R147 10K_4
3
VR_PWRGD_CK410
C182
C182
.1U/10V_4
.1U/10V_4
+1.5V
L22
L22
PBY160808T-301Y-N/2A/300ohm_6
PBY160808T-301Y-N/2A/300ohm_6
To SB
166 MHz
166 MHz
To LAN (LAN)
100 MHz
100 MHz
100 MHzTo Mini Card 1 (WLAN)
To CPU (DMI CLK) 100 MHz
To Card Reader
100 MHz
To SB (DMI CLK) 100 MHz
96 MHzTo CPU (PLL CLK)
To CPU (DPLSS CLK) 100 MHz
Control SRC_1
Control SRC_3
Control SRC_5
+3V
VR_PWRGD_CK410 [11]
100 MHzTo SB (SATA CLK)
Register B5b6 for CLKREQ_A#
0 = SRC1, 1=SRC2
Register B5b4 for CLKREQ_B#
0 = SRC3, 1=SRC4
Register B5b3 for CLKREQ_C#
0 = SRC5, 1=SRC6
2
PM_STPPCI#_R
R163 10K/J_4R163 10K/J_4
PM_STPCPU#
R153 10K/J_4R153 10K/J_4
CLKREQ_MPC#_R
R149 10K/J_4R149 10K/J_4
CLKREQ_MNC#_R
R202 10K/J_4R202 10K/J_4
CLKREQ_LAN#_R
R148 10K/J_4R148 10K/J_4
USB_48M
CFG input hardware strapping to allocate PLL assignment.
LOW = Both CPU and SRC clock drive from PLL3
HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
Contains 100kȍ pull-down resistor.
<EMI>
USB_48M
ITP_EN
FSB
FSC
33M_SEL
&ORFN*HQ,&
PCLK_SMB[11,20]
PDAT_SMB[11,20]
3
3
Size D ocume nt Number Rev
Size D ocume nt Number Rev
Size D ocume nt Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R374 20K/F_4R374 20K/F_4
C190 *10P/50V_4C190 *10P/50V_4
C192 *10P/50V_4C192 *10P/50V_4
C189 *10P/50V_4C189 *10P/50V_4
C176 *10P/50V_4C176 *10P/50V_4
C172 *10P/50V_4C172 *10P/50V_4
+3V
R203
R203
2.2K_4
2.2K_4
2
SMBCK1
1
2N7002K
2N7002K
+3V
Q16
Q16
R186
R186
2.2K_4
2.2K_4
2
SMBDT1
1
2N7002K
2N7002K
Q15
Q15
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
1
ZE6
ZE6
ZE6
235Friday, March 11, 2011
235Friday, March 11, 2011
235Friday, March 11, 2011
+3V
SMBCK1 [3,20]
SMBDT1 [3,20]
of
of
of
1C
1C
1C
5
DDR_STD(DDR)
M_A_A[14:0][5]
D D
M_A_BS0[5]
M_A_BS1[5]
M_A_BS2[5]
M_CS#0[5]
M_CS#1[5]
M_CLK0[5]
M_CLK0#[5]
M_CLK1[5]
M_CLK1#[5]
M_CKE0[5]
M_CKE1[5]
M_A_CAS#[5]
M_A_RAS#[5]
R130 10K_4R130 10K_4
R129 10K_4R129 10K_4
C C
B B
M_A_W E#[5]
SMBCK1[2,20]
SMBDT1[2,20]
M_ODT 0[5]
M_ODT 1[5]
M_A_DM[7:0][5]
M_A_DQS[7:0][5]
M_A_DQS#[7:0][5]
Place these Caps near So-Dimm0.
+1.5VSUS
C115
C115
4.7U/6.3V_6
4.7U/6.3V_6
A A
C112
C112
4.7U/6.3V_6
4.7U/6.3V_6
+3V
C129
C129
2.2u/6.3V_6
2.2u/6.3V_6
C116
C116
4.7U/6.3V_6
4.7U/6.3V_6
C126
C126
4.7U/6.3V_6
4.7U/6.3V_6
C123
C123
0.1u/10V_4
0.1u/10V_4
5
C125
C125
4.7U/6.3V_6
4.7U/6.3V_6
C124
C124
4.7U/6.3V_6
4.7U/6.3V_6
C113
C113
0.1u/10V_4
0.1u/10V_4
+0.75V_DDR_VTT
C118
C118
0.1u/10V_4
0.1u/10V_4
C114
C114
0.1u/10V_4
0.1u/10V_4
C117
C117
0.1u/10V_4
0.1u/10V_4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
DIMM0_SA0
DIMM0_SA1
SMBCK1
SMBDT1
M_A_DM0
M_A_DM1
M_A_DM3
M_A_DM2
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS3
M_A_DQS2
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#3
M_A_DQS#2
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
C111
C111
0.1u/10V_4
0.1u/10V_4
C127
C127
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
C128
C128
0.1u/10V_4
0.1u/10V_4
C122
C122
107
119
109
108
114
121
101
103
102
104
115
110
113
197
201
202
200
116
120
136
153
170
187
137
154
171
188
135
152
169
186
JDIM1A
JDIM1A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
A10/AP
84
A11
83
A12/BC#
A13
80
A14
78
A15
BA0
BA1
79
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
73
CKE0
74
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
DM4
DM5
DM6
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
DQS4
DQS5
DQS6
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDR3-DIMM0_H=4_RVS
DDR3-DIMM0_H=4_RVS
+SMDDR_VREF_DIMM
+
+
C110
C110
C108
C108
220u/2V_7343
220u/2V_7343
0.1u/10V_4
0.1u/10V_4
C119
C119
0.1u/10V_4
0.1u/10V_4
4
(204P)
(204P)
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
2.2u/6.3V_6
2.2u/6.3V_6
4
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
C107
C107
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
+SMDDR_VREF_DQ0
C132
C132
0.1u/10V_4
0.1u/10V_4
M_A_DQ7
M_A_DQ6
M_A_DQ3
M_A_DQ2
M_A_DQ0
M_A_DQ5
M_A_DQ1
M_A_DQ4
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ24
M_A_DQ25
M_A_DQ27
M_A_DQ26
M_A_DQ29
M_A_DQ28
M_A_DQ30
M_A_DQ31
M_A_DQ18
M_A_DQ23
M_A_DQ22
M_A_DQ19
M_A_DQ21
M_A_DQ17
M_A_DQ16
M_A_DQ20
M_A_DQ33
M_A_DQ32
M_A_DQ35
M_A_DQ34
M_A_DQ37
M_A_DQ36
M_A_DQ38
M_A_DQ39
M_A_DQ44
M_A_DQ45
M_A_DQ42
M_A_DQ46
M_A_DQ40
M_A_DQ41
M_A_DQ47
M_A_DQ43
M_A_DQ48
M_A_DQ49
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ61
M_A_DQ56
M_A_DQ63
M_A_DQ58
M_A_DQ57
M_A_DQ60
M_A_DQ59
M_A_DQ62
C131
C131
2.2u/6.3V_6
2.2u/6.3V_6
3
M_A_DQ[63:0] [5]
+SMDDR_VREF
3
R116
R116
1K/F_4
1K/F_4
R115 *0_6R115 *0_6
R117
R117
1K/F_4
1K/F_4
DDR3_DRAMRST#[5]
+1.5VSUS
+SMDDR_VREF_DIMM
2
+1.5VSUS
2.48A
+3V
R119 *10K_4R119 *10K_4
+3V
PM_EXTTS#0[4]
+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM
+SMDDR_VREF_DIMM
C109
C109
470p/50V_4
470p/50V_4
+SMDDR_VREF
2
JDIM1B
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM0_H=4_RVS
DDR3-DIMM0_H=4_RVS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
(204P)
(204P)
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
VTT1
VTT2
GND
GND
R138
R138
1K/F_4
1K/F_4
R140 *0_6R140 *0_6
R139
R139
1K/F_4
1K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
DDRIII SO-DIMM-0
DDRIII SO-DIMM-0
DDRIII SO-DIMM-0
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
205
206
+1.5VSUS
1
+0.75V_DDR_VTT
+SMDDR_VREF_DQ0
ZE6
ZE6
ZE6
335Friday, March 11, 2011
335Friday, March 11, 2011
335Friday, March 11, 2011
1
1A
1A
1A
of
of
of
5
PINEVIEW_M
PINEVIEW_M
U21C
U21C
D12
XDP_RSVD_00
A7
XDP_RSVD_01
D6
XDP_RSVD_02
C5
XDP_RSVD_03
C7
XDP_RSVD_04
T34T34
C6
XDP_RSVD_05
D8
XDP_RSVD_06
B7
XDP_RSVD_07
A9
R292 1K/F_4R292 1K/F_4
D D
C C
DMI_TXP0[8]
DMI_TXN0[8]
DMI_TXP1[8]
DMI_TXN1[8]
CLK_PCIE_DMIN[2]
CLK_PCIE_DMIP[2]
B B
XDP_RSVD_08
D9
XDP_RSVD_09
C8
XDP_RSVD_10
T29T29
B8
XDP_RSVD_11
C10
XDP_RSVD_12
D10
XDP_RSVD_13
B11
XDP_RSVD_14
B10
XDP_RSVD_15
B12
XDP_RSVD_16
T40T40
C11
XDP_RSVD_17
L11
RSVD
AA7
RSVD_TP
AA6
RSVD_TP
R5
RSVD_TP
R6
RSVD_TP
AA21
RSVD_TP
W21
RSVD_TP
T21
RSVD_TP
V21
RSVD_TP
Pineview-M 1.66G
Pineview-M 1.66G
U21A
U21A
F3
DMI_RXP_0
F2
DMI_RXN_0
H4
DMI_RXP_1
G3
DMI_RXN_1
N7
EXP_CLKINN
N6
EXP_CLKINP
R10
RSVD
R9
RSVD
N10
RSVD
N9
RSVD
K2
RSVD_K2
J1
RSVD_J1
M4
RSVD_M4
L3
RSVD_L3
Pineview-M 1.66G
Pineview-M 1.66G
REV = 1.1
REV = 1.1
VGA
VGA
DPL_REFSSCLKINP
DPL_REFSSCLKINN
PM_EXTTS#_1/DPRSLPVR
MISC
MISC
3 OF 6
3 OF 6
PINEVIEW_M
PINEVIEW_M
REV = 1.1
REV = 1.1
DMI
DMI
1 OF 6
1 OF 6
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
CRT_DDC_DATA
CRT_DDC_CLK
DAC_IREF
DPL_REFCLKINP
DPL_REFCLKINN
PM_EXTTS#_0
PWROK
RSTINB
HPL_CLKINN
HPL_CLKINP
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS
RSVD_TP
RSVD_TP
RSVD_K3
RSVD_M2
RSVD_N2
RSVD_L2
M30
M29
N31
P30
P29
N30
L31
L30
P28
Y30
Y29
AA30
AA31
K29
J30
L5
AA3
W8
W9
4
<Layout note>
Place within 750mil from CPU
VGA_HSYNC_R
R81 15/F_4R81 15/F_4
VGA_VSYNC_R
R80 15/F_4R80 15/F_4
CRT_R
CRT_G
CRT_B
VGA_IREF
G2
G1
H3
J2
L10
L9
L8
N11
P11
K3
L2
M2
N2
CRT_SDA [14]
R96 665/F_4R96 665/F_4
Close pin < 500mil
R79 *0/short_4R79 *0/short_4
<Layout note>
Place within 500mil from CPU pin
EXP_COMP
R91 49.9/F_4R91 49.9/F_4
EXP_RBIAS
R310 750/F_4R310 750/F_4
<Layout note>
Place within 500mil from CPU pin
PM_EXTTS#0
R77 10K_4R77 10K_4
CRT_R [14]
CRT_G [14]
CRT_B [14]
CRT_SCL [14]
CLK_MCH_BCLK# [2]
CLK_MCH_BCLK [2]
3
CRT_HSYNC [14]
CRT_VSYNC [14]
<Layout note>
Close to pin within 250mil
CRT_R CRT_G
R94
R94
150/F_4
150/F_4
<Layout note>
Close to pin within 500mil
DREFCLK [2]
DREFCLK# [2]
DREFSSCLK [2]
DREFSSCLK# [2]
PM_DPRSLPVR [11,26]
PM_EXTTS#0 [3]
IMVP_PWRGD [11,23,26]
PLTRST# [11,18,20,21,22,23]
IMVP_PWRGD
LBKLT_EN
R93
R93
100K_4
100K_4
DMI_RXP0 [8]
DMI_RXN0 [8]
DMI_RXP1 [8]
DMI_RXN1 [8]
CRT_B
R92
R92
R95
R95
150/F_4
150/F_4
150/F_4
150/F_4
<20090610(A1A)_Sighting Report Rev002_Number:3359187>
Avoid a glitch during system power up
LCD Panel Backlight
+3V
C82 0.1u/10V_4C82 0.1u/10V_4
U5
TC7SH0 8FUU5TC7SH0 8FU
2
1
3 5
R99 *0_4R99 *0_4
<Layout note>
PLACE TCK/TDI/TMS TERMINATION NEAR CPU
INT_TXLCLKN[14]
INT_TXLCLKP[14]
INT_TXLOUTN0[14]
INT_TXLOUTP 0[14]
INT_TXLOUTN1[14]
INT_TXLOUTP 1[14]
INT_TXLOUTN2[14]
INT_TXLOUTP 2[14]
INT_LVDS_PWM[14]
+3V
LVDS_CLK[14]
LVDS_DATA[14]
INT_LVDS_DIGON[14]
4
XDP PU
XDP_TMS
R63 51/J_4R63 51/J_4
XDP_TDI
R62 51/J_4R62 51/J_4
H_PREQ#
XDP_TCK
XDP_TRST#
XDP_BPM#5 : Length<200mil
R294 51/J_4R294 51/J_4
R293 51/J_4R293 51/J_4
R61 51/J_4R61 51/J_4
+3V
R90 2.37K/F_4R90 2.37K/F_4
LBKLT_EN
R89 *2.2K/J_4R89 *2.2K/J_4
R88 *2.2K/J_4R88 *2.2K/J_4
INT_LVDS_BLON [14]
+1.05V
+3V
U25
U26
R23
R24
N26
N27
R26
R27
LIBG
R22
J28
N22
N23
L27
L26
LCTLA_CLK
L23
LCTLB_ DATA
K25
K23
K24
H26
T8T8
G11
T39T39
E15
T13T13
G13
T10T10
F13
T33T33
B18
T41T41
B20
T36T36
C20
T37T37
B21
T9T9
G5
XDP_TDI
D14
T35T35
D13
XDP_TCK
B14
XDP_TMS
C14
XDP_TRST#
C16
H_THERMDA
D30
H_THERMDC
E30
C30
D31
R74 2.2K/J_4R74 2.2K/J_4
R69 2.2K/J_4R69 2.2K/J_4
<EMI>
C52
C52
*220P/50V_4
*220P/50V_4
U21D
U21D
LVD_A_CLKM
LVD_A_CLKP
LVD_A_DATAM_0
LVD_A_DATAP_0
LVD_A_DATAM_1
LVD_A_DATAP_1
LVD_A_DATAM_2
LVD_A_DATAP_2
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_CLK
LDDC_CLK
LDDC_DATA
LVDD_EN
BPM_1B_0
BPM_1B_1
BPM_1B_2
BPM_1B_3
BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD
RSVD
TDI
TDO
TCK
TMS
TRST_B
THRMDA_1
THRMDC_1
RSVD_C30
RSVD_D31
Pineview-M 1.66G
Pineview-M 1.66G
LVDS_CLK
LVDS_DATA
C61
C61
*220P/50V_4
*220P/50V_4
2
PINEVIEW_M
PINEVIEW_M
REV = 1.1
REV = 1.1
ICH
ICH
LVDS
LVDS
CPU
CPU
4 OF 6
4 OF 6
<Layout note>
Place within 500mil from CPU pin and 5mil spacing
Max 500mil Near CPU pin
R51
R51
976/F_4
976/F_4
R55
R55
3.32K/F_4
3.32K/F_4
SMI_B
A20M_B
FERR_B
LINT00
LINT10
IGNNE_B
STPCLK_B
DPRSTP_B
DPSLP_B
INIT_B
PRDY_B
PREQ_B
THERMTRIP_B
PROCHOT_B
CPUPWRGOOD
GTLREF
RSVD
RSVD
BCLKN
BCLKP
BSEL_0
BSEL_1
BSEL_2
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
EXTBGREF
C36
C36
1U/6.3V_4
1U/6.3V_4
E7
H7
H6
F10
F11
E5
F8
G6
G10
G8
T30T30
E11
H_PREQ#
F15
H_THRMTRIP#
E13
R295 68_4R295 68_4
C18
H_PWRGD
W1
H_GTLREF
A13
H27
VSS
L6
E17
H10
J10
CPU_BSEL0
K5
CPU_BSEL1
H5
CPU_BSEL2
K6
H30
H29
H28
G30
G29
F29
E29
L7
D20
H13
D18
K9
D19
H_EXBGREF
K7
1
H_SMI# [9]
H_A20M# [9]
H_FERR# [9]
H_INTR [9]
H_NMI [9]
H_IGNNE# [9]
H_STPCLK# [9]
ICH_DPRSTP# [11,26]
H_DPSLP# [11]
H_INIT# [ 9]
<20090511(A1A)_Checklist Rev0.7>
+1.05V
PROCHOT_B:68ohm±5% pull-up to Vcc1_05
(VCCP) at both CPU side and Intel MVP
H_PROCHOT# [26]
H_PWRGD [11]
CPU_BSEL1 [2]
CPU_BSEL2 [2]
VID0 [26]
VID1 [26]
VID2 [26]
VID3 [26]
VID4 [26]
VID5 [26]
VID6 [26]
CLK GEN no FSA pin for CPU_BSEL0,
so just pull high to fix it.
CPU_BSEL0
R65 470/J_4R65 470/J_4
CPU_BSEL1
R66 470/J_4R66 470/J_4
CPU_BSEL2
R64 470/J_4R64 470/J_4
<Layout note>
Place within 500mil from CPU pin
+1.05V+1.05V
R280
R280
1K/F_4
1K/F_4
1D: No Stuff C8007 (CRB v1.0)
H_GTLREFH_EXBGREF
C251
C251
R281
R281
1U/6.3V_4
1U/6.3V_4
2K/F_4
2K/F_4
CLK_CPU_BCLK# [2]
CLK_CPU_BCLK [2]
+1.05V
C257
C257
*220P/50V_4
*220P/50V_4
04
CPU FAN CTRL(THM)
&387KHUPDOPRQLWRU7+0
8/11 B-test : for EMI
C130
C130
*220p/50V_6
*220p/50V_6
FAN_PWM_B
5
FAN_SIG
CPUFAN#
6
FAN_SIG [22]
2ND_MBCLK[22]
2ND_MBDATA[22]
THERM_ALERT#[11,22]
R59 *0_4R59 *0_4
ALERT#:pull up at SB side
FAN_ON#
C121
C121
*220p/50V_6
*220p/50V_6
+3V
R137
R137
R133
R133
+3V
R128
R128
10K_4
10K_4
Q6
2
MMBT3904Q6MMBT3904
1 3
2
1 3
10K_4
10K_4
Q8
MMBT3904Q8MMBT3904
+3V
+5V
10K_4
10K_4
FAN_PWM_CNFAN_PWM_E
R126
R126
10K_4
10K_4
FAN_SIG
+5V
CN16
CN16
345
2
1
FAN
FAN
4
FAN_PWM_CN
A A
FAN_ON#
R124 10K_4R124 10K_4
CPUFAN#[22]
R76
R76
10K_4
10K_4
THERM_ALERT#_R
3
+3V
+3V
R52
R52
U4
U4
*10K_4
*10K_4
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
IC CTRL(8P) EMC1412-1-ACZL-TR
IC CTRL(8P) EMC1412-1-ACZL-TR
SMSC ADDRESS: 98H
SMSC : AL001412003
R75 *0/short_4R75 *0/short_4
1
VCC
2
DXP
3
DXN
5
GND
C54 0.1u/10V_4C54 0.1u/10V_4
H_THERMDA
C40
C40
2200p/50V_4
2200p/50V_4
H_THERMDC
<Layout Note>
Routing 10:10 mils and
away from noise source
with ground gard
125 Degree Protection(CPU)
IMVP_PWRGD
+1.05V
CPU
H_THRMTRIP#
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
R60
R60
56_4
56_4
Friday, March 11, 2011
Friday, March 11, 2011
Friday, March 11, 2011
+1.05V
3
Q2
2N7002KQ22N7002K
2
<20090721(B2A)>
Change Q7 from BAM700200F6
to BAM70020002 (with ESD
protection function)
1
R47
R47
1K_4
1K_4
2
Q1
1 3
MMBT3904Q1MMBT3904
R67 *0_4R67 *0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Pineview DMI/Display
Pineview DMI/Display
Pineview DMI/Display
1
SYS_SHDN# [25,26,30]
PM_THRMTRIP# [9]
ZE6
ZE6
ZE6
Tigerpoint
1B
1B
1B
354
354
354
5
D D
C C
DDR3 PWROK
SUSON[22,23,27,29]
HWPG_1.5V[22,23,27]
B B
A A
+3V_S5
53
1
4
2
U7
R121
R121
TC7SH08FUU7TC7SH08FU
12.1K/F_4
12.1K/F_4
DDRAM_PWROK
R120
R120
10K_4
10K_4
DDR3_DRAMRST#[3]
<Layout note>
Close to DDR_VREF pin
+SMDDR_VREF
<EMI>
DG 2.1 : It is strongly recommended that the SODIMM VREF motherboard traces, going from
their VREF resistor dividers to their specified SODIMM VREF pins, be ground referenced
on the motherboard where ever possible to help minimize risks of any possible noise
being coupled onto VREF. If they can't be referenced to ground we recommend placing
a site for a 0603 capacitor near the VREF divider. These 0603 capacitor sites must be
connected on one end to the non ground reference plane the VREF trace is referenced
5
to and the other end must be connected to ground.
R352 *0_4R352 *0_4
C297
C297
*1000p/50V_4
*1000p/50V_4
<Layout note>
Close to pin
+1.5VSUS
4
M_A_A[14..0][3]
M_A_WE#[3]
M_A_CAS#[3]
M_A_RAS#[3]
M_A_BS0[3]
M_A_BS1[3]
M_A_BS2[3]
M_CS#0[3]
M_CS#1[3]
M_CKE0[3]
M_CKE1[3]
M_ODT0[3]
M_ODT1[3]
M_CLK0[3]
M_CLK0#[3]
M_CLK1[3]
M_CLK1#[3]
R348 80.6/F_4R348 80.6/F_4
R349 80.6/F_4R349 80.6/F_4
+1.5VSUS
R351
R351
1K/F_4
1K/F_4
DDR_VREF
R353
R353
1K/F_4
1K/F_4
4
+1.5VSUS
R350
R350
*10K_4
*10K_4
C294 0.1U/10V_4C294 0.1U/10V_4
C295 0.01U/25V_4C295 0.01U/25V_4
C296
C296
0.1u/16V_6
0.1u/16V_6
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_WE#
M_A_CAS#
M_A_RAS#
M_A_BS0
M_A_BS1
M_A_BS2
M_CS#0
M_CS#1
M_CKE0
M_CKE1
M_ODT0
M_ODT1
M_CLK0
M_CLK0#
M_CLK1
M_CLK1#
DDRAM_PWROK
DDR_VREF
SM_RCOMP
SM_RCOMP#
AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10
AK22
AJ22
AK21
AJ20
AH20
AK11
AH22
AK25
AJ21
AJ25
AH10
AK10
AK24
AH26
AH24
AK27
AG15
AF15
AD13
AC13
AC15
AD15
AF13
AG13
AD17
AC17
AB15
AB17
AB11
AB13
AL28
AK28
AJ26
AK29
AH9
AJ8
AB4
AK8
U21B
U21B
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
DDR_A_WEB
DDR_A_CASB
DDR_A_RASB
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4
RSVD_AD17
RSVD_AC17
RSVD_AB15
RSVD_AB17
VSS
RSVD
RSVD_TP
RSVD_TP
DDR_VREF
DDR_RPD
DDR_RPU
RSVD
Pineview-M 1.66G
Pineview-M 1.66G
DDR_A
DDR_A
3
3
PINEVIEW_M
PINEVIEW_M
REV = 1.1
REV = 1.1
2 OF 6
2 OF 6
DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DM_0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DM_1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DM_2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DM_3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DM_4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DM_5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DM_6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DM_7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
AD3
AD2
AD4
AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3
AB8
AD7
AA9
AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6
AD8
AD10
AE8
AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10
AK5
AK3
AJ3
AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6
AG22
AG21
AD19
AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21
AE26
AG27
AJ27
AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27
AE30
AF29
AF30
AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28
AB27
AA27
AB26
AA24
AB25
W24
W22
AB24
AB23
AA23
W27
M_A_DQS0
M_A_DQS#0
M_A_DM0
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQS1
M_A_DQS#1
M_A_DM1
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQS2
M_A_DQS#2
M_A_DM2
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQS3
M_A_DQS#3
M_A_DM3
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQS4
M_A_DQS#4
M_A_DM4
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQS5
M_A_DQS#5
M_A_DM5
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQS6
M_A_DQS#6
M_A_DM6
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQS7
M_A_DQS#7
M_A_DM7
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
2
1
05
M_A_DQ[63..0] [3]
M_A_DM[7..0] [3]
M_A_DQS[7..0] [3]
M_A_DQS#[7..0] [3]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, March 11, 2011
Date: Sheet of
Friday, March 11, 2011
Date: Sheet of
Friday, March 11, 2011
2
Date: Sheet
PROJECT :
Pineview DDR
Pineview DDR
Pineview DDR
ZE6
ZE6
ZE6
1
1B
1B
1B
of
355
355
355
1
A A
B B
C C
D D
1
<Layout note>
Close to pin
+1.5VSUS
<Layout note>
VCCA_DDR and VCCACK_DDR rails can be
on the same source but make sure the
plane shapes are split near Pineview-M
to avoid noise coupling
+1.8V
2
R112 *0/short_6R112 *0/s hor t_6
R98
R98
0.2A/600ohm_6
0.2A/600ohm_6
2
C106
C106
22U/6.3V_8
22U/6.3V_8
VCC1.8_VCCACRTDAC
C79
C79
1u/6.3V_4
1u/6.3V_4
C102
C102
1U/6.3V_4
1U/6.3V_4
<Layout note>
Close to pin AA19
+1.8V
C323
C323
*22U/6.3V_8
*22U/6.3V_8
+1.05V
+1.05V
+1.05V
C84 2.2U/6.3V_6C84 2.2U/6.3V_6
C85 1U/6.3V_4C85 1U/6.3V_4
C74 1U/6.3V_4C74 1U/6.3V_4
C72 1U/6.3V_4C72 1U/6.3V_4
C77 1U/6.3V_4C77 1U/6.3V_4
C88 1U/6.3V_4C88 1U/6.3V_4
C78 1U/6.3V_4C78 1U/6.3V_4
C86 1U/6.3V_4C86 1U/6.3V_4
+1.5VSUS
R111 *0/short_8R111 *0/shor t_8
C101 2.2U/6.3V_6C101 2.2U/6.3V _6
C100 1U/6.3V_4C100 1U/6.3V_4
C99 1U/6.3V_4C99 1U/6.3V_4
C96 1U/6.3V_4C96 1U/6.3V_4
C103 1U/6.3V_4C103 1U/6.3V_4
VCC1.5_VCCCK_DDR
C278 22u/6.3V_8C278 22u/6.3V_8
C81 4.7U/6.3V_6C81 4.7U/6.3V_6
C76 1U/6.3V_4C76 1U/6.3V_4
C80 *0.1u/10V_4C80 *0.1u/10V_4
C94 *0.1u/10V_4C94 *0.1u/10V_4
C91 1U/6.3V_4C91 1U/6.3V_4
C93 1U/6.3V_4C93 1U/6.3V_4
C75 1U/6.3V_4C75 1U/6.3V_4
C253 1U/6.3V_4C253 1U/6.3V_4
C254 1U/6.3V_4C254 1U/6.3V_4
3
VCCGFX
U21E
U21E
T13
VCCGFX
T14
VCCGFX
T16
VCCGFX
T18
VCCGFX
T19
VCCGFX
V13
VCCGFX
V19
VCCGFX
W14
VCCGFX
W16
VCCGFX
W18
VCCGFX
W19
VCCGFX
AK13
VCCSM
AK19
VCCSM
AK9
VCCSM
AL11
VCCSM
AL16
VCCSM
AL21
VCCSM
AL25
VCCSM
AK7
VCCCK_DDR
AL7
VCCCK_DDR
U10
+1.05V
3
AC31
+3V
C256
C256
*1u/6.3V_4
*1u/6.3V_4
U5
U6
U7
U8
U9
V2
V3
V4
W10
W11
AA10
AA11
AA19
V11
T30
T31
J31
C3
B2
C2
A21
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCACK_DDR
VCCACK_DDR
VCCD_AB_DPL
VCCD_HMPLL
VCCSFR_AB_DPL
0.154A
VCCACRTDAC
0.006A
VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI_VID
Pineview-M 1.66G
Pineview-M 1.66G
1.38A
2.27A
5 OF 6
5 OF 6
1.32A
PINEVIEW_M
PINEVIEW_M
GFX/MCH
GFX/MCH
DDR
DDR
0.33A
4
EXP\CRT\PLL
EXP\CRT\PLL
4
REV = 1.1
REV = 1.1
POWER
POWER
DMI
DMI
3.5A
CPU
CPU
VCCSENSE
VSSSENSE
0.08A
0.06A
LVDS
LVDS
VCCA_DMI
VCCA_DMI
VCCA_DMI
0.104A
VCCSFR_DMIHMPLL
VCCA
VCCP
VCCP
VCCALVD
VCCDLVD
0.48A
RSVD
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCORE
A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21
C29
B29
VCC1.5_VCCA
Y2
D4
C255 *0.1u/10V_4C255 *0.1u/10V_4
B4
VCCP_VCCP
B3
V30
W31
VCCP_DMI
T1
C273 1U/6.3V_4C273 1U/6.3V_4
T2
C272 1U/6.3V_4C272 1U/6.3V_4
T3
VCCP_VCCAPLL_DMI
P2
VCC1.8_DMIHMPLL
AA1
E2
+1.05V
5
C69 1U/6.3V_4C 69 1U/6.3V_4
C58 1U/6.3V_4C 58 1U/6.3V_4
C39 1U/6.3V_4C 39 1U/6.3V_4
C57 1U/6.3V_4C 57 1U/6.3V_4
C32 22u/6.3V_8C32 22u/6.3V_8
C34 22u/6.3V_8C34 22u/6.3V_8
C33 22u/6.3V_8C33 22u/6.3V_8
C280 0.01U/25V_4C280 0.01U/25V_4
R291 *0/short_4R291 *0/short_4
VCC1.8_LCCALVD
5
R322 *0/short_6R322 *0/short_6
<Layout note>
Close to pin
+1.05V
<20090526(A1A)_EDS Rev0.7>
D4 pin is VCCP, not VCC
R315 *0/short_6R315 *0/short_6
R326 *0/short_4R326 *0/short_4
C284
C284
1u/6.3V_4
1u/6.3V_4
6
+1.5V
+1.05V
R100 0.1uH/300mA_6R100 0.1uH/300mA_6
C87
C87
22U/6.3V_8
22U/6.3V_8
+1.05V
R313 *0_4R 313 *0_4
+1.8V
C267
C267
*1u/6.3V_4
*1u/6.3V_4
6
7
VCORE
R56
R56
100/F_4
100/F_4
VCC_SENSE [26]
VSS_SENSE [26]
R57
R57
100/F_4
100/F_4
+1.8V
C92
C92
1u/6.3V_4
1u/6.3V_4
+1.05V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
7
PROJECT :
Pineview Power
Pineview Power
Pineview Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, March 11, 2011
Friday, March 11, 2011
Friday, March 11, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
ZE6
ZE6
ZE6
8
06
1B
1B
1B
of
356
356
356
8
1
PINEVIEW_M
PINEVIEW_M
U21F
U21F
REV = 1.1
REV = 1.1
A11
VSS
A16
VSS
A19
VSS
A29
RSVD_NCTF
A3
RSVD_NCTF
A30
RSVD_NCTF
A4
RSVD_NCTF
AA13
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA2
VSS
AA22
VSS
AA25
VSS
AA26
VSS
AA29
VSS
AA8
VSS
AB19
VSS
AB21
VSS
AB28
VSS
AB29
VSS
AB30
VSS
AC10
VSS
AC11
VSS
AC19
VSS
AC2
VSS
AC21
VSS
AC28
VSS
AC30
VSS
AD26
VSS
AD5
VSS
AE1
VSS
AE11
VSS
AE13
VSS
AE15
VSS
AE17
VSS
AE22
VSS
AE31
VSS
AF11
VSS
AF17
VSS
AF21
VSS
AF24
VSS
AF28
VSS
AG10
VSS
AG3
VSS
AH18
VSS
AH23
VSS
AH28
VSS
AH4
VSS
AH6
A A
AJ16
AJ31
AK23
AK30
AK31
AL13
AL19
AL23
AL29
AL30
AH8
AJ1
AK1
AK2
AL2
AL3
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19
VSS
VSS
RSVD_NCTF
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pineview-M 1.66G
Pineview-M 1.66G
6 OF 6
6 OF 6
F24
VSS
F28
VSS
F4
VSS
G15
VSS
G17
VSS
G22
VSS
G27
VSS
G31
VSS
H11
VSS
H15
VSS
H2
VSS
H21
VSS
H25
VSS
H8
VSS
J11
VSS
J13
VSS
J15
VSS
J4
VSS
K11
VSS
K13
VSS
K19
VSS
K26
VSS
K27
VSS
GND
GND
K28
VSS
K30
VSS
K4
VSS
K8
VSS
L1
VSS
L13
VSS
L18
VSS
L22
VSS
L24
VSS
L25
VSS
L29
VSS
M28
VSS
M3
VSS
N1
VSS
N13
VSS
N18
VSS
N24
VSS
N25
VSS
N28
VSS
N4
VSS
N5
VSS
N8
VSS
P13
VSS
P14
VSS
P16
VSS
P18
VSS
P19
VSS
P21
VSS
P3
VSS
P4
VSS
R25
VSS
R7
VSS
R8
VSS
T11
VSS
U22
VSS
U23
VSS
U24
VSS
U27
VSS
V14
VSS
V16
VSS
V18
VSS
V28
VSS
V29
VSS
W13
VSS
W2
VSS
W23
VSS
W25
VSS
W26
VSS
W28
VSS
W30
VSS
W4
VSS
W5
VSS
W6
VSS
W7
VSS
Y28
VSS
Y3
VSS
Y4
VSS
T29
VSS
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Friday, March 11, 2011
Friday, March 11, 2011
1
Friday, March 11, 2011
PROJECT :
Pineview GND
Pineview GND
Pineview GND
ZE6
ZE6
ZE6
07
1B
1B
1B
of
357
357
357
1
0110 : exchange USB port 1 and port 3
TGP
U20B
U20B
DMI_RXN0[4]
DMI_RXP0[4]
DMI_TXN0[4]
DMI_TXP0[4]
DMI_RXN1[4]
DMI_RXP1[4]
DMI_TXN1[4]
DMI_TXP1[4]
PE1RX-[18]
LAN
PE1RX+[18]
PE1TX-[18]
PE1TX+[18]
PE2RX-[20]
WLAN
PE2RX+[20]
PE2TX-[20]
PE2TX+[20]
PE3RX-[21]
A A
Card Reader
PE3RX+[21]
PE3TX-[21]
PE3TX+[21]
PE4RX-[20]
PE4RX+[20]
3G
PE4TX-[20]
PE4TX+[20]
C53 0.1U/10V_4C53 0.1U/10V_4
C46 0.1U/10V_4C46 0.1U/10V_4
C65 0.1U/10V_4C65 0.1U/10V_4
C59 0.1U/10V_4C59 0.1U/10V_4
C259 0.1U/10V_4C259 0.1U/10V_4
C262 0.1U/10V_4C262 0.1U/10V_4
C263 0.1U/10V_4C263 0.1U/10V_4
C266 0.1U/10V_4C266 0.1U/10V_4
C270 0.1U/10V_4C270 0.1U/10V_4
C268 0.1U/10V_4C268 0.1U/10V_4
C271 *3G@0.1U/10V_4C271 *3G@0.1U/10V_4
C274 *3G@0.1U/10V_4C274 *3G@0.1U/10V_4
DMI_TXN0_C
DMI_TXP0_C
DMI_TXN1_C
DMI_TXP1_C
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN3_C
PCIE_TXP3_C
PCIE_TXN4_C
PCIE_TXP4_C
R23
DMI0RXN
R24
DMI0RXP
P21
DMI0TXN
P20
DMI0TXP
T21
DMI1RXN
T20
DMI1RXP
T24
DMI1TXN
T25
DMI1TXP
T19
DMI2RXN
T18
DMI2RXP
U23
DMI2TXN
U24
DMI2TXP
V21
DMI3RXN
V20
DMI3RXP
V24
DMI3TXN
V23
DMI3TXP
K21
PERN1
K22
PERP1
J23
PETN1
J24
PETP1
M18
PERN2
M19
PERP2
K24
PETN2
K25
PETP2
L23
PERN3
L24
PERP3
L22
PETN3
M21
PETP3
P17
PERN4
P18
PERP4
N25
PETN4
N24
PETP4
TGP
DMI
DMI
USB
USB
PCI-E
PCI-E
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
USBRBIAS
USBRBIAS#
CLK48
H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2
USBOC#R_1
D4
USBOC#L_1
C5
USBOC#
D3
USBOC#R_1
D2
USBOC#
E5
USBOC#
E6
USBOC#
C2
USBOC#
C3
G2
USBRBIAS
G3
placed within 500 mil of the chipset
CLKUSB_48
F4
to fix charger port will auto wake up issue.
USBP0- [17]
USBP0+ [17]
USBP1- [17]
USBP1+ [17]
USBP2- [14]
USBP2+ [14]
USBP3- [17]
USBP3+ [17]
USBP4- [20]
USBP4+ [20]
USBP5- [20]
USBP5+ [20]
USBP6- [15]
USBP6+ [15]
USBP7- [20]
USBP7+ [20]
R303 *0/short_4R303 *0/short_4
R297 *0/short_4R297 *0/short_4
R314 22.6/F_4R314 22.6/F_4
CLKUSB_48 [2]
SYSTEM (Right down)
SYSTEM (Right up)
CCD
SYSTEM (Left)
SIM
3G
BT
WLAN
USBOC#R [17,22]
USBOC#L [17,22]
USBOC#R_1
USBOC#L_1
USBOC#
R305 8.2K_4R305 8.2K_4
R298 8.2K_4R298 8.2K_4
R306 1K/F_4R306 1K/F_4
+3V_S5
+1.5V
R78 24.9/F_4R78 24.9/F_4
CLK_PCIE_ICH#[2]
CLK_PCIE_ICH[2]
DMI_COMP
W23
W24
H24
J22
DMI_ZCOMP
DMI_IRCOMP
DMI_CLKN
DMI_CLKP
Tiger Point
Tiger Point
CLKUSB_48
R309
R309
*10/F_4
2
2
1
*10/F_4
C258
C258
*10P/50V_4
*10P/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Friday, March 11, 2011
Friday, March 11, 2011
Friday, March 11, 2011
PROJECT :
Tiger Point DMI/PCIE/USB
Tiger Point DMI/PCIE/USB
Tiger Point DMI/PCIE/USB
ZE6
ZE6
ZE6
358
358
358
1B
1B
1B
5
4
3
2
1
09
TGP
U20C
U20C
D D
C C
B B
PCH_GPIO36
R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12
AC17
AB13
AC13
AB15
Y14
AB16
AE24
AE23
AA14
V14
AD16
AB11
AB10
AD23
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
GPIO36
TGP
SATA
SATA
HOST
HOST
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
SATALED#
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THERMTRIP#
AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9
AD4
AC4
AD11
AC11
AD25
U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20
SATARBIAS#
R340 10K/J_4R340 10K/J_4
GA20
KBRST#
SATA_RXN0 [19]
SATA_RXP0 [19]
SATA_TXN0 [19]
SATA_TXP0 [19]
CLK_PCIE_SATA# [2]
CLK_PCIE_SATA [2]
SATALED#
GA20 [22]
H_A20M# [4]
H_IGNNE# [4]
H_INIT# [4]
H_INTR [4]
H_NMI [4]
KBRST# [22]
SERIRQ [22]
H_SMI# [4]
H_STPCLK# [4]
SATA HDD
<Layout note>
Close to pin within 500mil
R335 24.9/F_4R335 24.9/F_4
SATALED# [15]
+3V
+1.05V
R84
R84
56/J_4
56/J_4
<20090514(A1A)_Checklist Rev0.7>
SERIRQ:8.2K pull-up
A20GATE:10K pull-up
SERIRQ
GA20
KBRST#
PCH_GPIO36
<Layout note>
Close to pin
H_FERR# [4]
R107 8.2K_4R107 8.2K_4
R108 10K_4R108 10K_4
R338 10K/J_4R338 10K/J_4
R339 *10K/J_4R339 *10K/J_4
<Layout note>
Close to pin within 200mil
+1.05V
R103
R103
56/J_4
56/J_4
+3V
<Layout note>
Close to pin within 1"
PM_THRMTRIP# [4]
3
Tiger Point
Tiger Point
NOTE
烉
1. CPUSLP# is supported only on nettop platforms.
A A
5
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Friday, March 11, 2011
Friday, March 11, 2011
4
3
Friday, March 11, 2011
PROJECT :
Tiger Point Sata/Host
Tiger Point Sata/Host
Tiger Point Sata/Host
2
ZE6
ZE6
ZE6
1B
1B
1B
of
359
359
359
1
5
PCLK_ICH[2]
D D
<20090601(A1A)_Checklist Rev0.7>
Strap1#/strap2#: signals have weak
internal pull-ups
C C
EC_SCI#[22]
B B
+3V
EC_SCI#
T38T38
R271 10K/J_4R271 10K/J_4
R73 8.2K/J_4R73 8.2K/J_4
ICH Boot BIOS select
R71*1K_4 R71*1K_4
R299*1K_4 R299*1K_4
PCH_GPIO48
(INT PU)
PCH_GPIO48
PCH_GPIO17
Low = A16 swap override enabled
High = Default
PCH_GPIO17
(INT PU) Boot BIOS Location
0 1 SPI
10PCI
11LPC
A A
A16 SWAP Override strap
PCH_A16WP
(INT PU)
5
4
PCI_DEVSEL#
T27T27
PCI_IRDY#
PCI_SERR#
PCI_STOP#
PCI_LOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#
T26T26
T31T31
PCI_REQ1#
PCI_REQ2#
PCH_GPIO48
PCH_GPIO17
PCH_GPIO22
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#
PCH_A16WP
4
U20A
U20A
A5
PAR
B15
DEVSEL#
J12
PCICLK
A23
PCIRST#
B7
IRDY#
C22
PME#
B11
SERR#
F14
STOP#
A8
PLOCK#
A10
TRDY#
D10
PERR#
A16
FRAME#
A18
GNT1#
E16
GNT2#
G16
REQ1#
A20
REQ2#
G14
GPIO48/ STRAP1#
A2
GPIO17/ STRAP2#
C15
GPIO22
C9
GPIO1
B2
PIRQA#
D7
PIRQB#
B3
PIRQC#
H10
PIRQD#
E8
PIRQE#/GPIO2
D6
PIRQF#/GPIO3
H8
PIRQG#/GPIO4
F8
PIRQH#/GPIO5
D11
STRAP0#
K9
RSVD01
M13
RSVD02
(Default)
R72*1K_4 R72*1K_4
R300*1K_4 R300*1K_4
Tiger Point
Tiger Point
3
TGP
TGP
B22
AD0
D18
AD1
C17
AD2
C18
AD3
B17
AD4
C19
AD5
B18
AD6
B19
AD7
D16
PCI
PCI
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1
H16
M15
C13
L16
PCI_INTA#
PCI_INTC#
PCI_INTF#
PCI_INTB#
PCI_IRDY#
PCI_LOCK#
PCI_PERR#
PCI_TRDY#
PCI_DEVSEL#
PCI_FRAME#
PCI_REQ1#
PCI_REQ2#
PCI_STOP#
PCI_SERR#
EC_SCI#
PCI_INTD#
PCI_INTH#
PCI_INTG#
PCI_INTE#
PCH_GPIO22
IRQ
PIRQA
PIRQB
PIRQC
PIRQD
1
1
PIRQE
PIRQF
PIRQG
PIRQH
+3V
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: Sheet of
Date: Sheet of
3
Date: Sheet
2
RP4 8.2K_8P4RRP4 8.2K_8P4R
1
2
3
4
5
6
7
8
RP3 8.2K_8P4RRP3 8.2K_8P4R
1
2
3
4
5
6
7
8
RP5 8.2K_8P4RRP5 8.2K_8P4R
1
2
3
4
5
6
7
8
R272 8.2K/J_4R272 8.2K/J_4
R283 8.2K/J_4R283 8.2K/J_4
R54 10K_4R54 10K_4
RP1 8.2K_8P4RRP1 8.2K_8P4R
1
2
3
4
5
6
7
8
Description
USB UHCI Controlle r #1, #4
AC'97 Codec; option for SMBUS
USB UH Controller #3; SATA/IDE Native Mode
USB UHCI Controlle r #2
Internal LAN; Option for SCI, TCO, HPET#0,1,2
Option for SCI, TCO, HPET#0,1,2
Option for SCI, TCO, HPET#0,1,2
USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2
PCI_GNT#2 Internal PU
Friday, March 11, 2011
Friday, March 11, 2011
Friday, March 11, 2011
Should not be PD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
TigerPoint PCI(3/6)
TigerPoint PCI(3/6)
TigerPoint PCI(3/6)
2
1
+3V
+3V
+3V
+3V
+3V
R2848.2K_4 R2848.2K_4
+3V
ZE6
ZE6
ZE6
1
10
1B
1B
1B
of
3510
3510
3510
5
EMI
14M_ICH
R327
R327
*33/J_4
*33/J_4
C285
C285
*10P/50V_4
D D
*10P/50V_4
debug port for google require
C C
RTC(RTC)
B B
+3VPCU
VCCRTC
D33
D33
C293
C293
CH500H-40
CH500H-40
1u/10V_6
1u/10V_6
D32
D32
R344
R344
CH500H-40
CH500H-40
20K/F_6
20K/F_6
C288
C288
1u/10V_6
R354
R354
1K_4
1K_4
1u/10V_6
ACZ_BITCLK_AUDIO[16]
ACZ_RESET#_AUDIO[16]
ACZ_SDIN0[16]
ACZ_SDOUT_AUDIO[16]
ACZ_SYNC_AUDIO[16]
14M_ICH[2]
RTCRST#VCCRTC_3
G1
G1
12
*SHORT_PAD
*SHORT_PAD
20MIL 20MIL
1 3
Q10
Q10
MMBT3904
MMBT3904
2
12
A A
CN5
CN5
RTC SOCKET
RTC SOCKET
5
R160 2K/F_4R160 2K/F_4
C279 15P/50V_4C279 15P/50V_4
32.768KHz,+-20PPM
32.768KHz,+-20PPM
C275 15P/50V_4C275 15P/50V_4
VCCRTC_2VCCRTC_1VCCRTC_4
4
U20D
U20D
T18T18
AA5
LDRQ1#/GPIO23
T17T17
ACZ_BITCLK_R
ACZ_RST#_R
ACZ_SDOUT_R
ACZ_SYNC_R
14M_ICH
RTC_X1
RTC_X2
RTCRST#
PCLK_SMB
PDAT_SM B
T43T43
T46T46
T14T14
T15T15
T45T45
Platform Reset
U17
U17
PLT_RST#
R302 *0/short_4R302 *0/short _4
R161
R161
68.1K/F_4
68.1K/F_4
R162
R162
150K/F_4
150K/F_4
V6
LAD0/FWH0
AA6
LAD1/FWH1
Y5
LAD2/FWH2
W8
LAD3/FWH3
Y8
LDRQ0#
Y4
LFRAME#
P6
HDA_BIT_CLK
U2
HDA_RST#
W2
HDA_SDI0
V2
HDA_SDIN1
P8
HDA_SDIN2
AA1
HDA_SDOUT
Y1
HDA_SYNC
AA3
CLK14
U3
EE_CS
AE2
EE_DIN
T6
EE_DOUT
V3
EE_SHCLK
T4
LAN_CLK
P7
LANR_STSYNC
B23
LAN_RST#
AA2
LAN_RXD0
AD1
LAN_RXD1
AC2
LAN_RXD2
W3
LAN_TXD0
T7
LAN_TXD1
U4
LAN_TXD2
W4
RTCX1
V5
RTCX2
T5
RTCRST#
E20
SMBALERT#/GPIO11
H18
SMBCLK
E23
SMBDATA
H21
SMLALERT#
F25
SMLINK0
F24
SMLINK1
R2
SPI_MISO
T1
SPI_MOSI
M8
SPI_CS#
P9
SPI_CLK
R4
SPI_ARB
Tiger Point
Tiger Point
+3V
2
1
3 5
+5V_S5
C252 *0.1u/10V_4C252 *0.1u/ 10V_4
LPCAD0[20,22]
LPCAD1[20,22]
LPCAD2[20,22]
LPCAD3[20,22]
LPCFRAME#[20,22]
R321 33/J_4R321 33/J_4
R316 33/J_4R316 33/J_4
R324 33/J_4R324 33/J_4
R323 33/J_4R323 33/J_4
<20090529(A1A)_Checklist Rev0.7>
If integrated LAN is not used
LAN_RST# tie it to GND.
R320
R320
10M/J_4
Y3
Y3
PCLK_SM B[2,20]
PDAT_SM B[2,20]
4
10M/J_4
1 4
2 3
SMBALERT#
SMB_LINK_ALERT#
SMLINK0
SMLINK1
R165 2K/F_4R165 2K/F_4
1.Level 1 Environment-related Substances Should NEVER be Used.
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
*TC7SH08FU
*TC7SH08FU
4
EPROM
EPROM
3
LPC AUDIO LAN
LPC AUDIO LAN
R307
R307
100K_4
100K_4
3
TGP
TGP
RTC SMB SPI
RTC SMB SPI
BM_BUSY#/GPIO0
DPRSLPVR
STP_PCI#
STP_CPU#
CLKRUN#
CPUPWRGD/GPIO49
VRMPWRGD
MCH_SYNC#
MISC
MISC
PWRBTN#
SUS_STAT#/LPCPD#
SYS_RESET#
PLTRSTB
INTRUDER#
RSMRST#
INTVRMEN
BATLOW#
DPRSTP#
PLTRST# [4,18,20,21,22,23]
ACZ_SDOUT
(INT PD)
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO33
GPIO34
GPIO38
GPIO39
THRM#
SUSCLK
WAKE#
PWROK
SPKR
SLP_S3#
SLP_S4#
SLP_S5#
DPSLP#
RSVD31
T15
W16
W14
K18
H19
M17
A24
C23
P5
E24
AB20
Y16
AB19
R3
C24
D19
D20
F22
AC19
U14
AC1
AC23
AC24
AB22
AB17
V16
AC18
E21
H23
RI#
G22
D22
G18
G23
C25
T8
U10
AC3
AD3
J16
H20
E25
F21
B25
AB23
AA18
F20
0
0
1
BM_BUSY#
PCH_GPIO 6
PCH_GPIO 7
EC_SMI#
PCH_GPIO 9
PCH_GPIO 10
PCH_GPIO 12
PCH_GPIO 13
PCH_GPIO 14
PCH_GPIO 15
PCH_GPIO 24
DMI_AC_ENABLE
PCH_GPIO 26
PCH_GPIO 27
PCH_GPIO 28
CLKRUN#
PCH_GPIO 33
MBID0
MBID1
MBID2
MCH_SYNC#
DNBSWON#
ICH_RI#
SUSCLK
SYS_RST#
PLT_RST#
PCIE_WAKE#
SM_INTRUDER#
TPT_PWROK
EC_RSMRST#
ICH_INTVRMEN
PM_BATLOW#
<20090721(B2A)>
Stuff U19 and C275 and un-stuff R205 for power sequence
IMVP_PW RGD[4,23,26]
ACZ_SYNC
(INT PD)
0
0
1
1 1 x 4s(1 port/4 lanes)
2
T20T20
T19T19
EC_SMI# [22]
PM_DPRS LPVR [4, 26]
PM_STPPCI # [2 ]
PM_STPCPU # [ 2]
T44T44
1C: Intel suggestion enable AC mode
T28T28
T32T32
T11T11
CLKRUN# [22]
T16T16
H_PWRGD [4]
THERM_ALERT# [4,22]
VR_PWRGD_CK410 [2]
DNBSWON# [ 22,23]
T42T42
SUSCLK [22]
PCIE_WAKE# [18,20]
EC_RSMRST# [22,23]
SB_BEEP [16]
SUSB# [22]
SUSC# [22]
ICH_DPRSTP# [4,26]
H_DPSLP# [4]
TPT Power OK
HWPG[22,23]
ECPWROK[22, 23]
T12T12
R347 1M/F_6R347 1M/F_6
R331 332K/F_4R331 332K/F_4
+3V
U6
2
1
R135 0_4R135 0_4
R110 *0_4R110 *0_4
Description
4 x 1s
*
Reserved1
Reserved
2
1
<20090515(A1A)_Checklist Rev0.7>
BATLOW#:8.2K pull-up to V3ALWAYS
WAKE#:10K pull-up to VccSus3_3
SYS_RST#:10K pull-up to VccSus3_3
PCLK_SMB
PDAT_SM B
PCH_GPIO 10
PM_BATLOW#
THERM_ALERT#
DNBSWON#
PCH_GPIO 9
EC_SMI#
SYS_RST#
SMBALERT#
SMB_LINK_ALERT#
PCIE_WAKE#
SMLINK1
SMLINK0
PCH_GPIO 15
ICH_RI#
PCH_GPIO 12
PCH_GPIO 13
PCH_GPIO 14
MCH_SYNC#
CLKRUN#
BM_BUSY#
VCCRTC
DMI_AC_ENABLE
TPT_PWROK
EC_RSMRST#
C98 *0.1u/10V_4C98 *0.1u/10V_4
*TC7SH08FUU6*TC7SH08FU
4
3 5
INTVRMEN
1
0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Friday, March 11, 2011
Date: Sheet of
Friday, March 11, 2011
Date: Sheet of
Friday, March 11, 2011
TPT_PWROK
Enable internal VccSus1_5 VRM
(default)
Disable
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
TigerPoint GPIO
TigerPoint GPIO
TigerPoint GPIO
MBID2
MBID1
MBID0
1
R273 2.2K_4R273 2.2K_4
R288 2.2K_4R288 2.2K_4
R277 8.2K_4R277 8.2K_4
R282 8.2K_4R282 8.2K_4
R104 8.2K_4R104 8.2K_4
R276 *10K_4R276 *10K_4
R275 8.2K_4R275 8.2K_4
R286 10K_4R286 10K_4
R274 10K_4R274 10K_4
R285 10K_4R285 10K_4
R278 10K_4R278 10K_4
R296 10K_4R296 10K_4
R304 10K_4R304 10K_4
R308 10K_4R308 10K_4
R301 8.2K_4R301 8.2K_4
R279 10K_4R279 10K_4
R289 10K/J_4R289 10K/J_4
R287 10K/J_4R287 10K/J_4
R317 10K/J_4R317 10K/J_4
R337 1K/F _4R337 1K/F_4
R106 8.2K_4R106 8.2K_4
R333 8.2K_4R333 8.2K_4
R290 1K_4R290 1K_4
R336 10K_4R336 10K_4
R334 10K_4R334 10K_4
+3V
R329
R329
R343
R343
10K_4
10K_4
*10K_4
*10K_4
R332
R332
R328
R328
10K_4
10K_4
*10K_4
*10K_4
TPT_PWROK [ 23]
ZE6
ZE6
ZE6
of
11
+3V_S5
+3V
R342
R342
*10K_4
*10K_4
R330
R330
*10K_4
*10K_4
3511
3511
3511
1A
1A
1A
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