Acer Aspire One AO721 Schematics

5

4

3

2

1

Project code: 91.4HX01.001

-91/%ORFN'LDJUDP

Clock Generator

ICS9LPRS480BKLFT

D D

3

DDRIII 800

Slot 0

Slot 1

Giga LAN

RJ45

C C

CONN

MIC IN

24

MDI

Mini-Card

WLAN & 3G

AR8151

PCIE+USB 2.0

26

HD AUDIO CODEC

INT MIC

B B

ALC271

LINE OUT

2CH SPEAKER

DDRIII Channel A

18

DDRIII Channel B

17

)5$0(%8))(5

'55*0%,7

23

22

10

AZALIA

6LGHSRUW

PCIE

USB 2.0

AMD ASB2 CPU

4,5,6,7

HyperTransport

IN

OUT

RS880M

HyperTransport LINK0 CPU I/F DX10 IGP LVDS/TVOUT/TMDS DISPLAY PORT X2 Side Port Memory 1 X16 PCIE I/F 1 X4 PCIE I/F WITH SB 6 X1 PCIE I/F

SB800

USB2.0 (14)+1.1(2) SATA III (6 PORTS) 4 X1 PCIE GEN2 I/F INT. CLK GEN. GB MAC HW MONITOR PCI/PCI BDGE INT. RTC EC HD AUDIO LPC I/F SPI I/F ACPI 1.1

12,13,14,15,16

LINK0

16x16

8,9,10,11

A-Link 4X4

LPC Bus

RGB CRT

LVDS 2CH

Digital Display

USB 2.0

SATA

LPC debug

PCB P/N : 48.4HX01.0SB REVISION : SB

PCB STACKUP

TOP

GND

S

CRT

LCD

WXGA+

HDMI

Card Reader

RTS 5138

30

20

19

21

25

GND

BOTTOM

WEBCAM

BLUETOOTH

USB x 3

19

31

SD/MMC MS/MS Pro/xD

SATA HDD

25

31

SYSTEM DC/DC

RT8223

INPUTS

DCBATOUT

OUTPUTS

5V_S5(6A)

3D3V_S5(6A)

SYSTEM DC/DC

RT8209E

INPUTS OUTPUTS

DCBATOUT 1D5V_S3(7.5A)

SYSTEM DC/DC

RT8209E

INPUTS OUTPUTS

DCBATOUT 1D1V_S0(11A)

RT9026

5V_S5

RT9025

3D3V_S5 1D1V_S5

RT9025

3D3V_S5 CPU_VDDR

CHARGER

DCBATOUT

CPU DC/DC

INPUTS

DCBATOUT

DDR_VREF_S3

ISL88731A

OUTPUTSINPUTS

CHG_PWR

18V 6.0A

UP+5V

5V 100mA

ISL6265AHR

OUTPUTS

VCC_CORE_S0_0

0~1.55V 18A

VCC_CORE_S0_1

0~1.55V 18A

VDDNB

0~1.55V 18A

34

35

36

35

37

38

33

KBC

NPCE781B

SMB PS/2 KBC

Touch PAD

28

3

29

Int.

31

KB

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

29

2

A3 Date: Sheet

Date: Sheet

Block Diagram

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

1

-1

of

142Tuesday, January 05, 2010

-1

2MB

SPI

30

Thermal Sensor

G792

A A

CPU FAN

Flash ROM

5

4

5

4

3

2

1

Power on Sequence required:

SB800: 1, +3.3VDUAL ramp before +1.1VDUAL 2, +3.3V ramp before +1.8v 3, +1.8V ramp before +1.1v 4, +3.3v ramp before +1.1v 5, +3.3VALW_R ramping down time > 300us 6, 50uS <= All power rails except +3.3VALW_R <= 40mS 7, 100uS <= +3.3VALW_R <= 40mS

RS880:

D D

1, 0 <(+3.3V) - (+1.8v) < 2.1 2, +1.8V ramp before +1.1v

3. +1.1V ramp before VCC_NB

SB OUTPUT

SB INPUT

C C

CPU MEM CTL & DDR3 SODIMM PWRS

CPU_THM/SB/SB_SCL1/2

B B

SB_KB/SPI/LPC ROM PWRS

When IMC,always high per shorting JU3000 HDR

KBC is ready

KBC is powered by A_VBAT & +3.3VALW

USB

Pair

Device

USB1(HS)

0

1

MINICARD1

2

NC

3

NC

Cardreader

A A

PCIE Routing

LANE1

LANE2

LAN

MiniCard1

MiniCard2LANE3

5

4

USB2

5

USB3

6

Blue Tooth

7

89NC

WECAM

10

NC

MINIC2(3G sim)

11

MINIC2(3G)

NC1213

CPU_LDT_RST#

(SB TO CPU)

A_RST#/PCI_RST#

(SB OUTPUT)

CPU_PWROK

(SB TO CPU)

CPU_CLKP/N running

(CPU INPUT CLK)

HT_REFCLKP/N

(NB INPUT CLK)

NB_PWRGD

NB_PWRGD_IN

+1.2V_PWRGD

VCC_NB

VLDT

+1.1V

VRM_PWRGD

CPU_VDDR

CPU_VDD_RUN

CPU_VDDNB_RUN

VDDA_PWRGD

+2.5V_LDO

(CPU_VDDA_2.5_RUN)

+1.5V

1V8_PWRGD

GROUP A GROUP B

V3V5DUAL_PWRGD 1V1DUAL_PWRGD SYSTEM_DUAL_PG

+5V/+3.3V

RUN_EN_HIGH RUN_EN_LOW VDD_BOOST_LOW

SLP_S3#

VDRAM_PWRGD

MEM_VTT MEM_VREF

CPU_VDDIO_SUS

SLP_S5#

PWR_BTN#_EC

RSMRST#

DUAL RAILS

VDD_DUAL_EN

VDD_DUAL_EN_EC

PWR_BTN#_HW PWR_BTN#_SB

AC_OK (ACIN detect)

+5VALW/+3.3VALW

LDO:5.4V (from DCIN)

+VIN/+12V_HD

A_VBAT

+1.8V

1)+1.5V SWITCH TO +1.5VDUAL 2)LASSO _PWRON 3)LPCPD# for TPM 4) TO SB&KBCSB_PWRGD

VTT only will be shut down in S3 mode, and VTT for DDR3 SODIMM only.

4

20mS delay

+3.3VDUAL RC=~40ms

+5VDUAL/+3.3VDUAL/+1.5VDUAL/+1.1VDUAL When IMC, always on at all time( always PWR)

Power button pressed

Battery inse rted/AC IN

>1 mS Req.

RC=~22ms

RC=~4.7ms

VRM_PWRGD AND 1V8_PWRGD

RC=0

Power button from EC to SB

AC not present scenario = LOW AC present= high

3

>1 mS

>1 mS Req.

running

>1 mS>1 mS

Req.

-22 mS-500ms for extenal gen. NBPWRGD, For SB800, SB gen NBPW RGD

VCC_NB(all NB power) valid before NB_PWRGD.

SLP_S3# SYS_RST#

+1.2V_PWRGD

VCC_NB should not ramp before 1.1v

When IMC, it's same signals for PBT.

1V1DUAL_PWRGD 1V5_PWRGD/DNI KBC_GPIO77/DNI

to S3

stays active if AC present

SJV10-NL

Wistron Corporat ion

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

A2 Date: Sheet

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Table of Content

SJV10-NL

1

-1

242Tuesday, January 05, 2010

-1

of

5

3D3V_S0

R1

1 2

MGB1005G601EBP-GP

3D3V_CLK_VDD

12

-1 Change R1 to bead (68.00373.001)

C1

SC10U10V5KX-2GP

12

C5

C4

SCD1U10V2KX-4GP

4

12

C6

SCD1U10V2KX-4GP

12

C7

C8

SCD1U10V2KX-4GP

12

C9

SCD1U10V2KX-4GP

3

3D3V_S0

R2

1 2

2R3J-GPR22R3J-GP

DY

12

3D3V_48MPWR_S0

12

C10

C11

C11 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

2

1

3000mA.80ohm

D D

3D3V_S0

1D1V_S0

-1 Change R4 to bead (68.00373.001)

C C

B B

A A

R3

1 2

0R3J-0-U-GP

DY

R4

1 2

MGB1005G601EBP-GP

LAN

NB A-Link

SB A-Link

MINI1

MINI2

12

C13

SC10U6D3V3MX-GP

CLK_PCIE_LAN23

CLK_PCIE_LAN#23

CLK_NB_GPPSB9

CLK_NB_GPPSB#9

CLK_PCIE_SB12

CLK_PCIE_SB#12

CLK_PCIE_MINI126

CLK_PCIE_MINI1#26

CLK_PCIE_MINI226

CLK_PCIE_MINI2#26

5

1D1V_CLK_VDDIO

3D3V_CLK_VDD

MGB1005G601EBP-GP

12

C16

C17

SCD1U10V2KX-4GP

-1 Change R7 to bead (68.00373.001)

R7

1 2

SC1U10V2KX-1GP

12

C18

SCD1U10V2KX-4GP

12

C21

CLK_NBHT_CLK9 CLK_NBHT_CLK#9

12

C19

SCD1U10V2KX-4GP

1D1V_CLK_VDDIO

NB HT

3D3V_CLK_VDD

VDD_REF 3D3V_48MPWR_S0

CLKG_PD#

U1

26

VDDATIG

25

VDDATIG_IO

48

VDDCPU

47

VDDCPU_IO

16

VDDSRC

17

VDDSRC_IO

11

VDDSRC_IO

35

VDDSB_SRC

34

VDDSB_SRC_IO

40

VDDSATA

4

VDD

55

VDDHTT

56

VDDREF

63

VDD48

51

PD#

22

SRC0T_LPRS

21

SRC0C_LPRS

20

SRC1T_LPRS

19

SRC1C_LPRS

15

SRC2T_LPRS

14

SRC2C_LPRS

13

SRC3T_LPRS

12

SRC3C_LPRS

9

SRC4T_LPRS

8

SRC4C_LPRS SRC6T/SATAT_LPRS42GNDSATA

41

SRC6C/SATAC_LPRS

6

SRC7T_LPRS/27MHZ_SS

5

SRC7C_LPRS/27MHZ_NS

37

SB_SRC0T_LPRS

36

SB_SRC0C_LPRS

32

SB_SRC1T_LPRS

31

SB_SRC1C_LPRS

54

HTT0T_LPRS/66M

53

HTT0C_LPRS/66M

ICS9LPRS480BKLFT-GP

71.09480.A03

2ND = 71.00880.A03

9LRS4880,Wistron P/N??? 48Mhz

NB CLOCK INPUT TABLE

NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK GPPSB_REFCLK 100M DIFF

* RS880M can be used as clock buffer to output two PCIE r eferecence clocks By deault, chip will configured as input mode, BIOS can program it to output mode.

4

SMBCLK SMBDAT

ATIG0T_LPRS ATIG0C_LPRS ATIG1T_LPRS ATIG1C_LPRS

CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

CPUKG0T_LPRS CPUKG0C_LPRS

48MHZ_0

REF0/SEL_HTT66

REF1/SEL_SATA

REF2/SEL_27

GNDATIG

GND

GNDHTT GNDREF GNDCPU

GND48

GNDSRC GNDSRC

GNDSB_SRC

GND

RS880M

100M DIFF 100M DIFF 14M SE (1.1V) vref 100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

SB X1 change to smaller package(82.30005.A51)

GEN_XTAL_IN

61

X1

GEN_XTAL_OUT

62

X2

CLK_SMBCLK

2

CLK_SMBDAT

3

30 29 28 27

23 45 44 39 38

CPU HT

50 49

CLK_48

64

REF0

59

REF1

58

REF2

57

43 24 7 52 60 46 1

10 18

33 65

3

R5

1 2

DY

10MR2J-L-GP

CLK_NB_GFX 9

CLK_NB_GFX# 9

LAN_CLKREQ# 23

WLAN_CLKREQ# 26 WLAN2_CLKREQ# 26

CPU_CLK 6 CPU_CLK# 6

12

X1

X-14D31818M-50GP

82.30005.A51

2nd = 82.30005.C51

SRN0J-10-GP-U

1

4

RN38

23

SMBC0_SB 13,17,18 SMBD0_SB 13,17,18

CLKREQ# Internal pull Low

-1 Change R91,R92 to RN132.

2 3 1

4

RN132

RN132 SRN33J-5-GP-U

SRN33J-5-GP-U

-1 Reserve EC2 by RF request.

DY

R32

10KR2J-3-GP

-1 Change R34~R36 to RN134.

SC12P50V2JN-3GP

SC12P50V2JN-3GP C12

C12

1 2

-1 Change C12,C20 to 12pF.

SC12P50V2JN-3GP

1 2

C20

CLK48_Cardreader 25

12

10KR2J-3-GP

1 2

CLK48_USB 13

EC2

SC22P50V2JN-4GP

3D3V_S0

R33

DY

1 2

678

123

2

DY

R31

10KR2J-3-GP

1 2

RN134

RN134 SRN10KJ-6-GP

SRN10KJ-6-GP

4 5

3D3V_S0

-1 Change R27,R30 to RN133.

REF0_R

8 7 6

RN133

6 7 8

SRN75J-1-GP

RN1

1 2 3 45

SRN10KJ-6-GP

45 3 2 1

CLKG_PD# WLAN_CLKREQ# WLAN2_CLKREQ#

REF0

12

RFC1

DY

SC33P50V2JN-3GP

NB_OSC_1.1V

CLK_NB_14M 9

-1 Reserve RFC1 by RF request.

27MHz non-sprea ding singled clock on pin 5

1

and 27MHz spread clock on pin 6

0

*

100MHz differ ential spreading SRC clock

1

100MHz non-spreading differential SATA clock 100MHz differ ential spreading SRC clock

*0

66MHz 3.3V single ended HTT clock

1 0 * 100MHz differential HTT clock

REF0

REF1

REF2

SEL_27 REF2

SEL_SATA REF1

SEL_HTT66 REF0

CPU_CLK(200MHz)

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CLKGEN_ICS9LPRS480

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

342Friday, January 29, 2010

1

-1

of

-1

5

D D

HT_NB_CPU_CAD_H158 HT_NB_CPU_CAD_L158 HT_NB_CPU_CAD_H148 HT_NB_CPU_CAD_L148 HT_NB_CPU_CAD_H138 HT_NB_CPU_CAD_L138 HT_NB_CPU_CAD_H128 HT_NB_CPU_CAD_L128 HT_NB_CPU_CAD_H118 HT_NB_CPU_CAD_L118 HT_NB_CPU_CAD_H108 HT_NB_CPU_CAD_L108 HT_NB_CPU_CAD_H98 HT_NB_CPU_CAD_L98 HT_NB_CPU_CAD_H88 HT_NB_CPU_CAD_L88 HT_NB_CPU_CAD_H78 HT_NB_CPU_CAD_L78

C C

HT_NB_CPU_CAD_H68 HT_NB_CPU_CAD_L68 HT_NB_CPU_CAD_H58 HT_NB_CPU_CAD_L58 HT_NB_CPU_CAD_H48 HT_NB_CPU_CAD_L48 HT_NB_CPU_CAD_H38 HT_NB_CPU_CAD_L38 HT_NB_CPU_CAD_H28 HT_NB_CPU_CAD_L28 HT_NB_CPU_CAD_H18 HT_NB_CPU_CAD_L18 HT_NB_CPU_CAD_H08 HT_NB_CPU_CAD_L08

HT_NB_CPU_CLK_H18 HT_NB_CPU_CLK_L18

HT_NB_CPU_CLK_H08 HT_NB_CPU_CLK_L08

HT_NB_CPU_CTL_H18 HT_NB_CPU_CTL_L18

HT_NB_CPU_CTL_H08 HT_NB_CPU_CTL_L08

W7 W6

G6 G5

M2 M1

M8 M7

M3 M4

U6 U5 R7 R6 P6 P5

L6 L5 J6

J5 H4 H3

T3 T4 T2 T1 P3 P4 P2 P1

K3 K4 K2 K1 H2 H1

Y6 Y5

V2 V1

4

ACPU1A

L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0

L0_CLKIN_H1 L0_CLKIN_L1

L0_CLKIN_H0 L0_CLKIN_L0

L0_CTLIN_H1 L0_CTLIN_L1

L0_CTLIN_H0 L0_CTLIN_L0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

HT LINK

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0 L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AB6 AB5 AB9 AB8 AC7 AC6 AE6 AE5 AE9 AE8 AH3 AH4 AK3 AK4 AH1 AH2 Y1 Y2 Y4 Y3 AB1 AB2 AB4 AB3 AD4 AD3 AF1 AF2 AF4 AF3 AK1 AK2

AF6 AF5

AD1 AD2

Y8 Y9

V4 V3

3

HT_CPU_NB_CAD_H15 8 HT_CPU_NB_CAD_L15 8 HT_CPU_NB_CAD_H14 8 HT_CPU_NB_CAD_L14 8 HT_CPU_NB_CAD_H13 8 HT_CPU_NB_CAD_L13 8 HT_CPU_NB_CAD_H12 8 HT_CPU_NB_CAD_L12 8 HT_CPU_NB_CAD_H11 8 HT_CPU_NB_CAD_L11 8 HT_CPU_NB_CAD_H10 8 HT_CPU_NB_CAD_L10 8 HT_CPU_NB_CAD_H9 8 HT_CPU_NB_CAD_L9 8 HT_CPU_NB_CAD_H8 8 HT_CPU_NB_CAD_L8 8 HT_CPU_NB_CAD_H7 8 HT_CPU_NB_CAD_L7 8 HT_CPU_NB_CAD_H6 8 HT_CPU_NB_CAD_L6 8 HT_CPU_NB_CAD_H5 8 HT_CPU_NB_CAD_L5 8 HT_CPU_NB_CAD_H4 8 HT_CPU_NB_CAD_L4 8 HT_CPU_NB_CAD_H3 8 HT_CPU_NB_CAD_L3 8 HT_CPU_NB_CAD_H2 8 HT_CPU_NB_CAD_L2 8 HT_CPU_NB_CAD_H1 8 HT_CPU_NB_CAD_L1 8 HT_CPU_NB_CAD_H0 8 HT_CPU_NB_CAD_L0 8

HT_CPU_NB_CLK_H1 8 HT_CPU_NB_CLK_L1 8

HT_CPU_NB_CLK_H0 8 HT_CPU_NB_CLK_L0 8

HT_CPU_NB_CTL_H1 8 HT_CPU_NB_CTL_L1 8

HT_CPU_NB_CTL_H0 8 HT_CPU_NB_CTL_L0 8

2

1

ASB2

B B

A A

5

ASB2

71.TURON.B0U

4

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

3

2

Date: Sheet

CPU_HT_LINK I/F_(1/4)

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

-1

of

442Tuesday, January 26, 2010

of

442Tuesday, January 26, 2010

of

442Tuesday, January 26, 2010

1

-1

5

M_A_DQ[63..0]17 M_A_A[15..0]17

M_A_DM[7..0]17

M_A_DQS#[7..0]17

M_A_DQS[7..0]17

ACPU1B

D D

M_A_BS217 M_A_BS117 M_A_BS017

C C

M_A_DQS7 M_A_DQS#7 M_A_DQS6 M_A_DQS#6 M_A_DQS5 M_A_DQS#5 M_A_DQS4 M_A_DQS#4 M_A_DQS3 M_A_DQS#3 M_A_DQS2 M_A_DQS#2 M_A_DQS1 M_A_DQS#1 M_A_DQS0 M_A_DQS#0

M_CLK_DDR017 M_CLK_DDR#017 M_CLK_DDR117

B B

A A

M_CLK_DDR#117

M_CKE117 M_CKE017

M_ODT117

M_CS#117 M_CS#017

M_A_RAS#17 M_A_CAS#17 M_A_WE#17

DDR3_DRAMRST_A#17 DDR3_DRAMRST_B#18

PM_EXTTS#017

5

M_A_A15 M_B_A15 M_A_A14 M_A_A13 M_A_A12 M_A_A11 M_A_A10 M_A_A9 M_A_A8 M_A_A7 M_A_A6 M_A_A5 M_A_A4 M_A_A3 M_A_A2 M_A_A1 M_A_A0

P30 M29

AG28

P28

AC28

P27 R26 R27 U28 V30 U27 Y30

AB29

W29

AC26

R29 AC29 AE28

K30

G29

H29

H27

AJ11 AK12 AG15 AH15 AH22 AG22 AG26 AH26

E28 E25 G17

H17 E12

AK18

AJ17 AH17 AG17

Y28

Y27 AB27 AB26

W27 W26

P26

M26

D18

E20

E19

M30

M28

AJ29 AF27 AJ30

AG29 AH29

AE29 AH30

AF29

AC27

AF30

AE27

M32

T30

J29 F29

L28 L29

J27 J26

F28 F25

F12

F19

L27

GENEVA-GP

ACPU1B

MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0

MA_BANK2 MA_BANK1 MA_BANK0

MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0

MA_DQS_H8 MA_DQS_L8 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0

MA_CLK_H7 MA_CLK_L7 MA_CLK_H6 MA_CLK_L6 MA_CLK_H5 MA_CLK_L5 MA_CLK_H4 MA_CLK_L4 MA_CLK_H3 MA_CLK_L3 MA_CLK_H2 MA_CLK_L2 MA_CLK_H1 MA_CLK_L1 MA_CLK_H0 MA_CLK_L0

MA_CKE1 MA_CKE0

MA1_ODT1 MA1_ODT0 MA0_ODT1 MA0_ODT0

MA1_CS_L1 MA1_CS_L0 MA0_CS_L1 MA0_CS_L0

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L FREE|MA_EVENT_L

DDR III: CHANNEL A

MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10

MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0

MA_DM8 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0

4

M_A_DQ63

AG11

M_A_DQ62

AH11

M_A_DQ61

AJ12

M_A_DQ60

AJ14

M_A_DQ59

AF11

M_A_DQ58

AF12

M_A_DQ57

AG12

M_A_DQ56

AH12

M_A_DQ55

AK14

M_A_DQ54

AF15

M_A_DQ53

AH19

M_A_DQ52

AK20

M_A_DQ51

AF14

M_A_DQ50

AG14

M_A_DQ49

AF17

M_A_DQ48

AG19

M_A_DQ47

AG20

M_A_DQ46

AJ20

M_A_DQ45

AF22

M_A_DQ44

AK24

M_A_DQ43

AF19

M_A_DQ42

AF20

M_A_DQ41

AJ23

M_A_DQ40

AG23

M_A_DQ39

AF23

M_A_DQ38

AF25

M_A_DQ37

AH27

M_A_DQ36

AK30

M_A_DQ35

AJ25

M_A_DQ34

AG25

M_A_DQ33

AJ26

M_A_DQ32

AJ28

M_A_DQ31

D28

M_A_DQ30

G28

M_A_DQ29

D26

M_A_DQ28

E26

M_A_DQ27

F30

M_A_DQ26

E29

M_A_DQ25

F27

M_A_DQ24

H26

M_A_DQ23

H25

M_A_DQ22

D24

M_A_DQ21

H22

M_A_DQ20

E22

M_A_DQ19

F26

M_A_DQ18

G26

M_A_DQ17

D22

M_A_DQ16

G23

M_A_DQ15

G22

M_A_DQ14

G20

M_A_DQ13

G15

M_A_DQ12

F15

M_A_DQ11

D20

M_A_DQ10

F22

M_A_DQ9

D16

M_A_DQ8

E17

M_A_DQ7

H15

M_A_DQ6

H14

M_A_DQ5

G12

M_A_DQ4

H12

M_A_DQ3

E15

M_A_DQ2

E14

M_A_DQ1

E11

M_A_DQ0

F11 H30

M_A_DM7

AL12

M_A_DM6

AK16

M_A_DM5

AK22

M_A_DM4

AJ27

M_A_DM3

E27

M_A_DM2

E23

M_A_DM1

H19

M_A_DM0

G14

4

3

M_B_DQ[63..0]18

M_B_A[15..0]18

M_B_DM[7..0]18

M_B_DQS#[7..0]18

M_B_DQS[7..0]18

ACPU1C

P33 P31

AJ33

T32 T31

AD32

T33 V32 U33 V33 V31

W33

Y31 Y33 Y32

AC33

R33 AD33 AE33

K33

K31

G32

F32

L33

K32

H31

G33

H32 AM14 AN14

AL20 AM20 AN26 AM26 AN30 AM30

D33 D32 B28 A28 A21 B20 B16 A15

AN22 AM22 AN21 AM21 AA32 AA33 AB33 AB32 AB31 AB30 AD31 AD30

C22 B22 A22 A23

N33 P32

AK31 AH31 AK32 AH33

AK33

AF33

AJ32

AF31

AF32 AH32 AG33

L32

M33

J33

GENEVA-GP

MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0

MB_BANK2 MB_BANK1 MB_BANK0

MB_CHECK7 MB_CHECK6 MB_CHECK5 MB_CHECK4 MB_CHECK3 MB_CHECK2 MB_CHECK1 MB_CHECK0

MB_DQS_H8 MB_DQS_L8 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0

MB_CLK_H7 MB_CLK_L7 MB_CLK_H6 MB_CLK_L6 MB_CLK_H5 MB_CLK_L5 MB_CLK_H4 MB_CLK_L4 MB_CLK_H3 MB_CLK_L3 MB_CLK_H2 MB_CLK_L2 MB_CLK_H1 MB_CLK_L1 MB_CLK_H0 MB_CLK_L0

MB_CKE1 MB_CKE0

MB1_ODT1 MB1_ODT0 MB0_ODT1 MB0_ODT0

MB1_CS_L1 MB1_CS_L0 MB0_CS_L1 MB0_CS_L0

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L FREE|MB_EVENT_L

M_B_A14 M_B_A13 M_B_A12 M_B_A11 M_B_A10 M_B_A9 M_B_A8 M_B_A7 M_B_A6 M_B_A5 M_B_A4 M_B_A3 M_B_A2 M_B_A1 M_B_A0

M_B_BS218 M_B_BS118 M_B_BS018

M_B_DQS7 M_B_DQS#7 M_B_DQS6 M_B_DQS#6 M_B_DQS5 M_B_DQS#5 M_B_DQS4 M_B_DQS#4 M_B_DQS3 M_B_DQS#3 M_B_DQS2 M_B_DQS#2 M_B_DQS1 M_B_DQS#1 M_B_DQS0 M_B_DQS#0

M_CLK_DDR218 M_CLK_DDR#218 M_CLK_DDR318 M_CLK_DDR#318

M_CKE318 M_CKE218

M_ODT318 M_ODT218M_ODT017

M_CS#318 M_CS#218

M_B_RAS#18 M_B_CAS#18

M_B_WE#18

PM_EXTTS#117,18

3

2

MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26

DDR III: CHANNEL B

MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10

MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0

MB_DM8 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0

2

AN13 AL14 AL16 AN17 AN12 AM12 AM16 AN16 AL18 AN19 AM24 AN24 AM18 AN18 AL22 AN23 AM25 AL26 AN28 AL28 AL24 AN25 AN27 AM28 AM29 AL30 AL32 AL33 AK28 AN29 AM31 AM32 E33 D31 B31 A31 F33 F31 C32 B32 C30 A29 B26 A26 B30 A30 A27 C26 A24 B24 C18 A18 A25 C24 C20 A19 C16 A16 B14 A13 B18 A17 C14 A14

H33 AN15 AN20 AK26 AN31 C33 C28 A20 D14

1

M_B_DQ63 M_B_DQ62 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ58 M_B_DQ57 M_B_DQ56 M_B_DQ55 M_B_DQ54 M_B_DQ53 M_B_DQ52 M_B_DQ51 M_B_DQ50 M_B_DQ49 M_B_DQ48 M_B_DQ47 M_B_DQ46 M_B_DQ45 M_B_DQ44 M_B_DQ43 M_B_DQ42 M_B_DQ41 M_B_DQ40 M_B_DQ39 M_B_DQ38 M_B_DQ37 M_B_DQ36 M_B_DQ35 M_B_DQ34 M_B_DQ33 M_B_DQ32 M_B_DQ31 M_B_DQ30 M_B_DQ29 M_B_DQ28 M_B_DQ27 M_B_DQ26 M_B_DQ25 M_B_DQ24 M_B_DQ23 M_B_DQ22 M_B_DQ21 M_B_DQ20 M_B_DQ19 M_B_DQ18 M_B_DQ17 M_B_DQ16 M_B_DQ15 M_B_DQ14 M_B_DQ13 M_B_DQ12 M_B_DQ11 M_B_DQ10 M_B_DQ9 M_B_DQ8 M_B_DQ7 M_B_DQ6 M_B_DQ5 M_B_DQ4 M_B_DQ3 M_B_DQ2 M_B_DQ1 M_B_DQ0

M_B_DM7 M_B_DM6 M_B_DM5 M_B_DM4 M_B_DM3 M_B_DM2 M_B_DM1 M_B_DM0

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU_DDR_(2/4)

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

542Tuesday, January 26, 2010

1

-1

of

-1

5

4

3

2

1

2D5V Iomax=0.2A

3D3V_S0

U2

D D

RT9161-A-25PG-GP

74.09161.F3C

VOUT

GND

3 2

VIN

1

C22

SC1U10V3KX-4GP

IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491

12

Place near to CPU

CPU_VDDA_S0

12

C26

SCD1U10V2KX-4GP

LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.

12

C27

SC10U10V5KX-2GP

C28

SCD22U10V2KX-1GP

1D5V_S3

ACPU1D

1 2

DY

678

RN2

RN2 SRN300J-1-GP

SRN300J-1-GP

123

4 5

R40

C202

C201

1 2

0R0402-PAD

0R0402-PAD R41

R41

1 2

R42

1 2

12

R100

1KR2F-3-GP

M_VREF

12

R98

1KR2F-3-GP

CPU_LDT_RST#12,41

CPU_PWRGD12,41

CPU_LDT_STOP#9,12

RN35

1 2 3

SRN10J-7-GP

5

1D5V_S3

12

R842

R842 1KR2J-1-GP

1KR2J-1-GP

CPU_SIC

CPU_VDDNB_RUN_FB_H

4

CPU_VDDNB_RUN_FB_L

1D5V_S3

SCD1U16V2ZY-2GP

12

SCD1U16V2ZY-2GP

12

C C

CPU_VDDNB

B B

A A

DY

C29

C29 SC100P50V2JN-3GP

SC100P50V2JN-3GP

LDT_RST#_CPU

0R0402-PAD

0R0402-PAD 0R0402-PAD

0R0402-PAD

CPU_VDDNB_RUN_FB_L 33

LDT_PWROK

LDT_STP#_CPU

CPU_CLK3 CPU_CLK#3

Cloce To CPU

1 2

C30 SC3900P50V2KX-2GPC30 SC3900P50V2KX-2GP

1 2

C31 SC3900P50V2KX-2GPC31 SC3900P50V2KX-2GP

CPU_PWRGD_SVID_REG33

CPU_VDD0_RUN_FB_L33 CPU_VDD0_RUN_FB_H33

CPU_VDDNB_RUN_FB_H33

1D5V_S3

R49

1 2

R52

1 2

R54

1 2

0R0402-PAD

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

4

1 2

R38 169R2F-GPR38 169R2F-GP

510R2J-1-GP

CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L

510R2J-1-GP

CPU_TEST9_ANALOGIN

TP16

TP16 TP18

TP18 TP20

TP20 TP21

TP21

CLKCPU_IN

CLKCPU#_IN

LDT_PWROK LDT_STP#_CPU LDT_RST#_CPU

CPU_SIC

CPU_TDI CPU_TRST# CPU_TCK CPU_TMS

CPU_DBREQ#

M_VREF

1 2

CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

1 1 1 1

M_ZP M_ZN

R48

39D2R2F-L-GP

CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0

ACPU1D

A8

VDDA_1

B8

VDDA_2

A6

CLKIN_H

A7

CLKIN_L

D10

PWROK

E9

LDTSTOP_L

F9

RESET_L

AN4

SIC

AN5

SID

AM2

RSVD_SA0

AN3

ALERT_L

AM8

TDI

AL8

TRST_L

AK8

TCK

AN8

TMS

G9

DBREQ_L

D2

VSS_SENSE

E2

VLDT_SENSE

E1

VDD_SENSE

D1

VDDNB_SENSE

D3

VDDIO_SENSE

C2

VDDR_SENSE

A11

M_VREF

AM9

M_ZN_H

AN9

M_ZN_L

A9

BYPASSCLK_H

B9

BYPASSCLK_L

A5

PLLTEST0

B6

PLLTEST1

G8

ANALOGIN

F8

BP3

C8

BP2

D9

BP1

E8

BP0

C6

ANALOG_T

AH7

DIECRACKMON

AK5

GATE0

AJ7

DRAIN0

GENEVA-GP

CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0 CPU_TEST20_SCANCLK2

3

RSVD|CORE_TYPE

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

MISC

FBCLKOUT_H

FBCLKOUT_L

SCANSHIFTEN

PLLCHRZ_H

PLLCHRZ_L

SINGLECHAIN

ANALOGOUT

RN123

1 2 3 4 5 6

SRN1KJ-5-GP

SVC SVD

THERMDC THERMDA

TDO

DBRDY

RSVD3

HTREF1 HTREF0

SCANCLK1

TSTUPD

SCANEN

SCANCLK2

BURNIN_L

DIG_T

M_TEST

10 9 8 7

CPU_CORE_TYPE

M31

C1 B2

AL6 AM5

THERMTRIP#

AK6

PROCHOT#

AN6

CPU_TDO

AN7

CPU_DBRDY

H9

RSVD3

AM6 AJ9

CPU_HTREF1

V10

CPU_HTREF0

V9

B10 A10

AK7 AG8 AK9 AH9 AM7

G11 H11 AJ8 AM4 D7 B5

AG9

CPU_TEST24_SCANCLK1

CPU_TEST22_SCANSHIFTEN

CPU_TEST23_TSTUPD

CPU_TEST21_SCANEN

44D2R2F-GP

CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N

CPU_TEST24_SCANCLK1 CPU_TEST23_TSTUPD CPU_TEST22_SCANSHIFTEN CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2

CPU_TEST27_SINGLECHAIN CPU_TEST26_BURNIN_L

1

H_THERMDC 28 H_THERMDA 28

TP3TP3

2

1

R50

1 2

80D6R2F-L-GP

1D5V_S3

TP9TP9

12 12

THERMTRIP#

4

1

2 3

1D5V_S3

678

RN3

RN3 SRN300J-1-GP

SRN300J-1-GP

123

4 5

CPU_TEST26_BURNIN_L

CPU_DBREQ#

R44

1 2

0R0402-PAD

LDT_PWROK

12

R45

2K2R2J-2-GP

1D5V_SUS_Q2

B

Q1

C

E

MMBT3904-4-GP

84.T3904.C11

2ND = 84.03904.K11

CPU exceeds to 125

1D5V_S3

4

RN42

RN42 SRN1KJ-7-GP

SRN1KJ-7-GP

1

2 3

CPU_SVC 33 CPU_SVD 33

1D1V_S0

R4644D2R2F-GP R4644D2R2F-GP R47

R47

Route as 80ohm, diff R value is TBD

RN129

SRN1KJ-7-GP

HDT Connectors

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

SJV10-NL

Title

CPU_Control&Debug_(3/4)

Size Document Number Rev

A3

Date: Sheet

SJV10-NL

1 1 1 1 1 1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

PROCHOT#_SB 12

C33

C33 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 2

RSMRST# 28,29

к

TP109TP109 TP102TP102 TP104TP104 TP105TP105 TP106TP106 TP107TP107 TP108TP108

of

642Tuesday, January 26, 2010

of

642Tuesday, January 26, 2010

of

642Tuesday, January 26, 2010

-1

5

VCC_CORE VCC_CORE

D D

C C

K10 K12 K14 K18 K20 K21 K23

M10 M12

N11 N24

P15 P18

D4 D5 D6 E5 E6 E7 F5 F6 F7 H7 H8

J8

E4 J10 J12 J14 J18 J20 J21 J23

J9

N4 L11 L13

L7 L9

R4

M5

W4

N9

ACPU1E

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43

GENEVA-GP

VDD_85 VDD_84 VDD_83 VDD_82 VDD_81 VDD_80 VDD_79 VDD_78 VDD_77 VDD_76 VDD_75 VDD_74 VDD_73 VDD_72 VDD_71 VDD_70 VDD_69 VDD_68 VDD_67 VDD_66 VDD_65

POWER1

VDD_64 VDD_63 VDD_62 VDD_61 VDD_60 VDD_59 VDD_58 VDD_57 VDD_56 VDD_55 VDD_54 VDD_53 VDD_52 VDD_51 VDD_50 VDD_49 VDD_48 VDD_47 VDD_46 VDD_45 VDD_44

AE12 AD9 AE21 AD21 AD18 AD14 AD12 AD11 AC5 AE18 AC24 AC12 AC10 AB13 AB11 AE14 AA24 AA12 AA10 Y19 Y16 Y14 W5 W20 W18 W15 AE23 V24 V19 V16 V14 T20 T18 T15 T10 R5 R19 R16 R14 AC4 P24 P20

1D5V_S3 1D1V_S0

M27 Y26 U26 N32 U32 N30 P29 R28 R30 R32 U29

U30 W28 W30 W32

Y29

AA30 AB28 AE32 AC30 AC32 AE26 AE30

AF28 AG30 AG32 AD25 AA25 AC25

V25 P25 N25 M25 K25 L25 T25 Y25

AB25

BOTTOM SIDE DECOUPLING

VCC_CORE VCC_CORE

12

DY

B B

22U change to 10U

12

C36

C35

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

12

C37

SC10U6D3V5MX-3GP

12

C38

SC10U6D3V5MX-3GP

C39

12

C40

SCD01U25V2KX-3GP

SCD22U10V2KX-1GP

DY

12

C42

4

ACPU1F

VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15

POWER2

VDDIO_16 VDDIO_17 VDDIO_18 VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36 VDDIO_37 VDDIO_38

GENEVA-GP

12

C43

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

VLDT_A_1 VLDT_A_2 VLDT_A_3 VLDT_A_4

VLDT_B_1 VLDT_B_2 VLDT_B_3 VLDT_B_4

VDDR_1 VDDR_2 VDDR_3 VDDR_4

VDDR_5 VDDR_6 VDDR_7 VDDR_8

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6

PROGEN_L

FREE_1 FREE_2 FREE_3 FREE_4 FREE_5 FREE_6 FREE_7 FREE_8 FREE_9

12

C44

SC10U6D3V5MX-3GP

F1 F2 F3 F4

AL1 AL2 AL3 AL4

A12 B12 C12 D12

AK10 AL10 AM10 AN10

CPU_VDDNB

A3 A4 B3 B4 C3 C4

B11

G7 B7 AH8 AJ6 B25 AM3 AN11 P9 P8

12

C45

SC10U6D3V5MX-3GP

CPU_VDDR

12

C46

SCD22U10V2KX-1GP

12

C47

SCD01U25V2KX-3GP

N22 N23

M21

R15 R18

R20 D29 D30

G19 G25

G27 N10

B13 B15 B17

B19 B21 B23 B27 B29 B33 C10 P10 P14 P16 P19

C31 D11 D13 D15

D17 D19 D21 D23 D25 D27

E30 E32 F14 F17

T14 T16 F20 T19 T24

F23

B1 N2

P7

R1

R2

D8

R8

T9 U1

N1

G1 G2

3

ACPU1G

VSS_1 VSS_28 VSS_29 VSS_30 VSS_2 VSS_3 VSS_4 VSS_27 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_12 VSS_13 VSS_14 VSS_15 VSS_36 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_37 VSS_38 VSS_39 VSS_40 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_115

GENEVA-GP

GND1

VSS_45 VSS_44 VSS_43 VSS_42 VSS_26 VSS_25 VSS_41 VSS_24 VSS_23 VSS_22 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114

W19 W1 V20 V18 M11 L8 V15 L4 L30 L26 L24 L23 L22 L21 L2 L12 L10 L1 K9 M6 K24 K22 K16 M22 K13 M24 K11 M23 J7 W16 J4 W14 J32 J30 M13 J28 U8 J25 U4 J24 U7 U2 J2 J16 J13 J11 J1 H6 H5 H28 H23 H20 J22 M9 G4 G30 N12

2

ACPU1H

AM19

VSS_207

AF7

VSS_167

AF26

VSS_166

AE7

VSS_165

AF8

VSS_168

AF9

VSS_169

AG1

VSS_170

AG2

VSS_171

AG27

VSS_172

AG4

VSS_173

AG5

VSS_174

AG6

VSS_175

AG7

VSS_176

AE4

VSS_164

AE25

VSS_163

AE24

VSS_162

AE22

VSS_161

AE20

VSS_160

AE2

VSS_159

AE16

VSS_158

AE13

VSS_157

AH14

VSS_177

AE11

VSS_156

AE10

VSS_155

AE1

VSS_154

AD24

VSS_153

AD23

VSS_152

AD22

VSS_151

AH20

VSS_178

AH23

VSS_179

AH25

VSS_180

AH28

VSS_181

AD20

VSS_150

AD16

VSS_149

AD13

VSS_148

AD10

VSS_147

AC9

VSS_146

AC8

VSS_145 VSS_214A2VSS_215

AC23

VSS_144

AH5

VSS_182

AJ1

VSS_183

AJ15

VSS_184

W2

VSS_116

A32

VSS_213

W8

VSS_117

Y10

VSS_118

Y15

VSS_119

Y18

VSS_120

AJ19

VSS_185

AJ2

VSS_186

AJ22

VSS_187

AJ4

VSS_188

Y20

VSS_121

Y24

VSS_122

AK11

VSS_189

AK13

VSS_190

Y7

VSS_123

AA1

VSS_124

AA11

VSS_125

GENEVA-GP

GND2

VSS_191 VSS_192 VSS_193 VSS_194 VSS_126 VSS_127 VSS_128 VSS_195 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_137 VSS_138 VSS_205 VSS_206 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212

AK15 AK17 AK19 AK21 AA2 AA22 AA23 AK23 AA4 AA9 AB10 AB12 AB21 AB22 AB23 AB24 AK25 AK27 AK29 AJ5 AH6 AL31 AM1 AM13 AB7 AC1 AM15 AM17 AC11 AC13 AC2 AC21 AC22 AM23 AM27 AM33 AN2 AN32 AM11

1

DECOUPLING betweem CPU and DIMMs

-1 DY C35,Change C36 to 22uF. -1 DY C42,Change C43 to 22uF.

CPU_VDDR

4.7U change to 10U 10U x3 ,.22 x2

12

C567

SC10U6D3V5MX-3GP

12

C55

SCD22U10V2KX-1GP

12

C56

SCD22U10V2KX-1GP

12

C57

SCD22U10V2KX-1GP

1D1V_S0

12

C568

C569

SC10U6D3V5MX-3GP

12

C570

SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

12

C53

SCD22U10V2KX-1GP

12

C54

SCD22U10V2KX-1GP

12

C59

SC1KP50V2JN-2GP

PLACE CLOSE TO CPU AS POSSIBLE

1D5V_S3

12

C571

SCD1U10V2KX-4GP

12

C572

SCD1U10V2KX-4GP

12

C69

SCD22U10V2KX-1GP

12

C70

SCD22U10V2KX-1GP

12

C71

SCD22U10V2KX-1GP

12

C72

SCD22U10V2KX-1GP

12

C73

C74

SCD01U25V2KX-3GP

-1 Change C569 to 22uF.

10U x4 ,.22 x5 , .1ux2 ,.01ux1

It's required to add two 10uF/0603 size

CPU_VDDNB 1D5V_S3

A A

12

22U change to 10U

12

C76

C77

SC10U6D3V5MX-3GP

12

C79

SC22U6D3V5MX-2GP

DY

12

C80

SC10U6D3V5MX-3GP

12

C81

SCD22U10V2KX-1GP

12

C82

SCD22U10V2KX-1GP

-1 DY C80,Change C79 to 22uF.

5

4

3

for CPU_VDDIO_SUS,move 2x180pf from under CPU ballout by Beker, Ben.

12

C85

SC10U6D3V5MX-3GP

C86

SC10U6D3V5MX-3GP

2

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

CPU_Power_(4/4)

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

of

742Thursday, January 14, 2010

of

742Thursday, January 14, 2010

of

742Thursday, January 14, 2010

1

-1

5

HT_CPU_NB_CAD_H04 HT_CPU_NB_CAD_L04 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H24 HT_CPU_NB_CAD_L24 HT_CPU_NB_CAD_H34 HT_CPU_NB_CAD_L34 HT_CPU_NB_CAD_H44 HT_CPU_NB_CAD_L44 HT_CPU_NB_CAD_H54

D D

C C

B B

MINICARD1 MINICARD1 MINICARD2 MINICARD2

A A

A-LINK

5

HT_CPU_NB_CAD_L54 HT_CPU_NB_CAD_H64 HT_CPU_NB_CAD_L64 HT_CPU_NB_CAD_H74 HT_CPU_NB_CAD_L74

HT_CPU_NB_CAD_H84 HT_CPU_NB_CAD_L84 HT_CPU_NB_CAD_H94 HT_CPU_NB_CAD_L94 HT_CPU_NB_CAD_H104 HT_CPU_NB_CAD_L104 HT_CPU_NB_CAD_H114 HT_CPU_NB_CAD_L114 HT_CPU_NB_CAD_H124 HT_CPU_NB_CAD_L124 HT_CPU_NB_CAD_H134 HT_CPU_NB_CAD_L134 HT_CPU_NB_CAD_H144 HT_CPU_NB_CAD_L144 HT_CPU_NB_CAD_H154 HT_CPU_NB_CAD_L154

HT_CPU_NB_CLK_H04 HT_CPU_NB_CLK_L04 HT_CPU_NB_CLK_H14 HT_CPU_NB_CLK_L14

HT_CPU_NB_CTL_H04 HT_CPU_NB_CTL_L04 HT_CPU_NB_CTL_H14 HT_CPU_NB_CTL_L14

1 2

Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24

LAN

ALINK_NBRX_SBTX_P012 ALINK_NBRX_SBTX_N012 ALINK_NBRX_SBTX_P112 ALINK_NBRX_SBTX_N112 ALINK_NBRX_SBTX_P212 ALINK_NBRX_SBTX_N212 ALINK_NBRX_SBTX_P312 ALINK_NBRX_SBTX_N312

R55

R55 301R2F-GP

301R2F-GP

PCIE_RXP123 PCIE_RXN123 PCIE_RXP226 PCIE_RXN226 PCIE_RXP326 PCIE_RXN326

4

ANB1A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCALP HT_TXCALP HT_RXCALN

C23 A24

D4 C4 A3 B3 C2 C1 E5

F5 G5 G6

H5

H6

J6 J5 J7

J8 L5 L6

M8

L8 P7

M7

P5

M5

R8 P8 R6 R5 P4 P3 T4 T3

AE3 AD4 AE2 AD3 AD1 AD2

V5

W6

U5 U6 U8 U7

AA8

Y8

AA7

Y7

AA5 AA6

W5

Y5

4

HT_RXCTL1N HT_RXCALP

HT_RXCALN

RS880M-GP

ANB1B

GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N

SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

RS880M-GP

PART 1 OF 6

71.RS880.M02

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

HT_TXCALP HT_TXCALN

GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

PCIE I/F GFX

PCE_CALRP PCE_CALRN

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

SB_TX2P

SB_TX2N

SB_TX3P

SB_TX3N

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24 B25

A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5

AC8 AB8

3

HT_TXCALN

GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3

TXP1 TXN1 TXP2 TXN2 TXP3 TXN3

ALINK_NBTX_SBRX_P0 ALINK_NBTX_SBRX_N0 ALINK_NBTX_SBRX_P1 ALINK_NBTX_SBRX_N1 ALINK_NBTX_SBRX_P2 ALINK_NBTX_SBRX_N2 ALINK_NBTX_SBRX_P3 ALINK_NBTX_SBRX_N3

PCE_PCAL PCE_NCAL

Place < 100mils from pin AC8 and AB8

3

HT_NB_CPU_CAD_H0 4 HT_NB_CPU_CAD_L0 4 HT_NB_CPU_CAD_H1 4 HT_NB_CPU_CAD_L1 4 HT_NB_CPU_CAD_H2 4 HT_NB_CPU_CAD_L2 4 HT_NB_CPU_CAD_H3 4 HT_NB_CPU_CAD_L3 4 HT_NB_CPU_CAD_H4 4 HT_NB_CPU_CAD_L4 4 HT_NB_CPU_CAD_H5 4 HT_NB_CPU_CAD_L5 4 HT_NB_CPU_CAD_H6 4 HT_NB_CPU_CAD_L6 4 HT_NB_CPU_CAD_H7 4 HT_NB_CPU_CAD_L7 4

HT_NB_CPU_CAD_H8 4 HT_NB_CPU_CAD_L8 4 HT_NB_CPU_CAD_H9 4 HT_NB_CPU_CAD_L9 4 HT_NB_CPU_CAD_H10 4 HT_NB_CPU_CAD_L10 4 HT_NB_CPU_CAD_H11 4 HT_NB_CPU_CAD_L11 4 HT_NB_CPU_CAD_H12 4 HT_NB_CPU_CAD_L12 4 HT_NB_CPU_CAD_H13 4 HT_NB_CPU_CAD_L13 4 HT_NB_CPU_CAD_H14 4 HT_NB_CPU_CAD_L14 4 HT_NB_CPU_CAD_H15 4 HT_NB_CPU_CAD_L15 4

HT_NB_CPU_CLK_H0 4 HT_NB_CPU_CLK_L0 4 HT_NB_CPU_CLK_H1 4 HT_NB_CPU_CLK_L1 4

HT_NB_CPU_CTL_H0 4 HT_NB_CPU_CTL_L0 4 HT_NB_CPU_CTL_H1 4 HT_NB_CPU_CTL_L1 4

1 2

C87 SCD1U16V2KX-3GPC87 SCD1U16V2KX-3GP

1 2

C88 SCD1U16V2KX-3GPC88 SCD1U16V2KX-3GP

1 2

C89 SCD1U16V2KX-3GPC89 SCD1U16V2KX-3GP

1 2

C90 SCD1U16V2KX-3GPC90 SCD1U16V2KX-3GP

1 2

C91 SCD1U16V2KX-3GPC91 SCD1U16V2KX-3GP

1 2

C92 SCD1U16V2KX-3GPC92 SCD1U16V2KX-3GP

1 2

C93 SCD1U16V2KX-3GPC93 SCD1U16V2KX-3GP

1 2

C94 SCD1U16V2KX-3GPC94 SCD1U16V2KX-3GP

1 2

C95 SCD1U16V2KX-3GPC95 SCD1U16V2KX-3GP

1 2

C96 SCD1U16V2KX-3GPC96 SCD1U16V2KX-3GP

1 2

C97 SCD1U16V2KX-3GPC97 SCD1U16V2KX-3GP

1 2

C98 SCD1U16V2KX-3GPC98 SCD1U16V2KX-3GP

1 2

C501 SCD1U16V2KX-3GPC501 SCD1U16V2KX-3GP

1 2

C502 SCD1U16V2KX-3GPC502 SCD1U16V2KX-3GP

1 2

C99 SCD1U16V2KX-3GPC99 SCD1U16V2KX-3GP C100 SCD1U16V2KX-3GPC100 SCD1U16V2KX-3GP C101 SCD1U16V2KX-3GPC101 SCD1U16V2KX-3GP C102 SCD1U16V2KX-3GPC102 SCD1U16V2KX-3GP C103 SCD1U16V2KX-3GPC103 SCD1U16V2KX-3GP C104 SCD1U16V2KX-3GPC104 SCD1U16V2KX-3GP C105 SCD1U16V2KX-3GPC105 SCD1U16V2KX-3GP C106 SCD1U16V2KX-3GPC106 SCD1U16V2KX-3GP

1 2

R57 1K27R2F-L-GPR57 1K27R2F-L-GP

1 2

R58 2KR2F-3-GPR58 2KR2F-3-GP

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

R56

R56 301R2F-GP

301R2F-GP

PCIE_TXP1 23

PCIE_TXN1 23

PCIE_TXP2 26

PCIE_TXN2 26

PCIE_TXP3 26

PCIE_TXN3 26

ALINK_NBTX_C_SBRX_P0 12 ALINK_NBTX_C_SBRX_N0 12 ALINK_NBTX_C_SBRX_P1 12 ALINK_NBTX_C_SBRX_N1 12 ALINK_NBTX_C_SBRX_P2 12 ALINK_NBTX_C_SBRX_N2 12 ALINK_NBTX_C_SBRX_P3 12 ALINK_NBTX_C_SBRX_N3 12

1D1V_S0

2

HDMI_DATA2+ 21 HDMI_DATA2- 21 HDMI_DATA1+ 21 HDMI_DATA1- 21 HDMI_DATA0+ 21 HDMI_DATA0- 21 HDMI_CLK+ 21 HDMI_CLK- 21

2

1

RS880M Display Port Support (muxed on GFX)

DP0

DP1

GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1

LAN

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M_HT LINK&PCIe(1/4)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

of

842Tuesday, January 26, 2010

of

842Tuesday, January 26, 2010

of

842Tuesday, January 26, 2010

1

-1

5

R59

PLT_RST#12,29,30

D D

CPU_LDT_STOP#6,12

C C

NB_ALLOW_LDTSTOP12

1D8V_S0

L5

B B

1 2

220ohm 200mA

SBK160808T-221Y-N-GP

1D8V_S0

L6

1 2

220ohm 200mA

SBK160808T-221Y-N-GP

1 2

0R0402-PAD

1 2 3

74LVC1G08GW-1-GP

73.01G08.L04

73.7SZ08.DAH

VDDA18HTPLL

12

VDDA18PCIEPLL

12

B A GND

1D8V_S0

12

R69

R69 1KR2F-3-GP

1KR2F-3-GP

SB Change R71 from bead 470 ohm to RES 3.9 ohm

C579

C579 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

C580

C580 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

SYSREST#

12

C109

C109 SC220P50V2KX-3GP

SC220P50V2KX-3GP

1D8V_S0

U58

5

VCC

NB_ALLOW_LDTSTOP

Y

4

1D8V_S0

NB_LDT_STOP#

1D1V_S0

220ohm 200mA

R71

1 2

3D9R3-GP

1D8V_S0

12

TC1

L2

1 2

SBK160808T-221Y-N-GP

12

C120

DY

4

1ST 68.00217.711

2ND = 68.00119.111

1 2

SBK160808T-221Y-N-GP

220ohm 200mA

ST100U6D3VBML1GP

77.C1071.081

1

23

RN130

RN130 SRN150F-GP

SRN150F-GP

4

12

SC10U6D3V5MX-3GP

3D3V_S0

1 2

SBK160808T-221Y-N-GP

1D8V_S0

R65

CRT_GREEN

12

CRT_DDCCLK20 CRT_DDCDATA20

1D1V_S0_PLLVDD

12

C577

C577 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

C578

C578 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

1D1V_S0

RN5

1 2 3

SRN1KJ-7-GP

CLK_DDC_EDID19 DAT_DDC_EDID19

GMCH_HDMI_DATA21

GMCH_HDMI_CLK21

L1

220ohm 200mA

C110

CRT_BLUE CRT_RED

140R2F-GP

4

C110

12

SC1U10V2KX-1GP

R68

3D3V_S0_AVDD

12

C574

C574 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

12

C575

C575 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

1D8V_S0_AVDDQ

Close to NB ball

CRT_RED20 CRT_GREEN20 CRT_BLUE20

CRT_HSYNC20 CRT_VSYNC20

R70

1 2

715R2F-GP

1D8V_S0_PLVDD18

VDDA18HTPLL

VDDA18PCIEPLL

CLK_NBHT_CLK3 CLK_NBHT_CLK#3

SYSREST# NB_LDT_STOP#

NB_ALLOW_LDTSTOP

NB_REFCLK_N

CLK_NB_GFX CLK_NB_GFX#

CLK_NB_GPPSB3 CLK_NB_GPPSB#3

GMCH_HDMI_DATA GMCH_HDMI_CLK

RS780_AUX_CAL

12

NB_PWRGD13

CLK_NB_14M3

CLK_NB_GFX3 CLK_NB_GFX#3

3

SB Add C598 for solve CRT flicker issue

12

C598

C598 SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

-1 Change R60,R62 to RN136.

ANB1C

F12

AVDD1

E12

AVDD2

F14

AVDDDI

G15

AVSSDI

H15

AVDDQ

H14

AVSSQ

E17

C_Pr

F17

Y

F15

COMP_Pb

G18

RED

G17

REDb

E18

GREEN

F18

GREENb

E19

BLUE

F19

BLUEb

A11

DAC_HSYNC

B11

DAC_VSYNC

F8

DAC_SCL

E8

DAC_RSET

R74

R74 150R2F-1-GP

150R2F-1-GP

DAC_SDA

G14

DAC_RSET

A12

PLLVDD

D14

PLLVDD18

B12

PLLVSS

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESET#

A10

POWERGOOD

C10

LDTSTOP#

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN

F11

REFCLK_N

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP

V3

GPPSB_REFCLKN

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_CLK0/AUX0P

A8

DDC_DATA0/AUX0N

B7

DDC_CLK1/AUX1P

A7

DDC_DATA1/AUX1N

B10

STRP_DATA

G11

RESERVED

C8

AUX_CAL

RS880M-GP

3D3V_S0

4

RN136

RN136 SRN4K7J-8-GP

SRN4K7J-8-GP

1

2 3

CRT_VSYNC CRT_HSYNC

PART 3 OF 6

DDC_DATA0/AUX0N DDC_CLK0/AUX0P

CRT/TVOUT

LVTM

PM

CLOCKs PLL PWR

MIS.

2

Enables the Test Debug Bus using GPIO. RS880M

1 Disable 0 Enable

RS880M: Enables Side port memory

RS880M:HSYNC# Selects if Memory SIDE PORT is available or not

1 = Memory Side port Not available 0 = Memory Side port available Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]

TXOUT_L0P

TXOUT_L0N

TXOUT_L1P

TXOUT_L1N

TXOUT_L2P

TXOUT_L2N

TXOUT_L3P

TXOUT_L3N TXOUT_U0P

TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXCLK_LP TXCLK_LN TXCLK_UP

TXCLK_UN

VDDLTP18 VSSLTP18

VDDLT18_1 VDDLT18_2 VDDLT33_1 VDDLT33_2

VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7

LVDS_DIGON

LVDS_BLON

LVDS_ENA_BL

TMDS_HPD

HPD

SUS_STAT#

THERMALDIODE_P THERMALDIODE_N

TESTMODE

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

A13 B13

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

E9 F7 G12

D9 D10

D12 AE8

AD8

TESTMODE_NB

D13

LVDS_TXAOUT0+ 19 LVDS_TXAOUT0- 19 LVDS_TXAOUT1+ 19 LVDS_TXAOUT1- 19 LVDS_TXAOUT2+ 19 LVDS_TXAOUT2- 19

LVDS_TXACLK+ 19 LVDS_TXACLK- 19

C576

SC4D7U6D3V3KX-GP

SUS_STAT#

C576

1

4

TP39 TPAD14-GPTP39 TPAD14-GP

12

1D8V_S0_VDDLT18

12

23

RN6

RN6 SRN10KJ-5-GP

SRN10KJ-5-GP

HDMI_DETECT 21

SUS_STAT# 13

R73

R73 1K8R2F-GP

1K8R2F-GP

C119

C119 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

GMCH_LCDVDD_ON 19 BRIGHTNESS_AMD 19 KBC_BL_ON_IN 29

1

L33

1 2

BLM18PG471SN1D-GP

1D8V_S0

A A

5

1 2

4

R101

R101 301R2F-GP

301R2F-GP

NB_PWRGD

3

2

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M_video_STRAP(2/4)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

of

942Monday, February 01, 2010

of

942Monday, February 01, 2010

of

942Monday, February 01, 2010

1

-1

5

ANB1D

SPM_A0 SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5

D D

100R2F-L1-GP-U

R282

1 2

R82 40D2R2F-GPR82 40D2R2F-GP

1 2

R83 40D2R2F-GPR83 40D2R2F-GP

1D5V_S0

C C

B B

A A

1 2

SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13

SPM_BA0 SPM_BA1 SPM_BA2

SPM_RAS# SPM_CAS# SPM_WE# SPM_CS# SPM_CKE SPM_ODT

SPM_CLKN

SPM_COMPP SPM_COMPN

AB12

MEM_A0

AE16

MEM_A1

V11

MEM_A2

AE15

MEM_A3

AA12

MEM_A4

AB16

MEM_A5

AB14

MEM_A6

AD14

MEM_A7

AD13

MEM_A8

AD15

MEM_A9

AC16

MEM_A10

AE13

MEM_A11

AC14

MEM_A12

Y14

MEM_A13

AD16

MEM_BA0

AE17

MEM_BA1

AD17

MEM_BA2

W12

MEM_RAS#

Y12

MEM_CAS#

AD18

MEM_WE#

AB13

MEM_CS#

AB18

MEM_CKE

V14

MEM_ODT

V15

MEM_CKP

W14

MEM_CKN

AE12

MEM_COMPP

AD12

MEM_COMPN

RS880M-GP

SCD1U10V2KX-4GP

4

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC

MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11

MEM_DQS0P/DVO_IDCKP MEM_DQS0N/DVO_IDCKN

SBD_MEM/DVO_I/F

1D5V_S0

C133

12

C134

2 3

12

CLOSE TO NB

SPM_DQ0

AA18

SPM_DQ1

AA20

SPM_DQ2

MEM_DQ4

MEM_DM0

IOPLLVDD

IOPLLVSS

AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

SPM_DQ3 SPM_DQ4 SPM_DQ5 SPM_DQ6 SPM_DQ7 SPM_DQ8 SPM_DQ9 SPM_DQ10 SPM_DQ11 SPM_DQ12 SPM_DQ13 SPM_DQ14 SPM_DQ15

SPM_DQS0P SPM_DQS0N SPM_DQS1P SPM_DQS1N

SPM_DM0 SPM_DM1

IOPLLVDD18 IOPLLVDDSPM_CLKP

SPM_VREF

MEM_DQ2/DVO_DE

MEM_DQ3/DVO_D0 MEM_DQ5/DVO_D1

MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3

MEM_DQ9/DVO_D5 MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7

MEM_DQ12

MEM_DQ13/DVO_D9

MEM_DQS1P

MEM_DQS1N

MEM_DM1/DVO_D8

IOPLLVDD18

MEM_VREF

4

RN137

SRN1KJ-7-GP

1

SPM_VREF

-1 Change R84,R85 to RN137.

3

MEM_COMP_P and MEM_COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions

R80 BLM15AG121SN-1GPR80 BLM15AG121SN-1GP

1 2

R81 BLM15AG121SN-1GPR81 BLM15AG121SN-1GP

1 2

12

C131

C132

SC1U6D3V2KX-GP

R87

243R2F-2-GP

SC1U6D3V2KX-GP

SCD1U16V2ZY-2GP

12

C135

SCD1U16V2ZY-2GP

12

C136

SC1U6D3V2KX-GP

12

C137

1D5V_S0 1D5V_S0

-1 Change R76,R78 to RN138. -1 Change R77,R79 to RN139.

C127

C129

12

SCD1U10V2KX-4GP

CLOSE TO SDRAM

1D5V_S0

1D8V_S0

1D1V_S0

SPM_VREF2 SPM_VREF1

SPM_A0

12

SPM_A1 SPM_A2 SPM_A3 SPM_A4 SPM_A5 SPM_A6 SPM_A7 SPM_A8 SPM_A9 SPM_A10 SPM_A11 SPM_A12 SPM_A13

SPM_BA0 SPM_BA1 SPM_BA2

SPM_CLKP SPM_CLKN

SPM_CKE

SPM_DM1 SPM_DM0

SPM_WE# SPM_CAS# SPM_RAS#

1D5V_S0

SC1U6D3V2KX-GP

12

C138

DY

12

C139

SC10U6D3V5MX-3GP

C140

C140 SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

-1 DY C139,Change C140 to 22uF.

2

4

RN138

RN138 SRN1KJ-7-GP

SRN1KJ-7-GP

1

2 3

U3

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

H5TQ1G63BFR-12C-GP

VR.1GB0G.004

2nd = VR.1GB0B.006

2nd = VR.1GB0B.006 3rd = VR.1GB0T.002

3rd = VR.1GB0T.002

C128

C130

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

ODT

CS#

RESET#

NC#T7

NC#L9 NC#L1 NC#J9 NC#J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

12

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

SJV10-NL

SPM_DQS1P SPM_DQS1N

SPM_DQS0P SPM_DQS0N

SPM_ODT

SPM_CS#

SCD1U10V2KX-4GP

SPM_VREF1 SPM_VREF2

SCD1U10V2KX-4GP

4

1

2 3

SPM_DQ2 SPM_DQ1 SPM_DQ5 SPM_DQ3 SPM_DQ7 SPM_DQ0 SPM_DQ4 SPM_DQ6

SPM_DQ13

SPM_DQ8 SPM_DQ10 SPM_DQ12 SPM_DQ15 SPM_DQ11 SPM_DQ14

SPM_DQ9

RN139

RN139 SRN1KJ-7-GP

SRN1KJ-7-GP

1D5V_S0

12

R86

R86 10KR2J-3-GP

10KR2J-3-GP

DDR3_RST# 13

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M SIDE PORT(3/4)

Size Document Number Rev

A3

Date: Sheet

5

4

3

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

-1

of

10 42Wednesday, January 27, 2010

of

10 42Wednesday, January 27, 2010

of

10 42Wednesday, January 27, 2010

1

-1

5

1D1V_S0

D D

1D1V_S0

12

C C

1D8V_S0

80mil Width

12

1D8V_S0

12

0.6A per ANT Rev1.1, Page3

C143

C141

12

C142

SC2D2U10V3KX-1GP

SCD1U10V2KX-4GP

12

0.45A per ANT Rev1.1, Page3

C151

SCD1U10V2KX-4GP

12

C144

SC2D2U10V3KX-1GP

C164

12

C150

SC2D2U10V3KX-1GP

C168

SC10U6D3V3MX-GP

C177

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

12

C165

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

12

C170

SCD1U10V2KX-4GP

1D8V_S0

12

C178

SC1U10V2KX-1GP

12

C171

C152

SCD1U10V2KX-4GP

12

C167

C166

12

SCD1U10V2KX-4GP

12

C172

SCD1U10V2KX-4GP

12

C173

SCD1U10V2KX-4GP

M16

G19

AE25 AD24 AC23 AB22 AA21

W19

M17

M10

AA9 AB9 AD9 AE9

AE11 AD11

K16 L16

P16 R16 T16

H18 F20

E21 D22 B23 A23

Y20 V18

U17 T17 R17 P17

P10 K10

L10

T10 R10

U10

J17

J10

W9

H9

Y9

F9

G9

4

ANB1E

VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2

RS880M-GP

PART 5/6

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

POWER

VDD_MEM1

VDD_MEM2

VDD_MEM3

VDD_MEM4

VDD_MEM5

VDD_MEM6

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD33_1 VDD33_2

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

3

300mil Width

12

C146

SCD1U10V2KX-4GP

DY

1103

10A per ANT Rev1.1, Page3

1D1V_S0

12

C147

SC1U10V2KX-1GP

Per check list (Rev 0.02) RS780M: 1V ~ 1.1V, check PWR team

12

C155

C154

SCD1U10V2KX-4GP

DY

3D3V_S0

12

C585

SCD22U10V2KX-1GP

12

C157

C156

SCD1U10V2KX-4GP

1D5V_S0

12

C174

12

C595

SCD22U10V2KX-1GP

12

C158

SCD1U10V2KX-4GP

SC10U6D3V3MX-GP

C149

12

C148

SC1U10V2KX-1GP

12

C159

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

12

C582

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

12

C581

SC2D2U10V3KX-1GP

1D1V_S0

12

C161

C160

SCD22U10V2KX-1GP

12

C583

C584

SCD22U10V2KX-1GP

SC2D2U10V3KX-1GP

2

12

C162

SC10U6D3V3MX-GP

A25 D23 E22 G22 G24 G25 H19

M20 N22 P20 R19 R22 R24 R25 H20 U22

V19 W22 W24 W25

Y21

AD25

M14

N13

P12

P15

R11

R14

U14

U11

U15

V12 W11 W15

AC12 AA14

Y18

AB11 AB15 AB17 AB19 AE20 AB21

K11

J22 L17 L22 L24 L25

L12

T12

ANB1F

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

RS880M-GP

PART 6/6

GROUND

1

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

B B

A A

5

4

3

2

SJV10-NL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M PWR&GND(4/4)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

SJV10-NL

of

11 42Tuesday, January 05, 2010

of

11 42Tuesday, January 05, 2010

of

11 42Tuesday, January 05, 2010

1

-1

5

PCIE_RST#_R23,26

PLT_RST#9,29,30

C181 SCD1U16V2KX-3GPC181 SCD1U16V2KX-3GP

ALINK_NBRX_SBTX_P08 ALINK_NBRX_SBTX_N08 ALINK_NBRX_SBTX_P18 ALINK_NBRX_SBTX_N18 ALINK_NBRX_SBTX_P28 ALINK_NBRX_SBTX_N28

D D

ALINK_NBRX_SBTX_P38 ALINK_NBRX_SBTX_N38

1 2

C186 SCD1U16V2KX-3GPC186 SCD1U16V2KX-3GP

1 2

C187 SCD1U16V2KX-3GPC187 SCD1U16V2KX-3GP

1 2

C182 SCD1U16V2KX-3GPC182 SCD1U16V2KX-3GP

1 2

C183 SCD1U16V2KX-3GPC183 SCD1U16V2KX-3GP

1 2

C184 SCD1U16V2KX-3GPC184 SCD1U16V2KX-3GP

1 2

C188 SCD1U16V2KX-3GPC188 SCD1U16V2KX-3GP

1 2

C185 SCD1U16V2KX-3GPC185 SCD1U16V2KX-3GP

1 2

PCIE_VDDR

Place R <100mils form pins T25,T24

C C

B B

A A

-1 Change C193 to 12pF.

SC12P50V2JN-3GP

12

C193

5

2 3 1

ALINK_NBTX_C_SBRX_P08 ALINK_NBTX_C_SBRX_N08 ALINK_NBTX_C_SBRX_P18 ALINK_NBTX_C_SBRX_N18 ALINK_NBTX_C_SBRX_P28 ALINK_NBTX_C_SBRX_N28 ALINK_NBTX_C_SBRX_P38 ALINK_NBTX_C_SBRX_N38

R94 562R2F-GPR94 562R2F-GP R90 2K05R2F-GPR90 2K05R2F-GP

SB Change R43 from Dummy to 1M ohm.

X3

1 2

XTAL-25MHZ-102-GP

82.30020.851

2ND = 82.30020.A31

-1 Change R89,R88 to RN140.

SRN33J-5-GP-U

RN140

PCIE_RST#

ALINK_NBRX_C_SBTX_P0 ALINK_NBRX_C_SBTX_N0 ALINK_NBRX_C_SBTX_P1 ALINK_NBRX_C_SBTX_N1 ALINK_NBRX_C_SBTX_P2 ALINK_NBRX_C_SBTX_N2 ALINK_NBRX_C_SBTX_P3 ALINK_NBRX_C_SBTX_N3

PCIE_CALRN

CLK_PCIE_SB3 CLK_PCIE_SB#3

R43

1MR2F-GP

1 2 1 2

12

4

1 2

C191

C191 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

A_RST#

PCIE_CALRP

25M_X1

25M_X2

4

ASB1A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

SB820M-GP

71.SB820.M03

4

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

REQ2#/CLK_REQ8#/GPIO41

PCI INTERFACELPC

REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

ALLOW_LDTSTP/DMA_ACTIVE#

CLOCK GENERATOR

CPU

RTC

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR# REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44 GNT2#/GPO45

CLKRUN#

LOCK#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

PROCHOT#

LDT_PG LDT_STP# LDT_RST#

32K_X1 32K_X2

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

GAP-OPEN

SB Add G122.

G122

3

TPAD14-GP

TP38

PCI_CLK0_R

W2

PCI_CLK1

W1

PCI_CLK2

W3

PCI_CLK3

W4

PCI_CLK4

Y1 V2

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1

SB820 CSL 25-35:* Note: If PCI interface is not used,

AD1 AD2

then these balls can be used for alternate GPIO/GPO function

AC6 AE2

or left not connected.

AE1 AF8 AE3 AF1 AG1 AF2

PCI_AD23

AE9

PCI_AD24

AD9

PCI_AD25

AC11

PCI_AD26

AF6

PCI_AD27

AF4

PCI_AD28

AF3

PCI_AD29

AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19

G21 H21 K19 G22 J24

C1 C2 D2

B2 B1

VRAM_IDENT1 VRAM_IDENT2

GPIO34,35 internal pull high

VRAM_IDENT1 VRAM_IDENT2

LPCCLK0_R LPCCLK1_R

LDRQ0#

INT_SERIRQ 29

NB_ALLOW_LDTSTOP 9 PROCHOT#_SB 6 CPU_PWRGD 6,41

CPU_LDT_STOP# 6,9

CPU_LDT_RST# 6,41

RTC_X1 RTC_X2

RTC_CLK 28

RTC_AUX_S5

12

C192

2 1

3

TP38

PCI_CLK1 16 PCI_CLK2 16

PCI_CLK3 16

PCI_CLK4 16

PCI_AD23 16 PCI_AD24 16 PCI_AD25 16 PCI_AD26 16 PCI_AD27 16 PCI_AD28 16 PCI_AD29 16

-1 Add VRAM identify pins.

3D3V_S0 3D3V_S0

12

R331

1KR2F-3-GP

DY_HYNIX_ATI

12

R332

1KR2F-3-GP

DY_SAMSUNG

LPCCLK0_R 16 LPCCLK1_R 16

1

10MR2J-L-GP

12

C194

SCD1U16V2ZY-2GP

2 3

R97

LPC_LAD0 29,30 LPC_LAD1 29,30 LPC_LAD2 29,30 LPC_LAD3 29,30

LPC_LFRAME# 29,30

TP53 TPAD14-GPTP53 TPAD14-GP

SC1U10V2KX-1GP

VRAM_IDENT1

12

2

12

R334

1KR2F-3-GP

DY_SAMSUNG_ATI

12

R333

1KR2F-3-GP

DY_HYNIX

12

R96

R96 10KR2J-3-GP

10KR2J-3-GP

DY

RN7

SRN22-3-GP

4

1

SC15P50V2JN-2-GP

PM_CLKRUN# 29

EC3

EC3 EC4

EC4

C189

SC15P50V2JN-2-GP

X-32D768KHZ-34GPU

82.30001.661

82.30001.B21

2 3

12

C190

2

HYNIX VR.1GB0G.004

DEFAULT

LOW HIGHVRAM_IDENT2

RTC_AUX_S5

1 2

DY

SC22P50V2JN-4GP

1 2

SC22P50V2JN-4GP

DY

12

X2

SAMSUNG VR.1GB0B.006

ATI VR.1GB0T.002

HIGHHIGH LOW

HIGH

3D3V_AUX_S5

BAS16-1-GP

83.00016.B11

2ND = 83.00016.K11

3RD = 83.00016.F11

D30

2

3

1

1 2

R99

510R2J-1-GP

BAS40CW-GP

83.00040.E81

510R2J-1-GP

SB Add RTC charge circuit.

PCLK_FWH 30

PCLK_KBC 29

SB Change C189 to 22pF, C190 to 15pF.

-1 Change C189 to 15pF.

SJV10-NL

Title

ATi-SB820M_PCIE&PCI_(1/5)

Size Document Number Rev

A3

Date: Sheet

SJV10-NL

1

R861

3

RTC_BAT_R

12

1

2

MLX-CON2-13-GP

3 1

2 4

20.F1035.002

20.F0772.002

12 42Monday, February 01, 2010

of

RTC1

D31

1KR2J-1-GP

RTC_BAT_DRTC_BAT_DR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

5

PM_SLP_S3#19,27,28,29,35 PM_SLP_S4#29,35 PM_PWRBTN#29,41 SB_PWRGD27

TPAD14-GP

TPAD14-GP TPAD14-GP

D D

3D3V_S5

RN8

1

8

2

7

3

6

45

SRN10KJ-6-GP

3D3V_S0

4

RN37

RN37 SRN2K2J-1-GP

SRN2K2J-1-GP

1

C C

ACZ_SDATAOUT_R16

2 3

SMBC0_SB SMBD0_SB

3D3V_S0

3D3V_S5

TPAD14-GP TPAD14-GP

TPAD14-GP

PM_SLP_S4# ECSCI# PM_SLP_S3# EC_SWI#

SMBC0_SB 3,17,18 SMBD0_SB 3,17,18

RN9

1

8

2

7

3

6

45

SRN10KJ-6-GP

TP110

TP110 TP111

TP111 TP112

TP112

TP63

SUS_STAT# USB_OC#

PCIE_WAKE#

SB_TEST0 SB_TEST1 SB_TEST2

KA20GATE29 KBRCIN#29

ECSCI#29

SUS_STAT#9

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

PCIE_WAKE#23,26

NB_PWRGD9

ACZ_SPKR22

SB820 CSL 55-125:connect to side port

DDR3_RST#10

TP60

TP60 TP62

TP62

EC_SWI#29

USB_OC#

4

TP61TP61

NB_PWRGD

RSMRST#_SB

RI#

1

SUS_STAT#

ECSMI#_KBC GEVENT5# SYS_RST#

SMBC0_SB SMBD0_SB

ASB1D

J2

PCI_PME#/GEVENT4#

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_BTN#

H5

PWR_GOOD

G6

SUS_STAT#

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0#

AE21

KBRST#/GEVENT1#

K2

LPC_PME#/GEVENT3#

J29

LPC_SMI#/GEVENT23#

H2

GEVENT5#

J1

SYS_RESET#/GEVENT19#

H6

WAKE#/GEVENT8#

F3

IR_RX1/GEVENT20#

J6

THRMTRIP#/SMBALERT#/GEVENT2#

AC19

NB_PWRGD

G1

RSMRST#

AD19

CLK_REQ4#/SATA_IS0#/GPIO64

AA16

CLK_REQ3#/SATA_IS1#/GPIO63

AB21

SMARTVOLT1/SATA_IS2#/GPIO50

AC18

CLK_REQ0#/SATA_IS3#/GPIO60

AF20

SATA_IS4#/FANOUT3/GPIO55

AE19

SATA_IS5#/FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO227

F4

SDA1/GPIO228

AH21

CLK_REQ2#/FANIN4/GPIO62

AB18

CLK_REQ1#/FANOUT4/GPIO61

E1

IR_LED#/LLB#/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

H4

DDR3_RST#/GEVENT7#

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9#

G5

GBE_LED2/GEVENT10#

K3

GBE_STAT0/GEVENT11#

AA20

CLK_REQG#/GPIO65/OSCIN/IDLEEXT#

H3

BLINK/USB_OC7#/GEVENT18#

D1

USB_OC6#/IR_TX1/GEVENT6#

E4

USB_OC5#/IR_TX0/GEVENT17#

D4

USB_OC4#/IR_RX0/GEVENT16#

E8

USB_OC3#/AC_PRES/TDO/GEVENT15#

F7

USB_OC2#/TCK/GEVENT14#

E7

USB_OC1#/TDI/GEVENT13#

F8

USB_OC0#/TRST#/GEVENT12#

Part 4 of 5

3

USBCLK/14M_25M_48M_OSC

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P USB_HSD13N

USB 1.1USB MISCEMBEDDED CTRL

USB_HSD12P

USB 2.0

USB_HSD12N

USB_HSD11P

USB_HSD11N USB_HSD10P

USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

ACPI / WAKE UP EVENTS

GPIO

USB OC

A10 G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

CLK48_USB

USB_PCOMP

1 2

R102

R102 11K8R2F-GP

11K8R2F-GP

1%

Place R near pin14. Route it with 10mils Trace width and 25mils spacing to any signals in X, Y, Z directions.

USBPP12 26 USBPN12 26

USBPP11 26 USBPN11 26

USBPP9 19 USBPN9 19

USBPP7 31 USBPN7 31

USBPP6 31 USBPN6 31

USBPP5 31 USBPN5 31

USBPP4 25 USBPN4 25

USBPP1 26 USBPN1 26

USBPP0 31 USBPN0 31

2

1 2

DY

R103

R103 10KR2J-3-GP

10KR2J-3-GP

CLK48_USB_R2

SC10P50V2JN-4GP

CLK48_USB 3

1 2

DY

C195

USB

Pair

Device

USB1(HS)

0

1

MINICARD1

NC

2

NC

3

4

Cardreader

USB2

5

USB3

6

Blue Tooth

7

89NC

WECAM

10

NC

11

MINIC2(3G sim)

1213MINIC2(3G)

NC

1

ACZ_RST#_AUDIO22

ACZ_SDATAOUT_AUDIO22

ACZ_SDATAIN022

ACZ_SYNC_AUDIO22 ACZ_BITCLK_AUDIO22

B B

12

EC47

DY

SC33P50V2JN-3GP

DY

RN49

4 5 3 2 1

SRN33J-7-GP

3D3V_S5

6 7 8

R117

1 2

ACZ_BIT_CLK

ACZ_SDATAOUT_R

ACZ_SYNC_R

ACZ_RST#_R

10KR2J-3-GP

-1 Reserve EC47 for EMI issue.

RN46

4 5 3

6

2

7

1

3D3V_S5

A A

5

8

SRN10KJ-6-GP

4

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST#

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2#/GBE_STAT2/GPIO166

G29

FC_RST#/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

SB820M-GP

71.SB820.M03

HD AUDIO

GBE LAN

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217

KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

EMBEDDED CTRL

3

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

Strap Pin / define to us e LP C or SPI ROM

SB_GPO199 16 SB_GPO200 16

1KR2J-1-GP

12

R238

D22

3

RSMRST#_KBC29

3D3V_AUX_S5

4

RN43

RN43 SRN10KJ-5-GP

SRN10KJ-5-GP

1

2 3

S5_PWR_GD#

S5_PWR_GD

SB Change S5_PWR_GD pull high from R261 to RN43.

2

1

BAS16-6-GP

83.00016.F11

DY

SJV10-NL

Title

Size Document Number Rev

A3

Date: Sheet

SB Del net RSMRST#_SB pull high.

RSMRST#_SB

12

R535

100KR2J-1-GP

U17

34 2

5

1

6

2N7002KDW-GP

84.2N702.A3F

2ND = 84.DM601.03F

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ATi-SB820M_USB&GPIO_(2/5)

SJV10-NL

1

13 42Tuesday, January 26, 2010

S5_PWR_GD 34

of

-1

Acer Aspire One AO721 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual