Acer Aspire One AO521 Schematics
1
2
3
4
5
6
7
8
ZH9 Block Diagram (AMD Nile Platform)
DDR III,800 MT/s
HDT
A A
P4
Geneva
AMD ASB2 CPU
K125 (Athlon SC) 12W HT1
K325 (Athlon DC) 12W HT1
(812 balls ; 27x27mm)
P2~5
Channel A
HyperTransport LINK
16x16
UNBUFFERED
DDRIII SODIMM
P15
LVDS CON
HDMI CON
B B
VGA CON
P16
P17
P16
LVDS MUX
TMDS(PCIE 4x1)
DAC
PCIE GEN1
0
2
1
C C
LAN-AR8152L
3G
WLAN/WiMAX
SIM CARD
P23
Bluetooth
P21
4
P23
2
P23
8
5
P18
RS880M
HyperTransport LINK0 CPU I/F
DX10 IGP
SIDE PORT MEMORY
LVDS
1X16 PCIE I/F
1X4 PCIE I/F WITH SB
6X1 PCIE I/F
(21x21mm)
P6~9
A-Link X4
SB820M
USB2.0(14)+1.1(2)
SATA III(6 PORTS)
4X1 PCIE GEN2 I/F
PCI/PCI BDGE
INT. RTC
INT. CLK
EC
HD AUDIO
DDRIII
HD AUDIO I/F
SATA II I/F
SIDE PORT
DDRIII 128MB
AZALIA CODEC
CX20672
Mobile 2.5" HDD
P19
P22
P6
Headphone Jack
MIC In Jack
Digital MIC
Speaker Header
P19
LPC I/F
ACPI 1.1
(23x23mm)
P10~14
LPC
5 IN1
CARDREADER
P24
CCD
P16
USB PORT
P20
USB PORT
P20
06731
USB PORT
(Left)(Lower Right) (Upper Right)
P20
USB 2.0
BATTERY CHAGER
P26
D D
SYSTEM
5V/3V PCU
P27
AMD CPU Core
CPU_NB Core
P28
1
NB CORE
DDR 1.5VSUS
+1.1V
(VLDT)
P29
P30
P31
2
+1.8V
Discharge/+2.5V/
VDDR
P32
P33
Thermal Protection
P34
EC
Winbond NPCE781L
P25
SMBUS
CPU
THERMAL SENSOR
P4
Quanta Computer Inc.
Quanta Computer Inc.
P4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
6
Date: Sheet of
7
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
PROJECT :
Block Diagram
Block Diagram
Block Diagram
ZH9
1 40Sunday, March 28, 2010
1 40Sunday, March 28, 2010
1 40Sunday, March 28, 2010
8
4A
4A
4A
P25
Charger
5
PWM FAN
P26
Keyboard
3
Touch Pad
P18 P18
4
SPI Flash
5
D D
HT_CADINP[15..0]<6>
HT_CADINN[15..0]<6>
HT_CLKINP[1..0]<6>
C C
B B
HT_CLKINN[1..0]<6>
HT_CTLINP[1..0]<6>
HT_CTLINN[1..0]<6>
HT_CADOUTP[15..0]<6>
HT_CADOUTN[15..0]<6>
HT_CLKOUTP[1..0]<6>
HT_CLKOUTN[1..0]<6>
HT_CTLOUTP[1..0]<6>
HT_CTLOUTN[1..0]<6>
HT_CADINP[15..0]
HT_CADINN[15..0]
HT_CLKINP[1..0]
HT_CLKINN[1..0]
HT_CTLINP[1..0]
HT_CTLINN[1..0]
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]
HT_CTLOUTN[1..0]
4
HT_CADINP15
HT_CADINN15
HT_CADINP14
HT_CADINN14
HT_CADINP13
HT_CADINN13
HT_CADINP12
HT_CADINN12
HT_CADINP11
HT_CADINN11
HT_CADINP10
HT_CADINN10
HT_CADINP9
HT_CADINN9
HT_CADINP8
HT_CADINN8
HT_CADINP7
HT_CADINN7
HT_CADINP6
HT_CADINN6
HT_CADINP5
HT_CADINN5
HT_CADINP4
HT_CADINN4
HT_CADINP3
HT_CADINN3
HT_CADINP2
HT_CADINN2
HT_CADINP1
HT_CADINN1
HT_CADINP0
HT_CADINN0
HT_CLKINP1
HT_CLKINN1
HT_CLKINP0
HT_CLKINN0
HT_CTLINP1
HT_CTLINN1
HT_CTLINP0
W7
W6
M2
M1
M8
M7
M3
M4
U6
U5
R7
R6
P6
P5
L6
L5
J6
J5
H4
H3
G6
G5
T3
T4
T2
T1
P3
P4
P2
P1
K3
K4
K2
K1
H2
H1
Y6
Y5
V2
V1
3
U16A
U16A
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
HT LINK
HT LINK
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
HT_CADOUTP15
AB6
HT_CADOUTN15
AB5
HT_CADOUTP14
AB9
HT_CADOUTN14
AB8
HT_CADOUTP13
AC7
HT_CADOUTN13
AC6
HT_CADOUTP12
AE6
HT_CADOUTN12
AE5
HT_CADOUTP11
AE9
HT_CADOUTN11
AE8
HT_CADOUTP10
AH3
HT_CADOUTN10
AH4
HT_CADOUTP9
AK3
HT_CADOUTN9
AK4
HT_CADOUTP8
AH1
HT_CADOUTN8
AH2
HT_CADOUTP7
Y1
HT_CADOUTN7
Y2
HT_CADOUTP6
Y4
HT_CADOUTN6
Y3
HT_CADOUTP5
AB1
HT_CADOUTN5
AB2
HT_CADOUTP4
AB4
HT_CADOUTN4
AB3
HT_CADOUTP3
AD4
HT_CADOUTN3
AD3
HT_CADOUTP2
AF1
HT_CADOUTN2
AF2
HT_CADOUTP1
AF4
HT_CADOUTN1
AF3
HT_CADOUTP0
AK1
HT_CADOUTN0
AK2
HT_CLKOUTP1
AF6
HT_CLKOUTN1
AF5
HT_CLKOUTP0
AD1
HT_CLKOUTN0
AD2
HT_CTLOUTP1
Y8
HT_CTLOUTN1
Y9
HT_CTLOUTP0
V4
HT_CTLOUTN0HT_CTLINN0
V3
2
1
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
PROJECT :
ASB2 HT I/F 1/4
ASB2 HT I/F 1/4
ASB2 HT I/F 1/4
ZH9
4A
4A
4A
2 40Sunday, March 28, 2010
2 40Sunday, March 28, 2010
2 40Sunday, March 28, 2010
1
A
B
C
D
E
Processor Memory Interface
U16C
P33
MB_ADD15
P31
MB_ADD14
AJ33
MB_ADD13
T32
MB_ADD12
T31
MB_ADD11
AD32
MB_ADD10
T33
MB_ADD9
V32
MB_ADD8
U33
MB_ADD7
V33
MB_ADD6
V31
MB_ADD5
W33
MB_ADD4
Y31
MB_ADD3
Y33
MB_ADD2
Y32
MB_ADD1
AC33
MB_ADD0
R33
MB_BANK2
AD33
MB_BANK1
AE33
MB_BANK0
K33
MB_CHECK7
K31
MB_CHECK6
G32
MB_CHECK5
F32
MB_CHECK4
L33
MB_CHECK3
K32
MB_CHECK2
H31
MB_CHECK1
G33
MB_CHECK0
J33
MB_DQS_H8
H32
MB_DQS_L8
AM14
MB_DQS_H7
AN14
MB_DQS_L7
AL20
MB_DQS_H6
AM20
MB_DQS_L6
AN26
MB_DQS_H5
AM26
MB_DQS_L5
AN30
MB_DQS_H4
AM30
MB_DQS_L4
D33
MB_DQS_H3
D32
MB_DQS_L3
B28
MB_DQS_H2
A28
MB_DQS_L2
A21
MB_DQS_H1
B20
MB_DQS_L1
B16
MB_DQS_H0
A15
MB_DQS_L0
AN22
MB_CLK_H7
AM22
MB_CLK_L7
AN21
MB_CLK_H6
AM21
MB_CLK_L6
AA32
MB_CLK_H5
AA33
MB_CLK_L5
AB33
MB_CLK_H4
AB32
MB_CLK_L4
AB31
MB_CLK_H3
AB30
MB_CLK_L3
AD31
MB_CLK_H2
AD30
MB_CLK_L2
C22
MB_CLK_H1
B22
MB_CLK_L1
A22
MB_CLK_H0
A23
MB_CLK_L0
N33
MB_CKE1
P32
MB_CKE0
AK31
MB1_ODT1
AH31
MB1_ODT0
AK32
MB0_ODT1
AH33
MB0_ODT0
AK33
MB1_CS_L1
AF33
MB1_CS_L0
AJ32
MB0_CS_L1
AF31
MB0_CS_L0
AF32
MB_RAS_L
AH32
MB_CAS_L
AG33
MB_WE_L
L32
MB_RESET_L
M33
FREE|MB_EVENT_L
BOM@ASB2_CPU
BOM@ASB2_CPU
U16C
MB_DM8
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
AN13
AL14
AL16
AN17
AN12
AM12
AM16
AN16
AL18
AN19
AM24
AN24
AM18
AN18
AL22
AN23
AM25
AL26
AN28
AL28
AL24
AN25
AN27
AM28
AM29
AL30
AL32
AL33
AK28
AN29
AM31
AM32
E33
D31
B31
A31
F33
F31
C32
B32
C30
A29
B26
A26
B30
A30
A27
C26
A24
B24
C18
A18
A25
C24
C20
A19
C16
A16
B14
A13
B18
A17
C14
A14
H33
AN15
AN20
AK26
AN31
C33
C28
A20
D14
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ASB2 DDRIII MEMORY 2/4
ASB2 DDRIII MEMORY 2/4
ASB2 DDRIII MEMORY 2/4
E
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
DDR III: CHANNEL B
DDR III: CHANNEL B
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
ZH9
ZH9
ZH9
4A
4A
3 40Sunday, March 28, 2010
3 40Sunday, March 28, 2010
3 40Sunday, March 28, 2010
4A
U16B
U16B
M_A_A15
P30
M29
AG28
P28
T30
AC28
P27
R26
R27
U28
V30
U27
Y30
AB29
W29
AC26
R29
AC29
AE28
K30
J29
G29
F29
L28
L29
H29
H27
J27
J26
AJ11
AK12
AG15
AH15
AH22
AG22
AG26
AH26
E28
F28
E25
F25
G17
H17
E12
F12
AK18
AJ17
AH17
AG17
Y28
Y27
AB27
AB26
W27
W26
P26
M26
D18
F19
E20
E19
M30
M28
AJ29
AF27
AJ30
AG29
AH29
AE29
AH30
AF29
AC27
AF30
AE27
L27
M32
BOM@ASB2_CPU
BOM@ASB2_CPU
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MA_DQS_H8
MA_DQS_L8
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_CLK_H7
MA_CLK_L7
MA_CLK_H6
MA_CLK_L6
MA_CLK_H5
MA_CLK_L5
MA_CLK_H4
MA_CLK_L4
MA_CLK_H3
MA_CLK_L3
MA_CLK_H2
MA_CLK_L2
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0
MA_CKE1
MA_CKE0
MA1_ODT1
MA1_ODT0
MA0_ODT1
MA0_ODT0
MA1_CS_L1
MA1_CS_L0
MA0_CS_L1
MA0_CS_L0
MA_RAS_L
MA_CAS_L
MA_WE_L
MA_RESET_L
FREE|MA_EVENT_L
M_A_A14
M_A_A13
M_A_A12
M_A_A11
4 4
M_A_BANK2<15>
M_A_BANK1<15>
M_A_BANK0<15>
3 3
2 2
1 1
M_A_DQSP7<15>
M_A_DQSN7<15>
M_A_DQSP6<15>
M_A_DQSN6<15>
M_A_DQSP5<15>
M_A_DQSN5<15>
M_A_DQSP4<15>
M_A_DQSN4<15>
M_A_DQSP3<15>
M_A_DQSN3<15>
M_A_DQSP2<15>
M_A_DQSN2<15>
M_A_DQSP1<15>
M_A_DQSN1<15>
M_A_DQSP0<15>
M_A_DQSN0<15>
M_A_CLKP1<15>
M_A_CLKN1<15>
M_A_CLKP2<15>
M_A_CLKN2<15>
M_A_CKE1<15>
M_A_CKE0<15>
M_A_ODT1<15>
M_A_ODT0<15>
M_A_CS#1<15>
M_A_CS#0<15>
M_A_RAS#<15>
M_A_CAS#<15>
M_A_WE#<15>
M_A_RST#<15>
MEMHOT_MA#<15>
<Layout note>
Route as 60 ohms with
5/10 W/S from CPU pins.
M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0
R285 *0/J_4R285 *0/J_4
DDR III: CHANNEL A
DDR III: CHANNEL A
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
AG11
AH11
AJ12
AJ14
AF11
AF12
AG12
AH12
AK14
AF15
AH19
AK20
AF14
AG14
AF17
AG19
AG20
AJ20
AF22
AK24
AF19
AF20
AJ23
AG23
AF23
AF25
AH27
AK30
AJ25
AG25
AJ26
AJ28
D28
G28
D26
E26
F30
E29
F27
H26
H25
D24
H22
E22
F26
G26
D22
G23
G22
G20
G15
F15
D20
F22
D16
E17
H15
H14
G12
H12
E15
E14
E11
F11
H30
AL12
AK16
AK22
AJ27
E27
E23
H19
G14
M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0
M_A_DM7
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DM3
M_A_DM2
M_A_DM1
M_A_DM0
<BOM Note>
V105 : AJ00105VT00
K125 : AJ0K125VT02
M_A_DQ[0..63] <15>M_A_A[0..15]<15>
M_A_DM[0..7] <15>
K325 : AJ0K325VT02
K625 : AJ0K625VT03
A
B
C
5
CPU Thermal monitor(THM)
<20100303(C3A)>
Reserve R266,C315,C316,U15,R276,R410 and stuff R51~R53,R48,Q7~Q9,D2,D3,R411, for AMD SB-TSI.
2ND_MBCLK<25>
D D
THERM_ALERT#<12>
C C
2ND_MBDATA CPU_SID
2ND_MBDATA<25>
3
+3V
+1.5VSUS
R51
R51
2.2K/J_4
2.2K/J_4
2
Q8
MMBT3904Q8MMBT3904
13
21
D3 RB501V-40D3 RB501V -40
+3V
2
1
Q17*2N7002K Q17*2N7002K
R276 *10K/J_4R276 *10K/J_ 4
THERM_OVERT#
R48
R48
2.2K/J_4
2.2K/J_4
2
Q7
MMBT3904Q7MMBT3904
13
21
D2 RB501V-40D2 RB501V -40
R275
R275
*10K/J_4
*10K/J_4
THERM_ALERT#_R
R53
R53
2.2K/J_4
2.2K/J_4
2
Q9
13
MMBT3904Q9MMBT3904
U15
U15
8
VCC
SCLK
7
DXP
SDA
6
DXN
ALERT#
4
GND
OVERT#
*G786P81U
*G786P81U
ADDRESS: 0x4C(98H)
(1001100)
+1.5VSUS
R50
R50
1K/J_4
1K/J_4
<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard
R42
R42
1K/J_4
1K/J_4
CPU FAN(THM)
FANSIG<25>
+5V
THERM_OVERT#
THERM_ALERT#
CPUFAN#<25>
R410 *0/J_4R410 *0/J_4
R411 *0/short_4R411 *0/short_4
+5V
B B
THERM_FAN#
1 3
R31 *0/short_6R3 1 *0/short_6
2
Q5
MMBT3904Q5MMBT3904
+5V_FANVCC
C29
C29
0.01U/25V_4
0.01U/25V_4
R34
R34
10K/J_4
10K/J_4
FAN_PWM_CN
4
+3V
R266
R266
*200/J_4
*200/J_4
C315
C315
*0.1U/10V _4
*0.1U/10V _4
+3V_THMVCC
1
2
3
5
+3V
FAN CONN
Follow PDC pin define
R52
R52
1K/J_4
1K/J_4
CPU_ALERT_LTHERM_ALERT#
R44
R44
10K/J_4
10K/J_4
C316
C316
*2200P/5 0V_4
*2200P/5 0V_4
CPU_SIC2ND_MBCLK
CN13
CN13
1
2
5
3
6
4
FAN CONN
FAN CONN
H_THERMDA
H_THERMDC
+2.5V
CLK_CPU_BCLKP<10>
CPU CLK
CLK_CPU_BCLKN<10>
+1.5VSUS
R324
R324
1K/F_4
1K/F_4
R311
R311
1K/F_4
1K/F_4
L37 3A/30ohm_ 6L37 3A/30ohm_6
C372
C372
180P/50V_4
180P/50V_4
Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"
CPU_M_VRE F
C344
C344
0.01U/25V_4
0.01U/25V_4
DCR:0.03ohm
CLK_CPU_BCLKP
CLK_CPU_BCLKN
1000P/50V_4
1000P/50V_4
3
W/S= 15 mil/20mil
+CPUVDDA
C361
C361
C351
C351
4.7U/6.3V _6
4.7U/6.3V _6
0.22U/6.3 V_4
0.22U/6.3 V_4
C367 3900P/25V_4C367 3900P/25 V_4
C366 3900P/25V_4C366 3900P/25 V_4
<20091202(A1A)_Confirm with AMD's Reden>
RSVD_SA0 is a VSS pin, so connect to GND.
C355
C355
CPU_PWRGD<10>
CPU_LDT_STOP #<8 ,10>
CPU_LDT_RST#<10>
CPU_VDD_FB _L<28>
CPU_VDD_FB _H<28>
CPU_VDDNB_ FB_H<28>
CPU_VDDIO_FB_H<30>
CPU_VDDR_F B_H<33>
R271 39.2/F_4R271 39.2/F_4
CLOSE TO CPU WITHIN 1"
T78T78
T79T79
T82T82
T8T8
T6T6
T59T59
C345
C345
3300P/50V_4
3300P/50V_4
W/S= 15 mil/20mil
+CPUVDDA
R314
R314
169/F_4
169/F_4
T60T60
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASS CLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST9_ANALOGIN
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3
CPU_TEST2
+CPUVDDA
CLK_CPU_BCLKP_C
CLK_CPU_BCLKN_C
CPU_PWRGD
CPU_LDT_STOP #
CPU_LDT_RST#
SideBand Temp sense I2C
CPU_SIC
CPU_SID
RSVD_SA0
CPU_ALERT_L
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_DBREQ #
CPU_VLDT_FB _H
CPU_M_VRE F
M_ZP
M_ZN
250mA
A8
VDDA_1
B8
VDDA_2
A6
CLKIN_H
A7
CLKIN_L
D10
PWROK
E9
LDTSTOP_L
F9
RESET_L
AN4
SIC
AN5
SID
AM2
RSVD_SA0
AN3
ALERT_L
AM8
TDI
AL8
TRST_L
AK8
TCK
AN8
TMS
G9
DBREQ_L
D2
VSS_SENSE
E2
VLDT_SENSE
E1
VDD_SENSE
D1
VDDNB_SENSE
D3
VDDIO_SENSE
C2
VDDR_SENSE
A11
M_VREF
AM9
M_ZN_H
AN9
M_ZN_L
A9
BYPASSCLK_H
B9
BYPASSCLK_L
A5
PLLTEST0
B6
PLLTEST1
G8
ANALOGIN
F8
BP3
C8
BP2
D9
BP1
E8
BP0
C6
ANALOG_T
AH7
DIECRACKMON
AK5
GATE0
AJ7
DRAIN0
<Visual Comment>
<Visual Comment>
U16D
U16D
MISC
MISC
RSVD|CORE_TYPE
THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L
DBRDY
RSVD3
CPU_PRESENT_L
HTREF1
HTREF0
FBCLKOUT_H
FBCLKOUT_L
SCANCLK1
TSTUPD
SCANSHIFTEN
SCANEN
SCANCLK2
PLLCHRZ_H
PLLCHRZ_L
SINGLECHAIN
BURNIN_L
ANALOGOUT
DIG_T
M_TEST
2
M31
C1
SVC
B2
SVD
AL6
AM5
AK6
AN6
AN7
TDO
H9
AM6
AJ9
V10
V9
B10
A10
AK7
AG8
AK9
AH9
AM7
G11
H11
AJ8
AM4
D7
B5
AG9
CPU_CORE_ TYPE
CPU_SVC_R
CPU_SVD_R
H_THERMDC
H_THERMDA
CPU_THERMTRIP_ L#
CPU_PROCHO T_L#
CPU_TDO
CPU_DBRDY
RSVD3
CPU_PRESENT_L
CPU_HTREF1
CPU_HTREF0
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKO UT_N
CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST28_H_PLLCHRZ_ P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST27_SINGLECHA IN
CPU_TEST26_BURNIN_L
CPU_TEST10_ANALOGOUT
CPU_TEST8_DIG_T
T58T58
Place them to CPU within 1.5"
R76 44.2/F_4R76 44 .2/F_4
R75 44.2/F_4R75 44 .2/F_4
CPU_THERMTRIP_ L#
+1.5VSUS
<Layout note>
Keep net PWRGD, LDT_STOP#, LDT_RST# no stub
CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP #
<20091029(A1A)_47337_ASB2_scl_nda_1.00>
CPU_PRESENT_L net are pulled up to VDDIO with 1Kohm
CPU_TEST20_SCANCLK2 and CPU_TEST21_SCANEN net are pulled down to GND with 1Kohm
CPU_PRESENT_L
CPU_DBREQ #
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST26_BURNIN_L
CPU_TEST27_SINGLECHA IN
T63T63
Route as 80ohm, diff
R310 80.6/F_4R310 80.6/F_4
CPU_PROCHO T_L#
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST25_L_BYPASS CLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST23_TSTUPD
CPU_TEST9_ANALOGIN
<20091202(A1A)_Confirm with AMD's Reden>
CPU_TEST23_TSTUPD PD with 1K and add a test point
CPU_TEST10_ANALOGOUT
+1.1V_CPU_VLDT
T7T7
route as differential as short as possible.
T15T15
testpoint under package
T14T14
T81T81
+1.5VSUS
R39
R39
10K/J_4
10K/J_4
R45
R45
1K/J_4
1K/J_4
2
Q6
R41 *0/J_4R41 *0 /J_4
1 3
MMBT3904Q6MMBT3904
R46 *0/short_4R46 *0/short_ 4
R265 300/J_4R265 300/J_4
R273 *0/short_4R273 *0/short_4
R272 *0/short_4R272 *0/short_4
1
R309 300/J_4R309 300/J_4
R319 300/J_4R319 300/J_4
R308 300/J_4R308 300/J_4
R268 1K/J_4R268 1K/J_4
R307 300/J_4R307 300/J_4
R135 510/F_4R135 510/F_4
R264 1K/J_4R264 1K/J_4
R269 1K/J_4R269 1K/J_4
R270 *300/J_4R270 *300/J_4
R127 *300/J_4R127 *300/J_4
R126 *300/J_4R126 *300/J_4
R55 1K/J_4R55 1K/J_4
R267 1K/J_4R267 1K/J_4
R128 510/F_4R128 510/F_4
R123 1K/J_4R123 1K/J_4
R124 1K/J_4R124 1K/J_4
R47 1K/J_4R47 1K/J_4
R274 1K/J_4R274 1K/J_4
R54 1K/J_4R54 1K/J_4
R125 *0/short_4R125 *0/short_4
R330 *300/J_4R330 *300/J_4
CPU_THERMTRIP# <11>
SYS_SHDN# <2 7,34>
CPU_PROCHO T# <10>
SB_PROCHOT# <12>
+1.5V
+1.5VSUS
+1.1V_CPU_VLDT
+1.5V
R371
R371
*HDT@4.7K/J_ 4
*HDT@4.7K/J_ 4
+3V
Q18
Q18
3
2
*HDT@FDV301N
*HDT@FDV301N
1
CPU_LDT_RST#
4
HDT Connector
+1.5VSUS
A A
CPU_DBREQ #
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
C431 *HDT@0.1U/10 V_4C431 *HDT@0.1U/10V_4
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
KEY
KEY
CN18
CN18
*HDT@HDT CONN
*HDT@HDT CONN
5
CPU_LDT_RST_HT#
25
Serial VID
+1.5V
+1.5VSUS
+1.5V
+1.5VSUS
+1.5V
CPU_SVC_R
CPU_SVD_R CPU_SVD
CPU_PWRGD
To override VID,
Remove three 0ohms and install 220ohm of CPU_PWRGD to GND
R321 *2.2K/J_4R321 *2.2K/J_4
R326 1K/J_4R326 1K/J_4
R331 *1K/J_4R331 *1K/J_4
R322 1K/J_4R322 1K/J_4
R328 *1K/J_4R328 *1K/J_4
R312 *0/short_4R312 *0/short_4
R318 *0/short_4R318 *0/short_4
R323 *0/short_4R323 *0/short_4
R313 *220/J_4R313 *220/J_4
R317 *220/J_4R317 *220/J_4
R329 *220/J_4R329 *220/J_4
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
SVC/SVD net are pulled up to VDDIO with 1Kohm
CPU_SVC
CPU_PWRGD_SVID_ REG
3
CPU_SVC <28>
CPU_SVD <28>
CPU_PWRGD_SVID_ REG <28>
Pre-PWROK Metal MODE
SVC SVD Voltage Output
0 0
001
1
1
2
1
1.1V
1.0V
0.9V
0.8V
VFIX MODE(Don't Support)
Voltage Output
1.4V
1.2V
1.0V
0.8V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
ASB2 CTRL & DEBUG 3/4
ASB2 CTRL & DEBUG 3/4
ASB2 CTRL & DEBUG 3/4
1
ZH9
ZH9
ZH9
4 40Sunday, March 28, 2010
4 40Sunday, March 28, 2010
4 40Sunday, March 28, 2010
4A
4A
4A
0.7~1.1V
D D
C C
CPU_CORE CPU_VDDNB_CORE
U16E
U16E
D4
VDD_1
D5
VDD_2
D6
VDD_3
E5
VDD_4
E6
VDD_5
E7
VDD_6
F5
VDD_7
F6
VDD_8
F7
VDD_9
H7
VDD_10
H8
VDD_11
J8
VDD_12
E4
VDD_13
J10
VDD_14
J12
VDD_15
J14
VDD_16
J18
VDD_17
J20
VDD_18
J21
VDD_19
J23
VDD_20
J9
VDD_21
K10
VDD_22
K12
VDD_23
K14
VDD_24
K18
VDD_25
K20
VDD_26
K21
VDD_27
K23
VDD_28
N4
VDD_29
L11
VDD_30
L13
VDD_31
L7
VDD_32
L9
VDD_33
M10
VDD_34
M12
VDD_35
R4
VDD_36
M5
VDD_37
N11
VDD_38
N24
VDD_39
VDD_40W4VDD_46
N9
VDD_41
P15
VDD_42
P18
VDD_43
BOM@ASB2_CPU
BOM@ASB2_CPU
CPU_CORE
+
PC43
+
PC43
330U/2V_7343
330U/2V_7343
C86
C86
22U/6.3V_8
22U/6.3V_8
5
CPU_CORE
C84
C84
22U/6.3V_8
22U/6.3V_8
POWER1
POWER1
CPU_CORECPU_CORE +1.5VSUS +1.1V_CPU_VLDT
AE12
VDD_85
AD9
VDD_84
AE21
VDD_83
AD21
VDD_82
AD18
VDD_81
AD14
VDD_80
AD12
VDD_79
AD11
VDD_78
AC5
VDD_77
AE18
VDD_76
AC24
VDD_75
AC12
VDD_74
AC10
VDD_73
AB13
VDD_72
AB11
VDD_71
AE14
VDD_70
AA24
VDD_69
AA12
VDD_68
AA10
VDD_67
Y19
VDD_66
Y16
VDD_65
Y14
VDD_64
W5
VDD_63
W20
VDD_62
W18
VDD_61
W15
VDD_60
AE23
VDD_59
V24
VDD_58
V19
VDD_57
V16
VDD_56
V14
VDD_55
T20
VDD_54
T18
VDD_53
T15
VDD_52
T10
VDD_51
R5
VDD_50
R19
VDD_49
R16
VDD_48
R14
VDD_47
AC4
P24
VDD_45
P20
VDD_44
BOTTOM SIDE DECOUPLING
15A
C85
C85
C87
C87
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
C122
C122
C121
C121
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
C124
C124
22U/6.3V_8
22U/6.3V_8
C109
C109
0.22U/6.3V_4
0.22U/6.3V_4
M27
Y26
U26
N32
U32
N30
P29
R28
R30
R32
U29
U30
W28
W30
W32
Y29
AA30
AB28
AE32
AC30
AC32
AE26
AE30
AF28
AG30
AG32
AD25
AA25
AC25
V25
P25
N25
M25
K25
L25
T25
Y25
AB25
BOM@ASB2_CPU
BOM@ASB2_CPU
C123
C123
22U/6.3V_8
22U/6.3V_8
U16F
U16F
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38
C110
C110
0.01U/25V_4
0.01U/25V_4
4
VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
VDDR_1
VDDR_2
VDDR_3
VDDR_4
POWER2
POWER2
VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
PROGEN_L
FREE_1
FREE_2
FREE_3
FREE_4
FREE_5
FREE_6
FREE_7
FREE_8
FREE_9
C120
C120
0.22U/6.3V_4
0.22U/6.3V_4
180P/50V_4
180P/50V_4
C83
C83
F1
F2
F3
F4
AL1
AL2
CPU_VDDR
AL3
AL4
A12
B12
C12
D12
AK10
AL10
0.8~1.1V
AM10
AN10
CPU_VDDNB_CORE
A3
A4
B3
B4
C3
C4
B11
G7
B7
AH8
AJ6
B25
AM3
AN11
P9
P8
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
Add two 4.7uF for CPU_CORE
C130
C125
C125
0.01U/25V_4
0.01U/25V_4
C130
180P/50V_4
180P/50V_4
2A
C354
C354
22U/6.3V_8
22U/6.3V_8
3
2
PROCESSOR POWER AND GROUND
U16H
U16H
AM19
VSS_207
AF7
VSS_167
AF26
VSS_166
AE7
VSS_165
AF8
VSS_168
AF9
VSS_169
AG1
VSS_170
AG2
VSS_171
AG27
VSS_172
AG4
VSS_173
AG5
VSS_174
AG6
VSS_175
AG7
VSS_176
AE4
VSS_164
AE25
VSS_163
AE24
VSS_162
AE22
VSS_161
AE20
VSS_160
AE2
VSS_159
AE16
VSS_158
AE13
VSS_157
AH14
VSS_177
AE11
VSS_156
AE10
VSS_155
AE1
VSS_154
AD24
VSS_153
AD23
VSS_152
AD22
VSS_151
AH20
VSS_178
AH23
VSS_179
AH25
VSS_180
AH28
VSS_181
AD20
VSS_150
AD16
VSS_149
AD13
VSS_148
AD10
VSS_147
AC9
VSS_146
AC8
VSS_145
VSS_214A2VSS_215
AC23
VSS_144
AH5
VSS_182
AJ1
VSS_183
AJ15
VSS_184
W2
VSS_116
A32
VSS_213
W8
VSS_117
Y10
VSS_118
Y15
VSS_119
Y18
VSS_120
AJ19
VSS_185
AJ2
VSS_186
AJ22
VSS_187
AJ4
VSS_188
Y20
VSS_121
Y24
VSS_122
AK11
VSS_189
AK13
VSS_190
Y7
VSS_123
AA1
VSS_124
AA11
VSS_125
C106
C106
4.7U/6.3V_6
4.7U/6.3V_6
C380
C380
22U/6.3V_8
22U/6.3V_8
4.7U/6.3V_6
4.7U/6.3V_6
C371
C371
22U/6.3V_8
22U/6.3V_8
C105
C105
U16G
U16G
N22
N23
M21
R15
R18
R20
D29
D30
G19
G25
G27
N10
B1
N2
B13
B15
B17
B19
B21
B23
B27
B29
B33
C10
P10
P14
P16
P19
P7
C31
D11
D13
D15
R1
D17
D19
D21
D23
D25
D27
R2
D8
E30
E32
F14
F17
R8
T14
T16
F20
T19
T24
T9
U1
F23
N1
G1
G2
VSS_1
VSS_28
VSS_29
VSS_30
VSS_2
VSS_3
VSS_4
VSS_27
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_12
VSS_13
VSS_14
VSS_15
VSS_36
VSS_16
VSS_17
VSS_18
GND1
GND1
VSS_19
VSS_20
VSS_21
VSS_37
VSS_38
VSS_39
VSS_40
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_115
BOM@ASB2_CPU
BOM@ASB2_CPU
VSS_45
VSS_44
VSS_43
VSS_42
VSS_26
VSS_25
VSS_41
VSS_24
VSS_23
VSS_22
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
W19
W1
V20
V18
M11
L8
V15
L4
L30
L26
L24
L23
L22
L21
L2
L12
L10
L1
K9
M6
K24
K22
K16
M22
K13
M24
K11
M23
J7
W16
J4
W14
J32
J30
M13
J28
U8
J25
U4
J24
U7
U2
J2
J16
J13
J11
J1
H6
H5
H28
H23
H20
J22
M9
G4
G30
N12
PLACE CLOSE TO PROCESSOR AS POSSIBLE
GND2
GND2
BOM@ASB2_CPU
BOM@ASB2_CPU
VSS_191
VSS_192
VSS_193
VSS_194
VSS_126
VSS_127
VSS_128
VSS_195
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_137
VSS_138
VSS_205
VSS_206
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
AK15
AK17
AK19
AK21
AA2
AA22
AA23
AK23
AA4
AA9
AB10
AB12
AB21
AB22
AB23
AB24
AK25
AK27
AK29
AJ5
AH6
AL31
AM1
AM13
AB7
AC1
AM15
AM17
AC11
AC13
AC2
AC21
AC22
AM23
AM27
AM33
AN2
AN32
AM11
1
B B
+1.5VSUS
3A
C103
C103
C96
C96
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
+1.5VSUS
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
Add two 0.1uF for +1.5VSUS
C327
C327
C328
C328
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
C129
C129
10U/6.3V_8
10U/6.3V_8
C318
C318
0.01U/25V_4
0.01U/25V_4
C79
C79
10U/6.3V_8
10U/6.3V_8
C77
C77
180P/50V_4
180P/50V_4
C325
C325
C322
0.22U/6.3V_4
0.22U/6.3V_4
C322
0.22U/6.3V_4
0.22U/6.3V_4
0.22U/6.3V_4
0.22U/6.3V_4
<20091202(A1A)_Follow Bimini Rev1.2>
Add two 10uF for +1.5VSUS
C112
C112
C89
C89
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
CPU_VDDR
C114
C114
C75
C75
0.22U/6.3V_4
0.22U/6.3V_4
0.22U/6.3V_4
0.22U/6.3V_4
C108
C108
C76
C76
0.22U/6.3V_4
0.22U/6.3V_4
C71
C71
4.7U/6.3V_6
4.7U/6.3V_6
+1.1V
R351 *0/short_8R351 *0/short_8
Group1 Group2
1A
C73
C73
C72
C72
0.22U/6.3V_4
0.22U/6.3V_4
0.22U/6.3V_4
0.22U/6.3V_4
1.5A
+1.1V_CPU_VLDT
C319
C319
4.7U/6.3V_6
4.7U/6.3V_6
C317
C317
22U/6.3V_8
22U/6.3V_8
For VLDT_A
C321
C321
0.22U/6.3V_4
0.22U/6.3V_4
4.7U/6.3V_6
4.7U/6.3V_6
C360
C360
C350
C350
0.22U/6.3V_4
0.22U/6.3V_4
C320
C320
180P/50V_4
180P/50V_4
C343
C343
0.22U/6.3V_4
0.22U/6.3V_4
4.7U/6.3V_6
4.7U/6.3V_6
For VLDT_B
C368
C368
C356
C356
0.22U/6.3V_4
0.22U/6.3V_4
C352
C352
180P/50V_4
180P/50V_4
DECOUPLING BETWEEN PROCESSOR AND DIMMs
A A
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.5VSUS
4.7U/6.3V_6
4.7U/6.3V_6
C88
C97
4.7U/6.3V_6
4.7U/6.3V_6
5
C97
C92
C92
C88
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
If VSS plane is cut for VDDIO, place two
0.22uF & 180pF across the VDDIO-VSS
C326
C78
C78
C326
0.22U/6.3V_4
0.22U/6.3V_4
C329
C329
0.22U/6.3V_4
0.22U/6.3V_4
4
180P/50V_4
180P/50V_4
C323
C323
C324
C324
180P/50V_4
180P/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
PROJECT :
ASB2 PWR & GND 4/4
ASB2 PWR & GND 4/4
ASB2 PWR & GND 4/4
ZH9
4A
4A
5 40Sunday, March 28, 2010
5 40Sunday, March 28, 2010
5 40Sunday, March 28, 2010
1
4A
5
HT_CADOUTP0
HT_CADOUTN0
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP3
HT_CADOUTN3
HT_CADOUTP4
HT_CADOUTN4
HT_CADOUTP5
HT_CADOUTN5
HT_CADOUTP6
HT_CADOUTN6
HT_CADOUTP7
R320 301/F_4R320 301/F_4
25mils
0.5A
C436
C436
SPM@10U/6.3V_8
SPM@10U/6.3V_8
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
HT_CADOUTN7
HT_CADOUTP8
HT_CADOUTN8
HT_CADOUTP9
HT_CADOUTN9
HT_CADOUTP10
HT_CADOUTN10
HT_CADOUTP11
HT_CADOUTN11
HT_CADOUTP12
HT_CADOUTN12
HT_CADOUTP13
HT_CADOUTN13
HT_CADOUTP14
HT_CADOUTN14
HT_CADOUTP15
HT_CADOUTN15
HT_CLKOUTP0
HT_CLKOUTN0
HT_CLKOUTP1
HT_CLKOUTN1
HT_CTLOUTP0
HT_CTLOUTN0
HT_CTLOUTP1
HT_CTLOUTN1
+1.5V_SPM_VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
D D
C C
C442
C442
SPM@0.1U/10V_4
SPM@0.1U/10V_4
B B
+1.5V_SPM_VDDQ
A A
SPM_VREFCA
SPM_VREFDQ
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
SPM_BA0
SPM_BA1
SPM_BA2
SPM_CLKP
SPM_CLKN
SPM_CKE
SPM_ODT
SPM_CS#
SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_DQS0P
SPM_DQS1P
SPM_DM0
SPM_DM1
SPM_DQS0N
SPM_DQS1N
SP_DDR3_RST#<11>
C424
C424
SPM@0.1U/10V_4
SPM@0.1U/10V_4
R376 SPM@10K/J_4R376 SPM@10K/J_4
5
C425
C425
SPM@1U/10V_4
SPM@1U/10V_4
C441
C441
SPM@1U/10V_4
SPM@1U/10V_4
U7
U7
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
R373
R373
SPM@243/F_4
SPM@243/F_4
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
SDRAM DDR3
SDRAM DDR3
BOM@DDR3 SDRAM
BOM@DDR3 SDRAM
<20091202(A1A)_Confirm with Acer Jimmy>
side port memory use DD3
4
U20A
U20A
Y25
HT_RXCAD0P
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
M22
M23
R21
R20
HT_RXCALP HT_TXCALP
C23
HT_RXCALN
A24
R378 *0/short_6R378 *0/short_6
C439
C439
SPM@10U/6.3V_8
SPM@10U/6.3V_8
SPM_DQ2
SPM_DQ1
SPM_DQ3
SPM_DQ0
SPM_DQ7
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ11
SPM_DQ8
SPM_DQ12
SPM_DQ14
SPM_DQ9
SPM_DQ10
SPM_DQ15
SPM_DQ13
+1.5V_SPM_VDDQ
<BOM Note>
w/ sideport: U7:
AKD5LGGT506 : SAMSUNG DDRIII 800 1Gb K4W1G1646E-HC12 LF
AKD5LZGTW04 : HYNIX DDRIII 800 1Gb H5TQ1G63BFR-12C LF
AKD5LGGT700 : ATI DDRIII 800 1Gb 23EY2387MA12-SZ LF+HF
w/o sideport: U7 Non-stuff
4
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
RS880M
RS880M
+1.5V
+1.5V_SPM_VDDQ
PART 1 OF 6
PART 1 OF 6
+1.5V_SPM_VDDQ
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
T52T52
R358 SPM@40.2/F_4R358 SPM@40.2/F_4
R359 SPM@40.2/F_4R359 SPM@40.2/F_4
C443
C443
SPM@0.1U/10V_4
SPM@0.1U/10V_4
C440
C440
SPM@0.1U/10V_4
SPM@0.1U/10V_4
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
SPM_BA0
SPM_BA1
SPM_BA2
SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_CS#
SPM_CKE
SPM_ODT
SPM_CLKP
SPM_CLKN
R379
R379
SPM@1K/F_4
SPM@1K/F_4
SPM_VREFDQ SPM_VREFSPM_VREFCA
R377
R377
SPM@1K/F_4
SPM@1K/F_4
3
HT_CADINP0
D24
HT_CADINN0
D25
HT_CADINP1
E24
HT_CADINN1
E25
HT_CADINP2
F24
HT_CADINN2
F25
HT_CADINP3
F23
HT_CADINN3
F22
HT_CADINP4
H23
HT_CADINN4
H22
HT_CADINP5
J25
HT_CADINN5
J24
HT_CADINP6
K24
HT_CADINN6
K25
HT_CADINP7
K23
HT_CADINN7
K22
HT_CADINP8
F21
HT_CADINN8
G21
HT_CADINP9
G20
HT_CADINN9
H21
HT_CADINP10
J20
HT_CADINN10
J21
HT_CADINP11
J18
HT_CADINN11
K17
HT_CADINP12
L19
HT_CADINN12
J19
HT_CADINP13
M19
HT_CADINN13
L18
HT_CADINP14
M21
HT_CADINN14
P21
HT_CADINP15
P18
HT_CADINN15
M18
HT_CLKINP0
H24
HT_CLKINN0
H25
HT_CLKINP1
L21
HT_CLKINN1
L20
HT_CTLINP0
M24
HT_CTLINN0
M25
HT_CTLINP1
P19
HT_CTLINN1
R18
B24
HT_TXCALN
B25
R161 *SPM@100/F_4R161 *SPM@100/F_4
SPM_COMPP
SPM_COMPN
3
R115 301/F_4R115 301/F_4
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
AD16
AE17
AD17
W12
Y12
AD18
AB13
AB18
V14
V15
W14
AE12
AD12
+1.5V_SPM_VDDQ +1.5V_SPM_VDDQ
U20D
U20D
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
RS880M
RS880M
C418
C418
SPM@0.1U/10V_4
SPM@0.1U/10V_4
C417
C417
SPM@0.1U/10V_4
SPM@0.1U/10V_4
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]
HT_CTLOUTN[1..0]
HT_CADINP[15..0]
HT_CADINN[15..0]
HT_CLKINP[1..0]
HT_CLKINN[1..0]
HT_CTLINP[1..0]
HT_CTLINN[1..0]
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
MEM_VREF(NC)
R366
R366
SPM@1K/F_4
SPM@1K/F_4
R365
R365
SPM@1K/F_4
SPM@1K/F_4
MEM_DQ4(NC)
MEM_DM0(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
2
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
C414
C414
SPM@0.1U/10V_4
SPM@0.1U/10V_4
C413
C413
SPM@0.1U/10V_4
SPM@0.1U/10V_4
2
HT_CADOUTP[15..0] <2>
HT_CADOUTN[15..0] <2>
HT_CLKOUTP[1..0] <2>
HT_CLKOUTN[1..0] <2>
HT_CTLOUTP[1..0] <2>
HT_CTLOUTN[1..0] <2>
HT_CADINP[15..0] <2>
HT_CADINN[15..0] <2>
HT_CLKINP[1..0] <2>
HT_CLKINN[1..0] <2>
HT_CTLINP[1..0] <2>
HT_CTLINN[1..0] <2>
SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
SPM_DM0
SPM_DM1
+1.8V_NB_IOPLLVDD18
+1.1V_NB_IOPLLVDD
SPM_VREF
SPM@2.2U/6.3V_6
SPM@2.2U/6.3V_6
<BOM NOTE>
w/ sideport: L45,L46:CX8PG221003
w/o sideport: L45,L46:CS00003J951(0ohm)
R357
R357
SPM@1K/F_4
SPM@1K/F_4
R356
R356
SPM@1K/F_4
SPM@1K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
L46 BOM@1.4A/220ohm_6L46 BOM@1.4A/220ohm_6
L45 BOM@1.4A/220ohm_6L45 BOM@1.4A/220ohm_6
C410
C410
SPM@2.2U/6.3V_6
SPM@2.2U/6.3V_6
C409
C409
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
RS880-HT LINK/SPMEM I/F 1/4
RS880-HT LINK/SPMEM I/F 1/4
RS880-HT LINK/SPMEM I/F 1/4
1
15mA
+1.8V
26mA
+1.1V
ZH9
ZH9
ZH9
4A
4A
6 40Sunday, March 28, 2010
6 40Sunday, March 28, 2010
6 40Sunday, March 28, 2010
1
4A
5
U20B
U20B
D4
AE3
AD4
AE2
AD3
AD1
AD2
W6
AA8
AA7
AA5
AA6
W5
G5
G6
M8
M7
M5
C4
A3
B3
C2
C1
E5
F5
H5
H6
J6
J5
J7
J8
L5
L6
L8
P7
P5
R8
P8
R6
R5
P4
P3
T4
T3
V5
U5
U6
U8
U7
Y8
Y7
Y5
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
RS880M
RS880M
D D
C C
PCIE_RXP0<21>
PCIE_RXN0<21>
PCIE_RXP1<23> PCIE_TXP1 <23>
PCIE_RXN1<23>
PCIE_RXP2<23>
PCIE_RXN2<23>
B B
A_RXP0<10>
A_RXN0<10>
A_RXP1<10>
A_RXN1<10>
A_RXP2<10>
A_RXN2<10>
A_RXP3<10>
A_RXN3<10>
PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1 PCIE_TXN1_C
PCIE_RXP2
PCIE_RXN2
4
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
TX2_HDMI+_C
TX2_HDMI-_C
TX1_HDMI+_C
TX1_HDMI-_C
TX0_HDMI+_C
TX0_HDMI-_C
TXC_HDMI+_C
TXC_HDMI-_C
PCIE_TXP0_C
PCIE_TXN0_C
PCIE_TXP1_C
PCIE_TXP2_C
PCIE_TXN2_C
A_TXP0_C
A_TXN0_C
A_TXP1_C
A_TXN1_C
A_TXP2_C
A_TXN2_C
A_TXP3_C
A_TXN3_C
NB_PCIECALRP
NB_PCIECALRN
3
C393 HDM@0.1U/10V_4C393 HDM@0.1U/10V_4
C392 HDM@0.1U/10V_4C392 HDM@0.1U/10V_4
C396 HDM@0.1U/10V_4C396 HDM@0.1U/10V_4
C395 HDM@0.1U/10V_4C395 HDM@0.1U/10V_4
C398 HDM@0.1U/10V_4C398 HDM@0.1U/10V_4
C397 HDM@0.1U/10V_4C397 HDM@0.1U/10V_4
C406 HDM@0.1U/10V_4C406 HDM@0.1U/10V_4
C403 HDM@0.1U/10V_4C403 HDM@0.1U/10V_4
C427 0.1U/10V_4C427 0.1U/10V_4
C423 0.1U/10V_4C423 0.1U/10V_4
C218 0.1U/10V_4C218 0.1U/10V_4
C216 0.1U/10V_4C216 0.1U/10V_4
C419 3G@0.1U/10V_4C419 3G@0.1U/10V_4
C421 3G@0.1U/10V_4C421 3G@0.1U/10V_4
C420 0.1U/10V_4C420 0.1U/10V_4
C422 0.1U/10V_4C422 0.1U/10V_4
C430 0.1U/10V_4C430 0.1U/10V_4
C426 0.1U/10V_4C426 0.1U/10V_4
C435 0.1U/10V_4C435 0.1U/10V_4
C432 0.1U/10V_4C432 0.1U/10V_4
C433 0.1U/10V_4C433 0.1U/10V_4
C437 0.1U/10V_4C437 0.1U/10V_4
R168 1.27K/F_4R168 1.27K/F_4
R162 2K/F_4R162 2K/F_4
PCIE_TXP0 <21>
PCIE_TXN0 <21>
PCIE_TXN1 <23>
PCIE_TXP2 <23>
PCIE_TXN2 <23>
A_TXP0 <10>
A_TXN0 <10>
A_TXP1 <10>
A_TXN1 <10>
A_TXP2 <10>
A_TXN2 <10>
A_TXP3 <10>
A_TXN3 <10>
+1.1V
2
TX2_HDMI+ <17>
TX2_HDMI- <17>
TX1_HDMI+ <17>
TX1_HDMI- <17>
TX0_HDMI+ <17>
TX0_HDMI- <17>
TXC_HDMI+ <17>
TXC_HDMI- <17>
TO LAN
TO MINI PCIE 1
TO MINI PCIE 2
1
TO HDMI
RS880 Display Port Support (muxed on GFX)
DP0
A A
DP1
5
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
Date: Sheet of
2
PROJECT :
RS880-PCIE I/F 2/4
RS880-PCIE I/F 2/4
RS880-PCIE I/F 2/4
ZH9
1
4A
4A
4A
7 40Sunday, March 28, 2010
7 40Sunday, March 28, 2010
7 40Sunday, March 28, 2010
5
Note:Regarding LDT_STOP# signal,It's required within
40ns skew for both assertion and de-assertion between
NB and CPU.
D D
CPU_LDT_STOP#<4,10>
ALLOW_LDTSTOP<10>
C C
B B
STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO.
1 = Disable
0 = Enable
R353
R353
*300/J_4
*300/J_4
R352 *0/J_4R352 *0/J_4
Graphics PLL power
Graphics PLL power
HT LINK PLL power
PCIe PLL power
+
U18
U18
Open
Open
2
Drain
Drain
-
74LVC07+-
74LVC07
3 5
R131 *0/short_4R131 *0/short_4
CRT_VSYNC
+1.8V+1.8V
<20100303(C3A)>
Change R354 from CS22202JB18(2.2K) to
CS13002JB20(300ohm ) depend on the
measurement result, for LDTSTP# skew
issue.
C408
C408
0.1U/10V_4
0.1U/10V_4
4
Confirmed with AMD FAE Reden
Follow Bimini Rev1.2 for PLLVDD18 to prevent noise coupling
Change L8203 from bead to 3.9ohm
CRB:0.23A@all +1.1V PLLs
+1.8V
R354
R354
300/J_4
300/J_4
NB_LDT_STOP#
R122 1K/J_4R122 1K/J_4
NB_ALLOW_LDTSTOP
+1.1V
C146
C146
22U/6.3V_8
22U/6.3V_8
L40 1.4A/220ohm_6L40 1.4A/220ohm_6
R121 1.4A/220ohm_6R121 1.4A/220ohm_6
L10 1.4A/220ohm_6L10 1.4A/220ohm_6
L15 1.4A/220ohm_6L15 1.4A/220ohm_6
CRB:0.1A@all +1.8V PLLs
<20091009(A1A)_46105_rs880_scl_nda_1.04>
Pulled 4.7K 5% low to GND when internal CLK Gen. used
(For GFX Clock Pair)
R143 3K/J_4R143 3K/J_4
R147 *3K/J_4R147 *3K/J_4
4
DAC Analog power
<20100310(C3A)>
Change R336 from 0ohm(CS00002JB38) to bead(CX8PG221003) and C162 from
0.1uF(CH4102K1B03) to 2.2uF(CH52201K991), for monitor noise issue.
DAC Digital power
<20100319(RAMP)>
Add C415,C470,C499(1uF), for monitor noise issue.
DAC Bandgap Reference power
<20090810(A1A)_46659_RS880_Errata_nda_1.10>
The R channel's term. R change 140ohm (For the
voltage level mismatch, the Red is higher)
+1.8V
<20100323(RAMP)_Follow 46105_rs880_scl_nda_1.05>
Change R121 from 3.9ohm(CS-3902JB00) to bead(CX8PG221003)
and C159 from 4.7uF(CH5471M9907) to 2.2uF(CH52201K991)
C388 2.2U/6.3V_6C388 2.2U/6.3V_6
C159 2.2U/6.3V_6C159 2.2U/6.3V_6
NB_RST#_IN<10>
NB_PWRGD<11>
CLK_NB_HTREFP<10>
CLK_NB_HTREFN<10>
NB_REFCLK_P<10>
NB_REFCLK_N<10>
CLK_SBLINKP<10>
CLK_SBLINKN<10>
LCD_DATA<16>
LCD_CLK<16>
HDMI_DDC_DATA<17>
HDMI_DDC_CLK<17>
+NB_CORE_ON<29>
+3V
NB Core
STRP_DATA
1 = 0.95V
0 = 1.1 V
+3V
+1.8V
+1.8V
CRT_R<16>
CRT_G<16>
CRT_B<16>
C155 2.2U/6.3V_6C155 2.2U/6.3V_6
C174 2.2U/6.3V_6C174 2.2U/6.3V_6
3
L14 1.4A/220ohm_6L14 1.4A/220ohm_6
SCL:20mA
R336 1.4A/220ohm_6R336 1.4A/220ohm_6
L41 1.4A/220ohm_6L41 1.4A/220ohm_6
SCL:65mA
R363 ICK@4.7K/J_4R363 ICK@4.7K/J_4
R364 ICK@4.7K/J_4R364 ICK@4.7K/J_4
R144
R144
2K/J_4
2K/J_4
SCL:4mA
R134 140/F_4R134 140/F_4
R129 150/F_4R129 150/F_4
R120 150/F_4R120 150/F_4
SCL:20mA
SCL:120mA
R346 *0/short_4R346 *0/short_4
R139 *0/short_4R139 *0/short_4
+1.1V_NB_PLLVDD
+1.8V_NB_PLLVDD18
+1.8V_NB_VDDA18HTPLL
+1.8V_NB_VDDA18PCIEPLL
+3V_NB_AVDD
C163
C163
2.2U/6.3V_6
2.2U/6.3V_6
+1.8V_NB_AVDDDI
C162
C162
2.2U/6.3V_6
2.2U/6.3V_6
15mils
+1.8V_NB_AVDDQ
C160
C160
2.2U/6.3V_6
2.2U/6.3V_6
CRT_HSYNC<16>
CRT_VSYNC<16>
CRT_SDA<16>
CRT_SCL<16>
R325 715/F_6R325 715/F_6
SCL:20mA
NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP
CLK_NB_HTREFP
CLK_NB_HTREFN
CLK_NBGFXP
CLK_NBGFXN
CLK_SBLINKP
CLK_SBLINKN
LCD_DATA
LCD_CLK
T27T27
T18T18
STRP_DATA
R347 *150/F_4R347 *150/F_4
C415
C415
1U/6.3V_4
1U/6.3V_4
15mils
C470
C470
1U/6.3V_4
1U/6.3V_4
C499
C499
1U/6.3V_4
1U/6.3V_4
15mils
15mils
15mils
DAC_RSET
15mils
15mils
AUX_CAL
SCL:110mA
CRB:125mA
U20C
U20C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PW M_GPIO4)
B11
DAC_VSYNC(PW M_GPIO6)
E8
DAC_SDA(PCE_TCALRN)
F8
DAC_SCL(PCE_RCALRN)
G14
DAC_RSET(PW M_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PW M_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
A9
I2C_DATA
B9
I2C_CLK
B8
DDC_DATA/AUX0N(NC)
A8
DDC_CLK/AUX0P(NC)
B7
AUX1P(NC)
A7
AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS880M
RS880M
2
HPD(NC)
TESTMODE
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13
B13
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
D9
D10
D12
AE8
AD8
D13
R150
R150
SUS_STAT#_NB
TEST_EN
PART 3 OF 6
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
I
PM
I
I/O
CLOCKs PLL PWR
I/O
CLOCKs PLL PWR
MIS.
MIS.
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PW M_GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PW M_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
TXLOUT0+ <16>
TXLOUT0- <16>
TXLOUT1+ <16>
TXLOUT1- <16>
TXLOUT2+ <16>
TXLOUT2- <16>
TXLCLKOUT+ <16>
TXLCLKOUT- <16>
C386 2.2U/6.3V_6C386 2.2U/6.3V_6
+1.8V_NB_VDDLTP18
15mils
+1.8V_NB_VDDLT18
15mils
C377
C377
0.1U/10V_4
0.1U/10V_4
Confirmed with AMD Horace
LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be
pulled down with 4.7K
4.7K/J_4
4.7K/J_4
T26T26
R334
R334
1.8K/J_4
1.8K/J_4
1
LVDS or DVI/ HDMI PLL power
L39 1.4A/220ohm_6L39 1.4A/220ohm_6
L38 1.4A/220ohm_6L38 1.4A/220ohm_6
C369
C369
4.7U/6.3V_6
4.7U/6.3V_6
SCL:15mA
SCL:0.3A
CRB:0.22A
LVDS or DVI/ HDMI Digital power
Support Vari-Bright
INT_LVDS_DIGON <16>
INT_LVDS_PWM <16>
INT_LVDS_BLON <16>
R156 SPM@0/J_4R156 SPM@0/J_4
LVDS POWER
LVDS BL_PWM
LVDS BL_EN
INT_HDMI_HPD <17>
SUS_STAT# <11>
+1.8V
RS880M: Enables Side port memory
A A
Selects if Memory SIDE PORT is available or not
1 = Memory Side port Not available
0 = Memory Side port available
<BOM NOTE>
w/ sideport: R142 non-stuff
w/o sideport: R142 stuff
5
CRT_HSYNC
R142 BOM@3K/J_4R142 BOM@3K/J_4
R137 SPM@3K/J_4R137 SPM@3K/J_4
DFT_GPIO1: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
+3V
default values if not connected
EEPROM not implemented
4
+3V
R153 4.7K/J_4R153 4.7K/J_4
3
SUS_STAT#_NB
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PROJECT :
RS880-SYSTEM I/F 3/4
RS880-SYSTEM I/F 3/4
RS880-SYSTEM I/F 3/4
ZH9
4A
4A
8 40Sunday, March 28, 2010
8 40Sunday, March 28, 2010
1
8 40Sunday, March 28, 2010
4A
5
4
3
2
1
D11
E14
E15
J12
K14
M11
H7
VSSAPCIE10J4VSSAPCIE11R7VSSAPCIE12L1VSSAPCIE13L2VSSAPCIE14L4VSSAPCIE15
VSSAHT9
VSSAHT10
VSSAHT11
L17
L22
L24
L7
VSSAPCIE16M6VSSAPCIE17N4VSSAPCIE18P6VSSAPCIE19R1VSSAPCIE20R2VSSAPCIE21R4VSSAPCIE22V7VSSAPCIE23U4VSSAPCIE24V8VSSAPCIE25V6VSSAPCIE26W1VSSAPCIE27W2VSSAPCIE28W4VSSAPCIE29W7VSSAPCIE30W8VSSAPCIE31Y6VSSAPCIE32
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT21
VSSAHT20
L25
M20
+1.1V
P20
N22
SCL:0.4A
CRB:0.68A
V19
R19
R22
R24
R25
U22
H20
R145 *0/short_6R145 *0/short_6
R113 *0/short_6R113 *0/short_6
C192
C192
4.7U/6.3V_6
4.7U/6.3V_6
SCL:0.7A
CRB:0.64A
C213
C213
4.7U/6.3V_6
4.7U/6.3V_6
+1.8V
+1.8V
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
W22
W24
W25
CRB:0.68A
C211
C211
4.7U/6.3V_6
4.7U/6.3V_6
U20F
U20F
D D
C C
VSSAPCIE1A2VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9
PART 6/6
PART 6/6
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
A25
E22
D23
H19
G22
G24
G25
VSSAHT8
J22
HT LINK RX I/O power
HT LINK TX I/O power
R152 *0/short_6R152 *0/short_6
+1.1V
B B
PCIe TX Stage I/O power
+1.8V
L17 1.4A/220ohm_6L17 1.4A/220ohm_6
I/O Transform power
Memory I/O Transform
CRB:25mA
A A
AA4
AB5
AB1
VSSAPCIE33
GROUND
GROUND
VSSAHT26
VSSAHT27
VSS11
VSS12
VSS13
VSS14
VSS15
L12
Y21
P12
P15
N13
R11
M14
AD25
SCL:0.6A
C172
C172
4.7U/6.3V_6
4.7U/6.3V_6
SCL:0.7A
C152
C152
4.7U/6.3V_6
4.7U/6.3V_6
C190
C190
0.1U/10V_4
0.1U/10V_4
R157 *0/short_6R157 *0/short_6
R367 SPM@0/J_6R367 SPM@0/J_6
C197
C197
0.1U/10V_4
0.1U/10V_4
C191
C191
0.1U/10V_4
0.1U/10V_4
AB7
AC3
AC4
AE1
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSS16
VSS17
VSS18
VSS19
T12
R14
U14
U11
C168
C168
0.1U/10V_4
0.1U/10V_4
C150
C150
0.1U/10V_4
0.1U/10V_4
C207
C207
0.1U/10V_4
0.1U/10V_4
SCL:10mA
CRB:5mA
AE4
VSSAPCIE38
VSS20
U15
AB2
VSSAPCIE39
VSSAPCIE40
VSS21
VSS22
V12
W11
C193
C193
1U/10V_4
1U/10V_4
AE14
VSS2
VSS3G8VSS4
VSS1
VSS23
VSS24
VSS25
VSS26
VSS27
Y18
W15
AA14
AC12
+1.1V_NB_VDDHT
C164
C164
0.1U/10V_4
0.1U/10V_4
+1.1V_NB_VDDHTRX
C147
C147
0.1U/10V_4
0.1U/10V_4
+1.1V_NB_VDDHTTX
C188
C188
0.1U/10V_4
0.1U/10V_4
+1.8V_NB_VDDA18PCIE
C187
C187
0.1U/10V_4
0.1U/10V_4
+1.8V_NB_VDD18
+1.8V_NB_VDD18_MEM
L15
J15
VSS5
VSS7
VSS8
VSS9
VSS6
VSS10
VSS28
VSS29
VSS30
VSS31
VSS32
VSS34
VSS33
K11
AB11
AB15
AB17
AB19
AE20
AB21
35mils
C169
C169
0.1U/10V_4
0.1U/10V_4
40mils
C156
C156
0.1U/10V_4
0.1U/10V_4
20mils
C177
C177
0.1U/10V_4
0.1U/10V_4
25mils
C203
C203
0.1U/10V_4
0.1U/10V_4
15mils
C416
C416
BOM@1U/10V_4
BOM@1U/10V_4
U20E
U20E
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDDG18_1(VDD18_1)
G9
VDDG18_2(VDD18_2)
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS880M
RS880M
PART 5/6
PART 5/6
POWER
POWER
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDDG33_1(NC)
VDDG33_2(NC)
Without side-port: Connected to GND plane.
PIN NAME
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE
VDD18
VDD18_MEM
VDDPCIE
VDDC
VDD_MEM
VDD33
IOPLLVDD18
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
RX881/RS880 POWER DIFFERENCE TABLE
RX881
+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
GND
+1.1V +1.1V +1.8V
+1.1V
+0.95V~+1.1V
GND
+1.8V/1.5V
+3.3V
+1.1V_NB_VDDPCIE
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
C206
C206
0.1U/10V_4
0.1U/10V_4
C196
C196
0.1U/10V_4
0.1U/10V_4
C173
C173
0.1U/10V_4
0.1U/10V_4
+1.5V_NB_VDD_MEM
15mils
+3V_NB_VDD33
C167
C167
0.1U/10V_4
0.1U/10V_4
RS880
+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V
+3.3V
+1.8V+1.8V
130mils
C198
C198
0.1U/10V_4
0.1U/10V_4
550mils
C166
C166
0.1U/10V_4
0.1U/10V_4
C194
C194
0.1U/10V_4
0.1U/10V_4
PIN NAME
IOPLLVDD
AVDDDI
AVDDQ
PLLVDD
PLLVDD18
VDDA18PCIEPLL
VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33
C214
C214
BOM@0.1U/10V_4
BOM@0.1U/10V_4
C199
C199
1U/10V_4
1U/10V_4
C170
C170
0.1U/10V_4
0.1U/10V_4
C200
C200
0.1U/10V_4
0.1U/10V_4
R159 *0/short_6R159 *0/short_6
RX881 RS880
+1.1V
+1.1V
GND
+3.3VAVDD
GND +1.8V
GND +1.8V
+1.1V
GND
GND
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
GND
+1.8V
GND
NC
NC
SCL:2.5A
CRB:1.1A
C210
C210
C212
C212
1U/10V_4
1U/10V_4
4.7U/6.3V_6
4.7U/6.3V_6
C195
C195
0.1U/10V_4
0.1U/10V_4
C175
C175
0.1U/10V_4
0.1U/10V_4
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
SCL:100mA
C219
C219
SPM@0.1U/10V_4
SPM@0.1U/10V_4
+3V
SCL:60mA
CRB:60mA
R163 *0/short_8R163 *0/short_8
R160 *0/short_6R160 *0/short_6
SCL:10A
CRB:7.6A
C208
C208
C209
C209
C217
C217
SPM@0.1U/10V_4
SPM@0.1U/10V_4
+0.95V or +1.1V
+3.3V I/O power
PCIe Main I/O powerHT LINK Digital I/O power
+1.1V
+NB_CORE
C215
C215
SPM@0.1U/10V_4
SPM@0.1U/10V_4
Core Logic power
R179 SPM@0/J_6R179 SPM@0/J_6
C226
C226
SPM@4.7U/6.3V_6
SPM@4.7U/6.3V_6
For Side Port
+1.5V for DDR3
+1.8V for DDR2
If not support side port,
connect to GND.
Memory I/O
+1.5V
<BOM NOTE>
w/ sideport: C214:CH4102K1B03 ; C416:CH5102K9B06
w/o sideport: C214,C416:CS00002JB38(0ohm)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
PROJECT :
RS880-POWER 4/4
RS880-POWER 4/4
RS880-POWER 4/4
ZH9
9 40Sunday, March 28, 2010
9 40Sunday, March 28, 2010
9 40Sunday, March 28, 2010
1
4A
4A
4A
5
PCIE_RST#: Reset PCIe Slot/Device (PCIe interface from SB)
A_RST#: Reset NB, MXM, EC, PCIe Slot/Device (PCIe interface from NB)
NB
NB_RST#_IN<8>
EC
PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO SB820
D D
A_RST#_SB
R73 *0/short_4R73 *0/short_4
R65 *0/short_4R65 *0/short_4
+1.1V_SB_VDDAN_11_PCIE
C C
B B
A A
<20100325(RAMP)>
Change RP1~RP4,RP6~RP8 to shortpad.
to NB for A-LINK/PCIe REF CLK
to NB Display Eng
to MINI PCIE 2
to LAN
to MINI PCIE 1
to LAN chip 25MHz
<20100129(B2A)>
Stuff R345. (CLK for LAN from crystal
change to internal CLK.)
<20100310(C3A)>
Non-Stuff R345. (14M_25M_48M_OSC is S0 plane,
doesn't support WoL.)
CLK_SBLINKP<8>
CLK_SBLINKN<8>
NB_REFCLK_P<8>
NB_REFCLK_N<8>
CLK_NB_HTREFP<8>
CLK_NB_HTREFN<8>
CLK_CPU_BCLKP<4>
CLK_CPU_BCLKN<4>
CLK_PCIE_MNC_P<23>
CLK_PCIE_MNC_N<23>
CLK_PCIE_LANP<21>
CLK_PCIE_LANN<21>
CLK_PCIE_MPC_P<23>
CLK_PCIE_MPC_N<23>
CLK_25M_LAN<21>
5
<20100303(C3A)>
Change C411,C412 from CH02206JB08(22pF) to CH02706JB06(27pF), for Y4.
C102 150P/50V_4C102 150P/50V_4
A_RXP0<7>
A_RXN0<7>
A_RXP1<7>
A_RXN1<7>
A_RXP2<7>
A_RXN2<7>
A_RXP3<7>
A_RXN3<7>
A_TXP0<7>
A_TXN0<7>
A_TXP1<7>
A_TXN1<7>
A_TXP2<7>
A_TXN2<7>
A_TXP3<7>
A_TXN3<7>
<Layout note>
Share pad with other resisters
and close to external CLK Gen.
RP7 *ICK@0/short__4P2RRP7 *ICK@0/short__4P2R
4
2
RP2 *ICK@0/short__4P2RRP2 *ICK@0/short__4P2R
4
2
RP1 *ICK@0/short__4P2RRP1 *ICK@0/short__4P2R
4
2
RP8 *ICK@0/short__4P2RRP8 *ICK@0/short__4P2R
4
2
RP4 *3G@ICK@0/short__4P2RRP4 *3G@ICK@0/short__4P2R
4
2
RP6 *ICK@0/short__4P2RRP6 *ICK@0/short__4P2R
2
4
RP3 *ICK@0/short__4P2RRP3 *ICK@0/short__4P2R
4
2
R345 *ICK@22/J_4R345 *ICK@22/J_4
C411 27P/50V_4C411 27P/50V_4
Y4
Y4
25MHz-SB820M
25MHz-SB820M
C412 27P/50V_4C412 27P/50V_4
R350 590/F_4R350 590/F_4
R349 2K/F_4R349 2K/F_4
3
1
3
1
3
1
3
1
3
1
1
3
3
1
2 1
R89 33/J_4R89 33/J_4
C179 0.1U/10V_4C179 0.1U/10V_4
C180 0.1U/10V_4C180 0.1U/10V_4
C182 0.1U/10V_4C182 0.1U/10V_4
C181 0.1U/10V_4C181 0.1U/10V_4
C183 0.1U/10V_4C183 0.1U/10V_4
C184 0.1U/10V_4C184 0.1U/10V_4
C186 0.1U/10V_4C186 0.1U/10V_4
C185 0.1U/10V_4C185 0.1U/10V_4
R355
R355
1M/J_4
1M/J_4
A_RST#_SB_CA_RST#
A_RXP0_C
A_RXN0_C
A_RXP1_C
A_RXN1_C
A_RXP2_C
A_RXN2_C
A_RXP3_C
A_RXN3_C
A_TXP0
A_TXN0
A_TXP1
A_TXN1
A_TXP2
A_TXN2
A_TXP3
A_TXN3
PCIE_CALRP_SB
PCIE_CALRN_SB
CLK_SBSRCP
CLK_SBSRCN
SB_NB_REFCLKP
SB_NB_REFCLKN
SB_NB_HTCLKP
SB_NB_HTCLKN
SB_CPU_CLKP
SB_CPU_CLKN
SB_MNC_CLKP
SB_MNC_CLKN
SB_LAN_CLKP
SB_LAN_CLKN
SB_MPC_CLKP
SB_MPC_CLKN
SB_CLK_25M_LAN
25M_X1
25M_X2
4
U5A
U5A
P1
PCIE_RST#
L1
A_RST#
AD26
A_TX0P
AD27
A_TX0N
AC28
A_TX1P
AC29
A_TX1N
AB29
A_TX2P
AB28
A_TX2N
AB26
A_TX3P
AB27
A_TX3N
AE24
A_RX0P
AE23
A_RX0N
AD25
A_RX1P
AD24
A_RX1N
AC24
A_RX2P
AC25
A_RX2N
AB25
A_RX3P
AB24
A_RX3N
AD29
PCIE_CALRP
AD28
PCIE_CALRN
AA28
GPP_TX0P
AA29
GPP_TX0N
Y29
GPP_TX1P
Y28
GPP_TX1N
Y26
GPP_TX2P
Y27
GPP_TX2N
W28
GPP_TX3P
W29
GPP_TX3N
AA22
GPP_RX0P
Y21
GPP_RX0N
AA25
GPP_RX1P
AA24
GPP_RX1N
W23
GPP_RX2P
V24
GPP_RX2N
W24
GPP_RX3P
W25
GPP_RX3N
M23
PCIE_RCLKP/NB_LNK_CLKP
P23
PCIE_RCLKN/NB_LNK_CLKN
U29
NB_DISP_CLKP
U28
NB_DISP_CLKN
T26
NB_HT_CLKP
T27
NB_HT_CLKN
V21
CPU_HT_CLKP
T21
CPU_HT_CLKN
V23
SLT_GFX_CLKP
T23
SLT_GFX_CLKN
L29
GPP_CLK0P
L28
GPP_CLK0N
N29
GPP_CLK1P
N28
GPP_CLK1N
M29
GPP_CLK2P
M28
GPP_CLK2N
T25
GPP_CLK3P
V25
GPP_CLK3N
L24
GPP_CLK4P
L23
GPP_CLK4N
P25
GPP_CLK5P
M25
GPP_CLK5N
P29
GPP_CLK6P
P28
GPP_CLK6N
N26
GPP_CLK7P
N27
GPP_CLK7N
T29
GPP_CLK8P
T28
GPP_CLK8N
L25
14M_25M_48M_OSC
L26
25M_X1
L27
25M_X2
SB820M
SB820M
IC CTRL(605P)SB820M 218-0697014(FCBGA)
P/N : AJ069700T01
4
Part 1 of 5
Part 1 of 5
SB800
SB800
PCICLK4/14M_OSC/GPO39
PCI CLKS
PCI CLKS
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT3#/CLK_REQ7#/GPIO46
LDRQ1#/CLK_REQ6#/GPIO49
CLOCK GENERATOR
CLOCK GENERATOR
ALLOW_LDTSTP/DMA_ACTIVE#
CPU
CPU
RTC
RTC
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
FRAME#
DEVSEL#
PCI INTERFACELPC
PCI INTERFACELPC
REQ1#/GPIO40
GNT1#/GPO44
GNT2#/GPO45
CLKRUN#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LPCCLK0
LPCCLK1
LFRAME#
LDRQ0#
SERIRQ/GPIO48
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
32K_X1
32K_X2
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
CBE0#
CBE1#
CBE2#
CBE3#
IRDY#
TRDY#
STOP#
PERR#
SERR#
REQ0#
GNT0#
LOCK#
LAD0
LAD1
LAD2
LAD3
PAR
W2
W1
W3
W4
Y1
V2
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
AJ6
AG6
AG4
AJ4
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
G21
H21
K19
G22
J24
C1
C2
D2
B2
B1
20MIL
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCIRST#_L
+3V
AD23
AD24
AD25
AD26
AD27
SB820_MEMHOT#
INT_CLKREQ_MPC#
LPC_CLK0
LPC_CLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#_SB
LDRQ1#_SB
SERIRQ
ALLOW_LDTSTOP
CPU_PROCHOT#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_RST#
RTC_X1
RTC_X2
RTC_CLK
INTRUDER_ALERT#
VCCRTC_SB
3
T64T64
R69 33/J_4R69 33/J_4
BOARD_ID0
BOARD_ID1
<BOM Note>
BOARD_ID2
ID0/1/2 P/N Model
BOARD_ID3
000 AKD5LGGT506 SAM DDR3-800 1Gb K4W1G1646E-HC12
BOARD_ID4
001 AKD5LZGTW04 HYN DDR3-800 1Gb H5TQ1G63BFR-12C
010 AKD5LGGT700 ATI DDR3-800 1Gb 23EY2387MA12-SZ
R78 *10K/J_4R78 *10K/J_4
R296 BOM@10K/J_4R296 BOM@10K/J_4
R283 BOM@10K/J_4R283 BOM@10K/J_4
R63 *10K/J_4R63 *10K/J_4
R302 *10K/J_4R302 *10K/J_4
R300
R300
*0/J_4
*0/J_4
R342 22/J_4R342 22/J_4
R141 22/J_4R141 22/J_4
C115
C115
*0.1U/10V_4
*0.1U/10V_4
PCIRST#
C98 150P/50V_4C98 150P/50V_4
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
AD23 <14>
AD24 <14>
AD25 <14>
AD26 <14>
AD27 <14>
VDDR_1.2_EN="0" is for DDRIII-1066, VDDR=0.9V
VDDR_1.2_EN="1" is for DDRIII-1333, VDDR=1.05V
R293 *0/short_4R293 *0/short_4
T74T74
T76T76
LAD0 <23,25>
LAD1 <23,25>
LAD2 <23,25>
LAD3 <23,25>
LFRAME# <23,25>
T85T85
T83T83
SERIRQ <25>
ALLOW_LDTSTOP <8>
CPU_PROCHOT# <4>
CPU_PWRGD <4>
CPU_LDT_STOP# <4,8>
CPU_LDT_RST# <4>
RTC_CLK <25>
T62T62
R93 510/J_4R93 510/J_4
C116
C116
1U/10V_4
1U/10V_4
3
PCI_CLK1 <14>
PCI_CLK2 <14>
PCI_CLK3 <14>
PCI_CLK4 <14>
PCIRST# <23>
R77 SPM@10K/J_4R77 SPM@10K/J_4
R295 BOM@10K/J_4R295 BOM@10K/J_4
R284 BOM@10K/J_4R284 BOM@10K/J_4
R64 *10K/J_4R64 *10K/J_4
R303 *10K/J_4R303 *10K/J_4
VDDR_1.2_EN
CLKREQ_MPC# <23>
CLKRUN# <25>
LPC_CLK0 <14>
LPC_CLK1 <14>
LCLK_EC <25>
LCLK_DEBUG <23>
INTRUDER_ALERT# Left not connected (Southbridge
has 50-kohm internal pull-up to VBAT).
VCCRTC
+3V
R94
R94
R95
R95
*2.2K/J_4
*2.2K/J_4
*2.2K/J_4
*2.2K/J_4
2
Q10
Q10
*MMBT3904
*MMBT3904
1 3
From MINI PCIE 1
2
For AMD RST
For VDDR
MEM_1V5 is for gating the glitch on VDDR_1.2_EN
CPU_MEMHOT# <11,15>
RTC(RTC)
+3VPCU
VCCRTC_4
<20100119(B2A)_Bimini Rev1.4>
Non-stuff U21,C429,C428,R372,R300
(Nile doesn't support +1.05V for
DDR3-1333)
MEM_1V5<12>
VDDR_1.2_EN:
1 : VDDR =1.05V
0: VDDR = 0.90V (Default)
VCCRTC
D19
D19
CH500H-40
CH500H-40
D20
D20
CH500H-40
CH500H-40
R202
R202
1K/J_4
1K/J_4
20MIL
VCCRTC_3
BT1
BT1
RTC BATT
RTC BATT
2
1
RTC_X1
RTC_X2
2
Y2
2 3
1
32.768KHZY232.768KHZ
C111
C111
18P/50V_4
18P/50V_4
PLTRST#<21,23,24>
MINI-PCIE
LAN chip
Card reader
VDDR_1.2_EN
R56
R56
33/J_4
33/J_4
C80 0.1u/10V_4C80 0.1u/10V_4
A_RST#_AND
2
1
R368 *0/J_4R368 *0/J_4
G1
G1
12
*SHORT_PAD
*SHORT_PAD
R97
R97
*0/short_4
*0/short_4
4
C81
C81
10p/50V_4
10p/50V_4
R59 *0/J_4R59 *0/J_4
+3V
C429 *0.1U/10V_4C429 *0.1U/10V_4
U21
U21
3 5
*TC7SH08FU
*TC7SH08FU
+3V_S5
3 5
R372 *33/J_4R372 *33/J_4
4
20MIL
VCCRTC_2 VCCRTC_1
1 3
Q12
Q12
MMBT3904
MMBT3904
2
<20100303(C3A)>
Delete CN5 and Add BT1, for Battery SMT type.
<20100310(C3A)>
Swap BT1's pin, for pin define error
<BOM Note>
RTC BATTERY
AHL03001033 : JHT (18mAh)
AHL03001032 : MAT (17mAh)
AHL03001035 : FDK (15mAh)
4
<20100303(C3A)>
Change C93,C111 from CH02206JB08(22pF) to CH01806JB07(18pF), for Y2.
R7220M/J_6 R7220M/J_6
C93
C93
18P/50V_4
18P/50V_4
R213 8.06K/F_4R213 8.06K/F_4
R = (5V - 0.2V-2V)/0.2mA = 14k
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
A_RST#_SB
2
1
U4
U4
TC7SH08FU
TC7SH08FU
The Nile VDDR should be 0.9V
all the time. The 1.05V is only
for DDR3_1333 which is not
supported on Nile.
C428
C428
*150P/50V_4
*150P/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SB820-PCIE/CPU/LPC 1/5
SB820-PCIE/CPU/LPC 1/5
SB820-PCIE/CPU/LPC 1/5
R219 8.06K/F_4R219 8.06K/F_4
1
A_RST#_SB <25>
SB_GPIO_PCIE_RST# <11>
VDDR_OPT <33>
ZH9
ZH9
ZH9
10 40Sunday, March 28, 2010
10 40Sunday, March 28, 2010
10 40Sunday, March 28, 2010
68.1K/F_4
68.1K/F_4
150K/F_4
150K/F_4
R220
R220
R221
R221
+5VPCU
4A
4A
4A
5
+3V_S5
NC only ,Can't be install
R100 *2.2K/J_4R100 *2.2K/J_4
R98 *2.2K/J_4R98 *2.2K/J_4
R280 *2.2K/J_4R280 *2.2K/J_4
D D
SCL0/SDATA0 is +3.3V_S0 domain
To Clock gen/DDR/WLAN
+3V
R338 2.2K/J_4R338 2.2K/J_4
R335 2.2K/J_4R335 2.2K/J_4
SMBUS1~3 is +3.3V_S5 domain
If SMBUS and GPIO not implemented
10K PU to +3V_S5 or 10K PD
R279 10K/J_4R279 10K/J_4
R92 10K/J_4R92 10K/J_4
R133 10K/J_4R133 10K/J_4
R337 10K/J_4R337 10K/J_4
+1.8V
R136 10K/J_4R136 10K/J_4
R148 10K/J_4R148 10K/J_4
R340 300/J_4R340 300/J_4
To Azalia
ACZ_SDOUT
ACZ_SYNC
ACZ_BCLK
ACZ_RST#
ACZ_SDIN0
C C
B B
A A
SB_TEST0
SB_TEST1
SB_TEST2
SB_SCLK0
SB_SDATA0
SB_SCLK1
SB_SDATA1
SB_SCLK2
SB_SDATA2
SB_SCLK3
SB_SDATA3
NB_PWRGD
R85 33/J_4R85 33/J_4 R70 10K/J_4R70 10K/J_4
R86 33/J_4R86 33/J_4
R87 33/J_4R87 33/J_4
R88 *10K/J_4R88 *10K/J_4
R71 33/J_4R71 33/J_4
R90 *10K/J_4R90 *10K/J_4
C99 *10P/50V_4C99 *10P/50V_4
C100 *10P/50V_4C100 *10P/50V_4
C101 *10P/50V_4C101 *10P/50V_4
5
From MINI PCIE 2
From LAN
ACZ_SDOUT_AUDIO <19>
ACZ_SYNC_AUDIO <19>
ACZ_BITCLK_AUDIO <19>
ACZ_RST#_AUDIO <19>
ACZ_SDIN0 <19>
<20091030(A1A)_EMI's Suggest>
Add one 10pF to GND for BITCLK
CPU_MEMHOT#<10,15>
SUSB#<25>
SUSC#<25>
DNBSWON#<25>
ECPWROK<25>
SUS_STAT#<8>
GA20<25>
KBRST#<25>
EC_SMI#<25>
EC_SCI#<25>
PCIE_WAKE#<21,23>
CPU_THERMTRIP#<4>
NB_PWRGD<8>
EC_RSMRST#<25>
SB_GPIO_PCIE_RST#<10>
CLKREQ_MNC#<23>
SB_BEEP<19>
SB_SCLK0<15,23>
SB_SDATA0<15,23>
CLKREQ_LAN#<21>
SP_DDR3_RST#<6>
<20091202(A1A)_Confirm with AMD's Horace>
IDLEEXIT#(Multi function of Pin AA20) is used for server CPU.
USBOC#R<20>
USBOC#L<20>
ACZ_SDOUT<14>
4
T9T9
T13T13
T10T10
T19T19
HD audio interface is +3V_S5 voltage
R91 *0/J_4R91 *0/J_4
R294 *0/short_4R294 *0/short_4
R341 *0/short_4R341 *0/short_4
R333 *0/short_4R333 *0/short_4
R281 SPM@0/J_4R281 SPM@0/J_4
R277 *0/J_4R277 *0/J_4
R278 *0/J_4R278 *0/J_4
T73T73
T69T69
T68T68
T70T70
+3V_S5
T17T17
T22T22
4
SB_PWRGD
SUS_STAT#
SB_TEST0
SB_TEST1
SB_TEST2
SYS_RST#
CPU_THERMTRIP#
NB_PWRGD
RSMRST#
SB_GPIO_PCIE_RST#
INT_CLKREQ_MNC#
SB_SCLK0
SB_SDATA0
SB_SCLK1
SB_SDATA1
INT_CLKREQ_LAN#
LLB#
SHUTDOWN#
USBOC#67
USBOC#0
SB_JTAG_TDO
SB_JTAG_TCK
SB_JTAG_TDI
SB_JTAG_RST#
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0
ACZ_SYNC
ACZ_RST#
R84 10K/J_4R84 10K/J_4
R286 10K/J_4R286 10K/J_4
R83 10K/J_4R83 10K/J_4
R282 10K/J_4R282 10K/J_4
U5D
U5D
J2
PCI_PME#/GEVENT4#
K1
RI#/GEVENT22#
D3
SPI_CS3#/GBE_STAT1/GEVENT21#
F1
SLP_S3#
H1
SLP_S5#
F2
PWR_BTN#
H5
PWR_GOOD
G6
SUS_STAT#
B3
TEST0
C4
TEST1/TMS
F6
TEST2
AD21
GA20IN/GEVENT0#
AE21
KBRST#/GEVENT1#
K2
LPC_PME#/GEVENT3#
J29
LPC_SMI#/GEVENT23#
H2
GEVENT5#
J1
SYS_RESET#/GEVENT19#
H6
WAKE#/GEVENT8#
F3
IR_RX1/GEVENT20#
J6
THRMTRIP#/SMBALERT#/GEVENT2#
AC19
NB_PWRGD
G1
RSMRST#
AD19
CLK_REQ4#/SATA_IS0#/GPIO64
AA16
CLK_REQ3#/SATA_IS1#/GPIO63
AB21
SMARTVOLT1/SATA_IS2#/GPIO50
AC18
CLK_REQ0#/SATA_IS3#/GPIO60
AF20
SATA_IS4#/FANOUT3/GPIO55
AE19
SATA_IS5#/FANIN3/GPIO59
AF19
SPKR/GPIO66
AD22
SCL0/GPIO43
AE22
SDA0/GPIO47
F5
SCL1/GPIO227
F4
SDA1/GPIO228
AH21
CLK_REQ2#/FANIN4/GPIO62
AB18
CLK_REQ1#/FANOUT4/GPIO61
E1
IR_LED#/LLB#/GPIO184
AJ21
SMARTVOLT2/SHUTDOWN#/GPIO51
H4
DDR3_RST#/GEVENT7#
D5
GBE_LED0/GPIO183
D7
GBE_LED1/GEVENT9#
G5
GBE_LED2/GEVENT10#
K3
GBE_STAT0/GEVENT11#
AA20
CLK_REQG#/GPIO65/OSCIN
H3
BLINK/USB_OC7#/GEVENT18#
D1
USB_OC6#/IR_TX1/GEVENT6#
E4
USB_OC5#/IR_TX0/GEVENT17#
D4
USB_OC4#/IR_RX0/GEVENT16#
E8
USB_OC3#/AC_PRES/TDO/GEVENT15#
F7
USB_OC2#/TCK/GEVENT14#
E7
USB_OC1#/TDI/GEVENT13#
F8
USB_OC0#/TRST#/GEVENT12#
M3
AZ_BITCLK
N1
AZ_SDOUT
L2
AZ_SDIN0/GPIO167
M2
AZ_SDIN1/GPIO168
M1
AZ_SDIN2/GPIO169
M4
AZ_SDIN3/GPIO170
N2
AZ_SYNC
P2
AZ_RST#
T1
GBE_COL
T4
GBE_CRS
L6
GBE_MDCK
L5
GBE_MDIO
T9
GBE_RXCLK
U1
GBE_RXD3
U3
GBE_RXD2
T2
GBE_RXD1
U2
GBE_RXD0
T5
GBE_RXCTL/RXDV
V5
GBE_RXERR
P5
GBE_TXCLK
M5
GBE_TXD3
P9
GBE_TXD2
T7
GBE_TXD1
P7
GBE_TXD0
M7
GBE_TXCTL/TXEN
P4
GBE_PHY_PD
M9
GBE_PHY_RST#
V7
GBE_PHY_INTR
E23
PS2_DAT/SDA4/GPIO187
E24
PS2_CLK/SCL4/GPIO188
F21
SPI_CS2#/GBE_STAT2/GPIO166
G29
FC_RST#/GPO160
D27
PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
F29
PS2M_DAT/GPIO191
E27
PS2M_CLK/GPIO192
SB820M
SB820M
SB800
SB800
Part 4 of 5
Part 4 of 5
GBE LAN
GBE LAN
3
USBCLK/14M_25M_48M_OSC
ACPI / WAKE UP EVENTS
ACPI / WAKE UP EVENTS
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
HD AUDIO
HD AUDIO
EC_PWM3/EC_TIMER3/GPIO200
EMBEDDED CTRL
EMBEDDED CTRL
3
USB_FSD1P/GPIO186
USB_FSD0P/GPIO185
USB 1.1 USB MISCEMBEDDED CTRL
USB 1.1 USB MISCEMBEDDED CTRL
USB 2.0
USB 2.0
GPIO
GPIO
USB OC
USB OC
SCL3_LV/GPIO195
SDA3_LV/GPIO196
USB_RCOMP
USB_FSD1N
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
SCL2/GPIO193
SDA2/GPIO194
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
A10
G19
J10
H11
H9
J8
B12
A12
F11
E11
E14
E12
J12
J14
A13
B13
D13
C13
G12
G14
G16
G18
D16
C16
B14
A14
E18
E16
J16
J18
B17
A17
A16
B16
D25
F23
B26
E26
F25
E22
F22
E21
G24
G25
E28
E29
D29
D28
C29
C28
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
2
<20100129(B2A)>
Stuff R110. (CLK for Cardreader from crystal
change to internal CLK.)
SB_CLK_48M_CR
USB_RCOMP_SB
USB_FSD13P
USB_FSD13N
USB_FDS12P
USB_FSD12N
Controller Ports mapping
OHCI0 (dev-18, fun-0) Port 0 - 4
EHCI (dev-18, fun-2) Port 0 - 4
OHCI0 (dev-19, fun-0) Port 5 - 9
EHCI (dev-19, fun-2) Port 5 - 9
OHCI0 (dev-22, fun-0) Port 10 - 14
EHCI (dev-22, fun-2) Port 10 - 14
USB+_SIM <23>
USB-_SIM <23>
USBP7+ <20>
USBP7- <20>
USBP6+ <20>
USBP6- <20>
USBP5+ <18>
USBP5- <18>
USBP4+ <23>
USBP4- <23>
USBP3+ <16>
USBP3- <16>
USBP2+ <23>
USBP2- <23>
USBP1+ <24>
USBP1- <24>
USBP0+ <20>
USBP0- <20>
SB_SCLK2
SB_SDATA2
SB_SCLK3
SB_SDATA3
R110 ICK@22/J_4R110 ICK@22/J_4
R332 11.8K/F_6R332 11.8K/F_6
T75T75
T77T77
T72T72
T71T71
MM-SIM
CONN (Lower Right)
CONN (Upper Right)
BT
MNC
CCD
MPC
Card reader
CONN (Left)
EC_PWM2 <14>
EC_PWM3 <14>
2
OHCI (dev-20, fun-5)
1
CLK_48M_CR <24>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
to CARD READER 48MHz
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
PROJECT :
SB820-ACPI/GPIO/USB 2/5
SB820-ACPI/GPIO/USB 2/5
SB820-ACPI/GPIO/USB 2/5
ZH9
11 40Sunday, March 28, 2010
11 40Sunday, March 28, 2010
1
11 40Sunday, March 28, 2010
4A
4A
4A
5
4
3
2
1
SATA PORT 0,1,2,3
can support AHCI
mode
SATA_TXP0<22>
SATA HDD
D D
C C
SATA_TXN0<22>
SATA_RXN0<22>
SATA_RXP0<22>
To meet SB800 SCL1.02:
DNI SATA XTAL circuit's parts
B B
PLACE SATA AC COUPLING
CAPS CLOSE TO SB820
C141 0.01U/25V_4C141 0.01U/25V_4
C142 0.01U/16V_4C142 0.01U/16V_4
C140 0.01U/25V_4C140 0.01U/25V_4
C137 0.01U/25V_4C137 0.01U/25V_4
PLACE SATA_CAL
RES VERY CLOSE
TO BALL OF SB820
+1.1V_SB_VDDAN_11_SATA
R316 1K/F_4R316 1K/F_4
R315 931/F_4R315 931/F_4
SATALED#<22>
C151 *22P/50V_4C151 *22P/50V_4
Y3
Y3
*25MHz-SATA
*25MHz-SATA
C145 *22P/50V_4C145 *22P/50V_4
2 1
SATA_CALRP
SATA_CALRN
R304 10K/J_4R304 10K/J_4
+3V
SATA_X1
R114
R114
*1M/J_4
*1M/J_4
SATA_X2
SATA_TXP0_C
SATA_TXN0_C
SATA_RXN0_C
SATA_RXP0_C
U5B
U5B
AH9
SATA_TX0P
AJ9
SATA_TX0N
AJ8
SATA_RX0N
AH8
SATA_RX0P
AH10
SATA_TX1P
AJ10
SATA_TX1N
AG10
SATA_RX1N
AF10
SATA_RX1P
AG12
SATA_TX2P
AF12
SATA_TX2N
AJ12
SATA_RX2N
AH12
SATA_RX2P
AH14
SATA_TX3P
AJ14
SATA_TX3N
AG14
SATA_RX3N
AF14
SATA_RX3P
AG17
SATA_TX4P
AF17
SATA_TX4N
AJ17
SATA_RX4N
AH17
SATA_RX4P
AJ18
SATA_TX5P
AH18
SATA_TX5N
AH19
SATA_RX5N
AJ19
SATA_RX5P
AB14
SATA_CALRP
AA14
SATA_CALRN
AD11
SATA_ACT#/GPIO67
AD16
SATA_X1
AC16
SATA_X2
SB800
SB800
Part 2 of 5
Part 2 of 5
SERIAL ATA
SERIAL ATA
HW MONITOR
HW MONITOR
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FLASH
FLASH
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
TEMP_COMM
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
The flash controller function is NOT
supported by the SB820M.
AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
W5
W6
SB_PROCHOT#_C
Y9
W7
V9
W8
TEMPIN0
B6
TEMPIN1
A6
TEMPIN2
A5
B5
TEMP_COMM
C7
VIN0
A3
VIN1
B4
VIN2
A4
VIN3
C5
VIN4 VIN4
A7
VIN5
B7
VIN6
B8
VIN7
A8
R109 10K/J_4R109 10K/J_4
R108 10K/J_4R108 10K/J_4
R103 10K/J_4R103 10K/J_4
R290 10K/J_4R290 10K/J_4
R289 10K/J_4R289 10K/J_4
R288 10K/J_4R288 10K/J_4
R102 10K/J_4R102 10K/J_4
R409 10K/J_4R409 10K/J_4
R298 10K/J_4R298 10K/J_4
R301 10K/J_4R301 10K/J_4
R297 10K/J_4R297 10K/J_4
T45T45
T31T31
T39T39
T38T38
T37T37
T36T36
T43T43
T44T44
T32T32
IF THERE IS NO IDE, TEST
T33T33
POINTS FOR DEBUG BUS
T42T42
IS MANDATORY
T30T30
T29T29
T28T28
T23T23
T24T24
T21T21
T16T16
T80T80
T20T20
T25T25
T84T84
T34T34
T35T35
T40T40
T41T41
R106
R106
10K/J_4
10K/J_4
1 3
<20100119(B2A)_Bimini Rev1.4>
Non-stuff R408 ; stuff R409
(Nile doesn't support VDDR = +1.05V for DDR3-1333)
+3V
R105
R105
10K/J_4
10K/J_4
2
Q11
Q11
MMBT3904
MMBT3904
R107 10K/J_4R107 10K/J_4
THERM_ALERT# <4>
R408 *0/J_4R408 *0/J_4
SB_PROCHOT# <4>
+3V_S5
MEM_1V5 <10>
T67T67
T12T12
T11T11
T65T65
T66T66
A A
5
4
J5
SPI_DI/GPIO164
E2
SPI_DO/GPIO163
K4
SPI_CLK/GPIO162
K9
SPI_CS1#/GPIO165
G2
ROM_RST#/GPIO161
SB820M
SB820M
SPI ROM
SPI ROM
3
NC1
NC2
G27
Y2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ZH9
ZH9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
PROJECT :
SB820-SATA/HWM/SPI 3/5
SB820-SATA/HWM/SPI 3/5
SB820-SATA/HWM/SPI 3/5
ZH9
1
12 40Sunday, March 28, 2010
12 40Sunday, March 28, 2010
12 40Sunday, March 28, 2010
4A
4A
4A
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