Acer Aspire One AO521 Schematics

1

2

3

4

5

6

7

8

ZH9 Block Diagram (AMD Nile Platform)

DDR III,800 MT/s

HDT

A A

P4

Geneva

AMD ASB2 CPU

K125 (Athlon SC) 12W HT1
K325 (Athlon DC) 12W HT1

(812 balls ; 27x27mm)

P2~5

Channel A

HyperTransport LINK
16x16

UNBUFFERED
DDRIII SODIMM

P15

LVDS CON

HDMI CON

B B

VGA CON

P16

P17

P16

LVDS MUX

TMDS(PCIE 4x1)

DAC

PCIE GEN1

0

2

1

C C

LAN-AR8152L

3G

WLAN/WiMAX

SIM CARD

P23

Bluetooth

P21

4

P23

2

P23

8

5

P18

RS880M

HyperTransport LINK0 CPU I/F
DX10 IGP
SIDE PORT MEMORY

LVDS

1X16 PCIE I/F

1X4 PCIE I/F WITH SB
6X1 PCIE I/F

(21x21mm)

P6~9

A-Link X4

SB820M

USB2.0(14)+1.1(2)
SATA III(6 PORTS)
4X1 PCIE GEN2 I/F
PCI/PCI BDGE
INT. RTC
INT. CLK
EC
HD AUDIO

DDRIII

HD AUDIO I/F

SATA II I/F

SIDE PORT
DDRIII 128MB

AZALIA CODEC
CX20672

Mobile 2.5" HDD

P19

P22

P6

Headphone Jack
MIC In Jack
Digital MIC
Speaker Header

P19

LPC I/F
ACPI 1.1

(23x23mm)

P10~14

LPC

5 IN1
CARDREADER

P24

CCD

P16

USB PORT

P20

USB PORT

P20

06731

USB PORT

(Left)(Lower Right) (Upper Right)

P20

USB 2.0

BATTERY CHAGER

P26

D D

SYSTEM
5V/3V PCU

P27

AMD CPU Core
CPU_NB Core

P28

1

NB CORE

DDR 1.5VSUS

+1.1V
(VLDT)

P29

P30

P31

2

+1.8V

Discharge/+2.5V/
VDDR

P32

P33

Thermal Protection

P34

EC

Winbond NPCE781L

P25

SMBUS

CPU
THERMAL SENSOR

P4

Quanta Computer Inc.

Quanta Computer Inc.

P4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

6

Date: Sheet of

7

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

PROJECT :

Block Diagram

Block Diagram

Block Diagram

ZH9

1 40Sunday, March 28, 2010

1 40Sunday, March 28, 2010

1 40Sunday, March 28, 2010

8

4A

4A

4A

P25

Charger

5

PWM FAN

P26

Keyboard

3

Touch Pad

P18 P18

4

SPI Flash

5

D D

HT_CADINP[15..0]<6>
HT_CADINN[15..0]<6>
HT_CLKINP[1..0]<6>

C C

B B

HT_CLKINN[1..0]<6>
HT_CTLINP[1..0]<6>

HT_CTLINN[1..0]<6>
HT_CADOUTP[15..0]<6>
HT_CADOUTN[15..0]<6>
HT_CLKOUTP[1..0]<6>
HT_CLKOUTN[1..0]<6>
HT_CTLOUTP[1..0]<6>
HT_CTLOUTN[1..0]<6>

HT_CADINP[15..0]
HT_CADINN[15..0]

HT_CLKINP[1..0]

HT_CLKINN[1..0]
HT_CTLINP[1..0]

HT_CTLINN[1..0]
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]

HT_CLKOUTP[1..0]

HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]

HT_CTLOUTN[1..0]

4

HT_CADINP15

HT_CADINN15

HT_CADINP14

HT_CADINN14

HT_CADINP13

HT_CADINN13

HT_CADINP12

HT_CADINN12

HT_CADINP11

HT_CADINN11

HT_CADINP10

HT_CADINN10

HT_CADINP9

HT_CADINN9

HT_CADINP8

HT_CADINN8

HT_CADINP7

HT_CADINN7

HT_CADINP6

HT_CADINN6

HT_CADINP5

HT_CADINN5

HT_CADINP4

HT_CADINN4

HT_CADINP3

HT_CADINN3

HT_CADINP2

HT_CADINN2

HT_CADINP1

HT_CADINN1

HT_CADINP0

HT_CADINN0

HT_CLKINP1
HT_CLKINN1

HT_CLKINP0
HT_CLKINN0

HT_CTLINP1
HT_CTLINN1

HT_CTLINP0

W7
W6

M2
M1

M8
M7

M3
M4

U6
U5
R7
R6
P6
P5

L6
L5
J6

J5
H4
H3
G6
G5
T3
T4
T2
T1
P3
P4
P2
P1

K3
K4
K2
K1
H2
H1

Y6
Y5

V2
V1

3

U16A

U16A

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLIN_H0
L0_CTLIN_L0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

HT LINK

HT LINK

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

HT_CADOUTP15

AB6

HT_CADOUTN15

AB5

HT_CADOUTP14

AB9

HT_CADOUTN14

AB8

HT_CADOUTP13

AC7

HT_CADOUTN13

AC6

HT_CADOUTP12

AE6

HT_CADOUTN12

AE5

HT_CADOUTP11

AE9

HT_CADOUTN11

AE8

HT_CADOUTP10

AH3

HT_CADOUTN10

AH4

HT_CADOUTP9

AK3

HT_CADOUTN9

AK4

HT_CADOUTP8

AH1

HT_CADOUTN8

AH2

HT_CADOUTP7

Y1

HT_CADOUTN7

Y2

HT_CADOUTP6

Y4

HT_CADOUTN6

Y3

HT_CADOUTP5

AB1

HT_CADOUTN5

AB2

HT_CADOUTP4

AB4

HT_CADOUTN4

AB3

HT_CADOUTP3

AD4

HT_CADOUTN3

AD3

HT_CADOUTP2

AF1

HT_CADOUTN2

AF2

HT_CADOUTP1

AF4

HT_CADOUTN1

AF3

HT_CADOUTP0

AK1

HT_CADOUTN0

AK2

HT_CLKOUTP1

AF6

HT_CLKOUTN1

AF5

HT_CLKOUTP0

AD1

HT_CLKOUTN0

AD2

HT_CTLOUTP1

Y8

HT_CTLOUTN1

Y9

HT_CTLOUTP0

V4

HT_CTLOUTN0HT_CTLINN0

V3

2

1

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

PROJECT :

ASB2 HT I/F 1/4

ASB2 HT I/F 1/4

ASB2 HT I/F 1/4

ZH9

4A

4A

4A

2 40Sunday, March 28, 2010

2 40Sunday, March 28, 2010

2 40Sunday, March 28, 2010

1

A

B

C

D

E

Processor Memory Interface

U16C

P33

MB_ADD15

P31

MB_ADD14

AJ33

MB_ADD13

T32

MB_ADD12

T31

MB_ADD11

AD32

MB_ADD10

T33

MB_ADD9

V32

MB_ADD8

U33

MB_ADD7

V33

MB_ADD6

V31

MB_ADD5

W33

MB_ADD4

Y31

MB_ADD3

Y33

MB_ADD2

Y32

MB_ADD1

AC33

MB_ADD0

R33

MB_BANK2

AD33

MB_BANK1

AE33

MB_BANK0

K33

MB_CHECK7

K31

MB_CHECK6

G32

MB_CHECK5

F32

MB_CHECK4

L33

MB_CHECK3

K32

MB_CHECK2

H31

MB_CHECK1

G33

MB_CHECK0

J33

MB_DQS_H8

H32

MB_DQS_L8

AM14

MB_DQS_H7

AN14

MB_DQS_L7

AL20

MB_DQS_H6

AM20

MB_DQS_L6

AN26

MB_DQS_H5

AM26

MB_DQS_L5

AN30

MB_DQS_H4

AM30

MB_DQS_L4

D33

MB_DQS_H3

D32

MB_DQS_L3

B28

MB_DQS_H2

A28

MB_DQS_L2

A21

MB_DQS_H1

B20

MB_DQS_L1

B16

MB_DQS_H0

A15

MB_DQS_L0

AN22

MB_CLK_H7

AM22

MB_CLK_L7

AN21

MB_CLK_H6

AM21

MB_CLK_L6

AA32

MB_CLK_H5

AA33

MB_CLK_L5

AB33

MB_CLK_H4

AB32

MB_CLK_L4

AB31

MB_CLK_H3

AB30

MB_CLK_L3

AD31

MB_CLK_H2

AD30

MB_CLK_L2

C22

MB_CLK_H1

B22

MB_CLK_L1

A22

MB_CLK_H0

A23

MB_CLK_L0

N33

MB_CKE1

P32

MB_CKE0

AK31

MB1_ODT1

AH31

MB1_ODT0

AK32

MB0_ODT1

AH33

MB0_ODT0

AK33

MB1_CS_L1

AF33

MB1_CS_L0

AJ32

MB0_CS_L1

AF31

MB0_CS_L0

AF32

MB_RAS_L

AH32

MB_CAS_L

AG33

MB_WE_L

L32

MB_RESET_L

M33

FREE|MB_EVENT_L

BOM@ASB2_CPU

BOM@ASB2_CPU

U16C

MB_DM8
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

AN13
AL14
AL16
AN17
AN12
AM12
AM16
AN16
AL18
AN19
AM24
AN24
AM18
AN18
AL22
AN23
AM25
AL26
AN28
AL28
AL24
AN25
AN27
AM28
AM29
AL30
AL32
AL33
AK28
AN29
AM31
AM32
E33
D31
B31
A31
F33
F31
C32
B32
C30
A29
B26
A26
B30
A30
A27
C26
A24
B24
C18
A18
A25
C24
C20
A19
C16
A16
B14
A13
B18
A17
C14
A14

H33
AN15
AN20
AK26
AN31
C33
C28
A20
D14

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ASB2 DDRIII MEMORY 2/4

ASB2 DDRIII MEMORY 2/4

ASB2 DDRIII MEMORY 2/4

E

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25

DDR III: CHANNEL B

DDR III: CHANNEL B

MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10

MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

D

ZH9

ZH9

ZH9

4A

4A

3 40Sunday, March 28, 2010

3 40Sunday, March 28, 2010

3 40Sunday, March 28, 2010

4A

U16B

U16B

M_A_A15

P30

M29

AG28

P28
T30

AC28

P27
R26
R27
U28

V30
U27

Y30

AB29

W29

AC26

R29

AC29
AE28

K30

J29

G29

F29

L28

L29
H29
H27

J27
J26

AJ11
AK12
AG15
AH15
AH22
AG22
AG26
AH26

E28
F28
E25

F25
G17
H17

E12

F12

AK18

AJ17
AH17
AG17

Y28

Y27
AB27
AB26

W27
W26

P26

M26
D18

F19

E20

E19

M30
M28

AJ29
AF27
AJ30

AG29
AH29

AE29
AH30

AF29

AC27

AF30

AE27

L27

M32

BOM@ASB2_CPU

BOM@ASB2_CPU

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0

MA_DQS_H8
MA_DQS_L8
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0

MA_CLK_H7
MA_CLK_L7
MA_CLK_H6
MA_CLK_L6
MA_CLK_H5
MA_CLK_L5
MA_CLK_H4
MA_CLK_L4
MA_CLK_H3
MA_CLK_L3
MA_CLK_H2
MA_CLK_L2
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0

MA_CKE1
MA_CKE0

MA1_ODT1
MA1_ODT0
MA0_ODT1
MA0_ODT0

MA1_CS_L1
MA1_CS_L0
MA0_CS_L1
MA0_CS_L0

MA_RAS_L
MA_CAS_L
MA_WE_L

MA_RESET_L
FREE|MA_EVENT_L

M_A_A14
M_A_A13
M_A_A12
M_A_A11

4 4

M_A_BANK2<15>
M_A_BANK1<15>
M_A_BANK0<15>

3 3

2 2

1 1

M_A_DQSP7<15>
M_A_DQSN7<15>
M_A_DQSP6<15>
M_A_DQSN6<15>
M_A_DQSP5<15>
M_A_DQSN5<15>
M_A_DQSP4<15>
M_A_DQSN4<15>
M_A_DQSP3<15>
M_A_DQSN3<15>
M_A_DQSP2<15>
M_A_DQSN2<15>
M_A_DQSP1<15>
M_A_DQSN1<15>
M_A_DQSP0<15>
M_A_DQSN0<15>

M_A_CLKP1<15>
M_A_CLKN1<15>
M_A_CLKP2<15>
M_A_CLKN2<15>

M_A_CKE1<15>
M_A_CKE0<15>

M_A_ODT1<15>
M_A_ODT0<15>

M_A_CS#1<15>
M_A_CS#0<15>

M_A_RAS#<15>
M_A_CAS#<15>
M_A_WE#<15>

M_A_RST#<15>

MEMHOT_MA#<15>

<Layout note>
Route as 60 ohms with
5/10 W/S from CPU pins.

M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0

R285 *0/J_4R285 *0/J_4

DDR III: CHANNEL A

DDR III: CHANNEL A

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

AG11
AH11
AJ12
AJ14
AF11
AF12
AG12
AH12
AK14
AF15
AH19
AK20
AF14
AG14
AF17
AG19
AG20
AJ20
AF22
AK24
AF19
AF20
AJ23
AG23
AF23
AF25
AH27
AK30
AJ25
AG25
AJ26
AJ28
D28
G28
D26
E26
F30
E29
F27
H26
H25
D24
H22
E22
F26
G26
D22
G23
G22
G20
G15
F15
D20
F22
D16
E17
H15
H14
G12
H12
E15
E14
E11
F11

H30
AL12
AK16
AK22
AJ27
E27
E23
H19
G14

M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0

M_A_DM7
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DM3
M_A_DM2
M_A_DM1
M_A_DM0

<BOM Note>
V105 : AJ00105VT00
K125 : AJ0K125VT02

M_A_DQ[0..63] <15>M_A_A[0..15]<15>

M_A_DM[0..7] <15>

K325 : AJ0K325VT02
K625 : AJ0K625VT03

A

B

C

5

CPU Thermal monitor(THM)

<20100303(C3A)>
Reserve R266,C315,C316,U15,R276,R410 and stuff R51~R53,R48,Q7~Q9,D2,D3,R411, for AMD SB-TSI.

2ND_MBCLK<25>

D D

THERM_ALERT#<12>

C C

2ND_MBDATA CPU_SID

2ND_MBDATA<25>

3

+3V

+1.5VSUS

R51

R51

2.2K/J_4

2.2K/J_4

2

Q8

MMBT3904Q8MMBT3904

13

21

D3 RB501V-40D3 RB501V -40

+3V

2

1

Q17*2N7002K Q17*2N7002K

R276 *10K/J_4R276 *10K/J_ 4

THERM_OVERT#

R48

R48

2.2K/J_4

2.2K/J_4

2

Q7

MMBT3904Q7MMBT3904

13

21

D2 RB501V-40D2 RB501V -40

R275

R275
*10K/J_4

*10K/J_4

THERM_ALERT#_R

R53

R53

2.2K/J_4

2.2K/J_4

2

Q9

13

MMBT3904Q9MMBT3904

U15

U15

8

VCC

SCLK

7

DXP

SDA

6

DXN

ALERT#

4

GND

OVERT#

*G786P81U

*G786P81U

ADDRESS: 0x4C(98H)
(1001100)

+1.5VSUS

R50

R50
1K/J_4

1K/J_4

<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard

R42

R42
1K/J_4

1K/J_4

CPU FAN(THM)

FANSIG<25>

+5V

THERM_OVERT#
THERM_ALERT#

CPUFAN#<25>

R410 *0/J_4R410 *0/J_4
R411 *0/short_4R411 *0/short_4

+5V

B B

THERM_FAN#

1 3

R31 *0/short_6R3 1 *0/short_6

2

Q5
MMBT3904Q5MMBT3904

+5V_FANVCC

C29

C29

0.01U/25V_4

0.01U/25V_4

R34

R34
10K/J_4

10K/J_4

FAN_PWM_CN

4

+3V

R266

R266
*200/J_4

*200/J_4

C315

C315
*0.1U/10V _4

*0.1U/10V _4

+3V_THMVCC

1
2
3
5

+3V

FAN CONN
Follow PDC pin define

R52

R52
1K/J_4

1K/J_4

CPU_ALERT_LTHERM_ALERT#

R44

R44
10K/J_4

10K/J_4

C316

C316
*2200P/5 0V_4

*2200P/5 0V_4

CPU_SIC2ND_MBCLK

CN13

CN13

1
2

5

3

6

4

FAN CONN

FAN CONN

H_THERMDA

H_THERMDC

+2.5V

CLK_CPU_BCLKP<10>

CPU CLK

CLK_CPU_BCLKN<10>

+1.5VSUS

R324

R324

1K/F_4

1K/F_4

R311

R311

1K/F_4

1K/F_4

L37 3A/30ohm_ 6L37 3A/30ohm_6

C372

C372

180P/50V_4

180P/50V_4

Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"

CPU_M_VRE F

C344

C344

0.01U/25V_4

0.01U/25V_4

DCR:0.03ohm

CLK_CPU_BCLKP

CLK_CPU_BCLKN

1000P/50V_4

1000P/50V_4

3

W/S= 15 mil/20mil

+CPUVDDA

C361

C361

C351

C351

4.7U/6.3V _6

4.7U/6.3V _6

0.22U/6.3 V_4

0.22U/6.3 V_4

C367 3900P/25V_4C367 3900P/25 V_4

C366 3900P/25V_4C366 3900P/25 V_4

<20091202(A1A)_Confirm with AMD's Reden>
RSVD_SA0 is a VSS pin, so connect to GND.

C355

C355

CPU_PWRGD<10>

CPU_LDT_STOP #<8 ,10>

CPU_LDT_RST#<10>

CPU_VDD_FB _L<28>
CPU_VDD_FB _H<28>

CPU_VDDNB_ FB_H<28>
CPU_VDDIO_FB_H<30>
CPU_VDDR_F B_H<33>

R271 39.2/F_4R271 39.2/F_4

CLOSE TO CPU WITHIN 1"

T78T78
T79T79

T82T82
T8T8
T6T6
T59T59

C345

C345
3300P/50V_4

3300P/50V_4

W/S= 15 mil/20mil

+CPUVDDA

R314

R314
169/F_4

169/F_4

T60T60

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASS CLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST9_ANALOGIN
CPU_TEST17_BP3

CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3
CPU_TEST2

+CPUVDDA

CLK_CPU_BCLKP_C
CLK_CPU_BCLKN_C

CPU_PWRGD
CPU_LDT_STOP #
CPU_LDT_RST#

SideBand Temp sense I2C

CPU_SIC
CPU_SID
RSVD_SA0
CPU_ALERT_L

CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS

CPU_DBREQ #

CPU_VLDT_FB _H

CPU_M_VRE F
M_ZP
M_ZN

250mA

A8

VDDA_1

B8

VDDA_2

A6

CLKIN_H

A7

CLKIN_L

D10

PWROK

E9

LDTSTOP_L

F9

RESET_L

AN4

SIC

AN5

SID

AM2

RSVD_SA0

AN3

ALERT_L

AM8

TDI

AL8

TRST_L

AK8

TCK

AN8

TMS

G9

DBREQ_L

D2

VSS_SENSE

E2

VLDT_SENSE

E1

VDD_SENSE

D1

VDDNB_SENSE

D3

VDDIO_SENSE

C2

VDDR_SENSE

A11

M_VREF

AM9

M_ZN_H

AN9

M_ZN_L

A9

BYPASSCLK_H

B9

BYPASSCLK_L

A5

PLLTEST0

B6

PLLTEST1

G8

ANALOGIN

F8

BP3

C8

BP2

D9

BP1

E8

BP0

C6

ANALOG_T

AH7

DIECRACKMON

AK5

GATE0

AJ7

DRAIN0

<Visual Comment>

<Visual Comment>

U16D

U16D

MISC

MISC

RSVD|CORE_TYPE

THERMDC
THERMDA

THERMTRIP_L

PROCHOT_L

DBRDY

RSVD3

CPU_PRESENT_L

HTREF1
HTREF0

FBCLKOUT_H

FBCLKOUT_L

SCANCLK1

TSTUPD

SCANSHIFTEN

SCANEN

SCANCLK2

PLLCHRZ_H
PLLCHRZ_L

SINGLECHAIN

BURNIN_L

ANALOGOUT

DIG_T

M_TEST

2

M31

C1

SVC

B2

SVD

AL6
AM5
AK6
AN6

AN7

TDO

H9

AM6
AJ9

V10
V9

B10
A10

AK7
AG8
AK9
AH9
AM7

G11
H11
AJ8
AM4
D7
B5

AG9

CPU_CORE_ TYPE

CPU_SVC_R
CPU_SVD_R

H_THERMDC
H_THERMDA
CPU_THERMTRIP_ L#
CPU_PROCHO T_L#

CPU_TDO

CPU_DBRDY

RSVD3
CPU_PRESENT_L

CPU_HTREF1
CPU_HTREF0

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKO UT_N

CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2

CPU_TEST28_H_PLLCHRZ_ P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST27_SINGLECHA IN
CPU_TEST26_BURNIN_L
CPU_TEST10_ANALOGOUT
CPU_TEST8_DIG_T

T58T58

Place them to CPU within 1.5"

R76 44.2/F_4R76 44 .2/F_4
R75 44.2/F_4R75 44 .2/F_4

CPU_THERMTRIP_ L#

+1.5VSUS

<Layout note>
Keep net PWRGD, LDT_STOP#, LDT_RST# no stub

CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP #

<20091029(A1A)_47337_ASB2_scl_nda_1.00>
CPU_PRESENT_L net are pulled up to VDDIO with 1Kohm
CPU_TEST20_SCANCLK2 and CPU_TEST21_SCANEN net are pulled down to GND with 1Kohm

CPU_PRESENT_L
CPU_DBREQ #
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST26_BURNIN_L
CPU_TEST27_SINGLECHA IN

T63T63

Route as 80ohm, diff

R310 80.6/F_4R310 80.6/F_4

CPU_PROCHO T_L#

CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2

CPU_TEST25_L_BYPASS CLK_L

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST23_TSTUPD
CPU_TEST9_ANALOGIN

<20091202(A1A)_Confirm with AMD's Reden>
CPU_TEST23_TSTUPD PD with 1K and add a test point

CPU_TEST10_ANALOGOUT

+1.1V_CPU_VLDT

T7T7

route as differential as short as possible.

T15T15

testpoint under package

T14T14

T81T81

+1.5VSUS

R39

R39
10K/J_4

10K/J_4

R45

R45
1K/J_4

1K/J_4

2

Q6

R41 *0/J_4R41 *0 /J_4

1 3

MMBT3904Q6MMBT3904

R46 *0/short_4R46 *0/short_ 4

R265 300/J_4R265 300/J_4

R273 *0/short_4R273 *0/short_4
R272 *0/short_4R272 *0/short_4

1

R309 300/J_4R309 300/J_4
R319 300/J_4R319 300/J_4
R308 300/J_4R308 300/J_4

R268 1K/J_4R268 1K/J_4
R307 300/J_4R307 300/J_4
R135 510/F_4R135 510/F_4
R264 1K/J_4R264 1K/J_4
R269 1K/J_4R269 1K/J_4

R270 *300/J_4R270 *300/J_4
R127 *300/J_4R127 *300/J_4
R126 *300/J_4R126 *300/J_4
R55 1K/J_4R55 1K/J_4
R267 1K/J_4R267 1K/J_4
R128 510/F_4R128 510/F_4
R123 1K/J_4R123 1K/J_4
R124 1K/J_4R124 1K/J_4
R47 1K/J_4R47 1K/J_4
R274 1K/J_4R274 1K/J_4
R54 1K/J_4R54 1K/J_4
R125 *0/short_4R125 *0/short_4

R330 *300/J_4R330 *300/J_4

CPU_THERMTRIP# <11>

SYS_SHDN# <2 7,34>

CPU_PROCHO T# <10>
SB_PROCHOT# <12>

+1.5V

+1.5VSUS

+1.1V_CPU_VLDT

+1.5V

R371

R371

*HDT@4.7K/J_ 4

*HDT@4.7K/J_ 4

+3V

Q18

Q18

3

2

*HDT@FDV301N

*HDT@FDV301N

1

CPU_LDT_RST#

4

HDT Connector

+1.5VSUS

A A

CPU_DBREQ #
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

C431 *HDT@0.1U/10 V_4C431 *HDT@0.1U/10V_4

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24

KEY

KEY

CN18

CN18

*HDT@HDT CONN

*HDT@HDT CONN

5

CPU_LDT_RST_HT#

25

Serial VID

+1.5V

+1.5VSUS

+1.5V

+1.5VSUS

+1.5V

CPU_SVC_R
CPU_SVD_R CPU_SVD
CPU_PWRGD

To override VID,
Remove three 0ohms and install 220ohm of CPU_PWRGD to GND

R321 *2.2K/J_4R321 *2.2K/J_4

R326 1K/J_4R326 1K/J_4
R331 *1K/J_4R331 *1K/J_4

R322 1K/J_4R322 1K/J_4
R328 *1K/J_4R328 *1K/J_4

R312 *0/short_4R312 *0/short_4
R318 *0/short_4R318 *0/short_4
R323 *0/short_4R323 *0/short_4

R313 *220/J_4R313 *220/J_4
R317 *220/J_4R317 *220/J_4
R329 *220/J_4R329 *220/J_4

<20091028(A1A)_47337_ASB2_scl_nda_1.00>
SVC/SVD net are pulled up to VDDIO with 1Kohm

CPU_SVC
CPU_PWRGD_SVID_ REG

3

CPU_SVC <28>
CPU_SVD <28>
CPU_PWRGD_SVID_ REG <28>

Pre-PWROK Metal MODE

SVC SVD Voltage Output

0 0
001
1
1

2

1

1.1V

1.0V

0.9V

0.8V

VFIX MODE(Don't Support)

Voltage Output

1.4V

1.2V

1.0V

0.8V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ASB2 CTRL & DEBUG 3/4

ASB2 CTRL & DEBUG 3/4

ASB2 CTRL & DEBUG 3/4

1

ZH9

ZH9

ZH9

4 40Sunday, March 28, 2010

4 40Sunday, March 28, 2010

4 40Sunday, March 28, 2010

4A

4A

4A

0.7~1.1V

D D

C C

CPU_CORE CPU_VDDNB_CORE

U16E

U16E

D4

VDD_1

D5

VDD_2

D6

VDD_3

E5

VDD_4

E6

VDD_5

E7

VDD_6

F5

VDD_7

F6

VDD_8

F7

VDD_9

H7

VDD_10

H8

VDD_11

J8

VDD_12

E4

VDD_13

J10

VDD_14

J12

VDD_15

J14

VDD_16

J18

VDD_17

J20

VDD_18

J21

VDD_19

J23

VDD_20

J9

VDD_21

K10

VDD_22

K12

VDD_23

K14

VDD_24

K18

VDD_25

K20

VDD_26

K21

VDD_27

K23

VDD_28

N4

VDD_29

L11

VDD_30

L13

VDD_31

L7

VDD_32

L9

VDD_33

M10

VDD_34

M12

VDD_35

R4

VDD_36

M5

VDD_37

N11

VDD_38

N24

VDD_39
VDD_40W4VDD_46

N9

VDD_41

P15

VDD_42

P18

VDD_43

BOM@ASB2_CPU

BOM@ASB2_CPU

CPU_CORE

+

PC43

+

PC43
330U/2V_7343

330U/2V_7343

C86

C86
22U/6.3V_8

22U/6.3V_8

5

CPU_CORE

C84

C84
22U/6.3V_8

22U/6.3V_8

POWER1

POWER1

CPU_CORECPU_CORE +1.5VSUS +1.1V_CPU_VLDT

AE12

VDD_85

AD9

VDD_84

AE21

VDD_83

AD21

VDD_82

AD18

VDD_81

AD14

VDD_80

AD12

VDD_79

AD11

VDD_78

AC5

VDD_77

AE18

VDD_76

AC24

VDD_75

AC12

VDD_74

AC10

VDD_73

AB13

VDD_72

AB11

VDD_71

AE14

VDD_70

AA24

VDD_69

AA12

VDD_68

AA10

VDD_67

Y19

VDD_66

Y16

VDD_65

Y14

VDD_64

W5

VDD_63

W20

VDD_62

W18

VDD_61

W15

VDD_60

AE23

VDD_59

V24

VDD_58

V19

VDD_57

V16

VDD_56

V14

VDD_55

T20

VDD_54

T18

VDD_53

T15

VDD_52

T10

VDD_51

R5

VDD_50

R19

VDD_49

R16

VDD_48

R14

VDD_47

AC4
P24

VDD_45

P20

VDD_44

BOTTOM SIDE DECOUPLING

15A

C85

C85

C87

C87

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C122

C122

C121

C121

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C124

C124
22U/6.3V_8

22U/6.3V_8

C109

C109

0.22U/6.3V_4

0.22U/6.3V_4

M27

Y26
U26
N32
U32
N30

P29
R28
R30
R32
U29
U30

W28
W30
W32

Y29

AA30
AB28
AE32
AC30
AC32
AE26
AE30
AF28
AG30
AG32
AD25
AA25
AC25

V25

P25
N25
M25

K25

L25

T25

Y25

AB25

BOM@ASB2_CPU

BOM@ASB2_CPU

C123

C123
22U/6.3V_8

22U/6.3V_8

U16F

U16F

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38

C110

C110

0.01U/25V_4

0.01U/25V_4

4

VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4

VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4

VDDR_1
VDDR_2
VDDR_3
VDDR_4

POWER2

POWER2

VDDR_5
VDDR_6
VDDR_7
VDDR_8

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6

PROGEN_L

FREE_1
FREE_2
FREE_3
FREE_4
FREE_5
FREE_6
FREE_7
FREE_8
FREE_9

C120

C120

0.22U/6.3V_4

0.22U/6.3V_4

180P/50V_4

180P/50V_4

C83

C83

F1
F2
F3
F4

AL1
AL2

CPU_VDDR

AL3
AL4

A12
B12
C12
D12

AK10
AL10

0.8~1.1V

AM10
AN10

CPU_VDDNB_CORE

A3
A4
B3
B4
C3
C4

B11

G7
B7
AH8
AJ6
B25
AM3
AN11
P9
P8

<20091028(A1A)_47337_ASB2_scl_nda_1.00>
Add two 4.7uF for CPU_CORE

C130

C125

C125

0.01U/25V_4

0.01U/25V_4

C130

180P/50V_4

180P/50V_4

2A

C354

C354
22U/6.3V_8

22U/6.3V_8

3

2

PROCESSOR POWER AND GROUND

U16H

U16H

AM19

VSS_207

AF7

VSS_167

AF26

VSS_166

AE7

VSS_165

AF8

VSS_168

AF9

VSS_169

AG1

VSS_170

AG2

VSS_171

AG27

VSS_172

AG4

VSS_173

AG5

VSS_174

AG6

VSS_175

AG7

VSS_176

AE4

VSS_164

AE25

VSS_163

AE24

VSS_162

AE22

VSS_161

AE20

VSS_160

AE2

VSS_159

AE16

VSS_158

AE13

VSS_157

AH14

VSS_177

AE11

VSS_156

AE10

VSS_155

AE1

VSS_154

AD24

VSS_153

AD23

VSS_152

AD22

VSS_151

AH20

VSS_178

AH23

VSS_179

AH25

VSS_180

AH28

VSS_181

AD20

VSS_150

AD16

VSS_149

AD13

VSS_148

AD10

VSS_147

AC9

VSS_146

AC8

VSS_145
VSS_214A2VSS_215

AC23

VSS_144

AH5

VSS_182

AJ1

VSS_183

AJ15

VSS_184

W2

VSS_116

A32

VSS_213

W8

VSS_117

Y10

VSS_118

Y15

VSS_119

Y18

VSS_120

AJ19

VSS_185

AJ2

VSS_186

AJ22

VSS_187

AJ4

VSS_188

Y20

VSS_121

Y24

VSS_122

AK11

VSS_189

AK13

VSS_190

Y7

VSS_123

AA1

VSS_124

AA11

VSS_125

C106

C106

4.7U/6.3V_6

4.7U/6.3V_6

C380

C380
22U/6.3V_8

22U/6.3V_8

4.7U/6.3V_6

4.7U/6.3V_6

C371

C371
22U/6.3V_8

22U/6.3V_8

C105

C105

U16G

U16G

N22
N23

M21

R15
R18

R20
D29
D30

G19
G25

G27
N10

B1
N2

B13
B15
B17

B19
B21
B23
B27
B29
B33
C10
P10
P14
P16
P19

P7
C31
D11
D13
D15

R1
D17
D19
D21
D23
D25
D27

R2

D8
E30
E32
F14
F17

R8
T14
T16
F20
T19
T24

T9

U1
F23

N1

G1

G2

VSS_1
VSS_28
VSS_29
VSS_30
VSS_2
VSS_3
VSS_4
VSS_27
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_12
VSS_13
VSS_14
VSS_15
VSS_36
VSS_16
VSS_17
VSS_18

GND1

GND1

VSS_19
VSS_20
VSS_21
VSS_37
VSS_38
VSS_39
VSS_40
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_115

BOM@ASB2_CPU

BOM@ASB2_CPU

VSS_45
VSS_44
VSS_43
VSS_42
VSS_26
VSS_25
VSS_41
VSS_24
VSS_23
VSS_22
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114

W19
W1
V20
V18
M11
L8
V15
L4
L30
L26
L24
L23
L22
L21
L2
L12
L10
L1
K9
M6
K24
K22
K16
M22
K13
M24
K11
M23
J7
W16
J4
W14
J32
J30
M13
J28
U8
J25
U4
J24
U7
U2
J2
J16
J13
J11
J1
H6
H5
H28
H23
H20
J22
M9
G4
G30
N12

PLACE CLOSE TO PROCESSOR AS POSSIBLE

GND2

GND2

BOM@ASB2_CPU

BOM@ASB2_CPU

VSS_191
VSS_192
VSS_193
VSS_194
VSS_126
VSS_127
VSS_128
VSS_195
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_137
VSS_138
VSS_205
VSS_206
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

AK15
AK17
AK19
AK21
AA2
AA22
AA23
AK23
AA4
AA9
AB10
AB12
AB21
AB22
AB23
AB24
AK25
AK27
AK29
AJ5
AH6
AL31
AM1
AM13
AB7
AC1
AM15
AM17
AC11
AC13
AC2
AC21
AC22
AM23
AM27
AM33
AN2
AN32
AM11

1

B B

+1.5VSUS

3A

C103

C103

C96

C96

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

+1.5VSUS

<20091028(A1A)_47337_ASB2_scl_nda_1.00>
Add two 0.1uF for +1.5VSUS

C327

C327

C328

C328

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C129

C129
10U/6.3V_8

10U/6.3V_8

C318

C318

0.01U/25V_4

0.01U/25V_4

C79

C79

10U/6.3V_8

10U/6.3V_8

C77

C77

180P/50V_4

180P/50V_4

C325

C325

C322

0.22U/6.3V_4

0.22U/6.3V_4

C322

0.22U/6.3V_4

0.22U/6.3V_4

0.22U/6.3V_4

0.22U/6.3V_4

<20091202(A1A)_Follow Bimini Rev1.2>
Add two 10uF for +1.5VSUS

C112

C112

C89

C89

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

CPU_VDDR

C114

C114

C75

C75

0.22U/6.3V_4

0.22U/6.3V_4

0.22U/6.3V_4

0.22U/6.3V_4

C108

C108

C76

C76

0.22U/6.3V_4

0.22U/6.3V_4

C71

C71

4.7U/6.3V_6

4.7U/6.3V_6

+1.1V

R351 *0/short_8R351 *0/short_8

Group1 Group2

1A

C73

C73

C72

C72

0.22U/6.3V_4

0.22U/6.3V_4

0.22U/6.3V_4

0.22U/6.3V_4

1.5A

+1.1V_CPU_VLDT

C319

C319

4.7U/6.3V_6

4.7U/6.3V_6

C317

C317
22U/6.3V_8

22U/6.3V_8

For VLDT_A

C321

C321

0.22U/6.3V_4

0.22U/6.3V_4

4.7U/6.3V_6

4.7U/6.3V_6

C360

C360

C350

C350

0.22U/6.3V_4

0.22U/6.3V_4

C320

C320

180P/50V_4

180P/50V_4

C343

C343

0.22U/6.3V_4

0.22U/6.3V_4

4.7U/6.3V_6

4.7U/6.3V_6

For VLDT_B

C368

C368

C356

C356

0.22U/6.3V_4

0.22U/6.3V_4

C352

C352

180P/50V_4

180P/50V_4

DECOUPLING BETWEEN PROCESSOR AND DIMMs

A A

PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.5VSUS

4.7U/6.3V_6

4.7U/6.3V_6

C88

C97

4.7U/6.3V_6

4.7U/6.3V_6

5

C97

C92

C92

C88

4.7U/6.3V_6

4.7U/6.3V_6

4.7U/6.3V_6

4.7U/6.3V_6

<20091028(A1A)_47337_ASB2_scl_nda_1.00>
If VSS plane is cut for VDDIO, place two

0.22uF & 180pF across the VDDIO-VSS

C326

C78

C78

C326

0.22U/6.3V_4

0.22U/6.3V_4

C329

C329

0.22U/6.3V_4

0.22U/6.3V_4

4

180P/50V_4

180P/50V_4

C323

C323

C324

C324

180P/50V_4

180P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

ASB2 PWR & GND 4/4

ASB2 PWR & GND 4/4

ASB2 PWR & GND 4/4

ZH9

4A

4A

5 40Sunday, March 28, 2010

5 40Sunday, March 28, 2010

5 40Sunday, March 28, 2010

1

4A

5

HT_CADOUTP0
HT_CADOUTN0
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP3
HT_CADOUTN3
HT_CADOUTP4
HT_CADOUTN4
HT_CADOUTP5
HT_CADOUTN5
HT_CADOUTP6
HT_CADOUTN6
HT_CADOUTP7

R320 301/F_4R320 301/F_4

25mils

0.5A

C436

C436

SPM@10U/6.3V_8

SPM@10U/6.3V_8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

HT_CADOUTN7
HT_CADOUTP8

HT_CADOUTN8
HT_CADOUTP9
HT_CADOUTN9
HT_CADOUTP10
HT_CADOUTN10
HT_CADOUTP11
HT_CADOUTN11
HT_CADOUTP12
HT_CADOUTN12
HT_CADOUTP13
HT_CADOUTN13
HT_CADOUTP14
HT_CADOUTN14
HT_CADOUTP15
HT_CADOUTN15

HT_CLKOUTP0
HT_CLKOUTN0
HT_CLKOUTP1
HT_CLKOUTN1

HT_CTLOUTP0
HT_CTLOUTN0
HT_CTLOUTP1
HT_CTLOUTN1

+1.5V_SPM_VDDQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

D D

C C

C442

C442

SPM@0.1U/10V_4

SPM@0.1U/10V_4

B B

+1.5V_SPM_VDDQ

A A

SPM_VREFCA
SPM_VREFDQ

SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13

SPM_BA0
SPM_BA1
SPM_BA2

SPM_CLKP
SPM_CLKN
SPM_CKE

SPM_ODT
SPM_CS#
SPM_RAS#
SPM_CAS#
SPM_WE#

SPM_DQS0P
SPM_DQS1P

SPM_DM0
SPM_DM1

SPM_DQS0N
SPM_DQS1N

SP_DDR3_RST#<11>

C424

C424

SPM@0.1U/10V_4

SPM@0.1U/10V_4

R376 SPM@10K/J_4R376 SPM@10K/J_4

5

C425

C425
SPM@1U/10V_4

SPM@1U/10V_4

C441

C441
SPM@1U/10V_4

SPM@1U/10V_4

U7

U7

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

R373

R373
SPM@243/F_4

SPM@243/F_4

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

SDRAM DDR3

SDRAM DDR3

BOM@DDR3 SDRAM

BOM@DDR3 SDRAM

<20091202(A1A)_Confirm with Acer Jimmy>
side port memory use DD3

4

U20A

U20A

Y25

HT_RXCAD0P

Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22

M23

R21

R20

HT_RXCALP HT_TXCALP

C23

HT_RXCALN

A24

R378 *0/short_6R378 *0/short_6

C439

C439

SPM@10U/6.3V_8

SPM@10U/6.3V_8

SPM_DQ2
SPM_DQ1
SPM_DQ3
SPM_DQ0
SPM_DQ7
SPM_DQ4
SPM_DQ5
SPM_DQ6

SPM_DQ11
SPM_DQ8
SPM_DQ12
SPM_DQ14
SPM_DQ9
SPM_DQ10
SPM_DQ15
SPM_DQ13

+1.5V_SPM_VDDQ

<BOM Note>
w/ sideport: U7:
AKD5LGGT506 : SAMSUNG DDRIII 800 1Gb K4W1G1646E-HC12 LF
AKD5LZGTW04 : HYNIX DDRIII 800 1Gb H5TQ1G63BFR-12C LF
AKD5LGGT700 : ATI DDRIII 800 1Gb 23EY2387MA12-SZ LF+HF
w/o sideport: U7 Non-stuff

4

HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS880M

RS880M

+1.5V

+1.5V_SPM_VDDQ

PART 1 OF 6

PART 1 OF 6

+1.5V_SPM_VDDQ

HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

T52T52

R358 SPM@40.2/F_4R358 SPM@40.2/F_4
R359 SPM@40.2/F_4R359 SPM@40.2/F_4

C443

C443

SPM@0.1U/10V_4

SPM@0.1U/10V_4

C440

C440

SPM@0.1U/10V_4

SPM@0.1U/10V_4

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP
HT_TXCALN

SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13

SPM_BA0
SPM_BA1
SPM_BA2

SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_CS#
SPM_CKE
SPM_ODT

SPM_CLKP
SPM_CLKN

R379

R379
SPM@1K/F_4

SPM@1K/F_4

SPM_VREFDQ SPM_VREFSPM_VREFCA

R377

R377
SPM@1K/F_4

SPM@1K/F_4

3

HT_CADINP0

D24

HT_CADINN0

D25

HT_CADINP1

E24

HT_CADINN1

E25

HT_CADINP2

F24

HT_CADINN2

F25

HT_CADINP3

F23

HT_CADINN3

F22

HT_CADINP4

H23

HT_CADINN4

H22

HT_CADINP5

J25

HT_CADINN5

J24

HT_CADINP6

K24

HT_CADINN6

K25

HT_CADINP7

K23

HT_CADINN7

K22

HT_CADINP8

F21

HT_CADINN8

G21

HT_CADINP9

G20

HT_CADINN9

H21

HT_CADINP10

J20

HT_CADINN10

J21

HT_CADINP11

J18

HT_CADINN11

K17

HT_CADINP12

L19

HT_CADINN12

J19

HT_CADINP13

M19

HT_CADINN13

L18

HT_CADINP14

M21

HT_CADINN14

P21

HT_CADINP15

P18

HT_CADINN15

M18

HT_CLKINP0

H24

HT_CLKINN0

H25

HT_CLKINP1

L21

HT_CLKINN1

L20

HT_CTLINP0

M24

HT_CTLINN0

M25

HT_CTLINP1

P19

HT_CTLINN1

R18
B24

HT_TXCALN

B25

R161 *SPM@100/F_4R161 *SPM@100/F_4

SPM_COMPP
SPM_COMPN

3

R115 301/F_4R115 301/F_4

AB12
AE16

V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

Y14
AD16

AE17
AD17

W12

Y12
AD18
AB13
AB18

V14

V15

W14

AE12
AD12

+1.5V_SPM_VDDQ +1.5V_SPM_VDDQ

U20D

U20D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

RS880M

RS880M

C418

C418

SPM@0.1U/10V_4

SPM@0.1U/10V_4

C417

C417

SPM@0.1U/10V_4

SPM@0.1U/10V_4

HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]
HT_CTLOUTN[1..0]
HT_CADINP[15..0]
HT_CADINN[15..0]
HT_CLKINP[1..0]
HT_CLKINN[1..0]
HT_CTLINP[1..0]
HT_CTLINN[1..0]

PAR 4 OF 6

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)

MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)

MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

MEM_VREF(NC)

R366

R366
SPM@1K/F_4

SPM@1K/F_4

R365

R365
SPM@1K/F_4

SPM@1K/F_4

MEM_DQ4(NC)

MEM_DM0(NC)

IOPLLVDD(NC)
IOPLLVSS(NC)

2

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

C414

C414

SPM@0.1U/10V_4

SPM@0.1U/10V_4

C413

C413

SPM@0.1U/10V_4

SPM@0.1U/10V_4

2

HT_CADOUTP[15..0] <2>

HT_CADOUTN[15..0] <2>

HT_CLKOUTP[1..0] <2>

HT_CLKOUTN[1..0] <2>

HT_CTLOUTP[1..0] <2>

HT_CTLOUTN[1..0] <2>

HT_CADINP[15..0] <2>

HT_CADINN[15..0] <2>

HT_CLKINP[1..0] <2>

HT_CLKINN[1..0] <2>

HT_CTLINP[1..0] <2>

HT_CTLINN[1..0] <2>

SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15

SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N

SPM_DM0
SPM_DM1

+1.8V_NB_IOPLLVDD18
+1.1V_NB_IOPLLVDD

SPM_VREF

SPM@2.2U/6.3V_6

SPM@2.2U/6.3V_6

<BOM NOTE>
w/ sideport: L45,L46:CX8PG221003
w/o sideport: L45,L46:CS00003J951(0ohm)

R357

R357
SPM@1K/F_4

SPM@1K/F_4

R356

R356
SPM@1K/F_4

SPM@1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

L46 BOM@1.4A/220ohm_6L46 BOM@1.4A/220ohm_6
L45 BOM@1.4A/220ohm_6L45 BOM@1.4A/220ohm_6

C410

C410

SPM@2.2U/6.3V_6

SPM@2.2U/6.3V_6

C409

C409

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

RS880-HT LINK/SPMEM I/F 1/4

RS880-HT LINK/SPMEM I/F 1/4

RS880-HT LINK/SPMEM I/F 1/4

1

15mA

+1.8V

26mA

+1.1V

ZH9

ZH9

ZH9

4A

4A

6 40Sunday, March 28, 2010

6 40Sunday, March 28, 2010

6 40Sunday, March 28, 2010

1

4A

5

U20B

U20B

D4

AE3

AD4

AE2
AD3
AD1
AD2

W6

AA8

AA7

AA5

AA6

W5

G5
G6

M8

M7
M5

C4
A3
B3
C2
C1
E5
F5

H5
H6

J6
J5
J7

J8
L5
L6

L8
P7

P5
R8

P8
R6
R5
P4
P3
T4
T3

V5
U5

U6
U8
U7

Y8
Y7

Y5

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

RS880M

RS880M

D D

C C

PCIE_RXP0<21>
PCIE_RXN0<21>
PCIE_RXP1<23> PCIE_TXP1 <23>
PCIE_RXN1<23>
PCIE_RXP2<23>
PCIE_RXN2<23>

B B

A_RXP0<10>
A_RXN0<10>
A_RXP1<10>
A_RXN1<10>
A_RXP2<10>
A_RXN2<10>
A_RXP3<10>
A_RXN3<10>

PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1 PCIE_TXN1_C
PCIE_RXP2
PCIE_RXN2

4

PART 2 OF 6

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

AC8
AB8

TX2_HDMI+_C
TX2_HDMI-_C
TX1_HDMI+_C
TX1_HDMI-_C
TX0_HDMI+_C
TX0_HDMI-_C
TXC_HDMI+_C
TXC_HDMI-_C

PCIE_TXP0_C
PCIE_TXN0_C
PCIE_TXP1_C

PCIE_TXP2_C
PCIE_TXN2_C

A_TXP0_C
A_TXN0_C
A_TXP1_C
A_TXN1_C
A_TXP2_C
A_TXN2_C
A_TXP3_C
A_TXN3_C

NB_PCIECALRP
NB_PCIECALRN

3

C393 HDM@0.1U/10V_4C393 HDM@0.1U/10V_4
C392 HDM@0.1U/10V_4C392 HDM@0.1U/10V_4
C396 HDM@0.1U/10V_4C396 HDM@0.1U/10V_4
C395 HDM@0.1U/10V_4C395 HDM@0.1U/10V_4
C398 HDM@0.1U/10V_4C398 HDM@0.1U/10V_4
C397 HDM@0.1U/10V_4C397 HDM@0.1U/10V_4
C406 HDM@0.1U/10V_4C406 HDM@0.1U/10V_4
C403 HDM@0.1U/10V_4C403 HDM@0.1U/10V_4

C427 0.1U/10V_4C427 0.1U/10V_4
C423 0.1U/10V_4C423 0.1U/10V_4
C218 0.1U/10V_4C218 0.1U/10V_4
C216 0.1U/10V_4C216 0.1U/10V_4
C419 3G@0.1U/10V_4C419 3G@0.1U/10V_4
C421 3G@0.1U/10V_4C421 3G@0.1U/10V_4

C420 0.1U/10V_4C420 0.1U/10V_4
C422 0.1U/10V_4C422 0.1U/10V_4
C430 0.1U/10V_4C430 0.1U/10V_4
C426 0.1U/10V_4C426 0.1U/10V_4
C435 0.1U/10V_4C435 0.1U/10V_4
C432 0.1U/10V_4C432 0.1U/10V_4
C433 0.1U/10V_4C433 0.1U/10V_4
C437 0.1U/10V_4C437 0.1U/10V_4

R168 1.27K/F_4R168 1.27K/F_4
R162 2K/F_4R162 2K/F_4

PCIE_TXP0 <21>
PCIE_TXN0 <21>

PCIE_TXN1 <23>
PCIE_TXP2 <23>
PCIE_TXN2 <23>

A_TXP0 <10>
A_TXN0 <10>
A_TXP1 <10>
A_TXN1 <10>
A_TXP2 <10>
A_TXN2 <10>
A_TXP3 <10>
A_TXN3 <10>

+1.1V

2

TX2_HDMI+ <17>
TX2_HDMI- <17>
TX1_HDMI+ <17>
TX1_HDMI- <17>
TX0_HDMI+ <17>
TX0_HDMI- <17>
TXC_HDMI+ <17>
TXC_HDMI- <17>

TO LAN
TO MINI PCIE 1
TO MINI PCIE 2

1

TO HDMI

RS880 Display Port Support (muxed on GFX)

DP0

A A

DP1

5

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

Date: Sheet of

2

PROJECT :

RS880-PCIE I/F 2/4

RS880-PCIE I/F 2/4

RS880-PCIE I/F 2/4

ZH9

1

4A

4A

4A

7 40Sunday, March 28, 2010

7 40Sunday, March 28, 2010

7 40Sunday, March 28, 2010

5

Note:Regarding LDT_STOP# signal,It's required within
40ns skew for both assertion and de-assertion between
NB and CPU.

D D

CPU_LDT_STOP#<4,10>

ALLOW_LDTSTOP<10>

C C

B B

STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 = Disable
0 = Enable

R353

R353
*300/J_4

*300/J_4

R352 *0/J_4R352 *0/J_4

Graphics PLL power
Graphics PLL power

HT LINK PLL power
PCIe PLL power

+

U18

U18

Open

Open

2

Drain

Drain

-

74LVC07+-

74LVC07

3 5

R131 *0/short_4R131 *0/short_4

CRT_VSYNC

+1.8V+1.8V

<20100303(C3A)>
Change R354 from CS22202JB18(2.2K) to
CS13002JB20(300ohm ) depend on the
measurement result, for LDTSTP# skew
issue.

C408

C408

0.1U/10V_4

0.1U/10V_4

4

Confirmed with AMD FAE Reden
Follow Bimini Rev1.2 for PLLVDD18 to prevent noise coupling
Change L8203 from bead to 3.9ohm

CRB:0.23A@all +1.1V PLLs

+1.8V

R354

R354

300/J_4

300/J_4

NB_LDT_STOP#

R122 1K/J_4R122 1K/J_4

NB_ALLOW_LDTSTOP

+1.1V

C146

C146
22U/6.3V_8

22U/6.3V_8

L40 1.4A/220ohm_6L40 1.4A/220ohm_6
R121 1.4A/220ohm_6R121 1.4A/220ohm_6

L10 1.4A/220ohm_6L10 1.4A/220ohm_6
L15 1.4A/220ohm_6L15 1.4A/220ohm_6

CRB:0.1A@all +1.8V PLLs

<20091009(A1A)_46105_rs880_scl_nda_1.04>
Pulled 4.7K 5% low to GND when internal CLK Gen. used
(For GFX Clock Pair)

R143 3K/J_4R143 3K/J_4

R147 *3K/J_4R147 *3K/J_4

4

DAC Analog power

<20100310(C3A)>
Change R336 from 0ohm(CS00002JB38) to bead(CX8PG221003) and C162 from

0.1uF(CH4102K1B03) to 2.2uF(CH52201K991), for monitor noise issue.

DAC Digital power

<20100319(RAMP)>
Add C415,C470,C499(1uF), for monitor noise issue.

DAC Bandgap Reference power

<20090810(A1A)_46659_RS880_Errata_nda_1.10>
The R channel's term. R change 140ohm (For the
voltage level mismatch, the Red is higher)

+1.8V

<20100323(RAMP)_Follow 46105_rs880_scl_nda_1.05>
Change R121 from 3.9ohm(CS-3902JB00) to bead(CX8PG221003)
and C159 from 4.7uF(CH5471M9907) to 2.2uF(CH52201K991)

C388 2.2U/6.3V_6C388 2.2U/6.3V_6

C159 2.2U/6.3V_6C159 2.2U/6.3V_6

NB_RST#_IN<10>

NB_PWRGD<11>

CLK_NB_HTREFP<10>
CLK_NB_HTREFN<10>

NB_REFCLK_P<10>
NB_REFCLK_N<10>

CLK_SBLINKP<10>
CLK_SBLINKN<10>

LCD_DATA<16>
LCD_CLK<16>

HDMI_DDC_DATA<17>

HDMI_DDC_CLK<17>

+NB_CORE_ON<29>

+3V

NB Core
STRP_DATA

1 = 0.95V
0 = 1.1 V

+3V

+1.8V

+1.8V

CRT_R<16>
CRT_G<16>

CRT_B<16>

C155 2.2U/6.3V_6C155 2.2U/6.3V_6

C174 2.2U/6.3V_6C174 2.2U/6.3V_6

3

L14 1.4A/220ohm_6L14 1.4A/220ohm_6

SCL:20mA

R336 1.4A/220ohm_6R336 1.4A/220ohm_6

L41 1.4A/220ohm_6L41 1.4A/220ohm_6

SCL:65mA

R363 ICK@4.7K/J_4R363 ICK@4.7K/J_4

R364 ICK@4.7K/J_4R364 ICK@4.7K/J_4

R144

R144
2K/J_4

2K/J_4

SCL:4mA

R134 140/F_4R134 140/F_4
R129 150/F_4R129 150/F_4
R120 150/F_4R120 150/F_4

SCL:20mA
SCL:120mA

R346 *0/short_4R346 *0/short_4

R139 *0/short_4R139 *0/short_4

+1.1V_NB_PLLVDD
+1.8V_NB_PLLVDD18

+1.8V_NB_VDDA18HTPLL
+1.8V_NB_VDDA18PCIEPLL

+3V_NB_AVDD

C163

C163

2.2U/6.3V_6

2.2U/6.3V_6

+1.8V_NB_AVDDDI

C162

C162

2.2U/6.3V_6

2.2U/6.3V_6

15mils

+1.8V_NB_AVDDQ

C160

C160

2.2U/6.3V_6

2.2U/6.3V_6

CRT_HSYNC<16>
CRT_VSYNC<16>

CRT_SDA<16>

CRT_SCL<16>

R325 715/F_6R325 715/F_6

SCL:20mA

NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP

CLK_NB_HTREFP
CLK_NB_HTREFN

CLK_NBGFXP
CLK_NBGFXN

CLK_SBLINKP
CLK_SBLINKN

LCD_DATA
LCD_CLK

T27T27
T18T18

STRP_DATA

R347 *150/F_4R347 *150/F_4

C415

C415

1U/6.3V_4

1U/6.3V_4

15mils

C470

C470

1U/6.3V_4

1U/6.3V_4

C499

C499

1U/6.3V_4

1U/6.3V_4

15mils

15mils

15mils

DAC_RSET

15mils

15mils

AUX_CAL

SCL:110mA
CRB:125mA

U20C

U20C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PW M_GPIO4)

B11

DAC_VSYNC(PW M_GPIO6)

E8

DAC_SDA(PCE_TCALRN)

F8

DAC_SCL(PCE_RCALRN)

G14

DAC_RSET(PW M_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PW M_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

A9

I2C_DATA

B9

I2C_CLK

B8

DDC_DATA/AUX0N(NC)

A8

DDC_CLK/AUX0P(NC)

B7

AUX1P(NC)

A7

AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS880M

RS880M

2

HPD(NC)

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12
AE8

AD8
D13

R150

R150

SUS_STAT#_NB

TEST_EN

PART 3 OF 6

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

I

PM

I

I/O

CLOCKs PLL PWR

I/O

CLOCKs PLL PWR

MIS.

MIS.

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PW M_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PW M_GPIO5)

THERMALDIODE_P
THERMALDIODE_N

TXLOUT0+ <16>
TXLOUT0- <16>
TXLOUT1+ <16>
TXLOUT1- <16>
TXLOUT2+ <16>
TXLOUT2- <16>

TXLCLKOUT+ <16>

TXLCLKOUT- <16>

C386 2.2U/6.3V_6C386 2.2U/6.3V_6

+1.8V_NB_VDDLTP18

15mils

+1.8V_NB_VDDLT18

15mils

C377

C377

0.1U/10V_4

0.1U/10V_4

Confirmed with AMD Horace
LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be
pulled down with 4.7K

4.7K/J_4

4.7K/J_4

T26T26

R334

R334

1.8K/J_4

1.8K/J_4

1

LVDS or DVI/ HDMI PLL power

L39 1.4A/220ohm_6L39 1.4A/220ohm_6

L38 1.4A/220ohm_6L38 1.4A/220ohm_6

C369

C369

4.7U/6.3V_6

4.7U/6.3V_6

SCL:15mA

SCL:0.3A
CRB:0.22A

LVDS or DVI/ HDMI Digital power

Support Vari-Bright

INT_LVDS_DIGON <16>
INT_LVDS_PWM <16>
INT_LVDS_BLON <16>

R156 SPM@0/J_4R156 SPM@0/J_4

LVDS POWER
LVDS BL_PWM
LVDS BL_EN

INT_HDMI_HPD <17>

SUS_STAT# <11>

+1.8V

RS880M: Enables Side port memory

A A

Selects if Memory SIDE PORT is available or not
1 = Memory Side port Not available
0 = Memory Side port available

<BOM NOTE>
w/ sideport: R142 non-stuff
w/o sideport: R142 stuff

5

CRT_HSYNC

R142 BOM@3K/J_4R142 BOM@3K/J_4

R137 SPM@3K/J_4R137 SPM@3K/J_4

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use

+3V

default values if not connected

EEPROM not implemented

4

+3V

R153 4.7K/J_4R153 4.7K/J_4

3

SUS_STAT#_NB

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

RS880-SYSTEM I/F 3/4

RS880-SYSTEM I/F 3/4

RS880-SYSTEM I/F 3/4

ZH9

4A

4A

8 40Sunday, March 28, 2010

8 40Sunday, March 28, 2010

1

8 40Sunday, March 28, 2010

4A

5

4

3

2

1

D11

E14

E15

J12

K14

M11

H7

VSSAPCIE10J4VSSAPCIE11R7VSSAPCIE12L1VSSAPCIE13L2VSSAPCIE14L4VSSAPCIE15

VSSAHT9

VSSAHT10

VSSAHT11

L17

L22

L24

L7

VSSAPCIE16M6VSSAPCIE17N4VSSAPCIE18P6VSSAPCIE19R1VSSAPCIE20R2VSSAPCIE21R4VSSAPCIE22V7VSSAPCIE23U4VSSAPCIE24V8VSSAPCIE25V6VSSAPCIE26W1VSSAPCIE27W2VSSAPCIE28W4VSSAPCIE29W7VSSAPCIE30W8VSSAPCIE31Y6VSSAPCIE32

VSSAHT12

VSSAHT13

VSSAHT14

VSSAHT15

VSSAHT16

VSSAHT17

VSSAHT18

VSSAHT19

VSSAHT21

VSSAHT20

L25

M20

+1.1V

P20

N22

SCL:0.4A
CRB:0.68A

V19

R19

R22

R24

R25

U22

H20

R145 *0/short_6R145 *0/short_6

R113 *0/short_6R113 *0/short_6

C192

C192

4.7U/6.3V_6

4.7U/6.3V_6

SCL:0.7A
CRB:0.64A

C213

C213

4.7U/6.3V_6

4.7U/6.3V_6

+1.8V
+1.8V

VSSAHT22

VSSAHT23

VSSAHT24

VSSAHT25

W22

W24

W25

CRB:0.68A

C211

C211

4.7U/6.3V_6

4.7U/6.3V_6

U20F

U20F

D D

C C

VSSAPCIE1A2VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9

PART 6/6

PART 6/6

VSSAHT1

VSSAHT2

VSSAHT3

VSSAHT4

VSSAHT5

VSSAHT6

VSSAHT7

A25

E22

D23

H19

G22

G24

G25

VSSAHT8

J22

HT LINK RX I/O power

HT LINK TX I/O power

R152 *0/short_6R152 *0/short_6

+1.1V

B B

PCIe TX Stage I/O power

+1.8V

L17 1.4A/220ohm_6L17 1.4A/220ohm_6

I/O Transform power

Memory I/O Transform

CRB:25mA

A A

AA4

AB5

AB1

VSSAPCIE33

GROUND

GROUND

VSSAHT26

VSSAHT27

VSS11

VSS12

VSS13

VSS14

VSS15

L12

Y21

P12

P15

N13

R11

M14

AD25

SCL:0.6A

C172

C172

4.7U/6.3V_6

4.7U/6.3V_6

SCL:0.7A

C152

C152

4.7U/6.3V_6

4.7U/6.3V_6

C190

C190

0.1U/10V_4

0.1U/10V_4

R157 *0/short_6R157 *0/short_6
R367 SPM@0/J_6R367 SPM@0/J_6

C197

C197

0.1U/10V_4

0.1U/10V_4

C191

C191

0.1U/10V_4

0.1U/10V_4

AB7

AC3

AC4

AE1

VSSAPCIE34

VSSAPCIE35

VSSAPCIE36

VSSAPCIE37

VSS16

VSS17

VSS18

VSS19

T12

R14

U14

U11

C168

C168

0.1U/10V_4

0.1U/10V_4

C150

C150

0.1U/10V_4

0.1U/10V_4

C207

C207

0.1U/10V_4

0.1U/10V_4

SCL:10mA
CRB:5mA

AE4

VSSAPCIE38

VSS20

U15

AB2

VSSAPCIE39

VSSAPCIE40

VSS21

VSS22

V12

W11

C193

C193
1U/10V_4

1U/10V_4

AE14

VSS2

VSS3G8VSS4

VSS1

VSS23

VSS24

VSS25

VSS26

VSS27

Y18

W15

AA14

AC12

+1.1V_NB_VDDHT

C164

C164

0.1U/10V_4

0.1U/10V_4

+1.1V_NB_VDDHTRX

C147

C147

0.1U/10V_4

0.1U/10V_4

+1.1V_NB_VDDHTTX

C188

C188

0.1U/10V_4

0.1U/10V_4

+1.8V_NB_VDDA18PCIE

C187

C187

0.1U/10V_4

0.1U/10V_4

+1.8V_NB_VDD18
+1.8V_NB_VDD18_MEM

L15

J15

VSS5

VSS7

VSS8

VSS9

VSS6

VSS10

VSS28

VSS29

VSS30

VSS31

VSS32

VSS34

VSS33

K11

AB11

AB15

AB17

AB19

AE20

AB21

35mils

C169

C169

0.1U/10V_4

0.1U/10V_4

40mils

C156

C156

0.1U/10V_4

0.1U/10V_4

20mils

C177

C177

0.1U/10V_4

0.1U/10V_4

25mils

C203

C203

0.1U/10V_4

0.1U/10V_4

15mils

C416

C416
BOM@1U/10V_4

BOM@1U/10V_4

U20E

U20E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7

AE25

VDDHTTX_1

AD24

VDDHTTX_2

AC23

VDDHTTX_3

AB22

VDDHTTX_4

AA21

VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDDG18_1(VDD18_1)

G9

VDDG18_2(VDD18_2)

AE11

VDD18_MEM1(NC)

AD11

VDD18_MEM2(NC)

RS880M

RS880M

PART 5/6

PART 5/6

POWER

POWER

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDDG33_1(NC)
VDDG33_2(NC)

Without side-port: Connected to GND plane.

PIN NAME
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE
VDD18
VDD18_MEM
VDDPCIE
VDDC
VDD_MEM
VDD33
IOPLLVDD18

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

RX881/RS880 POWER DIFFERENCE TABLE

RX881

+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
GND
+1.1V +1.1V +1.8V
+1.1V

+0.95V~+1.1V

GND

+1.8V/1.5V

+3.3V

+1.1V_NB_VDDPCIE

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

C206

C206

0.1U/10V_4

0.1U/10V_4

C196

C196

0.1U/10V_4

0.1U/10V_4

C173

C173

0.1U/10V_4

0.1U/10V_4

+1.5V_NB_VDD_MEM

15mils

+3V_NB_VDD33

C167

C167

0.1U/10V_4

0.1U/10V_4

RS880

+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V

+3.3V
+1.8V+1.8V

130mils

C198

C198

0.1U/10V_4

0.1U/10V_4

550mils

C166

C166

0.1U/10V_4

0.1U/10V_4

C194

C194

0.1U/10V_4

0.1U/10V_4

PIN NAME
IOPLLVDD

AVDDDI
AVDDQ
PLLVDD
PLLVDD18
VDDA18PCIEPLL
VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33

C214

C214
BOM@0.1U/10V_4

BOM@0.1U/10V_4

C199

C199
1U/10V_4

1U/10V_4

C170

C170

0.1U/10V_4

0.1U/10V_4

C200

C200

0.1U/10V_4

0.1U/10V_4

R159 *0/short_6R159 *0/short_6

RX881 RS880

+1.1V

+1.1V

GND

+3.3VAVDD

GND +1.8V
GND +1.8V

+1.1V

GND
GND

+1.8V

+1.8V

+1.8V

+1.8V

+1.8V

GND

+1.8V

GND
NC

NC

SCL:2.5A
CRB:1.1A

C210

C210

C212

C212
1U/10V_4

1U/10V_4

4.7U/6.3V_6

4.7U/6.3V_6

C195

C195

0.1U/10V_4

0.1U/10V_4

C175

C175

0.1U/10V_4

0.1U/10V_4

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

10U/6.3V_8

SCL:100mA

C219

C219
SPM@0.1U/10V_4

SPM@0.1U/10V_4

+3V

SCL:60mA
CRB:60mA

R163 *0/short_8R163 *0/short_8

R160 *0/short_6R160 *0/short_6

SCL:10A
CRB:7.6A

C208

C208

C209

C209

C217

C217
SPM@0.1U/10V_4

SPM@0.1U/10V_4

+0.95V or +1.1V

+3.3V I/O power

PCIe Main I/O powerHT LINK Digital I/O power

+1.1V

+NB_CORE

C215

C215
SPM@0.1U/10V_4

SPM@0.1U/10V_4

Core Logic power

R179 SPM@0/J_6R179 SPM@0/J_6

C226

C226
SPM@4.7U/6.3V_6

SPM@4.7U/6.3V_6

For Side Port
+1.5V for DDR3
+1.8V for DDR2
If not support side port,
connect to GND.

Memory I/O

+1.5V

<BOM NOTE>
w/ sideport: C214:CH4102K1B03 ; C416:CH5102K9B06
w/o sideport: C214,C416:CS00002JB38(0ohm)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

PROJECT :

RS880-POWER 4/4

RS880-POWER 4/4

RS880-POWER 4/4

ZH9

9 40Sunday, March 28, 2010

9 40Sunday, March 28, 2010

9 40Sunday, March 28, 2010

1

4A

4A

4A

5

PCIE_RST#: Reset PCIe Slot/Device (PCIe interface from SB)
A_RST#: Reset NB, MXM, EC, PCIe Slot/Device (PCIe interface from NB)

NB

NB_RST#_IN<8>

EC

PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO SB820

D D

A_RST#_SB

R73 *0/short_4R73 *0/short_4
R65 *0/short_4R65 *0/short_4

+1.1V_SB_VDDAN_11_PCIE

C C

B B

A A

<20100325(RAMP)>
Change RP1~RP4,RP6~RP8 to shortpad.

to NB for A-LINK/PCIe REF CLK

to NB Display Eng

to MINI PCIE 2

to LAN

to MINI PCIE 1

to LAN chip 25MHz

<20100129(B2A)>
Stuff R345. (CLK for LAN from crystal
change to internal CLK.)

<20100310(C3A)>
Non-Stuff R345. (14M_25M_48M_OSC is S0 plane,
doesn't support WoL.)

CLK_SBLINKP<8>
CLK_SBLINKN<8>

NB_REFCLK_P<8>
NB_REFCLK_N<8>

CLK_NB_HTREFP<8>
CLK_NB_HTREFN<8>

CLK_CPU_BCLKP<4>
CLK_CPU_BCLKN<4>

CLK_PCIE_MNC_P<23>
CLK_PCIE_MNC_N<23>

CLK_PCIE_LANP<21>
CLK_PCIE_LANN<21>

CLK_PCIE_MPC_P<23>

CLK_PCIE_MPC_N<23>

CLK_25M_LAN<21>

5

<20100303(C3A)>
Change C411,C412 from CH02206JB08(22pF) to CH02706JB06(27pF), for Y4.

C102 150P/50V_4C102 150P/50V_4

A_RXP0<7>
A_RXN0<7>
A_RXP1<7>
A_RXN1<7>
A_RXP2<7>
A_RXN2<7>
A_RXP3<7>
A_RXN3<7>

A_TXP0<7>
A_TXN0<7>
A_TXP1<7>
A_TXN1<7>
A_TXP2<7>
A_TXN2<7>
A_TXP3<7>
A_TXN3<7>

<Layout note>
Share pad with other resisters
and close to external CLK Gen.

RP7 *ICK@0/short__4P2RRP7 *ICK@0/short__4P2R

4
2

RP2 *ICK@0/short__4P2RRP2 *ICK@0/short__4P2R

4
2

RP1 *ICK@0/short__4P2RRP1 *ICK@0/short__4P2R

4
2

RP8 *ICK@0/short__4P2RRP8 *ICK@0/short__4P2R

4
2

RP4 *3G@ICK@0/short__4P2RRP4 *3G@ICK@0/short__4P2R

4
2

RP6 *ICK@0/short__4P2RRP6 *ICK@0/short__4P2R

2
4

RP3 *ICK@0/short__4P2RRP3 *ICK@0/short__4P2R

4
2

R345 *ICK@22/J_4R345 *ICK@22/J_4

C411 27P/50V_4C411 27P/50V_4

Y4

Y4

25MHz-SB820M

25MHz-SB820M

C412 27P/50V_4C412 27P/50V_4

R350 590/F_4R350 590/F_4
R349 2K/F_4R349 2K/F_4

3
1

3
1

3
1

3
1

3
1

1
3

3
1

2 1

R89 33/J_4R89 33/J_4

C179 0.1U/10V_4C179 0.1U/10V_4
C180 0.1U/10V_4C180 0.1U/10V_4
C182 0.1U/10V_4C182 0.1U/10V_4
C181 0.1U/10V_4C181 0.1U/10V_4
C183 0.1U/10V_4C183 0.1U/10V_4
C184 0.1U/10V_4C184 0.1U/10V_4
C186 0.1U/10V_4C186 0.1U/10V_4
C185 0.1U/10V_4C185 0.1U/10V_4

R355

R355
1M/J_4

1M/J_4

A_RST#_SB_CA_RST#
A_RXP0_C

A_RXN0_C
A_RXP1_C
A_RXN1_C
A_RXP2_C
A_RXN2_C
A_RXP3_C
A_RXN3_C

A_TXP0
A_TXN0
A_TXP1
A_TXN1
A_TXP2
A_TXN2
A_TXP3
A_TXN3

PCIE_CALRP_SB
PCIE_CALRN_SB

CLK_SBSRCP
CLK_SBSRCN

SB_NB_REFCLKP
SB_NB_REFCLKN

SB_NB_HTCLKP
SB_NB_HTCLKN

SB_CPU_CLKP
SB_CPU_CLKN

SB_MNC_CLKP
SB_MNC_CLKN

SB_LAN_CLKP
SB_LAN_CLKN

SB_MPC_CLKP
SB_MPC_CLKN

SB_CLK_25M_LAN

25M_X1

25M_X2

4

U5A

U5A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

SB820M

SB820M

IC CTRL(605P)SB820M 218-0697014(FCBGA)
P/N : AJ069700T01

4

Part 1 of 5

Part 1 of 5

SB800

SB800

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI CLKS

PCI EXPRESS INTERFACES

PCI EXPRESS INTERFACES

REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

CLOCK GENERATOR

CLOCK GENERATOR

ALLOW_LDTSTP/DMA_ACTIVE#

CPU

CPU

RTC

RTC

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38

PCIRST#

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8

AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31

FRAME#

DEVSEL#

PCI INTERFACELPC

PCI INTERFACELPC

REQ1#/GPIO40

GNT1#/GPO44
GNT2#/GPO45

CLKRUN#

INTE#/GPIO32

INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

LPCCLK0
LPCCLK1

LFRAME#

LDRQ0#

SERIRQ/GPIO48

PROCHOT#

LDT_PG
LDT_STP#
LDT_RST#

32K_X1
32K_X2

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

CBE0#
CBE1#
CBE2#
CBE3#

IRDY#

TRDY#
STOP#

PERR#
SERR#
REQ0#

GNT0#

LOCK#

LAD0
LAD1
LAD2
LAD3

PAR

W2
W1
W3
W4
Y1

V2

AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

AJ6
AG6
AG4
AJ4

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

G21
H21
K19
G22
J24

C1
C2
D2

B2
B1

20MIL

PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

PCIRST#_L

+3V

AD23
AD24
AD25
AD26
AD27

SB820_MEMHOT#

INT_CLKREQ_MPC#

LPC_CLK0
LPC_CLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#_SB
LDRQ1#_SB
SERIRQ

ALLOW_LDTSTOP
CPU_PROCHOT#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_RST#

RTC_X1
RTC_X2
RTC_CLK

INTRUDER_ALERT#
VCCRTC_SB

3

T64T64

R69 33/J_4R69 33/J_4

BOARD_ID0
BOARD_ID1

<BOM Note>

BOARD_ID2

ID0/1/2 P/N Model

BOARD_ID3

000 AKD5LGGT506 SAM DDR3-800 1Gb K4W1G1646E-HC12

BOARD_ID4

001 AKD5LZGTW04 HYN DDR3-800 1Gb H5TQ1G63BFR-12C
010 AKD5LGGT700 ATI DDR3-800 1Gb 23EY2387MA12-SZ

R78 *10K/J_4R78 *10K/J_4
R296 BOM@10K/J_4R296 BOM@10K/J_4
R283 BOM@10K/J_4R283 BOM@10K/J_4
R63 *10K/J_4R63 *10K/J_4
R302 *10K/J_4R302 *10K/J_4

R300

R300

*0/J_4

*0/J_4

R342 22/J_4R342 22/J_4
R141 22/J_4R141 22/J_4

C115

C115
*0.1U/10V_4

*0.1U/10V_4

PCIRST#

C98 150P/50V_4C98 150P/50V_4

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

AD23 <14>
AD24 <14>

AD25 <14>
AD26 <14>
AD27 <14>

VDDR_1.2_EN="0" is for DDRIII-1066, VDDR=0.9V
VDDR_1.2_EN="1" is for DDRIII-1333, VDDR=1.05V

R293 *0/short_4R293 *0/short_4
T74T74

T76T76

LAD0 <23,25>
LAD1 <23,25>
LAD2 <23,25>
LAD3 <23,25>

LFRAME# <23,25>

T85T85
T83T83

SERIRQ <25>

ALLOW_LDTSTOP <8>

CPU_PROCHOT# <4>
CPU_PWRGD <4>

CPU_LDT_STOP# <4,8>

CPU_LDT_RST# <4>

RTC_CLK <25>

T62T62

R93 510/J_4R93 510/J_4

C116

C116
1U/10V_4

1U/10V_4

3

PCI_CLK1 <14>
PCI_CLK2 <14>
PCI_CLK3 <14>
PCI_CLK4 <14>

PCIRST# <23>

R77 SPM@10K/J_4R77 SPM@10K/J_4
R295 BOM@10K/J_4R295 BOM@10K/J_4
R284 BOM@10K/J_4R284 BOM@10K/J_4
R64 *10K/J_4R64 *10K/J_4
R303 *10K/J_4R303 *10K/J_4

VDDR_1.2_EN

CLKREQ_MPC# <23>

CLKRUN# <25>

LPC_CLK0 <14>
LPC_CLK1 <14>
LCLK_EC <25>
LCLK_DEBUG <23>

INTRUDER_ALERT# Left not connected (Southbridge
has 50-kohm internal pull-up to VBAT).

VCCRTC

+3V

R94

R94

R95

R95

*2.2K/J_4

*2.2K/J_4

*2.2K/J_4

*2.2K/J_4

2

Q10

Q10
*MMBT3904

*MMBT3904

1 3

From MINI PCIE 1

2

For AMD RST

For VDDR

MEM_1V5 is for gating the glitch on VDDR_1.2_EN

CPU_MEMHOT# <11,15>

RTC(RTC)

+3VPCU

VCCRTC_4

<20100119(B2A)_Bimini Rev1.4>
Non-stuff U21,C429,C428,R372,R300
(Nile doesn't support +1.05V for
DDR3-1333)

MEM_1V5<12>

VDDR_1.2_EN:
1 : VDDR =1.05V
0: VDDR = 0.90V (Default)

VCCRTC

D19

D19

CH500H-40

CH500H-40

D20

D20

CH500H-40

CH500H-40

R202

R202
1K/J_4

1K/J_4

20MIL

VCCRTC_3

BT1

BT1
RTC BATT

RTC BATT

2
1

RTC_X1

RTC_X2

2

Y2

2 3

1

32.768KHZY232.768KHZ

C111

C111
18P/50V_4

18P/50V_4

PLTRST#<21,23,24>

MINI-PCIE
LAN chip
Card reader

VDDR_1.2_EN

R56

R56
33/J_4

33/J_4

C80 0.1u/10V_4C80 0.1u/10V_4

A_RST#_AND

2
1

R368 *0/J_4R368 *0/J_4

G1

G1

12

*SHORT_PAD

*SHORT_PAD

R97

R97
*0/short_4

*0/short_4

4

C81

C81
10p/50V_4

10p/50V_4

R59 *0/J_4R59 *0/J_4

+3V

C429 *0.1U/10V_4C429 *0.1U/10V_4

U21

U21

3 5

*TC7SH08FU

*TC7SH08FU

+3V_S5

3 5

R372 *33/J_4R372 *33/J_4

4

20MIL

VCCRTC_2 VCCRTC_1

1 3

Q12

Q12

MMBT3904

MMBT3904

2

<20100303(C3A)>
Delete CN5 and Add BT1, for Battery SMT type.
<20100310(C3A)>
Swap BT1's pin, for pin define error

<BOM Note>
RTC BATTERY
AHL03001033 : JHT (18mAh)
AHL03001032 : MAT (17mAh)
AHL03001035 : FDK (15mAh)

4

<20100303(C3A)>
Change C93,C111 from CH02206JB08(22pF) to CH01806JB07(18pF), for Y2.

R7220M/J_6 R7220M/J_6

C93

C93
18P/50V_4

18P/50V_4

R213 8.06K/F_4R213 8.06K/F_4

R = (5V - 0.2V-2V)/0.2mA = 14k

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

A_RST#_SB

2
1

U4

U4
TC7SH08FU

TC7SH08FU

The Nile VDDR should be 0.9V
all the time. The 1.05V is only
for DDR3_1333 which is not
supported on Nile.

C428

C428
*150P/50V_4

*150P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SB820-PCIE/CPU/LPC 1/5

SB820-PCIE/CPU/LPC 1/5

SB820-PCIE/CPU/LPC 1/5

R219 8.06K/F_4R219 8.06K/F_4

1

A_RST#_SB <25>

SB_GPIO_PCIE_RST# <11>

VDDR_OPT <33>

ZH9

ZH9

ZH9

10 40Sunday, March 28, 2010

10 40Sunday, March 28, 2010

10 40Sunday, March 28, 2010

68.1K/F_4

68.1K/F_4

150K/F_4

150K/F_4

R220

R220

R221

R221

+5VPCU

4A

4A

4A

5

+3V_S5

NC only ,Can't be install

R100 *2.2K/J_4R100 *2.2K/J_4

R98 *2.2K/J_4R98 *2.2K/J_4

R280 *2.2K/J_4R280 *2.2K/J_4

D D

SCL0/SDATA0 is +3.3V_S0 domain

To Clock gen/DDR/WLAN

+3V

R338 2.2K/J_4R338 2.2K/J_4
R335 2.2K/J_4R335 2.2K/J_4

SMBUS1~3 is +3.3V_S5 domain
If SMBUS and GPIO not implemented
10K PU to +3V_S5 or 10K PD

R279 10K/J_4R279 10K/J_4
R92 10K/J_4R92 10K/J_4

R133 10K/J_4R133 10K/J_4
R337 10K/J_4R337 10K/J_4

+1.8V

R136 10K/J_4R136 10K/J_4
R148 10K/J_4R148 10K/J_4

R340 300/J_4R340 300/J_4

To Azalia

ACZ_SDOUT

ACZ_SYNC

ACZ_BCLK

ACZ_RST#

ACZ_SDIN0

C C

B B

A A

SB_TEST0

SB_TEST1

SB_TEST2

SB_SCLK0
SB_SDATA0

SB_SCLK1
SB_SDATA1

SB_SCLK2
SB_SDATA2

SB_SCLK3
SB_SDATA3

NB_PWRGD

R85 33/J_4R85 33/J_4 R70 10K/J_4R70 10K/J_4

R86 33/J_4R86 33/J_4

R87 33/J_4R87 33/J_4
R88 *10K/J_4R88 *10K/J_4

R71 33/J_4R71 33/J_4

R90 *10K/J_4R90 *10K/J_4

C99 *10P/50V_4C99 *10P/50V_4

C100 *10P/50V_4C100 *10P/50V_4

C101 *10P/50V_4C101 *10P/50V_4

5

From MINI PCIE 2

From LAN

ACZ_SDOUT_AUDIO <19>

ACZ_SYNC_AUDIO <19>

ACZ_BITCLK_AUDIO <19>

ACZ_RST#_AUDIO <19>

ACZ_SDIN0 <19>

<20091030(A1A)_EMI's Suggest>
Add one 10pF to GND for BITCLK

CPU_MEMHOT#<10,15>

SUSB#<25>

SUSC#<25>
DNBSWON#<25>
ECPWROK<25>

SUS_STAT#<8>

GA20<25>
KBRST#<25>

EC_SMI#<25>
EC_SCI#<25>

PCIE_WAKE#<21,23>

CPU_THERMTRIP#<4>

NB_PWRGD<8>

EC_RSMRST#<25>

SB_GPIO_PCIE_RST#<10>

CLKREQ_MNC#<23>

SB_BEEP<19>
SB_SCLK0<15,23>
SB_SDATA0<15,23>

CLKREQ_LAN#<21>

SP_DDR3_RST#<6>

<20091202(A1A)_Confirm with AMD's Horace>
IDLEEXIT#(Multi function of Pin AA20) is used for server CPU.

USBOC#R<20>
USBOC#L<20>

ACZ_SDOUT<14>

4

T9T9

T13T13

T10T10
T19T19

HD audio interface is +3V_S5 voltage

R91 *0/J_4R91 *0/J_4

R294 *0/short_4R294 *0/short_4

R341 *0/short_4R341 *0/short_4

R333 *0/short_4R333 *0/short_4

R281 SPM@0/J_4R281 SPM@0/J_4

R277 *0/J_4R277 *0/J_4
R278 *0/J_4R278 *0/J_4

T73T73
T69T69
T68T68
T70T70

+3V_S5

T17T17
T22T22

4

SB_PWRGD
SUS_STAT#
SB_TEST0
SB_TEST1
SB_TEST2

SYS_RST#

CPU_THERMTRIP#
NB_PWRGD

RSMRST#

SB_GPIO_PCIE_RST#

INT_CLKREQ_MNC#

SB_SCLK0
SB_SDATA0
SB_SCLK1
SB_SDATA1

INT_CLKREQ_LAN#

LLB#
SHUTDOWN#

USBOC#67

USBOC#0
SB_JTAG_TDO
SB_JTAG_TCK
SB_JTAG_TDI
SB_JTAG_RST#

ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0

ACZ_SYNC
ACZ_RST#

R84 10K/J_4R84 10K/J_4
R286 10K/J_4R286 10K/J_4

R83 10K/J_4R83 10K/J_4

R282 10K/J_4R282 10K/J_4

U5D

U5D

J2

PCI_PME#/GEVENT4#

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_BTN#

H5

PWR_GOOD

G6

SUS_STAT#

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0#

AE21

KBRST#/GEVENT1#

K2

LPC_PME#/GEVENT3#

J29

LPC_SMI#/GEVENT23#

H2

GEVENT5#

J1

SYS_RESET#/GEVENT19#

H6

WAKE#/GEVENT8#

F3

IR_RX1/GEVENT20#

J6

THRMTRIP#/SMBALERT#/GEVENT2#

AC19

NB_PWRGD

G1

RSMRST#

AD19

CLK_REQ4#/SATA_IS0#/GPIO64

AA16

CLK_REQ3#/SATA_IS1#/GPIO63

AB21

SMARTVOLT1/SATA_IS2#/GPIO50

AC18

CLK_REQ0#/SATA_IS3#/GPIO60

AF20

SATA_IS4#/FANOUT3/GPIO55

AE19

SATA_IS5#/FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO227

F4

SDA1/GPIO228

AH21

CLK_REQ2#/FANIN4/GPIO62

AB18

CLK_REQ1#/FANOUT4/GPIO61

E1

IR_LED#/LLB#/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

H4

DDR3_RST#/GEVENT7#

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9#

G5

GBE_LED2/GEVENT10#

K3

GBE_STAT0/GEVENT11#

AA20

CLK_REQG#/GPIO65/OSCIN

H3

BLINK/USB_OC7#/GEVENT18#

D1

USB_OC6#/IR_TX1/GEVENT6#

E4

USB_OC5#/IR_TX0/GEVENT17#

D4

USB_OC4#/IR_RX0/GEVENT16#

E8

USB_OC3#/AC_PRES/TDO/GEVENT15#

F7

USB_OC2#/TCK/GEVENT14#

E7

USB_OC1#/TDI/GEVENT13#

F8

USB_OC0#/TRST#/GEVENT12#

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST#

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2#/GBE_STAT2/GPIO166

G29

FC_RST#/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

SB820M

SB820M

SB800

SB800

Part 4 of 5

Part 4 of 5

GBE LAN

GBE LAN

3

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

ACPI / WAKE UP EVENTS

EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199

HD AUDIO

HD AUDIO

EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

EMBEDDED CTRL

3

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB 1.1 USB MISCEMBEDDED CTRL

USB 1.1 USB MISCEMBEDDED CTRL

USB 2.0

USB 2.0

GPIO

GPIO

USB OC

USB OC

SCL3_LV/GPIO195
SDA3_LV/GPIO196

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P

USB_HSD13N

USB_HSD12P

USB_HSD12N

USB_HSD11P

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P
USB_HSD9N

USB_HSD8P
USB_HSD8N

USB_HSD7P
USB_HSD7N

USB_HSD6P
USB_HSD6N

USB_HSD5P
USB_HSD5N

USB_HSD4P
USB_HSD4N

USB_HSD3P
USB_HSD3N

USB_HSD2P
USB_HSD2N

USB_HSD1P
USB_HSD1N

USB_HSD0P
USB_HSD0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217

KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

A10
G19

J10
H11

H9
J8

B12
A12

F11
E11

E14
E12

J12
J14

A13
B13

D13
C13

G12
G14

G16
G18

D16
C16

B14
A14

E18
E16

J16
J18

B17
A17

A16
B16

D25
F23
B26
E26
F25
E22
F22
E21

G24
G25
E28
E29
D29
D28
C29
C28

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

2

<20100129(B2A)>
Stuff R110. (CLK for Cardreader from crystal
change to internal CLK.)

SB_CLK_48M_CR

USB_RCOMP_SB

USB_FSD13P
USB_FSD13N

USB_FDS12P
USB_FSD12N

Controller Ports mapping
OHCI0 (dev-18, fun-0) Port 0 - 4
EHCI (dev-18, fun-2) Port 0 - 4
OHCI0 (dev-19, fun-0) Port 5 - 9
EHCI (dev-19, fun-2) Port 5 - 9
OHCI0 (dev-22, fun-0) Port 10 - 14
EHCI (dev-22, fun-2) Port 10 - 14

USB+_SIM <23>
USB-_SIM <23>

USBP7+ <20>
USBP7- <20>

USBP6+ <20>
USBP6- <20>

USBP5+ <18>
USBP5- <18>

USBP4+ <23>
USBP4- <23>

USBP3+ <16>
USBP3- <16>

USBP2+ <23>
USBP2- <23>

USBP1+ <24>
USBP1- <24>

USBP0+ <20>
USBP0- <20>

SB_SCLK2
SB_SDATA2
SB_SCLK3
SB_SDATA3

R110 ICK@22/J_4R110 ICK@22/J_4

R332 11.8K/F_6R332 11.8K/F_6

T75T75
T77T77

T72T72
T71T71

MM-SIM
CONN (Lower Right)

CONN (Upper Right)

BT

MNC

CCD

MPC

Card reader

CONN (Left)

EC_PWM2 <14>
EC_PWM3 <14>

2

OHCI (dev-20, fun-5)

1

CLK_48M_CR <24>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

to CARD READER 48MHz

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

PROJECT :

SB820-ACPI/GPIO/USB 2/5

SB820-ACPI/GPIO/USB 2/5

SB820-ACPI/GPIO/USB 2/5

ZH9

11 40Sunday, March 28, 2010

11 40Sunday, March 28, 2010

1

11 40Sunday, March 28, 2010

4A

4A

4A

5

4

3

2

1

SATA PORT 0,1,2,3
can support AHCI
mode

SATA_TXP0<22>

SATA HDD

D D

C C

SATA_TXN0<22>

SATA_RXN0<22>
SATA_RXP0<22>

To meet SB800 SCL1.02:
DNI SATA XTAL circuit's parts

B B

PLACE SATA AC COUPLING
CAPS CLOSE TO SB820

C141 0.01U/25V_4C141 0.01U/25V_4
C142 0.01U/16V_4C142 0.01U/16V_4

C140 0.01U/25V_4C140 0.01U/25V_4
C137 0.01U/25V_4C137 0.01U/25V_4

PLACE SATA_CAL
RES VERY CLOSE
TO BALL OF SB820

+1.1V_SB_VDDAN_11_SATA

R316 1K/F_4R316 1K/F_4
R315 931/F_4R315 931/F_4

SATALED#<22>

C151 *22P/50V_4C151 *22P/50V_4

Y3

Y3

*25MHz-SATA

*25MHz-SATA

C145 *22P/50V_4C145 *22P/50V_4

2 1

SATA_CALRP
SATA_CALRN

R304 10K/J_4R304 10K/J_4

+3V

SATA_X1

R114

R114
*1M/J_4

*1M/J_4

SATA_X2

SATA_TXP0_C
SATA_TXN0_C

SATA_RXN0_C
SATA_RXP0_C

U5B

U5B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

AH10

SATA_TX1P

AJ10

SATA_TX1N

AG10

SATA_RX1N

AF10

SATA_RX1P

AG12

SATA_TX2P

AF12

SATA_TX2N

AJ12

SATA_RX2N

AH12

SATA_RX2P

AH14

SATA_TX3P

AJ14

SATA_TX3N

AG14

SATA_RX3N

AF14

SATA_RX3P

AG17

SATA_TX4P

AF17

SATA_TX4N

AJ17

SATA_RX4N

AH17

SATA_RX4P

AJ18

SATA_TX5P

AH18

SATA_TX5N

AH19

SATA_RX5N

AJ19

SATA_RX5P

AB14

SATA_CALRP

AA14

SATA_CALRN

AD11

SATA_ACT#/GPIO67

AD16

SATA_X1

AC16

SATA_X2

SB800

SB800

Part 2 of 5

Part 2 of 5

SERIAL ATA

SERIAL ATA

HW MONITOR

HW MONITOR

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE#/GPIOD145

FC_AVD#/GPIOD146

FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150

FC_INT1/GPIOD144

FC_INT2/GPIOD147

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136

FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140

FLASH

FLASH

FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

TEMP_COMM

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180

The flash controller function is NOT
supported by the SB820M.

AH28
AG28
AF26

AF28
AG29
AG26
AF27
AE29
AF29
AH27

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

W5
W6

SB_PROCHOT#_C

Y9
W7

V9
W8

TEMPIN0

B6

TEMPIN1

A6

TEMPIN2

A5
B5

TEMP_COMM

C7

VIN0

A3

VIN1

B4

VIN2

A4

VIN3

C5

VIN4 VIN4

A7

VIN5

B7

VIN6

B8

VIN7

A8

R109 10K/J_4R109 10K/J_4
R108 10K/J_4R108 10K/J_4
R103 10K/J_4R103 10K/J_4

R290 10K/J_4R290 10K/J_4
R289 10K/J_4R289 10K/J_4
R288 10K/J_4R288 10K/J_4
R102 10K/J_4R102 10K/J_4
R409 10K/J_4R409 10K/J_4
R298 10K/J_4R298 10K/J_4
R301 10K/J_4R301 10K/J_4
R297 10K/J_4R297 10K/J_4

T45T45
T31T31
T39T39

T38T38
T37T37
T36T36
T43T43
T44T44
T32T32

IF THERE IS NO IDE, TEST

T33T33

POINTS FOR DEBUG BUS

T42T42

IS MANDATORY

T30T30
T29T29
T28T28
T23T23
T24T24
T21T21
T16T16
T80T80
T20T20
T25T25
T84T84
T34T34
T35T35
T40T40
T41T41

R106

R106
10K/J_4

10K/J_4

1 3

<20100119(B2A)_Bimini Rev1.4>
Non-stuff R408 ; stuff R409
(Nile doesn't support VDDR = +1.05V for DDR3-1333)

+3V

R105

R105
10K/J_4

10K/J_4

2

Q11

Q11
MMBT3904

MMBT3904

R107 10K/J_4R107 10K/J_4

THERM_ALERT# <4>

R408 *0/J_4R408 *0/J_4

SB_PROCHOT# <4>

+3V_S5

MEM_1V5 <10>

T67T67
T12T12
T11T11
T65T65
T66T66

A A

5

4

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1#/GPIO165

G2

ROM_RST#/GPIO161

SB820M

SB820M

SPI ROM

SPI ROM

3

NC1
NC2

G27
Y2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

PROJECT :

SB820-SATA/HWM/SPI 3/5

SB820-SATA/HWM/SPI 3/5

SB820-SATA/HWM/SPI 3/5

ZH9

1

12 40Sunday, March 28, 2010

12 40Sunday, March 28, 2010

12 40Sunday, March 28, 2010

4A

4A

4A

5

3.3V I/O power Core logic power

R74 *0/short_6R74 *0/short_6

+3V

C113

C113

22U/6.3V_8

D D

22U/6.3V_8

12

C334

C334

0.1U/10V_4

0.1U/10V_4

12

C336

C336

0.1U/10V_4

0.1U/10V_4

12

0.1U/10V_4

0.1U/10V_4

Not used: Connected to GND through a 0Ω.

A-Link Express III/PCIe PLL power

L42 1.4A/220ohm_6L42 1.4A/220ohm_6

+3V

C402

C402

C401

2.2U/6.3V_6

2.2U/6.3V_6

A-Link Express III/PCIe analog power

L44 4A/42ohm_8L44 4A/42ohm_8

+1.1V

C C

DCR=0.008Ω

Check

C407

C407

22U/6.3V_8

22U/6.3V_8

C401

*0.1U/10V_4

*0.1U/10V_4

+1.1V_SB_VDDAN_11_PCIE

+1.1V_SB_VDDAN_11_PCIE

12

C389

C389

0.1U/10V_4

0.1U/10V_4

SATA PHY PLL power

L35 1.4A/220ohm_6L35 1.4A/220ohm_6

+3V

SATA PHY analog / I/O Power

L13 4A/42ohm_8L13 4A/42ohm_8

+1.1V

DC R=0.008Ω

+1.1V_SB_VDDAN_11_SATA

C157

C157

22U/6.3V_8

22U/6.3V_8

+3V_SB_VDDPL_33_SATA

+1.1V_SB_VDDAN_11_SATA

12

C365

C365

0.1U/10V_4

0.1U/10V_4

USB PHY analog / I/O Power

L12 1.4A/220ohm_6L12 1.4A/220ohm_6

+3VSUS

Support S3 wake up

B B

USB PHY DLL analog power

+1.1VSUS

L34 1.4A/220ohm_6L34 1.4A/220ohm_6

+3VSUS_SB_VDDAN_33_USB_S

12

C149

C149

10U/6.3V_8

10U/6.3V_8

+1.1VSUS_SB_VDDAN_11_USB_S

Support S3 wake up

+3V_S5_SB_VDDIO_AZ_S

+3V_S5

R305 *0/short_6R305 *0/short_6

1.8V GPIOD I/O Power

12

C387

C387

0.1U/10V_4

0.1U/10V_4

C348

C348

2.2U/6.3V_6

2.2U/6.3V_6

12

C364

C364

0.1U/10V_4

0.1U/10V_4

12

C148

C148

10U/6.3V_8

10U/6.3V_8

C337

C337

2.2U/6.3V_6

2.2U/6.3V_6

12

C335

C335

2.2U/6.3V_6

2.2U/6.3V_6

+3V_SB_VDDPL_33_PCIE

600mA

12

C383

C383

1U/10V_4

1U/10V_4

93mA

C349

C349

*0.1U/10V_4

*0.1U/10V_4

567mA

12

12

C363

C363

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

50mils

658mA

12

12

C373

C373

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

20mils

xx mA

C342

C342

0.1U/10V_4

0.1U/10V_4

C382

C382

R344

R344
*0/short_4

*0/short_4

43mA

100mils

15mils

50mils

C357

C357

C374

C374

4

15mils

PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.

U5C

U5C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4

AC21

VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11

AA19

VDDIO_33_PCIGP_12

AF22

VDDIO_18_FC_1

AE25

VDDIO_18_FC_2

AF24

VDDIO_18_FC_3

AC22

VDDIO_18_FC_4

AE28

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

AD14

VDDPL_33_SATA

AJ20

VDDAN_11_SATA_1

AF18

VDDAN_11_SATA_4

AH20

VDDAN_11_SATA_2

AG19

VDDAN_11_SATA_3

AE18

VDDAN_11_SATA_5

AD18

VDDAN_11_SATA_6

AE16

VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

SB820M

SB820M

POWER

POWER

SB800

SB800

PCI/GPIO I/O

PCI/GPIO I/O

FLASH I/O

FLASH I/O

PCI EXPRESSSERIAL ATA

PCI EXPRESSSERIAL ATA

Support S3 wake up

R111 *0/short_6R111 *0/short_6

12

Part 3 of 5

Part 3 of 5

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7

CORE S03.3V_S5 I/O

CORE S03.3V_S5 I/O

VDDCR_11_8
VDDCR_11_9

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

VDDCR_11_GBE_S_1

GBE LAN

GBE LAN

VDDCR_11_GBE_S_2

VDDIO_GBE_S_1
VDDIO_GBE_S_2

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

VDDCR_11_S_1
VDDCR_11_S_2

VDDIO_AZ_S

CORE S5

CORE S5

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

VDDPL_33_SYS

USB I/O

USB I/O

VDDPL_11_SYS_S

PLL CLKGEN I/O

PLL CLKGEN I/O

VDDPL_33_USB_S

VDDAN_33_HWM_S

VDDXL_33_S

12

C144

C144
10U/6.3V_8

10U/6.3V_8

+1.1VSUS_SB_VDDCR_11_USB_S+1.1VSUS

C341

C341

0.1U/10V_4

0.1U/10V_4

3

100mils

N13
R15
N17
U13
U17
V12
V18
W12
W18

xx mA

K28
K29
J28
K26
J21
J20
K21
J22

V1
M10

L7
L9

M6
P8

A21
D21
B21
K10
L10
J9
T6
T8

F26
G26

M8
A11

B11

M21
L22
F19
D6
L20

+1.1V_SB_VDDAN_11_CLK

12

ICK@0.1U/10V_4

ICK@0.1U/10V_4

<45484_sb800_dg_nda_1.02>
Not use interal CLK Gen: Connected to +1.1V directly.

Not support GBE: Connected to GND.

20mils

15mils

20mils

xx mA

15mils

197mA

USB PHY core power

+3V_SB_VDDPL_33_SYS
+1.1V_S5_SB_VDDPL_11_SYS_S
+3VSUS_SB_VDDPL_33_USB_S
+3V_S5_SB_VDDAN_33_HWM_S

+3V_S5_SB_VDDXL_33_S

15mils

xx mA

12

C340

C340

0.1U/10V_4

0.1U/10V_4

510mA131mA

12

C347

C347

0.1U/10V_4

0.1U/10V_4

C378

C378

32mA

113mA

+1.1VSUS_SB_VDDCR_11_USB_S

+1.1V_SB_VDDCR+3V_SB_VDDIO_33_PCIGP

12

C346

C346

0.1U/10V_4

0.1U/10V_4

12

C379

C379

ICK@0.1U/10V_4

ICK@0.1U/10V_4

+3V_S5_SB_VDDIO_33_S

12

*0.1U/10V_4

*0.1U/10V_4

HD Audio I/O Power

+3V_S5_SB_VDDIO_AZ_S

12

*0.1U/10V_4

*0.1U/10V_4

12

C384

C339

C339

+1.1V_S5_SB_VDDCR_11_S

C370

C370

C384

2.2U/6.3V_6

2.2U/6.3V_6

12

C358

C358

2.2U/6.3V_6

2.2U/6.3V_6

C353

C353

1U/10V_4

1U/10V_4

R327 *0/short_6R327 *0/short_6

12

C338

C338

10U/6.3V_8

10U/6.3V_8

12

C359

C359

1U/10V_4

1U/10V_4

12

System Clock Gen analog/output power

12

ICK@1U/10V_4

ICK@1U/10V_4

C399

C399

12

C404

C404

ICK@1U/10V_4

ICK@1U/10V_4

S5 I/O Power

R339 *0/short_6R339 *0/short_6

12

C332

C332

2.2U/6.3V_6

2.2U/6.3V_6

S5 Core logic standby power

12

C390

C390

1U/10V_4

1U/10V_4

15mils
15mils

L33 1.4A/220ohm_6L33 1.4A/220ohm_6

+3V

System CLK Gen PLLs analog power

47mA

System CLK Gen PLLs analog power

62mA

USB PHY PLL analog power

17mA

Hardware monitor analog / I/O power

5mA

L36 1.4A/220ohm_6L36 1.4A/220ohm_6

2

+1.1V

Check

L16 4A/42ohm_8L16 4A/42ohm_8

DCR=0.008Ω

C178

C178

ICK@22U/6.3V_8

ICK@22U/6.3V_8

+3V_S5

R348 *0/short_6R348 *0/short_6

12

C391

C391

1U/10V_4

1U/10V_4

+3V_S5

WoL--> +3.3V_S5 rail
Non-WoL--> +3.3V_S0 rail

+3V_SB_VDDPL_33_SYS

12

C381

C381

*0.1U/10V_4

*0.1U/10V_4

+1.1V_S5

25-MHz XTAL I/O Power

12

C376

C376

2.2U/6.3V_6

2.2U/6.3V_6

+1.1V

U5E

U5E

Y14

VSSIO_SATA_1

Y16

VSSIO_SATA_2

AB16

VSSIO_SATA_3

AC14

VSSIO_SATA_4

AE12

VSSIO_SATA_5

AE14

VSSIO_SATA_6

AF9

VSSIO_SATA_7

AF11

VSSIO_SATA_8

AF13

VSSIO_SATA_9

AF16

VSSIO_SATA_10

AG8

VSSIO_SATA_11

AH7

VSSIO_SATA_12

AH11

VSSIO_SATA_13

AH13

VSSIO_SATA_14

AH16

VSSIO_SATA_15

AJ7

VSSIO_SATA_16

AJ11

VSSIO_SATA_17

AJ13

VSSIO_SATA_18

AJ16

VSSIO_SATA_19

A9

VSSIO_USB_1

B10

VSSIO_USB_2

K11

VSSIO_USB_3

B9

VSSIO_USB_4

D10

VSSIO_USB_5

D12

VSSIO_USB_6

D14

VSSIO_USB_7

D17

VSSIO_USB_8

E9

VSSIO_USB_9

F9

VSSIO_USB_10

F12

VSSIO_USB_11

F14

VSSIO_USB_12

F16

VSSIO_USB_13

C9

VSSIO_USB_14

G11

VSSIO_USB_15

F18

VSSIO_USB_16

D9

VSSIO_USB_17

H12

VSSIO_USB_18

H14

VSSIO_USB_19

H16

VSSIO_USB_20

H18

VSSIO_USB_21

J11

VSSIO_USB_22

J19

VSSIO_USB_23

K12

VSSIO_USB_24

K14

VSSIO_USB_25

K16

VSSIO_USB_26

K18

VSSIO_USB_27

H19

VSSIO_USB_28

Y4

EFUSE

D8

VSSAN_HWM

M19

VSSXL

P21

VSSIO_PCIECLK_1

P20

VSSIO_PCIECLK_2

M22

VSSIO_PCIECLK_3

M24

VSSIO_PCIECLK_4

M26

VSSIO_PCIECLK_5

P22

VSSIO_PCIECLK_6

P24

VSSIO_PCIECLK_7

P26

VSSIO_PCIECLK_8

T20

VSSIO_PCIECLK_9

T22

VSSIO_PCIECLK_10

T24

VSSIO_PCIECLK_11

V20

VSSIO_PCIECLK_12

J23

VSSIO_PCIECLK_13

SB820M

SB820M

1

SB800

SB800

Part 5 of 5

Part 5 of 5

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

GROUND

GROUND

VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

VSSPL_SYS

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

M20

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

A A

+1.1V_S5

L43 1.4A/220ohm_6L43 1.4A/220ohm_6

WoL--> +1.1V_S5 rail
Non-WoL--> +1.1V_S0 rail

5

+1.1V_S5_SB_VDDPL_11_SYS_S

C385

C385

12

C400

C400

2.2U/6.3V_6

2.2U/6.3V_6

12

*0.1U/10V_4

*0.1U/10V_4

Support S3 wake up

R117 *0/short_6R117 *0/short_6

<20100310(C3A)_Follow CRB>
Connect +3VSUS_SB_VDDPL_33_USB_S to
+3VSUS directly.

4

+3VSUS_SB_VDDPL_33_USB_S+3VSUS

C153

C153

2.2U/6.3V_6

2.2U/6.3V_6

C375

C375

0.1U/10V_4

0.1U/10V_4

3

+3V_S5 +3V_S5_SB_VDDAN_33_HWM_S

R287 *0/short_6R287 *0/short_6

12

0.1U/10V_4

0.1U/10V_4

C333

C333

12

C331

C331

*2.2U/6.3V_6

*2.2U/6.3V_6

As GPIOs: Stuff 0.1uF

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

PROJECT :

SB820-PWR/DECOUPLING 4/5

SB820-PWR/DECOUPLING 4/5

SB820-PWR/DECOUPLING 4/5

ZH9

of

13 40Sunday, March 28, 2010

13 40Sunday, March 28, 2010

13 40Sunday, March 28, 2010

1

4A

4A

4A

5

4

3

2

1

STANDARD STRAPS

<20091202(A1A)_Confirm with AMD's Horace>
PCI_CLK4 PU with 10K for both internal and external CLK Gen.

D D

EC_PWM2<11>
EC_PWM3<11>
LPC_CLK1<10>
LPC_CLK0<10>
PCI_CLK4<10>
PCI_CLK3<10>
PCI_CLK2<10>
PCI_CLK1<10>

ACZ_SDOUT<11>

+3V_S5 +3V+3V +3V +3V_S5+3V_S5

R61

R61
*10K/J_4

*10K/J_4

R60

R60
10K/J_4

10K/J_4

R68

R68
*10K/J_4

*10K/J_4

R82

R82
*10K/J_4

*10K/J_4

R81

R81
10K/J_4

10K/J_4

R66

R66
*10K/J_4

*10K/J_4

R67

R67
10K/J_4

10K/J_4

R79

R79
10K/J_4

10K/J_4

R80

R80
*10K/J_4

*10K/J_4

R343

R343
10K/J_4

10K/J_4

R146

R146
ICK@10K/J_4

ICK@10K/J_4

R138

R138

*10K/J_4

*10K/J_4

R119

R119

2.2K/J_4

2.2K/J_4

R132

R132
10K/J_4

10K/J_4

R130

R130
*2.2K/J_4

*2.2K/J_4

C C

B B

DEBUG STRAPS

PULL
HIGH

PULL
LOW

LOW POWER
MODE

PERFORMANCE
MODE

DEFAULT

This is
required as
the low
power mode
is not
supported on
the SB8xx.

AZ_SDOUT

PCI_CLK1

PCIe Gen II

PCIe Gen I

Not Applicable to
SB820M--Leave
provision for PD.

PCI_CLK2

Watchdog
Timer Enable

Watchdog
Timer Disable

DEFAULT

PCI_CLK3

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

PCI_CLK4

non_Fusion
CLK MODE

ICK@DEFAULT ICK@DEFAULT

FUSION
CLK MODE

PCICLK4:
CPU/NB HT Clock Selection
This strap is not used if the strap CLKGEN is
configured for external clock generator mode.

LPC_CLK0

EC
ENABLED

EC
DISABLED

DEFAULT

LPC_CLK1

CLKGEN
ENABLED

CLKGEN
DISABLED

ECK@DEFAULT

EC_PWM3 EC_PWM2

H, H=Reserved
H, L=SPI ROM

L, H=LPC ROM

DEFAULT

L, L=Reserved

internal have
pull Hi 10K

SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

AD23<10>
AD24<10>
AD25<10>
AD26<10>
AD27<10>

12

R292

R292
*2.2K/J_4

*2.2K/J_4

PCI_AD27 PCI_AD26

A A

PULL
HIGH

PULL
LOW

5

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

12

R291

R291
*2.2K/J_4

*2.2K/J_4

DISABLE ILA
AUTORUN

DEFAULT

ENABLE ILA
AUTORUN

4

12

R306

R306
*2.2K/J_4

*2.2K/J_4

12

PCI_AD25 PCI_AD24

USE FC
PLL

DEFAULT

BYPASS FC
PLL

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

R299

R299
*2.2K/J_4

*2.2K/J_4

12

PCI_AD23

DISABLE PCI
MEM BOOT

DEFAULT

ENABLE PCI
MEM BOOT

3

R112

R112
*2.2K/J_4

*2.2K/J_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZH9

ZH9

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

PROJECT :

SB820-STRAPS,PWRGD 5/5

SB820-STRAPS,PWRGD 5/5

SB820-STRAPS,PWRGD 5/5

ZH9

14 40Sunday, March 28, 2010

14 40Sunday, March 28, 2010

14 40Sunday, March 28, 2010

1

4A

4A

4A

5

4

3

2

1

Standard

Connector

1

1

2
3
5

4

6
7

8
9

10
11

12
13

14
15

16
17

18
19

20
21

22

2

23

24
25

26
27

28
29

30
31

32
33

34
35

36
37

38
39

40

41

42
43

44
45

46

48

47
49

50

D D

C C

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177

199

179
181
183
185
187
189
191
193
195
197
199

SMbus address A0

R262 *4.7K/J_4R262 *4.7K/J_4

+3V

R260 *4.7K/J_4R260 *4.7K/J_4

52

54

56

58

60

62

64

66

68

70

72

CON_SODIMM200_STD_V1

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

200

178

180

182

184

186

188

190

192

194

196

198

200

SA0_A
SA1_A

R258

R258

R263

R263

*0/short_4

*0/short_4

*0/short_4

*0/short_4

+1.5VSUS +SMDDR_VREF

R154

R154

*1K/F_4

*1K/F_4

R149

R149

*0/short_6

*0/short_6

MEM_VREF

C202

C201

R151

R151

*1K/F_4

*1K/F_4

B B

C201

0.01U/25V_4

0.01U/25V_4

+1.5VSUS +SMDDR_VREF

R57

R62

R62

*1K/F_4

*1K/F_4

R57

*0/short_6

*0/short_6

MEM_VREFCA

C90

R58

R58

*1K/F_4

*1K/F_4

A A

Confirmed with AMD FAE Reden
MA_EVENT_L should be PU(R8004) with 2.2K, not 1K
Not installed by default

C90

0.01U/25V_4

0.01U/25V_4

+1.5VSUS

+1.5VSUS

5

C202

1000P/50V_4

1000P/50V_4

<20100115(B2A)>
Add Power Symbol for +SMDDR_VTERM
disconnect issue.

+1.5VSUS

C91

C91

1000P/50V_4

1000P/50V_4

R43 *2.2K/J_4R43 *2.2K/J_4

R33 *2.2K/J_4R33 *2.2K/J_4

MEMHOT_MA#

M_A_RST#<3>

C32 *0.1U/10V_4C32 *0.1U/10V_4

2

1 3

Q4

Q4
*MMBT3904

*MMBT3904

M_A_A[0..15]<3>

M_A_BANK[0..2]<3>

M_A_DM[0..7]<3>

C35

C35

4.7U/6.3V_6

4.7U/6.3V_6

4

+3V

MEMHOT_MA#<3>

+SMDDR_VTERM

M_A_DQSP0<3>
M_A_DQSP1<3>
M_A_DQSP2<3>
M_A_DQSP3<3>
M_A_DQSP4<3>
M_A_DQSP5<3>
M_A_DQSP6<3>
M_A_DQSP7<3>

M_A_DQSN0<3>
M_A_DQSN1<3>
M_A_DQSN2<3>
M_A_DQSN3<3>
M_A_DQSN4<3>
M_A_DQSN5<3>
M_A_DQSN6<3>
M_A_DQSN7<3>

M_A_CLKP1<3>
M_A_CLKN1<3>
M_A_CLKP2<3>
M_A_CLKN2<3>

M_A_CKE0<3>
M_A_CKE1<3>

M_A_RAS#<3>
M_A_CAS#<3>
M_A_WE#<3>
M_A_CS#0<3>
M_A_CS#1<3>

M_A_ODT0<3>
M_A_ODT1<3>

SB_SDATA0<11,23>
SB_SCLK0<11,23>

C50 1U/6.3V_4C50 1U/6.3V_4

+SMDDR_VTERM

C38

C38

0.22U/6.3V_4

0.22U/6.3V_4

CPU_MEMHOT# <10,11>

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BANK0
M_A_BANK1
M_A_BANK2

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SA0_A
SA1_A

MEMHOT_MA#
MEM_VREF
MEM_VREFCA

C31

C31

0.22U/6.3V_4

0.22U/6.3V_4

+1.5VSUS

98

A0

97

A1

96

A2

95

A3/A4

92

A4/A3

91

A5/A6

90

A6/A5

86

A7/A8

89

A8/A7

85

A9

107

A10/AP

84

A11

83

A12_BC#

119

A13

80

A14

78

A15/BA3

109

BA0/BA1

108

BA1/BA0

79

BA2

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

110

RAS#

115

CAS#

113

WE#

114

S0#

121

S1#

116

ODT0

120

ODT1

197

SA0

201

SA1

200

SDA

202

SCL

199

VDDspd

30

RST#

198

EVENT#

1

VREF

126

VrefCA

203

VTT1

204

VTT2

2

VSS0

3

VSS1

8

VSS2

9

VSS3

13

VSS4

14

VSS5

19

VSS6

20

VSS7

25

VSS8

26

VSS9

31

VSS10

32

VSS11

VDD075VDD176VDD281VDD382VDD487VDD588VDD693VDD899VDD794VDD9

VSS1237VSS1338VSS1443VSS1544VSS16

H=4

100

105

106

111

112

117

118

123

124

CN15

CN15

M_A_DQ0

5

DQ0

VDD10

VDD11

DDR3 SO-DIMM

DDR3 SO-DIMM

VSS1854VSS1955VSS20

VSS17

48

60

61

49

3

DQ1

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53

(Standard )

(Standard )

DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

NC1

NC2
TEST

VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27

VSS26

VSS2572VSS2471VSS2366VSS2265VSS21

127

DDR3_SO-DIMM_SOCKET_1.5V_Standard

DDR3_SO-DIMM_SOCKET_1.5V_Standard

M_A_DQ1

7

M_A_DQ2

15

M_A_DQ3

17

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

16

M_A_DQ7

18

M_A_DQ8

21

M_A_DQ9

23

M_A_DQ10

33

M_A_DQ11

35

M_A_DQ12

22

M_A_DQ13

24

M_A_DQ14

34

M_A_DQ15

36

M_A_DQ16

39

M_A_DQ17

41

M_A_DQ18

51

M_A_DQ19

53

M_A_DQ20

40

M_A_DQ21

42

M_A_DQ22

50

M_A_DQ23

52

M_A_DQ24

57

M_A_DQ25

59

M_A_DQ26

67

M_A_DQ27

69

M_A_DQ28

56

M_A_DQ29

58

M_A_DQ30

68

M_A_DQ31

70

M_A_DQ36

129

M_A_DQ37

131

M_A_DQ35

141

M_A_DQ39

143

M_A_DQ38

130

M_A_DQ32

132

M_A_DQ33

140

M_A_DQ34

142

M_A_DQ40

147

M_A_DQ41

149

M_A_DQ46

157

M_A_DQ47

159

M_A_DQ44

146

M_A_DQ45

148

M_A_DQ42

158

M_A_DQ43

160

M_A_DQ52

163

M_A_DQ49

165

M_A_DQ54

175

M_A_DQ55

177

M_A_DQ53

164

M_A_DQ48

166

M_A_DQ51

174

M_A_DQ50

176

M_A_DQ61

181

M_A_DQ60

183

M_A_DQ63

191

M_A_DQ62

193

M_A_DQ56

180

M_A_DQ57

182

M_A_DQ58

192

M_A_DQ59

194

77
122

M_A_TEST

125

196
195
190
189
185
184
179
178
173
172
168
167
162
161
156
155
151
150
145
144
139
138
134
133
128

M_A_DQ[0..63] <3>

T61T61

2

+1.5VSUS

+

+

+1.5VSUS

C82

C82
100U/6.3V_3528

100U/6.3V_3528

C132

C132

0.1U/10V_4

0.1U/10V_4

C107

C107
*0.1U/10V_4

*0.1U/10V_4

+

+

C143

C143
100U/6.3V_3528

100U/6.3V_3528

C131

C117

C117

0.1U/10V_4

0.1U/10V_4

C95

C95
*0.1U/10V_4

*0.1U/10V_4

C119

C119

0.1U/10V_4

0.1U/10V_4

C127

C127
*0.1U/10V_4

*0.1U/10V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

C131

0.1U/10V_4

0.1U/10V_4

C104

C104
*0.1U/10V_4

*0.1U/10V_4

+SMDDR_VTERM <30>
+SMDDR_VREF <30>

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDR3 SODIMM: ONE CHANNEL

DDR3 SODIMM: ONE CHANNEL

DDR3 SODIMM: ONE CHANNEL

C139

C139

0.1U/10V_4

0.1U/10V_4

C126

C126
*0.1U/10V_4

*0.1U/10V_4

1

ZH9

ZH9

ZH9

C94

C94
*0.1U/10V_4

*0.1U/10V_4

15 40Sunday, March 28, 2010

15 40Sunday, March 28, 2010

15 40Sunday, March 28, 2010

C138

C138

0.1U/10V_4

0.1U/10V_4

4A

4A

4A

5

HALL IC(HSR)

Hall IC ESD PU

APX9132H
AI-TRG

EM-6781-T3 1.5KV

D D

C C

TYPE

2KV

CMOS N/A

CMOS N/A

<20100125(B2A)>
Change Hall IC from AL003661003
to AL009132001 ; non-stuff R254

+3V

R256

R256
10K/J_4

10K/J_4

DISPON

Q15

Q15

2N7002K

2N7002K

2

Q16

Q16
DTC144EU

DTC144EU

1 3

CRT(CRT)

CRT_R<8>

B B

<20090810(A1A)_46659_RS880_Errata_nda_1.10>
The R channel's term. R change 140ohm (For the
voltage level mismatch, the Red is higher)

+3V

A A

CRT_G<8>
CRT_B<8>

C301 0.22U/25V_6C301 0.22U/25V_6

C5

C5

0.1U/10V_4

0.1U/10V_4

+3VPCU

3

BL#

2

1

Q14

Q14

2N7002K

2N7002K

<20100115(B2A)>
Add F1(fuse) to meet IEC 60950-1
2nd certificationand.

CRTVDD5

CRT_BYP

CRT_R1
CRT_G1
CRT_B1

5

+3V

R253

R253
10K/J_4

10K/J_4

3

1

R254 *100K/J_4R254 *100K/J_4

LID#

2

1

C314

C314

3

MR1

0.1U/10V_4

0.1U/10V_4

2

1
7

8
2

3
4
5

6

MR1
APX9132H

APX9132H

D27 BAS316D27 BAS316

Confirmed with AMD Horace

R257

R257

LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be

4.7K/J_4

4.7K/J_4

pulled down with 4.7K

+5V

<20100128(B2A)>
Change L30,L31,L32 from CX8LL680001 to CX08T470004

R244

R244

R245

R245

R243

R243

C308

140/F_4

140/F_4

150/F_4

150/F_4

<Layout note>
Close to CONN

U10

U10

VCC_SYNC

SYNC_OUT2

SYNC_OUT1
VCC_DDC
BYP

VCC_VIDEO

VIDEO_1
VIDEO_2
VIDEO_3

GND

IP4772_Rout=10ohm

IP4772_Rout=10ohm

DDC_OUT1
DDC_OUT2

150/F_4

150/F_4

SYNC_IN2
SYNC_IN1

DDC_IN1
DDC_IN2

C308
10P/50V_4

10P/50V_4

16
14

15
13

10
11

9
12

4

LCD POWER SWITCH(LDS)

D28 *5.5V/25V/410P_4D28 *5.5V/25V/410P_4

1 2

LID# <25>

INT_LVDS_BLON <8>

EC_FPBACK# <25>

F1

F1

SMD1206P100TF/1A/1.8A/6V

SMD1206P100TF/1A/1.8A/6V

<Layout note>
PLACE inductances 90 DEGREE FROM EACH OTHER

C306

C306
10P/50V_4

10P/50V_4

CRT_VSYNC1
CRT_HSYNC1

CRT_SCL
CRT_SDA

4

+5V_CRT

12

L31 3A/47ohm_6L31 3A/47ohm_6
L32 3A/47ohm_6L32 3A/47ohm_6
L30 3A/47ohm_6L30 3A/47ohm_6

C307

C307
10P/50V_4

10P/50V_4

R240 18/J_4R240 18/J_4
R241 18/J_4R241 18/J_4

CRT_VSYNC <8>
CRT_HSYNC <8>

<20090812(A1A)_46105_rs880_scl_nda_1.03>
CRT DDC are +5V tolerance

D25 SSM14D25 SSM14

VSYNC_R
HSYNC_R

LCDVCC_1

INT_LVDS_DIGON<8>

C2 0.1U/10V_4C2 0.1U/10V_4

C303

C303

C304

C304

10P/50V_4

10P/50V_4

10P/50V_4

10P/50V_4

L28 0.5A/22ohm_6L28 0.5A/22ohm_6
L29 0.5A/22ohm_6L29 0.5A/22ohm_6

R242

R242

4.7K/J_4

4.7K/J_4

CRT_SCL <8>

3

R38 *0/short_8R38 *0/short_8

C56

6
7

2
8
3
9
4

10

5

CRTVSYNC
CRTHSYNC

C56

0.1U/10V_4

0.1U/10V_4

+3V

6
4
3

R49

R49

4.7K/J_4

4.7K/J_4

Confirmed with AMD Horace
LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be
pulled down with 4.7K

<20100128(B2A)>
Change CN11(CRT CONN) from DFDS15FR138 to
DFDS15FR204.

1617

CN11

CN11

CRT_11

111

CRT_SDA

12
13

CRTVSYNC

14

CRT_SCL

15

CRT CONN

CRT CONN

C4 *10P/50V_4C4 *10P/50V_4
C300 *100P/50V_4C300 *100P/50V_4
C302 *100P/50V_4C302 *100P/50V_4
C1 *100P/50V_4C1 *100P/50V_4
C3 *100P/50V_4C3 *100P/50V_4

C55

C55

C70

C70

0.1U/10V_4

0.1U/10V_4

2.2U/6.3V_6

2.2U/6.3V_6

C74

C74

4.7U/10V_6

4.7U/10V_6

CRTVDD5

CRT_R1
CRT_G1
CRT_B1 CRTHSYNC

C305

C305
10P/50V_4

10P/50V_4

CRTVDD5

R3

4.7K/J_4R34.7K/J_4

CRT_SDA <8>

3

LCDVCC

C57

C57

0.01U/16V_4

0.01U/16V_4

U2

U2

IN
IN
ON/OFF

IC(5P) G5243AT11U

IC(5P) G5243AT11U

Irush=1.5A

C58

C58

2.2U/6.3V_6

2.2U/6.3V_6

OUT
GND
GND

T1T1

CRTVDD5
CRTVSYNC
CRTHSYNC
CRT_SCL
CRT_SDA

2

1

CAMERA POWER(CCD)

+3V

<20100309a(C3A)>
Reserve R375, for S3 hang up issue

<20100319a(RAMP)>
Delete R375 (no need)

R255 *0/short_6R255 *0/short_6

CCD_POWER

C309 10U/10V_8

C309 10U/10V_8
C311 1000P/50V_4C311 1000P/50V_4
C310 *0.1U/10V_4C310 *0.1U/10V_4

+

+

CCD_POWER

0.15A

LCD MODULE(LDS)

VIN

R32 *0/short_6R32 *0/short_6

4.7U/25V_8

1
2
5

USBP3-<11>

USBP3+<11>

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

<20091215(A1A)_Follow EMI's Suggest>
Change series component of DMIC_DAT from 33ohm to bead
Change series component of DMIC_CLK from 0ohm to bead

DMIC_DAT<19>

DMIC_CLK<19>

+3V

4.7U/25V_8

C27 *0.1U/10V_4C27 *0.1U/10V_4

C20 *0.1U/10V_4C20 *0.1U/10V_4

TXLCLKOUT-<8>
TXLCLKOUT+<8>

R259 4.7K/J_4R259 4.7K/J_4
R261 4.7K/J_4R261 4.7K/J_4

<EMI>

*220P/50V_4

*220P/50V_4

INT_LVDS_PWM<8>

CONTRAST<25>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

20mA*24pcs=480mA

V_BLIGHT

C39

C39

C49

C49

0.1U/50V_6

0.1U/50V_6

LCDVCC

+3V

CCD_POWER

DISPON
LCD_VADJ

TXLOUT2-<8>

TXLOUT2+<8>

TXLOUT1-<8>

TXLOUT1+<8>

TXLOUT0-<8>

TXLOUT0+<8>

LCD_CLK<8>
LCD_DATA<8>

<EMI>

L5

L5

L4 1A/470ohm_6L4 1A/470ohm_6

C313

C313

R40 *0/short_4R40 *0/short_4
R37 *0/J_4R37 *0/J_4
C51 *0.1U/10V_4C51 *0.1U/10V_4

TXLOUT2­TXLOUT2+

TXLOUT1­TXLOUT1+

TXLOUT0­TXLOUT0+

TXLCLKOUT­TXLCLKOUT+

LCD_CLK
LCD_DATA

+3V

1A/470ohm_6

1A/470ohm_6

LCD_CLK
LCD_DATA

C312

C312

*220P/50V_4

*220P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

CRT/LVDS

CRT/LVDS

CRT/LVDS

LCDVCC
LCDVCC

CCD_POWER

DMIC_DAT_CN
DMIC_CLK_CN

LCD_VADJ

LCD_VADJ

1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DMIC_CLK_CN

C52

C52

*68P/50V_4

*68P/50V_4

ZH9

ZH9

ZH9

16 40Sunday, March 28, 2010

16 40Sunday, March 28, 2010

16 40Sunday, March 28, 2010

CN1

CN1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

LCD CONN

LCD CONN

DMIC_DAT_CN

*68P/50V_4

*68P/50V_4

31

31

32

32

C53

C53

4A

4A

4A

5

4

3

2

1

HDMI HPD SENSE

(HDM)

Close to HDMI Connector

R27 HDM@715/F_4R27 HDM@715/F_4

D D

+5V

HDM@2N7002K

HDM@2N7002K

R28

R28

HDM@100K/F_4

HDM@100K/F_4 R252 HDM@0_4R252 HDM@0_4

3

Q3

Q3

2

1

R24 HDM@715/F_4R24 HDM@715/F_4
R23 HDM@715/F_4R23 HDM@715/F_4
R21 HDM@715/F_4R21 HDM@715/F_4
R20 HDM@715/F_4R20 HDM@715/F_4
R16 HDM@715/F_4R16 HDM@715/F_4
R251 HDM@715/F_4R251 HDM@715/F_4
R248 HDM@715/F_4R248 HDM@715/F_4

TX2_HDMI+
TX2_HDMI­TX1_HDMI+
TX1_HDMI­TX0_HDMI+
TX0_HDMI­TXC_HDMI+
TXC_HDMI-

+3V

R249

R249

HDM@10K/F_4

HDM@10K/F_4

INT_HDMI_HPD<8>

3

+3V

R247

R247
HDM@10K/F_4

HDM@10K/F_4

3

Q1

Q1

HDM@2N7002K

HDM@2N7002K

1

R10

2

R10

HDM@200K/F_4

HDM@200K/F_4

HDMI_DETHDMI_DET_R

R9

R9
HDM@200K/F_4

HDM@200K/F_4

Q2

Q2

C C

B B

A A

5

EMI reserve for HDMI(HDM) ESD Protect

Close connector

TX2_HDMI+

TX2_HDMI­TX1_HDMI+

TX1_HDMI­TX0_HDMI+

TX0_HDMI­TXC_HDMI+

TXC_HDMI-

R26

R26
*HDM@100/F_4

*HDM@100/F_4

R22

R22
*HDM@100/F_4

*HDM@100/F_4

R19

R19
*HDM@100/F_4

*HDM@100/F_4

R250

R250
*HDM@100/F_4

*HDM@100/F_4

4

HDMI_DDC_CLK
HDMI_DDC_DATA

HDMI_DET

TX0_HDMI+
TX0_HDMI-

TXC_HDMI+
TXC_HDMI-

TX2_HDMI+
TX2_HDMI-

TX1_HDMI+

close to HDMI connector

U11

U11

1

1

2

2

3

GND_3/8

4

4

5

5

*HDM@RClamp0524P

*HDM@RClamp0524P
U12

U12

1

1

2

2

3

GND_3/8

4

4

5

5

*HDM@RClamp0524P

*HDM@RClamp0524P
U14

U14

1

1

2

2

3

GND_3/8

4

4

5

5

*HDM@RClamp0524P

*HDM@RClamp0524P

10

9
7

6

10

9
7

6

10

9
7

6

TXC_HDMI+<7>
TXC_HDMI-<7>

3

HDMI_DDC_CLK

10

HDMI_DDC_DATA

9
7

6

10
9

7
6

10
9

7
6

HDMI_DET

TX0_HDMI+
TX0_HDMI-

TXC_HDMI+
TXC_HDMI-

TX2_HDMI+
TX2_HDMI-

TX1_HDMI+
TX1_HDMI-TX1_HDMI-

<20091215(A1A)_Follow EMI's suggestion>
add a common mode chock in HDMI CLK to
prevent AMD issue

<20100324(RAMP)>
Delete L1 and change R13,R14 to shortpad.

2

HDM@2N7002K

HDM@2N7002K

1

<20100115(B2A)>
Add F2(fuse) to meet IEC 60950-1
2nd certificationand.

+5V

<Layout note>
colse to HDMI connector

R14 *HDM@0/short_4R14 *HDM@0/short_4

R13 *HDM@0/short_4R13 *HDM@0/short_4

HDM@SMD1206P100TF/1A/1.8A/6V

HDM@SMD1206P100TF/1A/1.8A/6V

2

R246 HDM@0_4R246 HDM@0_4

F2

F2

12

TXC_HDMI+_R
TXC_HDMI-_R

HDMI_HPD_EC# <25>

HDMI PORT

CN12

CN12

TX2_HDMI+<7>
TX2_HDMI-<7>

TX1_HDMI+<7>
TX1_HDMI-<7>

TX0_HDMI+<7>
TX0_HDMI-<7>

HDMI_DDC_CLK<8>

HDMI_DDC_DATA<8>

<20100310(C3A)>
Delete D26(BC0SSM14Z21),
for HDMI certification

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

TX2_HDMI+
TX2_HDMI-

TX1_HDMI+
TX1_HDMI-

TX0_HDMI+
TX0_HDMI-

TXC_HDMI+_R
TXC_HDMI-_R

HDMI_DDC_CLK
HDMI_DDC_DATA

+5V_HDMI

HDMI_DET

C6

C6
HDM@0.22u/6.3V_4

HDM@0.22u/6.3V_4

HDMI_DDC_CLK
HDMI_DDC_DATA

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

HDMI

HDMI

HDMI

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

HDM@QJ1119C-NK01-8F

HDM@QJ1119C-NK01-8F

R12 HDM@4.7K/J_4R12 HDM@4.7K/J_4
R11 HDM@4.7K/J_4R11 HDM@4.7K/J_4

ZH9

ZH9

ZH9

17 40Sunday, March 28, 2010

17 40Sunday, March 28, 2010

17 40Sunday, March 28, 2010

1

SHELL1
SHELL3

SHELL4
SHELL2

20
22

23
21

+5V

4A

4A

4A

5

<20100303(C3A)>

KEYBOARD(KBC)

CN3

CN3

1
2

KB CONN

KB CONN

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25
26

D D

C C

MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15

MX7 <25>
MX6 <25>
MX5 <25>
MY0 <25>
MY1 <25>
MY2 <25>
MX4 <25>
MY3 <25>
MY4 <25>
MY5 <25>
MY6 <25>
MY7 <25>
MY8 <25>
MX3 <25>
MY9 <25>
MX2 <25>
MX1 <25>
MY10 <25>
MY11 <25>
MX0 <25>
MY12 <25>
MY13 <25> BT_POWERON#<25>
MY14 <25>
MY15 <25>

Change CP1~CP6 footprint from 8p4r-0402 to
8p4r-0402-smt, for SMT open issue.

<EMI>

MX7

7 8

MX6

5

MX5

3

MY0

1

MY1

7 8

MY2

5

MX4

3

MY3

1

MY4

7 8

MY5

5

MY6

3

MY7

1

MY8

7 8

MX3

5

MY9

3

MX2

1

MX1

7 8

MY10

5

MY11

3

MX0

1

MY12

7 8

MY13

5

MY14

3

MY15

1

0402 size

4

CP2

CP2

6

*220P_8P4R

*220P_8P4R

4
2

CP3

CP3

6

*220P_8P4R

*220P_8P4R

4
2

CP4

CP4

6

*220P_8P4R

*220P_8P4R

4
2

CP5

CP5

6

*220P_8P4R

*220P_8P4R

4
2

CP6

CP6

6

*220P_8P4R

*220P_8P4R

4
2

CP1

CP1

6

*220P_8P4R

*220P_8P4R

4
2

3

BLUETOOTH(BTM)

Q13

Q13

+3V

1

C267

C267
*BT@0.1U/10V_4

*BT@0.1U/10V_4

R207

R207

BT@10K/J_4

BT@10K/J_4

BT@AO3413

BT@AO3413

2

C261

C261
BT@0.1U/10V_4

BT@0.1U/10V_4

2

1

BT PWR LED

T77H056.00
T60H928.33

61mA

3

+

+

C260

C260
BT@0.22U/25V_6

BT@0.22U/25V_6

BT_POWER

C258

C258
BT@1000P/50V_4

BT@1000P/50V_4

USBP5+<11>

USBP5-<11>

C256

C256

*BT@0.1U/10V_4

*BT@0.1U/10V_4

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

+3V
+3V

C257

C257
*BT@0.1U/10V_4

*BT@0.1U/10V_4

CN7

CN7

1
2

7
3
456

BT@BT_CONN

BT@BT_CONN

TOUCH PAD(TPD)

+5V

3mA

<EMI>

+5V_TP

L9 3A/120ohm_8L9 3A/120ohm_8

B B

A A

CX121T30001:3A/120ohm_8

C136

C136

0.1U/10V_4

0.1U/10V_4

3
4
5
6

<20100126(B2A)>
Change L9 from CS00004JA40 to CX121T30001 and L7,L8
from CS00003J951 to CX08T121000, for RF issue.

TP switch

TP switch

SW3

SW3

5

+5V

1
2

CN2

CN2

TP_L#

1
2
3
4
567

8

TP_CONN

TP_CONN

<20100126(B2A)>
Change SW2,SW3 from DHP00AC1G00 to DHP00533K00, for SMT issue.

TP_L# TP_R#

12

D23

D23
*14V/38V/100P_4

*14V/38V/100P_4

TP_R#

+5V_TP

TPDATA_CN
TPCLK_CN

C135

C135

10P/50V_4

10P/50V_4

4

<EMI>

L8 0.4A/120ohm_6L8 0.4A/120ohm_6
L7 0.4A/120ohm_6L7 0.4A/120ohm_6

CX08T121000:0.4A/120ohm_6
CX121T04000:0.4A/120ohm_6

C134

C134
10P/50V_4

10P/50V_4

SW2

TP switch

TP switch

SW2

3
4
5
6

1
2

R104

R104

4.7K/J_4

4.7K/J_4

12

D24

D24
*14V/38V/100P_4

*14V/38V/100P_4

R101

R101

4.7K/J_4

4.7K/J_4

3

TPDATA <25>
TPCLK <25>

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

KB/BT/TP/LED/Power Connector

KB/BT/TP/LED/Power Connector

KB/BT/TP/LED/Power Connector

ZH9

ZH9

ZH9

4A

4A

4A

18 40Sunday, March 28, 2010

18 40Sunday, March 28, 2010

18 40Sunday, March 28, 2010

1

5

4

3

2

1

<Layout note>

AUDIO CODEC

LDO_OUT_3.3V

AVDD_3.3 pin is output of
internal LDO. Do NOT connect
to external supply.

C248

C248

C254

C254

0.1u/10V_4

0.1u/10V_4

10U/10V_8

10U/10V_8

ADOGND

1.03A ; peak:2.5A

+5V_ADO

R233 *0/short_8R233 *0/short_8

C284

C284

C278

C278

10U/10V_8

10U/10V_8

0.1u/10V_4

R226

R226

0.1/F_1206

0.1/F_1206

C275

C275

0.1u/10V_4

0.1u/10V_4

15

17

RPWR_5.0

CLASSDREF

SENSE_A

PORTB_R
PORTB_L

B_BIAS

C_BIAS
PORTC_R
PORTC_L

NC_DR

NC_DL
PORTA_R

PORTA_L

AVEE
FLY_N
FLY_P

EP_GND

41

ADOGND

<Layout note>
Place EMI components close to audio codec.

0.1u/10V_4

Layout Note: Path from +5V to LPWR_5.0 and
RPWR_5.0 must be very low resistance ( <0.01 ohms).

Place bypass caps very close to device.

CLASSD_5V

C269

C269

C271

C271

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

FLY_N
FLY_P

SENSE_A

MIC_BIAS
MIC1_R1
MIC1_L1

HPOUT-R
HPOUT-L

C270 1u/6.3V_4C270 1u/6.3V_4

36

35
34
33

32
31
30

25
24

23
22

21
20
19

<20100119(B2A)_FAE Request>
Change Pin41 from GND to AGND for thermal holes.

Recommended EMI components

L27 3A/120ohm_8L27 3A/120ohm_8

DCR:0.04ohm

L26 3A/120ohm_8L26 3A/120ohm_8

DCR:0.04ohm

C280

C280

C285

C285

1000P/50V_4

1000P/50V_4

1000P/50V_4

1000P/50V_4

+5V

<20100126(B2A)>
Change R234,R239 from 0ohm(CS00003J951) to 6.8ohm(CS-6803J900), for SPL

<20100323(RAMP)>
Change R234,R239 from 6.8ohm(CS-6803J900) to 6.8ohm(CS-6802FB00), for cost and shortage issue.

R234 6.8/F_4R234 6.8/F_4

SPK_R-

R237 *0/short_6R237 *0/short_6

SPK_R+
SPK_L-

R238 *0/short_6R238 *0/short_6

R239 6.8/F_4R239 6.8/F_4

SPK_L+

HPL

L22 1A/600ohm_6L22 1A/600ohm_6
L25 1A/600ohm_6L25 1A/600ohm_6

HPR

R230

R230

R217

R217

680P/50V_4

680P/50V_4

*1K/J_4

*1K/J_4

*1K/J_4

*1K/J_4

MIC_BIAS

R180 100/J_4R180 100/J_4

MIC1_L2

R184 100/J_4R184 100/J_4

MIC1_R2

<20100309(C3A)>
Change L18,L21 from 0ohm to CX08T601000, for EMI issue.

L18 1A/600ohm_6L18 1A/600ohm_6
L21 1A/600ohm_6L21 1A/600ohm_6

C244

C244
*470P/50V_4

*470P/50V_4

SPK_R-_CN

C291

C291
*47P/50V_4

*47P/50V_4

C294

C294
*1U/6.3V_4

*1U/6.3V_4

CN9

C298

C298
*1U/6.3V_4

*1U/6.3V_4

HPL_SYS

LINEOUT_JD#

12

D22

D22

*14V/38V/100P_4

*14V/38V/100P_4

ADOGND

R186

R186

2.2K/J_4

2.2K/J_4

1
2
6
3
4

5

BLACK

BLACK

Normal Open Jack

SPEAKER-CON

SPEAKER-CON

CN4

CN4

CN9

4
3

5

2

6

1

CN8

CN8

1
2
6
3
4

5

BLACK

BLACK

Normal Open Jack

7

8

C295

C295
*47P/50V_4

*47P/50V_4

SPK_R+_CN
SPK_L-_CN

C297

C297
*47P/50V_4

*47P/50V_4

C299

C299
*47P/50V_4

*47P/50V_4

SPK_L+_CN

<Layout note>20091223
follow EMI suggestion , modify PIN6 from dummy to ADOGND

C283

C283

C272

C272

680P/50V_4

680P/50V_4

ADOGND

R176

R176

2.2K/J_4

2.2K/J_4

MIC1_L3
MIC1_R3

<Layout note>20091223
follow EMI suggestion , modify PIN6 from dummy to ADOGND

MIC1_L4
MIC1_R4

MIC1_JD#

12

C227

C227

D21

D21

*14V/38V/100P_4

*14V/38V/100P_4

*470P/50V_4

*470P/50V_4

ADOGND

ADOGND

7

8

C279

C279
10U/10V_8

10U/10V_8

AVEE

C287

C287

0.1u/10V_4

0.1u/10V_4

SPK_R+

SPK_R-

SPK_L-

SPK_L+

C286

C286

1000P/50V_4

1000P/50V_4

C281

C281
10U/10V_8

10U/10V_8

JACK DETECT RESISTORS

Sense resistor 5.11K must be connected to
same power supply that is used for
VAUX_3.3 pins.

LINEOUT_JD#
MIC1_JD#

SENSE_A

+3V_ADO

SENSE PIN A

R174

R174

5.11K/F_4

5.11K/F_4

R182 39.2K/F_4R182 39.2K/F_4
R178 10K/F_4R178 10K/F_4

Port Configuration

Port A: Headphone jack (jack shared with S/PDIF)
Port B: Internal analog mono mic (stereo option)/Line In
Port C: Microphone jack
Port D: LineOut jack(need cap) or Headphone jack(cap less)
Port G: Internal stereo speakers
Port J: Optional Internal stereo digital mic
Port H: S/PDIF (jack shared with headphone)

C289

C289
10U/10V_8

10U/10V_8

R172 *0/short_6R172 *0/short_6
R183 *0/short_6R183 *0/short_6
R385 *0/short_6R385 *0/short_6

R415 *0/short_4R415 *0/short_4
R416 *0/short_4R416 *0/short_4

R417 *0/short_4R417 *0/short_4
R418 *0/short_4R418 *0/short_4

C288

C288

1000P/50V_4

1000P/50V_4

R419 *0/short_4R419 *0/short_4
R420 *0/short_4R420 *0/short_4

ADOGND

<20100309(C3A)>
Delete R380,R375 ; Chagne C415,C290 to R415,R416(0ohm),
Stuff R172,R183,R385, Add R417~R420(0ohm), for EMI issue.

<20100311(C3A)>
Change R415,R417 to shortpad, for layout issue

<20100324(RAMP)>
Change R172,R183,R385,R416,R418~R420 to shortpad.

Speaker (AMP)

Earphone(AMP)

<20100309(C3A)>
Change L22,L25 from 0ohm to CX08T601000, C272,C283 to CH1686K9B00, for EMI issue.

HPOUT-L

R223 39/J_4R223 39/J_4
R227 39/J_4R227 39/J_4

HPOUT-R HPR_SYS

<20100309(C3A)>
Change R223,R227 from 5.1ohm(CS-5102JB03)
to 39ohm(CS03902JB21), for FSOV spec

System MIC(AMP)

C229 2.2U/6.3V_6C229 2.2U/6.3V_6

MIC1_L1

C231 2.2U/6.3V_6C231 2.2U/6.3V_6

MIC1_R1

MIC1_L3
MIC1_R3

C241

C241
1u/6.3V_4

1u/6.3V_4

FILT_1.8V

U8

RESET#

BIT_CLK
SYNC
SDATA_IN
SDATA_OUT

PC_BEEP
SPDIF
GPIO0/EAPD#

GPIO1/SPK_MUTE#

DMIC_CLK
DMIC_1/2

FILT_1.65V

C240

C240

0.1u/10V_4

0.1u/10V_4

3

FILT_1.8

2

11

ACZ_RST#_AUDIO<11>

SPK_MUTE#

+3V_ADO

50mA

C234

C234
1u/6.3V_4

1u/6.3V_4

ACZ_BITCLK_AUDIO<11>

ACZ_SYNC_AUDIO<11>

ACZ_SDOUT_AUDIO<11>

C253

C253

0.1u/10V_4

0.1u/10V_4

<20100119(B2A)_For ESDissue>
Add D38 for ESD issue

ACZ_SDIN0<11>

DMIC_CLK<16>

DMIC_DAT<16>

R167 *0/short_4R167 *0/short_4

+3V_ADO

D38

D38

1 2

5.5V/25V/410P_4

5.5V/25V/410P_4

SB_BEEP<11>

+3V_ADO

C230

C235

C235
10U/10V_8

10U/10V_8

C230
10U/10V_8

10U/10V_8

C259

C259

C276

C276

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

Note:

To support Wake-on-Jack, the CODEC VAUX_3.3 pins
must be powered by a Standby supply.

10K only needed if supply to VAUX_3.3 is

C238

C238

removed during system re-start.

0.1u/10V_4

0.1u/10V_4

R189

R189
10K_4

10K_4

Use as needed for EMI.

C252 *22p/50V_4C252 *22p/50V_4

D12*BAS316 D12*BAS316

D18*BAS316 D18*BAS316

D11*BAS316 D11*BAS316

R206 *0/short_4R206 *0/short_4
R204 33/J_4R204 33/J_4

R216 33/J_4R216 33/J_4

ACZ_RST#_AUDIO

EAPD#

AMP_MUTE#

C247 *22p/50V_4C247 *22p/50V_4

R185 100/J_4R185 100/J_4

AMP_MUTE# <25>

ACZ_BCLK_CODEC
ACZ_SDIN0_CODEC

C268 0.1u/10V_4C268 0.1u/10V_4

EAPD#
SPK_MUTE#

C246

C246

10U/10V_8

10U/10V_8

C265 *22p/50V_4C265 *22p/50V_4

DMIC_CLK_CH

ADOGND

C243

C243

0.1u/10V_4

0.1u/10V_4

9

5
8
6
4

10
39
38

37

40

1

D D

+3V +3V_ADO

R181 *0/short_6R181 *0/short_6

C C

B B

A A

7

VDD_IO

VAUX_3.3

LEFT+

18

DVDD_3.3

CX20672-11ZU8CX20672-11Z

LEFT-13RIGHT-

SPK_L-_CH

SPK_L+_CH

27

29

28

FILT_1.65

AVDD_HP26AVDD_3.3

RIGHT+

14

16

L24 3A/120ohm_8L24 3A/120ohm_8

L23 3A/120ohm_8L23 3A/120ohm_8

LDO_OUT_3.3V

12

AVDD_5V

LPWR_5.0

SPK_R+_CH

SPK_R-_CH

DCR:0.04ohm

DCR:0.04ohm

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

AUDIO CODEC CX20672

AUDIO CODEC CX20672

AUDIO CODEC CX20672

1

ZH9

ZH9

ZH9

4A

4A

4A

of

of

of

19 40Sunday, March 28, 2010

19 40Sunday, March 28, 2010

19 40Sunday, March 28, 2010

5

USB(USB)

+5VPCU

+3VPCU

*10K/J_4

*10K/J_4

USB_EN#<25>

D D

+5VPCU

C C

R140

R140

C165

C165

4.7U/10V_6

4.7U/10V_6

USB_EN#

C362

C362

4.7U/10V_6

4.7U/10V_6

USB_EN#

U19

U19
IC(8P)G547 E2P81U

IC(8P)G547 E2P81U

2

IN1
IN23OUT2

4

EN#

1

GND

9

GND-C

U17

U17
IC(8P)G547 E2P81U

IC(8P)G547 E2P81U

2

IN1
IN23OUT2

4

EN#

1

GND

9

GND-C

OUT3
OUT1

2A

5VUSB_MB

8

OUT3

7
6

OUT1

5

OC#

2A

5VUSBPW R

8
7
6

5

OC#

4

<Layout note>

USBOC#L <11>

USBP0-<11>
USBP0+<11>

<20100324(RAMP)>
Delete L6,L11,L47 and change
R360,R361,R96,R99,R116,R118 to shortpad.

USBOC#R <11>

USBP6-<11>
USBP6+<11>

USBP7-<11>
USBP7+<11>

Co-lay

R360 *0/short_4R360 *0/short_4

R361 *0/short_4R361 *0/short_4

<Layout note>
Co-lay

R96 *0/short_4R9 6 *0/short_4

R99 *0/short_4R9 9 *0/short_4

<Layout note>
Co-lay

R116 *0/short_4R116 *0/short_4

R118 *0/short_4R118 *0/short_4

+

+

USBP0-_CN
USBP0+_CN

C222

C222

C223

USBP6-_CN
USBP6+_CN

C118

C118

USBP7-_CN
USBP7+_CN

C154

C154

5VUSBPW R

C223
*0.1U/10V _4

*0.1U/10V _4

C128

C128
*0.1U/10V _4

*0.1U/10V _4

C158

C158
*0.1U/10V _4

*0.1U/10V _4

*0.1U/10V _4

*0.1U/10V _4

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

*0.1U/10V _4

*0.1U/10V _4

*0.1U/10V _4

*0.1U/10V _4

<Layout note>
Close to CONN

C405

C405
100U/6.3V_3528

100U/6.3V_3528

12

D30

D30
*5V/30V/0.2P_4

*5V/30V/0.2P_4

+

+

C330

C330
100U/6.3V_3528

100U/6.3V_3528

12

D4

D4
*5V/30V/0.2P_4

*5V/30V/0.2P_4

+

+

C394

C394
100U/6.3V_3528

100U/6.3V_3528

12

D6

D6
*5V/30V/0.2P_4

*5V/30V/0.2P_4

3

2

1

EMI(EMC)

C290

C290

VIN_SRC +3V

0.1U/10V_4

0.1U/10V_4

C176

C176

0.1U/10V_4

0.1U/10V_4

CN17

CN17

1

VDD

2

D-

3

D+

4

12

D29

D29
*5V/30V/0.2P_4

*5V/30V/0.2P_4

C133

C133

0.1U/10V_4

0.1U/10V_4

12

D5

D5
*5V/30V/0.2P_4

*5V/30V/0.2P_4

C161

C161

0.1U/10V_4

0.1U/10V_4

12

D7

D7
*5V/30V/0.2P_4

*5V/30V/0.2P_4

GND1

USB_CONN

USB_CONN

<20100128(B2A)>
Change CN14,16,17(USB CONN) from DFHS04FR201
to DFHS04FR362.

<20100303(C3A)>
Change back CN14,16,17(USB CONN) to DFHS04FR201.

CN14

CN14

1

VDD

2

D-

3

D+

4

GND1

USB_CONN

USB_CONN

CN16

CN16

1

VDD

2

D-

3

D+

4

GND1

USB_CONN

USB_CONN

Left

GND6
GND5

GND7
GND8

Upper Right

GND6
GND5

GND7
GND8

Lower Right

GND6
GND5

GND7
GND8

<20100309(C3A)>
Add C290, for RF issue

+3VPCU +3VPCU

C471

6
5

7
8

6
5

7
8

6
5

7
8

C471

0.1U/10V_4

0.1U/10V_4

+3VPCU +3VPCU +3VPCU +3VPCU +3V PCU

C474

C474

0.1U/10V_4

0.1U/10V_4

+5VPCU +5VPCU +5VPCU +5VPCU +5V PCU

C484

C484

0.1U/10V_4

0.1U/10V_4

+5V +5V +5V +5V +5V

C489

C489

0.1U/10V_4

0.1U/10V_4

+5V +5V +5V +5V +5V

C494

C494

0.1U/10V_4

0.1U/10V_4

+3V +3V +3V +3V

C504

C504

0.1U/10V_4

0.1U/10V_4

<20100310(C3A)>
Add some 0.1uF to connect power plane, for RF issue.

+3VPCU

C472

C472

0.1U/10V_4

0.1U/10V_4

C475

C475

0.1U/10V_4

0.1U/10V_4

+5VPCU +5VPCU

C485

C485

0.1U/10V_4

0.1U/10V_4

C490

C490

0.1U/10V_4

0.1U/10V_4

C495

C495

0.1U/10V_4

0.1U/10V_4

<20100324(RAMP)>
Non-stuff C506, for interference issue

C505

C505

0.1U/10V_4

0.1U/10V_4

<20100324(RAMP)>
Delete C479,C480,C483, for ASSY issue.

C473

C473

0.1U/10V_4

0.1U/10V_4

C476

C476

C477

C477

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C481

C481

C482

C482

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C487

C487

C486

C486

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C492

C492

C491

C491

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C496

C496

C497

C497

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C507

C507

C506

C506

0.1U/10V_4

0.1U/10V_4

*0.1U/10V _4

*0.1U/10V _4

C478

C478

0.1U/10V_4

0.1U/10V_4

C488

C488

0.1U/10V_4

0.1U/10V_4

C493

C493

0.1U/10V_4

0.1U/10V_4

C498

C498

0.1U/10V_4

0.1U/10V_4

HOLE(OTH)

HOLE24

HOLE24

HG-TC236BC276D130P2

HG-TC236BC276D130P2

2
3

B B

4

1

8

HOLE22

HOLE22

*HG-C276D9 4P2

*HG-C276D9 4P2

2

5

3

6

4

7

1

8

9

HOLE25

HOLE25

*hg-tc252be225x276d94p2

*hg-tc252be225x276d94p2

2

5

3

6

4

7

1

8

HOLE7

HOLE7

*HG-C276D9 4P2

*HG-C276D9 4P2

2

5

3

6

4

7

1

8

9

A A

HOLE8

HOLE8

*HG-TE354X3 15BC276 D94P2

*HG-TE354X3 15BC276 D94P2

2

5

3

6

4

7

1

8

9

HG-TC236BC276D130P2

HG-TC236BC276D130P2

5
6
7

9

*HG-C276D9 4P2

*HG-C276D9 4P2

2
3
4

*HG-C276D9 4P2

*HG-C276D9 4P2

2
3
4

*HG-C276D9 4P2

*HG-C276D9 4P2

2
3
4

*HG-TE335X2 56BC276 D94P2

*HG-TE335X2 56BC276 D94P2

2
3
4

TOP(HDD Hole)

HOLE18

HOLE18

2

5

3

6

4

7

1

8

9

HOLE17

HOLE17

5
6
7

1

8

9

HOLE34

HOLE34

5
6
7

1

8

9

HOLE23

HOLE23

5
6
7

1

8

9

HOLE15

HOLE15

5
6
7

1

8

9

5

HOLE33

HOLE33

*HG-C276D9 4P2

*HG-C276D9 4P2

2

5

3

6

4

7

1

8

9

HOLE9

HOLE9

*HG-TE315X2 95BC276 D94P2

*HG-TE315X2 95BC276 D94P2

2

5

3

6

4

7

1

8

9

HOLE14

HOLE14

*HG-TC276BC2 56D94P2

*HG-TC276BC2 56D94P2

2

5

3

6

4

7

1

8

9

HOLE6

HOLE6

*HG-TE354X3 15BC276 D94P2-1

*HG-TE354X3 15BC276 D94P2-1

2

5

3

6

4

7

1

8

9

HOLE5

HOLE5

*HG-TE295X2 87BC276 D94P2

*HG-TE295X2 87BC276 D94P2

2

5

3

6

4

7

1

8

9

HOLE10

HOLE10

*HG-TE354X2 93BC276 D94P2

*HG-TE354X2 93BC276 D94P2

2
3
4

1

8

9

HOLE32

HOLE32

*HG-C276D9 4P2

*HG-C276D9 4P2

2
3
4

1

8

9

HOLE31

HOLE31

*HG-C276D9 4P2

*HG-C276D9 4P2

2
3
4

1

8

9

<20100119(B2A)_ME Request>
Change Hole30 to NPTH
<20100122(B2A)>
Change all Hole's footprint for
<20100125(B2A)>
Change Hole's footprint (HOLE12,HOLE25,HOLE1,HOLE2,HOLE20,PAD1) ; Delete HOLE3,HOLE4
<20100126(B2A)>
Change Hole's footprint (HOLE12)
<20100128(B2A)>
Change PAD2,Hole5,Hole12 footprint ; add two holes (Hole35,Hole36)
<20100129(B2A)>
Update Hole13,19,25~29 footprint.
<20100201(B2A)>
Delete the GND of Hole11 ; add a nut(MBFJ6002010) on Hole26 on BOT side.
<20100309(B2A)>
Change Hole26 footprint to HG-TC236BC256D150P2

BOT
(Mini-PCIe Hole)

5
6
7

5
6
7

5
6
7

HOLE28

HOLE28
H-TC197BC157D106P2

H-TC197BC157D106P2

1

HOLE27

HOLE27
H-TC197BC157D106P2

H-TC197BC157D106P2

1

HOLE29

HOLE29
H-TC197BC157D106P2

H-TC197BC157D106P2

1

󱅁󵉴

4

BOT(Thermal Hole)

HOLE19

HOLE19
H-TC197BC157D126P2

H-TC197BC157D126P2

1

HOLE21

HOLE21

HG-TC197BC295D126P2

HG-TC197BC295D126P2

2

5

3

6

4

7

1

8

9

HOLE13

HOLE13
H-TC197BC157D126P2

H-TC197BC157D126P2

1

HOLE12

HOLE12

hg-tc276b e305x295d 126p2

hg-tc276b e305x295d 126p2

2

5

3

6

4

7

1

8

9

HOLE26

HOLE26

HG-TC236BC256D150P2

HG-TC236BC256D150P2

2

5

3

6

4

7

1

8

9

HOLE30

HOLE30
*H-O106X8 7D106X8 7N

*H-O106X8 7D106X8 7N

1

HOLE16

HOLE16
*o-zh9-1

*o-zh9-1

1

HOLE20

HOLE20
*O-ZH9-2

*O-ZH9-2

1

HOLE11

HOLE11
*H-C87D87N

*H-C87D87N

1

3

HOLE35

HOLE35
*H-C118D11 8N

*H-C118D11 8N

1

HOLE36

HOLE36
*H-C118D11 8N

*H-C118D11 8N

1

HOLE2

HOLE2
*hg-te799x646be799x42 1d94p2

*hg-te799x646be799x42 1d94p2

1
2
3

45678

9

HOLE1

HOLE1
*hg-e768x39 4d94p2

*hg-e768x39 4d94p2

1
2
3
4
5

678

9

10111213161817141519202122

101112

PAD1

PAD1

*emipad394 X752np

*emipad394 X752np

1

PAD2

PAD2

*emipad394 X752np

*emipad394 X752np

1

18
17
16

13

14

15

27
26
25
24
23

+1.5V +1.5 V +1.5V +1.5V

C515

C515

0.1U/10V_4

0.1U/10V_4

VIN VIN

C522

C522

0.1U/10V_4

0.1U/10V_4

VIN VIN VIN VIN VIN

C524

C524

0.1U/10V_4

0.1U/10V_4

2

C516

C516

0.1U/10V_4

0.1U/10V_4

C523

C523

0.1U/10V_4

0.1U/10V_4

C525

C525

0.1U/10V_4

0.1U/10V_4

C517

C517

C518

C518

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

C527

C527

C526

C526

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

0.1U/10V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

USB on Board/LED/SW/HOLE

USB on Board/LED/SW/HOLE

USB on Board/LED/SW/HOLE

C528

C528

0.1U/10V_4

0.1U/10V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZH9

ZH9

ZH9

20 40Sunday, March 28, 2010

20 40Sunday, March 28, 2010

20 40Sunday, March 28, 2010

1

4A

4A

4A

VDDCT_REG

C37

C37

0.1U/16V_4

0.1U/16V_4

33P/50V_4C43 33P/50V_4C43

Y1

Y1

25MHz-LAN

25MHz-LAN

33P/50V_4C44 33P/50V_4C44

5

<Layout note>
Close to Pin40

C47

C47
52SWR@0.1U/16V_4

52SWR@0.1U/16V_4

R35 *52LDO@0/J_6R35 *52LDO@0/J_6

12

C48

C48
*52LDO@1U/10V_4

*52LDO@1U/10V_4

C67

C67

1 2

*3P/50V_4

*3P/50V_4

2 1

<20100303(C3A)_FAE's suggestion>
Change L3 from CV-4710MN03 to CV-4710TZ01.

L3 52SWR@4.7uH/1AL3 52SWR@4.7uH/1A

DCR:0.15ohm

C30

C30
52SWR@10U/10V_8

52SWR@10U/10V_8

VDDCT

XTLI_LAN

XTLO_LAN
XTLI_LAN

<20100129(B2A)>
Non-stuff Y1,C43,C44 ; Stuff C67. Change the value of C43,C44 from
27pF to 33pF. (CLK for LAN from crystal change to internal CLK.)

<20100310(C3A)>
Stuff Y1,C43,C44 ; Non-Stuff C67. (14M_25M_48M_OSC is S0 plane,
doesn't support WoL.)

<BOM note>
If center tap power come from internal switch regulator
=>Stuff 52SWR@ (Default)
If center tap power come from internal LDO
=>Stuff 52LDO@

C46

D D

C C

C46

52SWR@1000P/50V_4

52SWR@1000P/50V_4

CLK_25M_LAN<10>

4

C69

C69
10U/10V_8

10U/10V_8

AVDDL

<Layout note>
Close to LAN Chip
1nF reserved for EMI

43

RN2

RN2

49.9/F_4P2R

49.9/F_4P2R

1 2

C18

C18

*1000P/50V_4

*1000P/50V_4

<Layout note>
Close to Pin1

12

C45

C45

1U/10V_4

1U/10V_4

PCIE_WAKE#<11,23>

12

C41

C41
1U/10V_4

1U/10V_4

+3V_S5 +3V_LAN

LX

76.1mA ; 30mil

R36 *0/short_6R36 *0/short_6

Int. PU in SB

20mil

VDDCT

C40

C40

0.1U/16V_4

0.1U/16V_4

20mil

AVDDH

12

C33

C33

C34

C34

1U/10V_4

1U/10V_4

0.1U/16V_4

0.1U/16V_4

C21

C21

0.1U/16V_4

0.1U/16V_4

3

C36

C36

0.1U/16V_4

0.1U/16V_4

PLTRST#<10,23,24>

20mil

C42

C42

0.1U/16V_4

0.1U/16V_4

R29 2.37K/F_4R29 2.37K/F_4

43

1 2

C14

C14

0.1U/16V_4

0.1U/16V_4

*1000P/50V_4

*1000P/50V_4

C28

C28

1000P/50V_4

1000P/50V_4

VDDCT_REG

XTLO_LAN
XTLI_LAN

TX0P
TX0N

TX1P
TX1N

RN1

RN1

49.9/F_4P2R

49.9/F_4P2R

C15

C15

RBIAS

U1

U1

1

VDD33

2

PERSTn

3

WAKEn

4

VDDCT_REG

5

VDDCT

6

AVDDL_REG

7

XTLO

8

XTLI

9

AVDDH_REG

10

RBIAS

11

TRXP0

12

TRXN0

13

NC

14

TRXP1

15

TRXN1

16

NC

17

NC

18

NC

19

NC

20

NC

21

NC

AR8152-AL1A-RL

AR8152-AL1A-RL

2

Power Sequence:
VDD33 to PERSTn >= 100ms

CLKREQn

AR8152

AR8152

5X5mm

5X5mm

40-Pin QFN

40-Pin QFN

AR8152-A : w/o 802.3az
AR8152-B : w/ 802.3az

SMDATA

TESTMODE

TEST_RST

REFCLK_N
REFCLK_P

DVDDL_REG

AVDDH

DVDDL

SMCLK

TX_N
TX_P

AVDDL

AVDDL

RX_P

RX_N

LED0
LED1

GND

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

LX

41

+3V_S5

R413

R413
*4.7K/J_4

*4.7K/J_4

R412 *0/short_4R412 *0/short_4

SMBUS for debug only

R15 4.7K/J_4R15 4.7K/J_4

PCIE_RXN0_LAN
PCIE_RXP0_LAN

LAN_ACTLED
LAN_LINKLED#
LX

40mil

AVDDH

C9

C9

0.1U/16V_4

0.1U/16V_4

<20100303(C3A)>
Reserve R413,R414, for e-fuse.

DVDDL

C8

C8

0.1U/16V_4

0.1U/16V_4

+3V_LAN

C7 0.1u/10V_4C7 0.1u/10V_4
C10 0.1u/10V_4C10 0.1u/10V_4

CLK_PCIE_LANN <10>
CLK_PCIE_LANP <10>

PCIE_TXP0 <7>
PCIE_TXN0 <7>

C19

C19

0.1U/16V_4

0.1U/16V_4

C11

C11

0.1U/16V_4

0.1U/16V_4

C13

C13

0.1U/16V_4

0.1U/16V_4

DVDDL

12

C16

C16
1U/10V_4

1U/10V_4

1

PU in CLK Gen.

R414

R414
*1K/J_4

*1K/J_4

PCIE_RXN0 <7>
PCIE_RXP0 <7>

AVDDL

20mil

CLKREQ_LAN# <11>

VDD33

+1.1V analog power

+3V_S5

+1.1V digital power
+2.7V analog power

B B

+1.7V analog power

1
31/34
24
22
5

AVDDL
DVDDL
AVDDH
VDDCT

ATHEROS

AR8152

AVDDL_REG
AVDDH_REG
DVDDL_REG
VDDCT_REG

6

+1.1V regulator output (For all the analog 1.1V supply pins)

9

+2.7V regulator output (Connected to pin 22)

37

+1.1V regulator output (For all the digital 1.1V supply pins)

4

LX

+1.8V regulator output (For VDDCT when LDO mode)

40

+1.7V Switching regulator (For VDDCT when switching mode)

RJ45

TRANSFORMER

U13

U13

TX1N

8

TD-

7

TD+

6

CT

5

NC

4

NC

3

CT

2

RD­RD+1RX+

NS0014 LF_Bothhand

NS0014 LF_Bothhand

TX-

TX+

CT
NC
NC
CT

RX-

VDDCT

L2 *0/short_6L2 *0/short_6

CX8EG601000: 0.5A/600ohm_6

C22

C22

1U/6.3V_4

1U/6.3V_4

AVDD_CEN

0.1U/16V_4C24 0.1U/16V_4C24
*1000P/50V_4C26 *1000P/50V_4C26

0.1U/16V_4C23 0.1U/16V_4C23
*1000P/50V_4C25 *1000P/50V_4C25

TX1P

TX0N
TX0P

1nF reserved for EMI

A A

5

4

9
10
11
12
13
14
15
16

C12

C12

1000P/3KV_1808

1000P/3KV_1808

X-TX1N
X-TX1P

TERM0

TERM1

X-TX0N
X-TX0P

TERM9

R18

R18
75/F_8

75/F_8

R17

R17
75/F_8

75/F_8

R25 5.1K/J_8R25 5.1K/J_8

R30 *52LDO@5.1K/J_8R30 *52LDO@5.1K/J_8

3

Active LED Pin:
Non-overclocking=>active high

C54 *0.1u/50V_8C54 *0.1u/50V_8

LINK LED Pin:
SWR mode=>active low
LDO mode=>active high

LAN_ACTLED

LAN_LINKLED#

LAN_LINKLED#

+3V_S5

LAN_ACTLED

<20100125(B2A)>
Connect pin4,5,7,8 of CN10 to net
TERM9, for EMI and Safety issue

R7 *52LDO@0/J_8R7 *52LDO@0/J_8
R6 52SWR@510/J_6R6 52SWR@510/J_6

R5 *52LDO@510/J_6R5 *52LDO@510/J_6
R4 *52SWR@0/short_8R4 *52SWR@0/short_8

2

CN10

CN10

12

R8 510/J_6R8 510/J_6C17 *0.1u/50V_8C17 *0.1u/50V_8

TERM9

X-TX1N

TERM9

X-TX1P
X-TX0N
X-TX0P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Y-

10

Y+

8

NC4/3-

7

NC/3+

6

RX-/1-

5

NC2/2-

4

NC1/2+

3

RX+/1+

2

TX-/0-

1

TX+/0+

11

G-

9

G+

RJ45-CONN

RJ45-CONN

LAN AR8152L

LAN AR8152L

LAN AR8152L

<20100125(B2A)>
Change CN10 from DFTJ12FR069(SUY) to
DFTJ12FR066(FOX), for SMT issue.

14

GND

13

GND

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

ZH9

ZH9

ZH9

4A

4A

21 40Sunday, March 28, 2010

21 40Sunday, March 28, 2010

21 40Sunday, March 28, 2010

4A

5

CN21

2.5" SATA HDD(HDD)

D D

CN21

SATA CONN

SATA CONN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C459

C459

0.1U/10V_4

0.1U/10V_4

4

SATA_TXP0 <12>
SATA_TXN0 <12>

SATA_RXN0 <12>
SATA_RXP0 <12>

1A

5V_SATA

C460

C460
*0.1U/10V_4

*0.1U/10V_4

C296

C296
10U/10V_8

10U/10V_8

+

+

R236 *0/short_8R236 *0/short_8

C461

C461
100U/6.3V_3528

100U/6.3V_3528

3

<20100115(B2A)>
Change TX and RX pairs pin define for HDD can not be recognized.

+5V

<20100303(C3A)>
Swap U23's pin1 and pin3, pin4 and pin6, for layout issue.

<Layout note>
Close to CONN

U23

U23
*CM1213-04SO

SATA_TXN0

SATA_TXP0

*CM1213-04SO

1

CH1

2

VN
CH23CH3

CH4

SATA_RXP0

6
5

VP

SATA_RXN0

4

+5V

2

1

C C

<20091214(A1A)_Confirm with Acer Johnson_Yeh>

LED/SW(UIF)

+3V

CAPS LED

NUM LED

B B

HDD LED

3G LED

WLAN LED

A A

BT LED

The JV01_NL and SJV01_NL had 4 LEDs --> Power / Battery / HDD / Communication

<20100203(B2A)>
Change R401 from CS13302JB21 to CS12702JB14
Change R402 from CS13302JB21 to CS14702JB28
Change R403 from CS13302JB21 to CS11202JB21
Change R404,R406 from CS13302JB21 to CS15602JB19
Change R405,R407 from CS13302JB21 to CS13602JB13
For LED's light issue.

<20100326(RAMP)>
Change R401 from CS12702JB14 to CS13302JB21
Change R404,R406 from CS15602JB19 to CS14702JB28
Change R403 from CS11202JB21 to CS12702JB14
Change R405,R407 from CS13602JB13 to CS12702JB14
For LED's light issue.

LED6

LED6

3 1

LED_BULE

LED_BULE

LED5

LED5

23

LED_AMBER/BLUE

LED_AMBER/BLUE

1

ID(Left-->Right)

R401 330/J_4R401 330/J_4

D31 *5.5V/25V/410P_4D31 *5.5V/25V/410P_4

1 2

D33 *3G@5.5V/25V/410P_4D33 *3G@5.5V/25V/410P_4

1 2

R403 3G@270/J_4R403 3G@270/J_4
R402 470/J_4R402 470/J_4

D32 *5.5V/25V/410P_4D32 *5.5V/25V/410P_4

1 2

SATALED# <12>

3G_LED# <23>

RF_LED# <23>

<LED spec>

󶁪

BLUE
Vf = 2.7~3.2V 󶁫 If = 5mA
BLUE/ORANGE
BH→Vf = 2.7~3.7V 󶁫 If = 20mA max=25mA
S2→Vf = 1.7~2.4V

PWR indicator

PWR LED

SUS LED

FULL LED

CHG LED

󶁪

󶁫

If = 20mA max=25mA

+3V_S5

+3VPCU

+3V

LED2

LED2

2 1

LED_BLUE

LED_BLUE

LED1

LED1

2 1

LED_BLUE

LED_BLUE

LED3

LED3

LED_AMBER/BLUE

LED_AMBER/BLUE

LED4

LED4

LED_AMBER/BLUE

LED_AMBER/BLUE

3
5

6

power switch

power switch

R2 330/J_4R2 330/J_4

R1 330/J_4R1 330/J_4

23
1

23
1

Power LED/BATT LED/HDD LED/WiFi LED

5

4

3

2

<20100125(B2A)>
Change SW1 from DHP00AC1G00 to DHP00533K00, for SMT issue.

SW1

SW1

2
14

12

D37 *5.5V/25V/410P_4D37 *5.5V/25V/410P_4

1 2

R407 270/J_4R407 270/J_4
R406 470/J_4R406 470/J_4

D36 *5.5V/25V/410P_4D36 *5.5V/25V/410P_4

1 2

D35 *5.5V/25V/410P_4D35 *5.5V/25V/410P_4

1 2

R405 270/J_4R405 270/J_4
R404 470/J_4R404 470/J_4

D34 *5.5V/25V/410P_4D34 *5.5V/25V/410P_4

1 2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

NBSWON#

D1

D1

5.5V/25V/410P_4

5.5V/25V/410P_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SATA HDD/LED/SW

SATA HDD/LED/SW

SATA HDD/LED/SW

NBSWON# <25>

PWRLED# <25>
SUSLED# <25>

BATLED0# <25>
BATLED1# <25>

ZH9

ZH9

ZH9

1

22 40Sunday, March 28, 2010

22 40Sunday, March 28, 2010

22 40Sunday, March 28, 2010

4A

4A

4A

5

Mini Card(MPC)

R369 0/J_4R369 0/J_4
R370 0/J_4R370 0/J_4

MINI1_WAKE#

+3V_Mini1_VDD

PCIE_WAKE#<11,21>

P80_CLK
SDP_VIS

CLK_PCIE_MPC_P<10>
CLK_PCIE_MPC_N<10>

P80_DAT

+3V_Mini1_VDD

PCIRST#<10>
LCLK_DEBUG<10>

CLKREQ_MPC#<10>

3

PCIE_TXP1<7>
PCIE_TXN1<7>

PCIE_RXP1<7>
PCIE_RXN1<7>

Q19

Q19

*2N7002K

*2N7002K

2

R388 *10K/J_4R388 *10K/J_4

1

P80_CLK<25>
SDP_VIS<25>

D D

P80_DAT<25>

C C

CN19

CN19

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

MINI-CARD1

MINI-CARD1

53

+3.3V

GND

+1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

W_DISABLE#

GND

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V

GND

+3.3V

GND54GND

4

+3V_Mini1_VDD

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

+1.5V_Mini1_VDD

WLAN_SDA0
WLAN_SCL0

WIMAX_LED#

C463 *0.1U/10V_4C463 *0.1U/10V_4

C464 *0.1U/10V_4C464 *0.1U/10V_4
R394 *0/J_4R394 *0/J_4
R395 *0/J_4R395 *0/J_4

PLTRST#
RF_EN

R389 *0/short_4R389 *0/short_4
R390 *0/short_4R390 *0/short_4
R391 *0/short_4R391 *0/short_4
R396 *0/short_4R396 *0/short_4
R397 *0/short_4R397 *0/short_4

+3V_Mini1_VDD

WLAN_LED#

R392 *0/short_4R392 *0/short_4

PLTRST# <10,21,24>
RF_EN <25>

LFRAME# <10,25>
LAD3 <10,25>
LAD2 <10,25>
LAD1 <10,25>
LAD0 <10,25>

R399

R399
*10K/J_4

*10K/J_4

USBP2+ <11>

USBP2- <11>

SB_SDATA0 <11,15>
SB_SCLK0 <11,15>

3

Turn off WLAN LED when 3G module is on

R422 *0/J_4R422 *0/J_4

RF_LED_ON

R421 *0/short_4R421 *0/short_4

Q20

Q20

2

2N7002K

2N7002K

1

3

<20100122(B2A)>
Change Q20 from BAM00840001(PMOS) to BAM70020002(NMOS)
For LED cannot be full turn on issue.

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

3G_LED#

RF_LED# <22>

Fun. Model

WLAN

WLAN

WLAN

2

RF_LED_EN <25>

<20100309(C3A)>
Add R421 and stuff R190, for purple LED issue

+3V +3VSUS +1.5V USBPCIE

Atheros
AR9285(HB95)

Broadcom
BCM94313

Realtek
RTL8191SE

V X X

V

(295mA)

X X

1

R393 *0/short_8R393 *0/short_8

+3VSUS

R400 *0/J_8R400 *0/J_8

+3V_Mini1_VDD+3V

+1.5V

R398 *0/J_8R398 *0/J_8

C468

C468
*10U/10V_8

*10U/10V_8

0.75A

C462

C462

0.1U/10V_4

0.1U/10V_4

+1.5V_Mini1_VDD

C466

C466

*1000P/50V_4

*1000P/50V_4

C467

C467

0.1U/10V_4

0.1U/10V_4

0.5A

C438

C438

0.1U/10V_4

0.1U/10V_4

C465

C465
*0.1U/10V_4

*0.1U/10V_4

C434

C434

0.1U/10V_4

0.1U/10V_4

C469

C469
*10U/10V_8

*10U/10V_8

SMBUS CLKREQ# WAKE# DISABLE# PERST# LED SIZE

XV V V V

V

WLAN#

Half

WLAN# Half

VXXXX V V V V WLAN# Half

+3V_Mini2_VDD

C255

C255

3G@10U/10V_8

3G@10U/10V_8

USB

PCIE

X XXX X X

V

X WWAN#

V V

V

V

C68

C68
3G@1U/10V_6

3G@1U/10V_6

1 2

+3V

X V

X

+3VSUS

R192 *0/short_8R192 *0/short_8
R205 *0/short_6R205 *0/short_6

R208 *3G@0/J_8R208 *3G@0/J_8
R215 *3G@0/J_6R215 *3G@0/J_6

+3VSUS

V

(2.75/1.1A)

V

(2.75/1.1A)

V

(2.75/0.99A)

V

(643mA)

+3V

+1.5V

X XXXX XX X V V V V WWAN#

X

UIM_PWR

Mini Card 2(MNC)

+3V_Mini2_VDD

CN20

P80_CLK

JSIM1

JSIM1

6

CLK(C3)
D-(C8)7VCC(C1)

8

D+(C4)

9

CT

10

CD

3G@SIM-Conn

3G@SIM-Conn

SDP_VIS

P80_DAT

<20100303(C3A)>
Change JSIM1 footprint from sim-ce01x-3-14p
tosim-ce01x-3-14p-smt, for SMT open issue.

GND(C5)

VPP(C6)
RST(C2)

DATA(C7)

GND14GND12GND11GND

13

3G_WAKE<25>

B B

3G_WAKE_2<25>

R188 *3G@0/J_4R188 *3G@0/J_4

PCIE_TXP2<7>
PCIE_TXN2<7>

PCIE_RXP2<7>
PCIE_RXN2<7>

CLK_PCIE_MNC_P<10>
CLK_PCIE_MNC_N<10>

CLKREQ_MNC#<11>

R235 *3G@0/J_4R235 *3G@0/J_4

MultiMedia SIM

A A

USB-_SIM<11>
USB+_SIM<11>

*3G@0.1U/10V_4

*3G@0.1U/10V_4

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

UIM_CLK

C66

C66

C65

C65
*3G@0.1U/10V_4

*3G@0.1U/10V_4

5

CN20

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

3G@MINI-CARD2

3G@MINI-CARD2

Max: 7.5mA (Option)

1

UIM_PWR

2

UIM_VPP

3

UIM_RST

4

UIM_DATA

5

53

+3.3V

GND

+1.5V
LED_WPAN#
LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

W_DISABLE#

GND

UIM_VPP
UIM_RST
UIM_CLK

UIM_DATA

UIM_PWR

+1.5V

GND

+3.3V

GND54GND

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RST

UIM_VPP

4

+1.5V_Mini2_VDD

+3V_Mini2_VDD

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

C60 3G@27P/50V_4C60 3G@27P/50V_4

C63 3G@10P/50V_4C63 3G@10P/50V_4

C64 3G@10P/50V_4C64 3G@10P/50V_4

C62 3G@27P/50V_4C62 3G@27P/50V_4

C61 3G@33P/50V_4C61 3G@33P/50V_4

C245 *3G@0.1U/10V_4C245 *3G@0.1U/10V_4

C249 *3G@0.1U/10V_4C249 *3G@0.1U/10V_4

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

PLTRST#_3G

UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR

R222 *3G@0/J_4R222 *3G@0/J_4

WLAN_LED#
3G_LED#

PLTRST#

3G_EN <25>

+3V_Mini2_VDD +3V

<20100309(C3A)>

R190

R190

Stuff R190, for purple LED issue

10K/J_4

10K/J_4

USBP4+ <11>
USBP4- <11>

UIM_CLK

3G_LED# <22>

<20100119(B2A)>
Stuff R222 (EM770W: PERST# / Gobi2000: NC / F3307: NC)
<20100311(C3A)>
Non-stuff R222(CS00002JB38), for Huawei EM770W cannot be detected issue.

Fun.

3G

3G

3G

3G

Wimax

U3

U3

1

CH1

2

VN
CH23CH3

*3G@CM1293-04SO

*3G@CM1293-04SO

3

Model

Qualcomm
Gobi2000

HUAWEI
EM770W

Option
GTM382

Ericsson
F3307

Intel
5150(512...)

6

CH4

5

VP

4

UIM_VPPUIM_RST

UIM_DATA

Peak:2.75A
Normal:1.1A

C274

C236

C236

3G@0.1U/10V_4

3G@0.1U/10V_4

+1.5V

R362 *3G@0/J_8R362 *3G@0/J_8

UIM SMBUS

C274

3G@0.1U/10V_4

3G@0.1U/10V_4

+1.5V_Mini2_VDD

C242

C242

3G@0.1U/10V_4

3G@0.1U/10V_4

C237

C237
*3G@1000P/50V_4

*3G@1000P/50V_4

CLKREQ# WAKE# DISABLE# PERST# LED SIZEUIM_Vpp

0.5A

V V

X

XX

X

X

X

V

<20090604(A1A)_Qualcomm design guide>
Place 0.1uF near connector's VCC pin

C59

C59
3G@0.1U/10V_4

3G@0.1U/10V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

3G@0.1U/10V_4

3G@0.1U/10V_4

X

XX XXX XX WWAN#X

V

12

C293

3G@0.47U/6.3V_4

3G@0.47U/6.3V_4

C264

C264
*3G@0.1U/10V_4

*3G@0.1U/10V_4

C293

C292

C292

VX V

V V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Mini-Card/WL/3G/SIM

Mini-Card/WL/3G/SIM

Mini-Card/WL/3G/SIM

C266

C266
3G@10P/50V_4

3G@10P/50V_4

PCM

WWAN#

X

Full

Full

V

Full

FullV V V

WLAN#
WWAN#

ZH9

ZH9

ZH9

23 40Sunday, March 28, 2010

23 40Sunday, March 28, 2010

23 40Sunday, March 28, 2010

1

Full

4A

4A

4A

5

4

3

2

1

AU6437B52-GBL-GR (MMC)

D D

R387

R387

*100K/J_4

*100K/J_4

C458

C458

C454

C454

XTALSEL

+3V

C457

C457
*0.1U/16V_4

*0.1U/16V_4

Y5
*12MHz-CRY5*12MHz-CR

2 1

R381 *0/J_4R381 *0/J_4

Clock input selection
'1' for 48MHz input [Default]
'0' for 12MHz input

C C

PLTRST#<10,21,23>

*0.47U/16V_6

*0.47U/16V_6

<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"

USBP1+<11>
USBP1-<11>

*0.1U/16V_4

B B

*0.1U/16V_4

C455 *18P/50V_4C455 *18P/50V_4

C456 *18P/50V_4C456 *18P/50V_4

<EMI>

C448

A A

C448
*2.2P/50V_4

*2.2P/50V_4

C449

C449
*2.2P/50V_4

*2.2P/50V_4

5

R382 *0/short_4R382 *0/short_4

+3V

CLK_48M_CR<11>

+3V_CR

C446

C446

4.7U/10V_6

4.7U/10V_6

XI

<20100129(B2A)>
Non-stuff Y5,C455,C456 ; Stuff R383. (CLK for
Cardreader from crystal change to internal CLK.)

XO

USBP1+
USBP1-

+3V_CR

R383 *0/short_4R383 *0/short_4
R386 *0/short_4R386 *0/short_4

+3.3V: 43mA

+3V_CR

CLK_48M_CR_R
CARD_RST#

R384 330/J_4R384 330/J_4

USBP1+
USBP1-

+1.8V_CARD

+3V_CR

C445

C445

0.1U/16V_4

0.1U/16V_4

+1.8V_CARD

C453

C453

0.1U/16V_4

0.1U/16V_4

C444

C444

0.1U/16V_4

0.1U/16V_4

1
2
3
4
5
6
7
8

XI

9

XO XD_CE#

10
11
12

C451

C451

4.7U/10V_6

4.7U/10V_6

C452

C452

4.7U/10V_6

4.7U/10V_6

U22

U22

GPON7
EXT48IN
RSTN
REXT
VD33P
DP
DM
VS33P
XI
XO
VDD
VDD

48

VDDH

V1813CF_V33

VCC_XD

C450

C450

2.2U/6.3V_6

2.2U/6.3V_6

T92T92

T91T91

XTALSEL

CRMD_N

NBMD

CTRL1/SD_WP/XD_CLE

43

46

47

44

45

VDD

GND

TRIST

NBMD

XTALSEL

AU6437B52-GBL-GR

AU6437B52-GBL-GR

V3317VDD20SDWPEN

AVDD5V

VDDHM18AGND5V

14

19

15

16

VCC_XD

+1.8V_CARD

+3V_CR

4

CTRL3/SD_CD#/XD_WE#

41

CTRL142CTRL3

GND

DATA7

DATA1

DATA0

39

40

DATA0

DATA1

XDCDN22EEPCLK

CTRL4

21

XD_CD#

CTRL4/MS_INS#/XD_RE#

C447

C447

0.1U/16V_4

0.1U/16V_4

DATA6EEPCLK

38

37

CTRL0 trace length shorter ,
surround with GND.

DATA7

DATA6

36

CTRL0

DATA5

35

DATA5

CTRL2/SD_CMD/XD_RDY

34

CTRL2

GPI4

33

GPI4

DATA4

32

DATA4

DATA3

31

DATA3

DATA2

30

DATA2

XD_WP#

29

XDWPN

GPI2

28

GPI2

27

XDCEN

EEPDATA

26

23

EEPDATA

24

GPI1

25

GPI1

SD write protect
1:decided by SDWP[Default]
0:letting SD always
write-able

T90T90

CTRL0/XD_ALE/MS_BS

T88T88

T86T86
T89T89

T87T87

R374*0/J_4 R374*0/J_4

<EMI>

CTRL0/XD_ALE/MS_BS

CTRL1/SD_WP/XD_CLE

3

DATA0
DATA1
DATA2
DATA3

<Layout note>
Close to connector

R218 *0/short_4R218 *0/short_4
R214 *0/short_4R214 *0/short_4
R232 *0/short_4R232 *0/short_4
R231 *0/short_4R231 *0/short_4

<Layout note>
Close to Connector

R212 *0/short_4R212 *0/short_4

R225 *0/short_4R225 *0/short_4

SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3

SD_CLK

MS_SCLK

C263

C263
*10P/50V_4

*10P/50V_4

C277

C277
*10P/50V_4

*10P/50V_4

CTRL2/SD_CMD/XD_RDY
CTRL4/MS_INS#/XD_RE#
XD_CE#
CTRL1/SD_WP/XD_CLE
CTRL0/XD_ALE/MS_BS
CTRL3/SD_CD#/XD_WE#
XD_WP#
DATA0
DATA1
SD_DATA2 SD_DATA1
SD_DATA3
CTRL2/SD_CMD/XD_RDY

VCC_XD

MS_SCLK
DATA3
CTRL4/MS_INS#/XD_RE#
DATA2
DATA0

2

4 IN 1 CARD READER (MMC)

CN6

CN6

1

XD-R/B

2

XD-RE

3

XD-CE

4

XD-CLE

5

XD-ALE

6

XD-WE

7

XD-WP

8

XD-D0

9

XD-D1

10

SD-DAT2

11

SD-DAT3

12

SD-CMD

13

4IN1-GND1

14

MS-VCC

15

MS-SCLK

16

MS-DATA3

17

MS-INS

18

MS-DATA2

19

MS-DATA0

CONN_CARDREADER

CONN_CARDREADER

45mA

MS-DATA1

MS-BS

4IN1-GND2

23mA32mA

SD-VCC
SD-CLK

SD-DAT0

XD-D2
XD-D3
XD-D4

SD-DAT1

XD-D5
XD-D6
XD-D7

XD-VCC

XD-CD-SW

SD-WP-SW

SD-CD-SW

SHIELD1-GND
SHIELD2-GND
SHIELD3-GND
SHIELD4-GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DATA1

20

CTRL0/XD_ALE/MS_BS

21
22
23

SD_CLK

24

SD_DATA0

25

DATA2

26

DATA3

27

DATA4

28
29

DATA5

30

DATA6

31

DATA7

32
33

XD_CD#

34

CTRL1/SD_WP/XD_CLE

35

CTRL3/SD_CD#/XD_WE#

36

37
38
41
42

<Layout note>
Close to pin5 of connector

VCC_XD

4.7U/10V_6

4.7U/10V_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

AU6437 (Card Reader)

AU6437 (Card Reader)

AU6437 (Card Reader)

1

VCC_XD

<Layout note>
Close to pin41 of connector

C282

C282

ZH9

ZH9

ZH9

VCC_XD

R229

R229

5.1K/J_4

5.1K/J_4

C262

C262

0.1U/16V_4

0.1U/16V_4

4A

4A

24 40Sunday, March 28, 2010

24 40Sunday, March 28, 2010

24 40Sunday, March 28, 2010

4A

5

L20 1A/22ohm_6L20 1A/22ohm_6

EC(KBC)

+3VPCU

<20090602(A1A)_Vendor suggest>
Add 2.2ohm series resister for
ESD/EOS issue

D D

DS page248, GA20/KBRST# are VCC well, but
they were held low when VDD well is off.

C C

B B

A A

R203 2.2/J_6R203 2.2/J_6

<20090831(A1A)_EC team suggest>

1.remove diode from EC_SCI#

<EMI>

LCLK_EC

R158

R158
*22/J_4

*22/J_4

C205

C205
*10P/50V_4

*10P/50V_4

SDP_VIS<23>
P80_CLK<23>
P80_DAT<23>

30mA

+3V_VCC_EC

C225

C225

C251

C251

4.7U/6.3V_6

4.7U/6.3V_6

0.1U/16V_4

0.1U/16V_4

EC_FPBACK#<16>

SDP_VIS MY9

R166 *0/J_4R166 *0/J_4

P80_CLK

R165 *0/J_4R165 *0/J_4
R164 *0/J_4R164 *0/J_4

P80_DAT

5

LAD0<10,23>
LAD1<10,23>
LAD2<10,23>
LAD3<10,23>

A_RST#_SB<10>

MY10
MY11

C204

C204

C250

C250

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

LFRAME#<10,23>

LCLK_EC<10>

CLKRUN#<10>

GA20<11>
KBRST#<11>

EC_SCI#<11>

T48T48

SERIRQ<10>
EC_SMI#<11>

MX0<18>
MX1<18>
MX2<18>
MX3<18>
MX4<18>
MX5<18>
MX6<18>
MX7<18>

MY0<18>
MY1<18>
MY2<18>
MY3<18>
MY4<18>
MY5<18>
MY6<18>
MY7<18>
MY8<18>

MY9<18>
MY10<18>
MY11<18>
MY12<18>
MY13<18>
MY14<18>
MY15<18>

MBCLK<26>

MBDATA<26>

2ND_MBCLK<4>

2ND_MBDATA<4>

TPCLK<18>

TPDATA<18>

+1.8V_ON<29,30,32>

BT_POWERON#<18>

MAINON<29,30,32,33>

RTC_CLK<10>

R199 *0/short_4R199 *0/short_4

E781AGND

C221

C221

0.1U/16V_4

0.1U/16V_4

EC_FPBACK#
E_KEY
A_RST#_SB

SERIRQ

E781AGND

C224

C224

0.1U/16V_4

0.1U/16V_4

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA

TPCLK
TPDATA

RTC_CLK_EC

4

+A3VPCU

C232

C232

C228

C228

4.7U/6.3V_6

4.7U/6.3V_6

0.1U/16V_4

0.1U/16V_4

19

46

76

88

VCC1

VCC2

VCC3

3

LFRAME

126

LAD0

127

LAD1

128

LAD2

1

LAD3

2

LCLK

8

GPIO11/CLKRUN

121

GPIO85/GA20

122

KBRST/GPIO86

29

ECSCI/GPIO54

6

GPIO24/LDRQ

124

GPIO10/LPCPD

7

LREST

123

GPIO67/PWUREQ

125

SERIRQ

9

GPIO65/SMI

54

KBSIN0

55

KBSIN1

56

KBSIN2

57

KBSIN3

58

KBSIN4

59

KBSIN5

60

KBSIN6

61

KBSIN7

53

KBSOUT0/JENK

52

KBSOUT1/TCK

51

KBSOUT2/TMS

50

KBSOUT3/TDI

49

KBSOUT4/JEN0

48

KBSOUT5/TDO

47

KBSOUT6/RDY

43

KBSOUT7

42

KBSOUT8

41

KBSOUT9/SDP_VIS

40

KBSOUT10/P80_CLK

39

KBSOUT11/P80_DAT

38

KBSOUT12/GPIO64

37

KBSOUT13/GPIO63

36

KBSOUT14/GPIO62

35

KBSOUT15/GPIO61/XOR_OUT

34

GPIO60/KBSOUT16

33

GPIO57/KBSOUT17

70

GPIO17/SCL1

69

GPIO22/SDA1

67

GPIO73/SCL2

68

GPIO74/SDA2

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27PSDAT2

12

GPIO25/PSCLK3

13

GPIO12/PSDAT3

77

GPIO00/32KCLKIN

79

GPIO02

NPCE781L(A0DX)

NPCE781L(A0DX)

1A/22ohm_6

1A/22ohm_6

E781AGND

4

<Layout note>
Place every 0.1uF
close to every
power pin

U6

U6

102

115

VCC4

VCC5

AVCC

LPC

LPC

KB

KB

SMB

SMB

PS/2

PS/2

GND1

GND2

GND3

GND4

GND5

5

18

45

78

89

L19

L19

E781AGND

116

GND6

A/D

A/D

D/A

D/A

GPIO

GPIO

TIMER

TIMER

SPI

SPI

IR

IR

FIU

FIU

103

GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3

GPIO05
GPIO04

GPI94/DA0
GPI95/DA1
GPI96/DA2

GPI97

GPIO01/TB2

GPIO03
GPIO06
GPIO07

GPIO23/SCL3

GPIO30/CIRTX2

GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM

GPIO36

GPIO40/F_PWM

GPIO42/TCK
GPIO43/TMS

GPIO44/TDI

GPIO45/E_PWM

GPIO46/CIRRXM/TRST

GPO47

GPIO50/TDO

GPIO51

GPIO52/CIRTX2/RDY

GPIO53
GPIO81

GPO82/TEST

GPO84/TRIST

GPIO41

GPIO56/TA1
GPIO20/TA2
GPIO14/TB1

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO66/G_PWM

GPIO77

GPO76/SHBM

GPIO75

GPIO72/IRRX1/SIN2

GPIO70/IRRX2_IRSL0

GPIO71/IRTX/SOUT2

GPIO87/CIRRXM/SIN_CR

GPIO34/CIRRXL

GPIO16/CIRTX

GPO83/SOUT_CR/XORTR

F_SDI

F_SDO

F_CS0
F_SCK

GPIO55/CLKOUT

VCC_POR

VREF

VCORF

AGND

44

VCORF_uR

C220

C220

1U/10V_4

1U/10V_4

+3V_VDD_EC

4

VDD

10mA

97
98
99
100
108
96

101
105
106
107

64
95
93
94
119
109
120
65
66
15
16
17
20
21
22
23
24
25
26
27
28
91
110
112
80

31
117
63

32
118
62
81

84
83
82

75
73
74
113
14
114
111

86
87
90
92

30
85
104

TPD_TRIP

HDMI_SENSE

BATLED0#
BATLED1#

SUSLED#

TEST#

3G_WAKE_2

PWRLED#

RF_EN
HWPG

SPI_SDI_uR
SPI_SDO_uR
SPI_CS0#_uR
SPI_SCK_uR

ECDB_CLOCK
VCC_POR#
+A3VPCU

3

R155 *0/J_6R155 *0/J_6

D8

21

BAS316D8BAS316

C171

C171

0.1U/10V_4

0.1U/10V_4

T53T53

T49T49
T50T50

R210 22/J_4R210 22/J_4
R211 22/J_4R211 22/J_4

T46T46
R209 47K/J_4R209 47K/J_4

3

1 2

E781AGND

<20090602(A1A)_ Vendor suggest>
Place 10nF-0.1u F capacitors fo r
every AD input. And close to the AD
input.

+3VPCU

+3V

R191

R191
100K/F_6

ICMNT <26>

E781AGND

ACIN <26>
NBSWON# <22>
LID# <16>
SUSB# <11>

BATLED0# <22>USB_EN#<20>
BATLED1# <22>
VRON <28,33>

SUSLED# <22>

AMP_MUTE# <19>

CPUFAN# <4>
3G_WAKE <23>
VIN_ON <26>

D/C# <26>

S5_ON <27,31,34>

HDMI_HPD_EC# <17>
DNBSWON# <11>

RF_LED_EN <23>
3G_WAKE_2 <23>

SUSON <30,33>

FANSIG <4>
CONTRAST <16>
PWRLED# <22>

3G_EN <23>

EC_RSMRST# <11>

SUSC# <11>
ECPWROK <11>

RF_EN <23>

+3VPCU

100K/F_6

TEMP_MBAT <26>

12

C239

C239

0.01U/16V_4

0.01U/16V_4

E781AGND

<20090831(A1A)_EC team suggest>

1.remove diode from DNBSWON#

<20090721_FAE suggestion>
Stuff 100K and close to EC side
for improving power consumption

E781AGND

*100K/F(NTC)_4

*100K/F(NTC)_4

SPI_SDI_uR

C189

C189

4.7U/6.3V_6

4.7U/6.3V_6

C233

C233
3300P/50V_4

3300P/50V_4

XORTR#

SPI_SDO_uR_R
SPI_SCK_uR_R

INTERNAL KEYBOARD STRIP SET

+3VPCU

RP5 10K/J_10P8RRP5 10K/J_10P8R

10

MX4 MX2

9

MX5

8

MX6

7 4

MX7

R171 10K/J_4R171 10K/J_4

MY0

2

+3V

R187

R187
*47K/J_6

*47K/J_6

RT1

RT1

t

t

Plam Rest
Thermal Sersor

R201

R201
100K/J_4

100K/J_4

MX3

1
2

MX1

3

MX0

56

+3VPCU

2

I/O ADDRESS SETTING

no test mode selected (normal operation)

TEST Mode

XOR-tree test mode
ICT mode

Reserved exclusively for Nuvoton use

SHBM=0: Enable shared memory with host BIOS

TEST#
XORTR#
RF_LED_EN

SHBM

3G_EN

TEST#

1

R177 *10K/J_4R177 *10K/J_4
R175 *10K/J_4R175 *10K/J_4
R173 *10K/J_4R173 *10K/J_4
R200 10K/J_4R200 10K/J_4

SM BUS PU

MBCLK
MBDATA

2ND_MBCLK
2ND_MBDATA

1ST: Battery
2ND: CPU Thermal Sensor / DTS
3RD: VGA Thermal Sensor

BATLED0#

R193 100K/J_4R193 100K/J_4
R194 100K/J_4R194 100K/J_4

BATLED1#

<20090831(A1A)_EC team suggest>

1.change R7027/R7028 to 1M or 100K ohm

2.change PWR/SUS LED's power from +3VPCU to +3V_S5 or +3VSUS
can reduce pull-high resistor of SUSLED#/PWRLED#

R198 4.7K/J_4R198 4.7K/J_4
R197 4.7K/J_4R197 4.7K/J_4

R195 4.7K/J_4R195 4.7K/J_4
R196 4.7K/J_4R196 4.7K/J_4

+3VPCU

SPI FLASH

R224 22/J_4R224 22/J_4

HWPG

+3VPCU

SPI_SDI_uR

R228 10K/J_4R228 10K/J_4

+3VPCU

<20100319(RAMP)>
Non-stuff D9,D17, for cost down.

HWPG_VDDR<33>
HWPG_NB_CORE<29>

HWPG_1.5V<30>
HWPG_1.1V<31>
HWPG_1.8V<32,33>
HWPG_SYS<27>

CPU_COREPG<28>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

SPI_SDI_uR_R
SPI_SDO_uR_R
SPI_SCK_uR_R
SPI_CS0#_uR

1/13 Comfirm by vendor mail :
If the Southbridge enables 'Long Wait Abort' by default, the
flash device should be 50MHz (or faster)

D10 BAS316D10 BAS316
D13 BAS316D13 BAS316
D9 *BAS316D9 *BAS316
D15 BAS316D15 BAS316
D16 BAS316D16 BAS316
D17 *BAS316D17 *BAS316
D14 BAS316D14 BAS316

NPCE781L & FLASH

NPCE781L & FLASH

NPCE781L & FLASH

1

TRIST#

XORTR#

X X
001

0
0

1

00 or 11

0

+3VPCU

+3V

VDD

HOLD

VSS

WP

R169

R169

ZH9

ZH9

ZH9

8
7
3
4

*0/short_4

*0/short_4

25 40Sunday, March 28, 2010

25 40Sunday, March 28, 2010

25 40Sunday, March 28, 2010

+3VPCU

U9

U9

2

SO

5

SI

6

SCK

1

CE

W25Q80BVSSIG_8Mbits

W25Q80BVSSIG_8Mbits

HWPG_R

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

C273

C273

0.1U/16V_4

0.1U/16V_4

+3V

R170

R170

10K/J_4

10K/J_4

HWPG

4A

4A

4A

ACIN<25>

TEMP_MBAT_C

PR5

PR5
100/J_4

100/J_4

5

0.1U/50V_6

0.1U/50V_6

PR8

PR8
*0/short_4

*0/short_4

47P/50V_4

47P/50V_4

PC37

PC37

0.1U/50V_6

0.1U/50V_6

PR7 100/J_4PR7 100/J_4

PC3

PC3

PR6

PR6
100/J_4

100/J_4

PC38

PC38

47P/50V_4

47P/50V_4

PC36

PC36
2200P/50V_4

2200P/50V_4

PC1

PC1

100P/50V_4

100P/50V_4

PC4

PC4

MBDATA <25>

+3VPCU

PC2

PC2

0.1U/25V_4

0.1U/25V_4

MBCLK <25>

PL2

PL2

HI0805R800R-00/5A/80ohm_8

HI0805R800R-00/5A/80ohm_8

PL1

PL1

HI0805R800R-00/5A/80ohm_8

HI0805R800R-00/5A/80ohm_8

PR149

PR149
100K/F_4

100K/F_4

PU1

PU1
CM1293A-04SO

CM1293A-04SO

1

CH1

2

VN

POWER_JACK

POWER_JACK

dcjk-2dc2003-000111-3p-v

dcjk-2dc2003-000111-3p-v

PJ2

PJ2

1
2

3

456

7

D D

C C

B B

Batt_Conn

Batt_Conn

PJ1

PJ1

89
7
6
5
4
3
2
1

10

A A

CH23CH3

Add ESD diode base on EC FAE suggestion

5

4

VA

PC41

PC41

0.1U/50V_6

0.1U/50V_6

PD5

PD5
SW1010CPT

SW1010CPT

HI0805R800R-00/5A/80ohm_8

HI0805R800R-00/5A/80ohm_8

PL4

PL4

HI0805R800R-00/5A/80ohm_8

HI0805R800R-00/5A/80ohm_8

PL3

PL3

TEMP_MBAT <25>

MBDATA

6

CH4

5

VP

MBCLKTEMP_MBAT

4

4

PDS1040S-13

PDS1040S-13

PC39

PC39

0.1U/50V_6

0.1U/50V_6

82.5K/F_4

82.5K/F_4

22K/F_4

22K/F_4

BAT-VMBAT+

+3VPCU

PD4

PD4

1
2

SMAJ20A

SMAJ20A

PR25

PR25

49.9/F_4

49.9/F_4

PR157

PR157

PR164

PR164

PC108

PC108

*1U/10V_4

*1U/10V_4

3

PD3

PD3

MBDATA

MBCLK

DCIN

88731ACSET

0.01U/25V_4

0.01U/25V_4

2 1

+3VPCU

PC95

PC95

0.1U/25V_4

0.1U/25V_4

PC104

PC104

PC12

PC12

0.1U/25V_4

0.1U/25V_4

PC102

PC102
*0.01U/25V_4

*0.01U/25V_4

1

11

VDDSMB

9

SDA

10

SCL

13

ACOK

22

DCIN

2

ACIN

3

VREF

4

ICOMP

5

NC

6

VCOMP

PR150

PR150

2.21K/F_4

2.21K/F_4

PC96

PC96

0.01U/25V_4

0.01U/25V_4

10/F_6

10/F_6

NC

GND33GND32GND31GND

VIN_SRC

CSIP_1

PR166

PR166

30

NC

7

0.1U/50V_6

0.1U/50V_6

PC8

PC8

0.1U/25V_4

0.1U/25V_4

CSIP

28

CSSP

PC40

PC40

3

PQ6

PQ6

AOL1413

AOL1413

1 6
2
3

PQ3

PQ3

IMD2AT108

IMD2AT108

PC121

PC121

1U/10V_4

1U/10V_4

PR22

PR22

2.7/J_6

2.7/J_6

88731B_2

25

ISL88731_UGATE

24

ISL88731_PHASE

23

ISL88731_LGATE

20

19

CSOP

18

CSON

17

PR151

PR151
*0/short_4

*0/short_4

16

15
29

1
3

5
4

88731B_1

10/F_6

10/F_6

PC107

PC107

0.1U/25V_4

0.1U/25V_4

10/F_6

10/F_6

4

PC111

PC111

1U/10V_4

1U/10V_4

PD15

PD15
*RB500V-40

*RB500V-40
PC122

PC122

0.1U/50V_6

0.1U/50V_6

PR155

PR155

PR153

PR153

CSOP_1

PR152

PR152
100/J_4

100/J_4

52

BAT-V

PR59 *0/short_6PR59 *0/short_6

VA2

PR62

PR62
220K/F_6

220K/F_6

PR60

PR60
220K/F_6

220K/F_6

PR18

PR18
10/F_6

CSIN

27

10/F_6

CSSN

26

VCC

PR163

PR163

4.7/J_6

4.7/J_6

ISL88731_VDDP

21

VDDP

BOOT

UGATE

PHASE

LGATE

PGND

CSOP

CSON

NC

VBF

GND

ICM

8

GND

NC

PU8

PU8

ISL88731A

ISL88731A

12

14

ISL88731 thermal pad

ICMNT

tie to Pin12

ICMNT <25>

BAT-V

1u/25V_6

1u/25V_6

PC42

PC42

2

1 2

CSIP_1 VIN_SRC

PC19

PC19

2200P/50V_4

2200P/50V_4

AO4932

AO4932

D1

D1

1

D1 S1/D2

D1 S1/D2

2

G2

G2

3

S2

S2

4

PQ33

PQ33

0.01_3720

0.01_3720
PR64

PR64

G1

G1

PR63

PR63
150K_4

150K_4

8
7
6
5

1
3

D/C# <25>

PC15

PC15

0.1U/50V_6

0.1U/50V_6

PR160

PR160

2.2/F_4

2.2/F_4

PC114

PC114
2200P/50V_4

2200P/50V_4

PQ5

PQ5

AOL1413

AOL1413

4

PR61

PR61
39K_4

39K_4

PC45

PC45

0.1U/50V_6

0.1U/50V_6

VIN_SRC

PC171

PC171

4.7U/25V_8

4.7U/25V_8

PL5

PL5

6.8uH/4.5A_7X7X3

6.8uH/4.5A_7X7X3

CSOP_1

BAT-V

VINVIN_SRC

52

VIN_SRC

2200P/50V_4

2200P/50V_4

PC44

PC44

1 2

EC1

EC1

0.1U/50V_6

0.1U/50V_6

0.01_3720

0.01_3720
PR159

PR159

EC3

EC3

2200P/50V_4

2200P/50V_4

PC106

PC106

2200P/50V_4

2200P/50V_4

10U/25V_1206

10U/25V_1206

1

1
3

PR19

PR19
33K/J_6

33K/J_6

PQ1

PQ1

DMN601K-7

DMN601K-7

PC118

PC118

PQ30

PQ30

AOL1413

AOL1413

4

3

2

1

PC117

PC117

10U/25V_1206

10U/25V_1206

PR24

PR24

10K/J_6

10K/J_6

BAT-V

52

*0.1U/50V_6

*0.1U/50V_6

PC105

PC105

0.01U/25V_4

0.01U/25V_4

EC2

EC2

3

VIN_ON<25>

3

2

2

PQ4

PQ4
DMN601K-7

DMN601K-7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

PROJECT :

PROJECT :

CHARGER (ISL88731)

CHARGER (ISL88731)

CHARGER (ISL88731)

1

ZH9

ZH9

ZH9

4A

4A

26 40Sunday, March 28, 2010

26 40Sunday, March 28, 2010

26 40Sunday, March 28, 2010

4A

MAIND

SUSD

5

MAIND <30,33>

SUSD <31,33>

SYS_SHDN#<4,34>

4

PR124 *0/short_4PR124 *0/short_4

3

VL

2

1

5V_EN

5V_DL

PC73

PC73
1U/25V_6

1U/25V_6

PR105

PR105
22/J_8

22/J_8

3V5V_EN

12

PR128

PR128
39K/F_4

39K/F_4

PR126

PR126
*0/short_4

*0/short_4

3V_EN

PD11

PD11

CHN217UPT

CHN217UPT

PD12

PD12

CHN217UPT

CHN217UPT

PR112 133K/F_4PR112 133K/F_4

PC79

PC79

0.1U/50V_6

0.1U/50V_6

2

3

1

2

3

1

PC78

PC78
1U/25V_6

1U/25V_6

PR133

PR133
390K/J_4

390K/J_4

PR132

PR132
150K/J_4

150K/J_4

0.1U/50V_6

0.1U/50V_6

0.1U/50V_6

0.1U/50V_6

+5VPCU

DDPWRGD_R

PC74

PC74

PC76

PC76

PC89

PC89

0.1U/25V_4

0.1U/25V_4

5V_EN

PR106

PR106
1/F_6

1/F_6

PR101

PR101

*0/J_4

*0/J_4

9
10
11
12
13
14
15
16
37
36

PC88

PC88

0.01U/25V_4

0.01U/25V_4

BYP
OUT1
FB1
ILIM1
PGOOD1
EN1
DH1
LX1
PAD
PAD

PAD33PAD34PAD

35

VL

PC75

PC75

1U/10V_4

1U/10V_4

VL

PC90

PC90

4.7U/6.3V_6

4.7U/6.3V_6
PR135

PR135
*0/short_4

*0/short_4

5

6

3

7

4

8

NC

VIN

LDO

ONLDO

LDOREFIN

PU7

PU7
RT8206

RT8206

BST117DL118PVCC19NC20GND21PGND22DL223BST2

1

REF

TON2VCC

PGOOD2

24

PR102

PR102

PR131

PR131

*0/J_4

*0/J_4

PC86

PC86

0.1U/25V_4

0.1U/25V_4

REF

REFIN2

ILIM2
OUT2
SKIP#

EN2
DH2

LX2

PR137

PR137
*0/short_6

*0/short_6

*0/short_4

*0/short_4

PR129

PR129
*0/short_4

*0/short_4

PC87

PC87
1U/10V_4

1U/10V_4

PR127 *0/J_4PR127 *0/J_4

REFIN2

32
31
30
29

DDPWRGD_R

28

3V_EN

27
26
25

PR111

PR111
1/F_6

1/F_6

PR122

PR122
137K/F_4

137K/F_4

PC82

PC82

0.1U/50V_6

0.1U/50V_6

PR125

PR125
*0/J_4

*0/J_4

3V_DH

4

3V_LX

4

PQ45

PQ45

FDMC8296

FDMC8296

3V_DL

SKIP REF

PR130 *0/J_4PR130 *0/J_4

PR134 *0/short_4PR134 *0/short_4

0.1U/50V_6

52

PQ46

PQ46
FDMC8884

FDMC8884

3

1

52

PD13

PD13
SX34

SX34

3

1

PR115 *0/short_4PR115 *0/short_4
PR120 *0/J_4PR120 *0/J_4

DDPWRGD_R

PL13

PL13

3.3uH/6A_7X7X3

3.3uH/6A_7X7X3

PR113

PR113

2.2/F_4

2.2/F_4

PC80

PC80
2200P/50V_4

2200P/50V_4

+3VPCU

PR138 *0/short_4PR138 *0/short_4

PC163

PC163
*10U/25V_1206

*10U/25V_1206

PR136

PR136
*100K/F_4

*100K/F_4

PR119

PR119
*0/J_4

*0/J_4

PR121

PR121
*0/J_4

*0/J_4

PC157

PC157

PC156

PC156

2200P/50V_4

2200P/50V_4

0.1U/50V_6

VIN_SRC

D D

PR123

PR123

*0/short_4

PC152

PC152

0.1U/50V_6

0.1U/50V_6

PC153

PC153

2200P/50V_4

2200P/50V_4

PC162

PC162

*10u/25V_1206

*10u/25V_1206

PC158

PC158

4.7U/25V_8

4.7U/25V_8

*0/short_4

52

PQ43

+5VPCU

PL12

PL12

2R2uH/8A_7X7X3

C C

B B

PC150

PC150

10U/25V_1206

10U/25V_1206

+5VPCU

330U/6.3V_7343

330U/6.3V_7343

+

+

PC154

PC154

0.1U/50V_6

0.1U/50V_6

PR117

PR117
*0/J_4

*0/J_4

PC149

PC149

PR114

PR114
*0/short_4

*0/short_4

2R2uH/8A_7X7X3

PR185

PR185

2.2/F_4

2.2/F_4

PC155

PC155

2200P/50V_4

2200P/50V_4

PQ43

FDMC8884

FDMC8884

PD10

PD10
SX34

SX34

5V_DH

4

3

1

5V_LX SKIP

52

4

PQ44

PQ44

3

1

FDMC8296

FDMC8296

+15V

+3VPCU

0.1U/50V_6

0.1U/50V_6

VIN_SRC

+3VPCU

PC85

PC85

+

+

PC83

PC83

HWPG_SYS <25>

330U/6.3V_7343

330U/6.3V_7343

+3VPCU

+3V_S5

PR143

PR139

PR139
1M/J_6

1M/J_6

A A

S5_ON<25,31,34>

2

PQ24

PQ24

DTC144EU

DTC144EU

PR146

PR146

1 3

1M/J_6

1M/J_6

5

PR143
22/J_8

22/J_8

3

2

PQ23

PQ23
DMN601K-7

DMN601K-7

1

+15VVIN_SRC

PR141

PR141
1M/J_6

1M/J_6

3

PC92

2

PQ29

PQ29
DMN601K-7

DMN601K-7

1

4

PC92
1000P/50V_4

1000P/50V_4

+3VPCU

3

2

PQ21

PQ21
AO3404

AO3404

1

MAIND MAINDS5D

+3V_S5

3

+5VPCU

5

4

PQ47

PQ47

213

AON7410

AON7410

+5V

+3VPCU

SUSD

5

4

PQ20

PQ20

213

AON7410

AON7410

Quanta Computer Inc.

Quanta Computer Inc.

+3V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SYSTEM 5V/3V (RT8206B)

SYSTEM 5V/3V (RT8206B)

SYSTEM 5V/3V (RT8206B)

3

2

PQ22

PQ22
AO3404

AO3404

1

+3VSUS

ZH9

ZH9

ZH9

4A

4A

27 40Sunday, March 28, 2010

27 40Sunday, March 28, 2010

27 40Sunday, March 28, 2010

1

4A

5

PR37

PR37

49.9/0.1%_6

49.9/0.1%_6

D D

CPU_VDD_FB_H<4>

CPU_VDD_FB_L<4>

PR32

PR32
*0/short_4

*0/short_4

PR47

PR47
*0/short_4

*0/short_4

SNS_POS_VDD_0

SNS_NEG_VDD_0

Parallel

C C

8380VREF

8380TSET

PC129

PC129

0.22u/6.3V_4

0.22u/6.3V_4 PC100

PR20

PR20

PR40

PR40

*0/short_4

*0/short_4

2.55K/F_4

2.55K/F_4

PR28

PR28
*49.9K/F_4

*49.9K/F_4

CPU_SVD<4>

B B

CPU_VDDNB_FB_H<4>

CPU_SVC<4>

PR39

PR39

49.9K/F_4

49.9K/F_4

CPU_SVD
CPU_SVC

PC124

PC124

0.1u/25V_4

0.1u/25V_4

SNS_NEG_VDD_1

SNS_POS_VDD_1

PR23*0_4 PR23*0_4

8380VREF

PR26

PR26
PR38

PR38

*0/short_4

*0/short_4

PR15

PR15

49.9/0.1%_6

49.9/0.1%_6

PC126

PC126

1u/6.3V_4

1u/6.3V_4

PR46

PR46

43.2K/F_4

43.2K/F_4

PR45

PR45

6.2K/F_4

6.2K/F_4

PR27

PR27
665/F_4

665/F_4

PR34

PR34
665/F_4

665/F_4

PR169

PR169

49.9/0.1%_6

49.9/0.1%_6

8380VREF

PR1

PR1
22_6

22_6

*0/short_4

*0/short_4

8380VREF

PR29

PR29

49.9/0.1%_6

49.9/0.1%_6

1.2K/F_4

1.2K/F_4

470P/50V_4

470P/50V_4

+5VPCU

PR21

PR21

PR17

PR17

1.2K/F_4

1.2K/F_4

PC119

PC119

12

8380ILIM

PC130

PC130
1000p/50V_4

1000p/50V_4

8380SVD
8380SVC

PC120

PC120

220p/50V_4

220p/50V_4

CPU_VDDNB_CORE

4

CPU_CORE

8380RSP1

8380RSN1

PR167

PR167
27K/F_4

27K/F_4

PC125

PC125
470P/50V_4

470P/50V_4

PR168

PR168

32.4K/F_4

32.4K/F_4

8380RSP2

25
26
27
28
29
30
31
32

PC127

PC127
470P/50V_4

470P/50V_4

1 2

12

COMPV1
VDDA
VREF
TSET
ILIM
SVD
SVC
COMPV2

12

3

PR13

PR13

VRON<25,33>

*0/short_4

*0/short_4

PR204

PR204
*330/F_4

*330/F_4

PR16

PR16
1K/F_4

1K/F_4

PC99

PC99

0.22u/25V_6

0.22u/25V_6

PR3

PR3
2_6

2_6

PR4

PR4
2_6

2_6

PC98

PC98

0.22u/25V_6

0.22u/25V_6

PR10

PR10

1.91K/F_4

1.91K/F_4

1

+5VPCU

21

PD1

PD1
RB501V-40

RB501V-40

CPU_PWRGD_SVID_REG<4>

PR11

PR11
10K_4

10K_4

PC6

PC6
1000p/50V_4

1000p/50V_4

8380SC

8380EN

8380RSN1

8380RSP1

8380CSP1

8380CSN1

18

20

RSP1

CSN1

8380CSN2

8380CSP2

PR14

PR14
*100K/F_4

*100K/F_4

21

4

CSP1

19

EN

6

8380VIN

17

HDR1

GNDA38GNDA39GNDA

PWR_OK

BST1
LDR1

GNDP

VDDP
HDR2

BST2

PG7CSN25VIN

LDR2

GNDA35GNDA36GNDA

11

PR154

PR154
27K/F_4

27K/F_4

PC103

PC103
1000p/50V_4

1000p/50V_4

40

16

LX1

8380BST1

15
14
13
12
8
10
9

LX2

37

+3V

12

VIN

41

24

23

22

SC

RSN1

GNDA42GNDA

PU9

PU9

OZ8380

OZ8380

RSN21GNDA33RSP22VFIX3CSP2

GNDA

34

8380VFIX

8380RSP2

8380RSN2

12

+3V

+1.5V

PQ9

PQ9

*AO3402

*AO3402

2

3

+3V

8380HDR1

8380LX1

21

PD2

PD2
RB501V-40

RB501V-40

8380LDR1

PC100
1u/6.3V_4

1u/6.3V_4

+5VPCU

8380HDR2

+5VPCU

8380LDR2

8380LX2

CPU_COREPG <25>

+3V

PR205

PR205
*1K/F_4

*1K/F_4

4

4

PQ36

PQ36
AOL1718

AOL1718

D1

D1

1

D1 S1/D2

D1 S1/D2

2

G2

G2

3

S2

S2

4

PQ31

PQ31
AO4932

AO4932

T2T2

12

12

+

+

PC110

PC110

100u/25V_6X5.8

100u/25V_6X5.8

PC16

PC169

PC169

4.7U/25V_8

4.7U/25V_8

5

PQ32

PQ32

213

AOL1448

AOL1448

5

213

G1

G1

PR174

PR174

2.2/F_6

2.2/F_6

PC131

PC131
1000P/50V_6

1000P/50V_6

8
7
6
5

PR9

PR9
*0/short_6

*0/short_6

PC168

PC168

*10U/25V_1206

*10U/25V_1206

PR165

PR165

2.2/F_6

2.2/F_6

PC113

PC113
1000P/50V_6

1000P/50V_6

8380CSP2
8380CSN2

PC16

0.1u/50V_6

0.1u/50V_6

PC172

PC172

*10U/25V_1206

*10U/25V_1206

PC170

PC170

4.7U/25V_8

4.7U/25V_8

1uH

1uH

PR171

PR171

4.99K/F_4

4.99K/F_4

PR12

PR12

4.22K/F_4

4.22K/F_4

PC7

PC7

100p/50V_4

100p/50V_4

PL6

PL6

PR162

PR162

4.99K/F_4

4.99K/F_4

PC116

PC116

68n/25V_6

68n/25V_6

T54T54

PC93

PC93

0.1u/50V_6

0.1u/50V_6

PR170

PR170

10K_6_NTC

10K_6_NTC

2

T55T55

12

Close to Phase
Inductor

PR158

PR158

2.2/F_4

2.2/F_4

PC109

PC109

6.8n/25V_4

6.8n/25V_4

1

8380CSN1
8380CSP1

VIN

PC115

PC115

100p/50V_4

100p/50V_4

0.1U/50V_6

0.1U/50V_6

PR161

PR161

5.62K/F_4

5.62K/F_4

PR2

PR2

3.92K/F_4

3.92K/F_4

PL7

PL7

0.36uH

0.36uH

VIN

T5T5

PC112

PC112

10K_6_NTC

10K_6_NTC

PR173

PR173

PC5

PC5

6.8n/25V_4

6.8n/25V_4

PC11

PC11

330u/2V_7343

330u/2V_7343

PR156

PR156

2.2/F_4

2.2/F_4

Close to Phase
Inductor

T3T3

+

+

PC10

PC10
330u/2V_7343

330u/2V_7343

OCP: 20A

12A

T4T4

CPU_CORE

+

+

OCP: 3A

T57T57

CPU_VDDNB_CORE

1.5A

+

+

PC94

PC94
330u/2V_7343

330u/2V_7343

T56T56

12

PC101

PC101
10u/25V_1206

10u/25V_1206

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

AMD CPU Core (OZ8380)

AMD CPU Core (OZ8380)

AMD CPU Core (OZ8380)

ZH9

ZH9

ZH9

28 40Sunday, March 28, 2010

28 40Sunday, March 28, 2010

1

28 40Sunday, March 28, 2010

4A

4A

4A

5

<25,30,32>

4

3

2

1

PR78

PR78

10/F_4

10/F_4

D D

PR202

PR202

*10K/F_4

PR84

PR84

10K/F_4

10K/F_4

PR82

PR82

*10K/F_4

*10K/F_4

*10K/F_4

+3VSUS

PC54

PC54

0.1U/25V_4

0.1U/25V_4

PC50

PC50

1U/10V_4

1U/10V_4

+1.8V_ON

MAINON<25,30,32,33>

C C

HWPG_NB_CORE<25>

PR81

PR81
1M/J_6

1M/J_6

PC52

PC52

*1000P/50V_4

*1000P/50V_4

PU5

PU5
UP6111AQDD

UP6111AQDD

15

EN/DEM

16

TON

1

VOUT

2

VDD

3

FB

4

PGOOD

6

GND

5

NC

14

NC

BOOT

UGATE

PHASE

VDDP

LGATE

PGND

TPAD

OC

PR90

PR90

2.2/F_6

2.2/F_6

13
12
11
10
9
8
7
17

TON=3.85p*RTON*Vout/(Vin-0.5)

B B

Frequency=Vout/(Vin*TON)

TON=3.85p*1M*1/(Vin-0.5)

NB_CORE_FB

Frequency=1/(0.0036767)=272K

R1

R2

PR76

PR76

2.67K/F_4

2.67K/F_4

PR77

PR77
10K/F_4

10K/F_4

PC49

PC49

33P/50V_4

33P/50V_4

Rdson=13mOhm

L(ripple current)
=(19-1)*1/(1u*272k*19)

A A

~3.646A

VOUT=(1+R1/R2)*0.75

PR79 *0/short_6PR79 *0/short_6

13m*9.5=RILIM*20uA
RILIM=6.19K

5

4

+5VPCU

PD6

PD6
RB500V-40

RB500V-40

PC60

PC60

4.7U/6.3V_6

PC58

PC58

UGATE-NB_CORE
PHASE-NB_CORE

PR88

PR88

6.19K/F_4

6.19K/F_4

LGATE-NB_CORE

4.7U/6.3V_6

PR85

PR85
1/F_6

1/F_6

0.1U/50V_6

0.1U/50V_6

PC57

PC57
1U/10V_4

1U/10V_4

Rds*OCP=RILIM*20uA

PR75

PR75

13K/F_4

NB_CORE_FB

3

13K/F_4

PQ8

PQ8

DMN601K-7

DMN601K-7

3

1

0.01U/25V_4

0.01U/25V_4

2

PC46

PC46

DMN601K-7

DMN601K-7

4

4

PQ40

PQ40

FDMC8296

FDMC8296

PR70

PR70

10K/F_4

10K/F_4

PR66

PR66
100/J_4

100/J_4

PQ7

PQ7

3

3

+5VPCU

3

1

*100K/J_4

*100K/J_4

52

52

2

PR68

PR68

1

1

PQ41

PQ41
FDMC8884

FDMC8884

1.0uH/11A_7X7X3

1.0uH/11A_7X7X3

PR91

PR91

2.2/F_4

2.2/F_4

PC66

PC66
2200P/50V_4

2200P/50V_4

PR69

PR69
*0/J_4

*0/J_4

12

2

PC173

PC173

*10U/25V_1206

*10U/25V_1206

PC167

PC68

PC68

0.1U/50V_6

0.1U/50V_6

PC167

4.7U/25V_8

4.7U/25V_8

PL11

PL11

330U/2V_7343

330U/2V_7343

PC134

PC134

2200P/50V_4

2200P/50V_4

+

+

PC69

PC69

0.1U/50V_6

0.1U/50V_6

PC67

PC67

10U/10V_8

10U/10V_8

PC61

PC61

HI --- 0.95V
LOW ---1.1V

+NB_CORE_ON <8>

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

NB_CORE(UP6111A)

NB_CORE(UP6111A)

NB_CORE(UP6111A)

1

VIN

0.95V/7.5A
OCP: 9.5A

ZH9

ZH9

ZH9

29 40Sunday, March 28, 2010

29 40Sunday, March 28, 2010

29 40Sunday, March 28, 2010

+NB_CORE

4A

4A

4A

5

4

3

2

1

[PWM]

PC25

PC25

4.7U/6.3V_6

4.7U/6.3V_6

PC23

1/F_6

1/F_6

DRVH

PR50

PR50

*0/J_4

*0/J_4

20

LL

S5_1.8V
S3_1.8V

PC23

0.1U/50V_6

0.1U/50V_6

19

DRVL

PGND

CS_GND

CS

V5IN

V5FILT

PGOOD

12

+5VPCU

18

17

PR30 9.1K/F_4PR30 9.1K/F_4

16

15

14

13

PR36

PR36
620K/F_4

620K/F_4
PR41

PR41
*0/short_4

*0/short_4
PR48

PR48
*0/short_4

*0/short_4

PR33

PR33

5.1/F_6

5.1/F_6

12

PC13

PC13

1U/6.3V_4

1U/6.3V_4

PR31

PR31
*100K/F_4

*100K/F_4

VIN

SUSON <25,33>
MAINON <25,29,32,33>

+3VPCU

HWPG_1.5V <25>

(For RT8207A 400KHZ )

(10u*PR35)/Rdson+Delta_I/2=Iocp

52

4

3

1

52

PR44

PR44
*0/J_4

*0/J_4

4

3

1

+5VPCU

12

PC14

PC14

1U/6.3V_4

1U/6.3V_4

S5_1.8V S3_1.8V

PR55

PR55
*0/short_4

*0/short_4

Rdson=13mOhm

L(ripple current)
=(19-1.8)*1.8/(2.2u*400k*19)
~1.03A

13m*7=RILIM*10uA
RILIM=9.1K

PQ35

PQ35
FDMC8884

FDMC8884

PQ34

PQ34
FDMC8296

FDMC8296

PR172

PR172

2.2/F_4

2.2/F_4

PC128

PC128
2200P/50V_4

2200P/50V_4

PR186

PR186
*2.2/F_4

*2.2/F_4

PC159

PC159
*2200P/50V_4

*2200P/50V_4

2.2uH/8A_7X7X3

2.2uH/8A_7X7X3
PL8

PL8

MAIND

2200P/50V_4

2200P/50V_4

330U/2V_7343

330U/2V_7343

PR201

PR201
0/J_4

0/J_4

PC123

PC123

PC31

PC31

+1.5VSUS

+

+

+1.8V_D

PC165

PC165
*4.7U/25V_8

*4.7U/25V_8

PC164

PC164
*4.7U/25V_8

*4.7U/25V_8

PC32

PC32
10U/10V_8

10U/10V_8

12

+

+

PC151

PC151

100u/25V_6X5.8

100u/25V_6X5.8

VIN

1.5V/5.1A
OCP: 7A

+1.5VSUS

PR49

D D

C C

+SMDDR_VTERM<15>

CPU_VDDIO_FB_H<4>

0.375A

+SMDDR_VREF<15>

0.08A

PC30

PC30

4.7U/6.3V_6

4.7U/6.3V_6

+1.5VSUS

PC29

PC29

33N/25V_4

33N/25V_4

PR54

PR54
*0/J_4

*0/J_4

PC27

PC27

4.7U/6.3V_6

4.7U/6.3V_6

+5VPCU

*33P/50V_4

*33P/50V_4

PC26

PC26

24

25

VTT

GND

1

VTTGND

2

VTTSNS

3

GND

4

MODE

5

VTTREF

6

COMP

NC7VDDQSNS8VDDQSET9S310S511NC

FOR DDR III

PR51

PR51

10K/F_4

10K/F_4

PR49

21

23

22

VBST

VLDOIN

RT8207A

RT8207A

PU2

PU2

VOUT=(1+R1/R2)*0.75

R1

PR52

PR52

10K/F_4

10K/F_4

B B

R2

PR56 *0/short_6PR56 *0/short_6

MAIND

MAIND <27,33>

VIN_SRC

PR197

PR197
*1M/F_4

*1M/F_4

PR198

PR198
1M/F_4

1M/F_4

+1.8V_ON<25,29,32>

PR196

PR196
100K_4

100K_4

12

2

PQ50

PQ50

*DTC144EUA

*DTC144EUA

1 3

+1.5V

PR199

PR199
22_8

22_8

3

2

PQ55

PQ55
DMN601K-7

DMN601K-7

1

+15V

PR200

PR200
*1M/F_4

*1M/F_4

+1.8V_D

3

2

PQ54

PQ54
DMN601K-7

DMN601K-7

1

2

PC161

PC161
*2.2n/50V_4

*2.2n/50V_4

+1.5VSUS

3

1

4A

PQ42

PQ42
AO3404

AO3404

+1.5V

0.054A

A A

5

4

3

1/29 modify for sequence

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

DDR 1.5V(RT8207A)

DDR 1.5V(RT8207A)

DDR 1.5V(RT8207A)

ZH9

ZH9

ZH9

30 40Sunday, March 28, 2010

30 40Sunday, March 28, 2010

30 40Sunday, March 28, 2010

1

4A

4A

4A

5

4

3

2

1

PR74

PR74

10/F_4

10/F_4

PU4

PU4
UP6111AQDD

UP6111AQDD

15
16

1
2
3
4
6
5

14

R1

R2

EN/DEM
TON
VOUT
VDD
FB
PGOOD
GND
NC
NC

PR72

PR72

4.7K/F_4

4.7K/F_4

PR73

PR73
10K/F_4

10K/F_4

BOOT
UGATE
PHASE

OC

VDDP

LGATE

PGND

TPAD

33P/50V_4

33P/50V_4

PC47

PC47

PR87

PR87

2.2/F_6

2.2/F_6

13
12
11
10
9
8
7
17

S5_ON<25,27,34>

HWPG_1.1V<25>

MAIND

SUSD

PR67 *0/short_6PR67 *0/short_6

PR83

PR83

10K/F_4

10K/F_4

+3VSUS

PR71

PR71

*10K/F_4

*10K/F_4

MAIND <27,30,33>

SUSD <27,33>

PC53

PC53

0.1U/25V_4

0.1U/25V_4

PC48

PC48

1U/10V_4

1U/10V_4

PR80

PR80
1M/J_6

1M/J_6

PC51

PC51

*1000P/50V_4

*1000P/50V_4

1.1V_FB

D D

C C

B B

VOUT=(1+R1/R2)*0.75

TON=3.85p*RTON*Vout/(Vin-0.5)

Rdson=13mOhm

Frequency=Vout/(Vin*TON)

A A

TON=3.85p*1M*1/(Vin-0.5)

Frequency=1/(0.0036767)=272K

L(ripple current)
=(19-1.1)*1.1/(1u*272k*19)
~3.81A

13m*8.5=RILIM*20uA
RILIM=5.49K

5

4

3

+5VPCU

PD7

PD7
RB500V-40

RB500V-40

PC55

PC55

4.7U/6.3V_6

PR89

PR89
1/F_6

1/F_6

0.1U/50V_6

0.1U/50V_6

PC56

PC56
1U/10V_4

1U/10V_4

PC59

PC59

4.7U/6.3V_6

1.1V_DH

1.1V_LX

PR86

PR86

5.49K/F_4

5.49K/F_4

1.1V_DL

Rds*OCP=RILIM*20uA

PR65 *0/short_4PR65 *0/short_4

4

4

PQ39

PQ39

FDMC8296

FDMC8296

52

PQ38

PQ38
FDMC8884

FDMC8884

3

1

PL9

PL9

1.0uH/11A_7X7X3

1.0uH/11A_7X7X3

52

3

PR176

PR176

2.2/F_4

2.2/F_4

PC135

PC135

1

2200P/50V_4

2200P/50V_4

2200P/50V_4

2200P/50V_4

330U/2V_7343

330U/2V_7343

SUSD

PC63

PC63

+

+

PC145

PC145

2

PC71

PC71

10U/10V_8

10U/10V_8

+1.1V_S5

3

1

PC62

PC62

0.1U/50V_6

0.1U/50V_6

PC70

PC70

0.1U/50V_6

0.1U/50V_6

4A

PQ37

PQ37
AO3404

AO3404

4.7U/25V_8

4.7U/25V_8

+1.1VSUS

PC166

PC166

PC174

PC174

*10U/25V_1206

*10U/25V_1206

0.6A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

VCCP 1.1V(UP6111A)

VCCP 1.1V(UP6111A)

VCCP 1.1V(UP6111A)

ZH9

ZH9

ZH9

1

VIN

1.1V/7.3A
OCP: 8.5A

+1.1V_S5

31 40Sunday, March 28, 2010

31 40Sunday, March 28, 2010

31 40Sunday, March 28, 2010

4A

4A

4A

5

D D

+3VPCU

4

3

2

1

1.8V/1.418A
OCP: 6A

+1.8V

PC140

PC140

0.1U/25V_4

PC141

PC141
10U/10V_8

10U/10V_8

C C

PR178

PR178
0/J_4

MAINON

MAINON

0/J_4

MAINON <25,29,30,33>

PC139

PC139
1000P/50V_4

1000P/50V_4

0.1U/25V_4

PR183

PR183

5.49K/F_4

5.49K/F_4

PC143

PC143
*100P/50V_4

*100P/50V_4

+1.8V_EN
54418_VFB

PC147

PC147
4700P/25V_4

4700P/25V_4

PR184

PR184
182K/F_4

182K/F_4

PU11 HPA00835RTERPU11 HPA00835RTER

16

VIN

1

VIN

2

VIN

15

EN

6

VSNS

7

COMP

8

RT/CLK

9

SS

22

PC144

PC144

0.01U/25V_4

0.01U/25V_4

BOOT

PWRGD

GND
GND

AGND

PAD17PAD18PAD19PAD20PAD21PAD

PH
PH
PH

10
11
12
13
14
3
4
5

PR177 1/F_6PR177 1/F_6

PC138

PC138

0.1U/50V_6

0.1U/50V_6

PR179

PR179

*10K/J_4

*10K/J_4

PL10

PL10

3.3uH/6A_7X7X3

3.3uH/6A_7X7X3

HWPG_1.8V <25,33>

+3VSUS

54418_VFB

PR181

PR181
100K/F_4

100K/F_4

R1

PC142

PC142

0.1U/25V_4

0.1U/25V_4

PC148

PC148

10U/10V_8

10U/10V_8

PC146

PC146

10U/10V_8

10U/10V_8

PR182

+3V

B B

+1.8V_ON<25,29,30>

PR189

PR189
*0/J_4

*0/J_4

PR187

PR187
*0/J_4

*0/J_4

PR188

PR188
*0/J_4

*0/J_4

V0=0.8*(R1+R2)/R2

+1.8V_EN

PR182

78.7K/F_4

78.7K/F_4

R2

1/29 modify for sequence

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

+1.8V(TPS54418)

+1.8V(TPS54418)

+1.8V(TPS54418)

ZH9

ZH9

ZH9

4A

4A

32 40Sunday, March 28, 2010

32 40Sunday, March 28, 2010

32 40Sunday, March 28, 2010

1

4A

5

4

3

2

1

PC160

PC160
*2.2n/50V_4

*2.2n/50V_4

+1.1V_DMAIND

2.5V/0.188A

PC133

PC133
10U/10V_8

10U/10V_8

+1.1V_S5

578

3 6

241

+

+

PC132

PC132
*100U/6.3V_3528

*100U/6.3V_3528

PQ48

PQ48
AO4468

AO4468

5.78A

+2.5V

+1.1V

VIN_SRC

PR191

PR191
*1M/F_4

*1M/F_4

D D

HWPG_1.8V<25,32>

+3V

PR57

1
6

5

1.2VADJ0.9V

2

+15V

PR57
100K/F_4

100K/F_4

HWPG_VDDR <25>

PR35

PR35

4.02K/F_6

4.02K/F_6

0.8V

PR43

PR43

30.1K/F_6

30.1K/F_6

Vout =0.8(1+R1/R2)
=0.9V

PR140

PR140
1M/J_6

1M/J_6

3

PQ25

PQ25
DMN601K-7

DMN601K-7

1

PC21

PC21

10u/10V_8

10u/10V_8

PC91

PC91
*2200P/50V_4

*2200P/50V_4PQ27

+5VPCU

PU3

PC34

PC34
*0.1u/50V_6

*0.1u/50V_6

*DMN601K-7

*DMN601K-7

PU3
RT9025-25PSP

RT9025-25PSP

4

VPP

2

VEN

3

VIN

8

GND

9

GND

PQ2

PQ2

PC28

PC28
*220P/50V_4

*220P/50V_4

+1.1VSUS

2

2

3

1

PGOOD

VO

NC

ADJ

7

3

1

PR144

PR144
22/J_8

22/J_8

PQ26

PQ26
DMN601K-7

DMN601K-7

PR42

PR42
*22.1K/F_4

*22.1K/F_4

PC20

PC20

0.1u/50V_6

PR142

PR142
1M/J_6

1M/J_6

PR147

PR147
1M/J_6

1M/J_6

0.1u/50V_6

PC35

PC35

0.1u/50V_6

0.1u/50V_6

PR53 *33_4PR53 *33_4

+3VSUS

PR145

PR145
22/J_8

22/J_8

3

2

1

PQ27
DMN601K-7

DMN601K-7

PR58

PR58
*0/short_4

*0/short_4

VRON<25,28>

C C

B B

SUSON<25,30>

PR148

PR148

100K/J_4

100K/J_4

2

PQ28

PQ28

DTC144EU

DTC144EU

+1.5VSUS

SUS_ON_G

1 3

VDDR_OPT<10>

12

PC33

PC33

10u/10V_8

10u/10V_8

VIN_SRC

CPU_VDDR_FB_H <4>

PR175

PR175
*0/J_4

*0/J_4

CPU_VDDR

0.75A

SUSD <27,31>

PR195

PR195
100K_4

100K_4

12

2

3

1

MAINON

PR194

PR194
1M/F_4

1M/F_4

PQ56

PQ56
*DMN601K-7

*DMN601K-7

1/25 modify for sequence

PR180 *0/short_4PR180 *0/short_4

2

+3VPCU

2.2U/6.3V_6

2.2U/6.3V_6

PC136

PC136
*0.1U/25V_4

*0.1U/25V_4

+1.1V

PC137

PC137

3

1

PR192

PR192
22_8

22_8

PQ53

PQ53
DMN601K-7

DMN601K-7

3
2
1

PU10

PU10

SHDN
GND
VIN

G9091-250

G9091-250

+15V

PR193

PR193
*1M/F_4

*1M/F_4

+1.1V_D

3

2

PQ52

PQ52
DMN601K-7

DMN601K-7

1

PR190

PR190
0/J_4

0/J_4

5

VO

4

NC

VIN_SRC

PR97

PR103

PR103
1M/J_6

1M/J_6

A A

PR104

PR104
1M/J_6

1M/J_6

5

2

PQ11

PQ11

DTC144EU

DTC144EU

1 3

MAINON<25,29,30,32>

PR96

PR96

100K/J_4

100K/J_4

PR97
22/J_8

22/J_8

3

2

PQ13

PQ13
DMN601K-7

DMN601K-7

1

PR98

PR98
22/J_8

22/J_8

3

2

PQ14

PQ14
DMN601K-7

DMN601K-7

1

4

3

2

1

PR99

PR99
22/J_8

22/J_8

PQ15

PQ15
DMN601K-7

DMN601K-7

+1.5V

PR118

PR118
22/J_8

22/J_8

3

2

PQ18

PQ18
DMN601K-7

DMN601K-7

1

+15V+5V+3V +1.1V

PR116

PR116
1M/J_6

1M/J_6

MAINDMAINON_ON_G

3

2

PQ19

PQ19
DMN601K-7

DMN601K-7

1

PC84

PC84
*2200P/50V_4

*2200P/50V_4

3

MAIND <27,30>

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet

PROJECT :

Discharge (2.5V/1.2V/VDDR)

Discharge (2.5V/1.2V/VDDR)

Discharge (2.5V/1.2V/VDDR)

ZH9

ZH9

ZH9

4A

4A

4A

of

33 40Sunday, March 28, 2010

33 40Sunday, March 28, 2010

1

33 40Sunday, March 28, 2010

1

2

VIN

3

4

5

A A

S5_ON

PR107

PR107

1.74K/F_4

1.74K/F_4

VLVL

B B

PR110

PR110

10K/J(NTC) _6

10K/J(NTC) _6

3

C C

S5_ON<25,27,31>

2

PQ17

PQ17
DMN601K-7

DMN601K-7

1

PR108

PR108
200K/F_4

200K/F_4

2.469V

PR109

PR109
200K/F_4

200K/F_4

2

PQ12

PQ12

DTC144EU

DTC144EU

3
2

PD9

PD9
SW1010CPT

SW1010CPT

PR100

PR100
1M/F_4

1M/F_4

TSNS_ON

1 3

PC72

PC72

0.1U/25V_4

PU6A

PU6A
LM393

LM393

0.1U/25V_4

1

84

+

+

-

-

1

PQ10

PQ10
AO3409

2

AO3409

3

Thermal protection

PR92

PR92
200K/F_4

200K/F_4

PC81

PC81

0.1U/25V_4

0.1U/25V_4

+3VPCU

3

2

PQ16

PQ16
DMN601K-7

DMN601K-7

1

SYS_SHDN# <4,27>

VL

PR93

PR93
100K/F_4

100K/F_4

PR94

PR94
10K/F_4

10K/F_4

4.95V

PR95

PR95
1M/F_4

1M/F_4

D D

1

2

5
6

PU6B

PU6B

+

+

-

-

LM393

LM393

PD8

PD8

7

RB500V-40

RB500V-40

T51T51

For EC control thermal protection (output 3.3V)

3

4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

Thermal protect

Thermal protect

Thermal protect

ZH9

ZH9

ZH9

34 40Sunday, March 28, 2010

34 40Sunday, March 28, 2010

34 40Sunday, March 28, 2010

5

4A

4A

4A

5

4

3

2

1

INTERNAL CLOCK MODE

D D

A SO-DIMM

Page 15

C C

Page 25

EC

Debug card

HD AUDIO

Page 19

M_A_CLKP/N

800MHz

RTC_CLK

33MHz

LPC_CLK0

33MHz

AZ_BIT_CLK

24MHz

AMD
ASB2 CPU

Page 2~5

CPU_CLKP/N

AMD NORTHBRIDGE
RS880M

200MHz

A-LINK

AMD SB820
INT CLK MODE

Page 6~9

100MHz

100MHz

NB_GFX_REFCLKP/N

SPM_CLK

800MHz

100MHz

100MHz

HT_REFCLKP/N

NB_REFCLK_P/N

SIDE PORT MEMORY CHIP

PCIE_PE0_CLKP/N

100MHz

PCIE_PE1_CLKP/N

100MHz

PCIE_LAN_CLKP/N

100MHz

Page 6

MINICARD-WLAN

MINICARD-3G

LAN-AR8152

Page 23

Page 23

Page 21

Page 10

B B

For MASTER For RTC

(25MHz)

(32.768KHz)

For SATA

(25MHz)-DNI

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Clock Distribution Diagram

Clock Distribution Diagram

Clock Distribution Diagram

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

ZH9

ZH9

ZH9

4A

4A

4A

35 40Sunday, March 28, 2010

35 40Sunday, March 28, 2010

35 40Sunday, March 28, 2010

1

5

CPU core

(OZ8380)

PU?

VIN

NorthBridge

(uP6111AQDD)

D D

PU?

+5VPCU

VIN

SYSTEM

5V/3V

(RT8206B)

PU?

C C

+3VPCU

ADAPTER

BATTERY

CHARGER

ISL88731HRZ-T

PU?

VIN

4

CPU_CORE@20A

<0.7V-1.1V,12A>

CPU_VDDNB_CORE@3A

<0.9V,1.5A>

+NB_CORE@9.5A

<0.95V~1.1V,6A>

+5VPCU

<AC/DC Insert>

AO3404

PQ??

+3VPCU

<AC/DC Insert>

AO3404

PQ?

AO3404

PQ?

AO3404

PQ?

G909-150T1U

PU?

HPA00835RTER

PU?

+5V

<MAIND>

+3V_S5

<S5D>

+3VSUS

<SUSD>

+3V

<MAIND>

+2.5V

<MAINON>

+1.8V

<MAINON>

3

POWER

Distribution

VIN LCD Backlight, CPU_CORE,NB_CORE, +5VPCU, +3VPCU, +1.5VSUS, +1.1V_S5

CPU_CORE

CPU_VDDNB_CORE

NB_CORE

+5VPCU

+5V

+1.8V

+3VPCU

+3V_S5

+3VSUS

+3V

CPU

power supply for on-die NorthBridge

NorthBridge power supply

USB Connecter

CRT,Touch Pad ,Audio codec,SATA
NB & SB power supply
RTC, Hall Sensor, System LED, EC, BIOS, Acer ID EEPROM, +3V_S5, +3VSUS, +3V

SouthBridge,LAN , LAN EEPROM , RJ45 LED

3G

CLK_GEN, CPU, NB,SB, LCD power switch,CCD, DMIC, BT, System LED, Codec, WLAN/Wimax, Card reader, EC

+2.5V CPU,Discharge

+1.5VSUS

CPU,DDR,Discharge

+1.5V CPU,DDR,NB

+SMDDR_VTERM

+SMDDR_VREF

+1.1V_S5

+1.1VSUS

+1.1V

CPU_VDDR

DDR

CPU, DDR

NorthBridge,Discharge

Southbridge
CLK_GEN,CPU,NB,SB

CPU

2

1

BOM Structure

+1.5VSUS

<SUSD>

VIN

B B

DDR PWR

1.5V

RT8207A

+1.5VSUS

PU?

AO3404

PQ?

RT9025-25PSP

PU?

+SMDDR_VTERM@0.5A

<0.75V@0.375A>

+SMDDR_VREF@0.25A

<0.75V@0.08A>

+1.5V

<MAIND>

CPU_VDDR

<VRON>

Fun. Description
SPM@

w/ Sideport RAM

3G@

w/ 3G module

BT@

w/ BT module

HDM@

w/ HDMI

BOM@

BOM Control

SB Core logic
standby power

UP6111AQDD

A A

5

PU?

+1.1V_S5

+1.1V_S5@8.5A

<1.1V,7.3A>

AO4468

PQ?

AO3404

PQ?

4

+1.1V

<MAIND>

+1.1VSUS

<SUSD>

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZH9

PROJECT :

ZH9

PROJECT :

Size Do cument Numbe r Rev

Size Do cument Numbe r Rev

Size Do cument Numbe r Rev

Power Tree

Power Tree

Power Tree

Date: Sheet

Date: Sheet

3

2

Date: Sheet

1

ZH9

36 40Sunday, March 28, 20 10

36 40Sunday, March 28, 20 10

36 40Sunday, March 28, 20 10

of

of

of

4A

4A

4A

5

Nile Power On Sequence

From VBAT

From AC,BATT

From PWM to EC

From Button to EC

D D

From EC to PWM

From PWM to EC

From EC to SB
From EC to SB
From SB to EC

From EC to PWM

From PWM to EC

From EC to PWM

From PWM to EC

C C

GROUP A

From EC to PWM

From PWM to EC,SB

GROUP B

From PWM to EC

From EC to SB

B B

From SB to CPU

From SB to NB

VCCRTC
VIN
+5VPCU +3VPCU

HWPG_SYS

NBSWON#

S5_ON

+3.3V_S5

+1.1V_S5

HWPG_1.1V

EC_RSMRST#
DNBSWON#
SUSC#,SUSB#

SUSON

+3.3VSUS

CPU_VDDIO_SUS(+1.5VSUS)
MEM_VTT,MEM_VREF
+1.1VSUS

HWPG_1.5V(SUS)

MAINON

+5V/3.3V
+1.8V

HWPG_1.8V

+2.5V
+1.5V
+1.1V
+NB_CORE

HWPG_NB_CORE

VRON

CPU_VDDNB_CORE
CPU_CORE

CPU_COREPG

CPU_VDDR

HWPG_VDDR

+1.1V_CPU_VLDT

SB_PWRGD(ECPWROK)

NB_PWRGD,NB_PWRGD_INFrom SB to NB

HT_REFCLKP/N(NB INPUT CLK)

CPU_CLKP/N(CPU INPUT CLK)

CPU_PWRGD
NB_RST#_IN

CPU_LDT_RST#From SB to CPU

4

3

EC_RSMRST# not de-asserted until at least 10 ms after S5_3.3V is valid.

(EC define)

100ms

SB_PWRGD(ECPWROK) de-asserted at least 80 ns before VDDCR_11(+1.1V) drops 5% from nominal value.

RC=~22ms , CPU_VDDNB_CORE should not ramp before 1.1V

RC=~4.7ms

SB_PWRGD rise time<50ms

SB_PWRGD to NB_PWRGD:22~500ms

HT REFCLKP/N ramp before NB_PWRGD >= 1 ms.

>1ms

CPU_CLKP/N ramp before CPU_PWRGD >= 1 ms.

>1ms

A_RST# to PCI_RST#<100ns

SB_PWRGD to A_RST#:101~113ms

>1ms

>1ms

2

Power on sequence required:

SB820:

1.EC_RSMRST# ramp up time (10% to 90%) <= 50 ms

2.SB_PWRGD(ECPWROK) rise time <= 50 ms

3.SB_PWRGD(ECPWROK) fail time <= 1 ms

4.SB_PWRGD(ECPWROK) de-asserted at least 1 ns before EC_RSMRST# is
asserted when entering G3 state.

5.VBAT will be valid at least 5 seconds before S5_3.3V and S5_1.1V are
ramped up to allow start time for internal RTC.

6.50us<=all power rails rise time except +3.3V_S5<=40ms

7.100us<=+3.3V_S5 rise time<=40ms

8.+1.8V_S0 rails cannot ramp before the +3.3V_S0 rails.

9.+1.1V_S0 rails cannot ramp before the +1.8V_S0 rails.

10.+1.1V_S0 rails cannot ramp before the +3.3V_S0 rails.

11.+1.1V_S5 rails cannot ramp before the +3.3V_S5 rails.

12.+3V_S5 ramp down time > 300 µs.

RS880:

1.+1.1V valid before NB_PWRGD HIGH >= 1 ms

2.+1.8V_NB_IOPLLVDD18c(+1.8V) cannot ramp before the 3.3-V rails

3.+1.5V_SPM_VDDQ(+1.5V)cannot ramp before the 3.3-V rails

4.+1.8V_NB_VDDLTP18(+1.8V)cannot ramp before the 3.3-V rails

5.+1.8V_NB_PLLVDD18(1.8V)cannot ramp before the 3.3-V rails

6.3.3-V rails cannot exceed the 1.8/1.5-V Sideport or 1.8-V Display
and PLL rails by > 2.1 V.

7.IOPLLVDD/PLLVDD(+1.1V) cannot ramp up before the 1.8/1.5-V Sideport
or 1.8-V Display and PLL rails.

8.VDDC(+NB_CORE) rail cannot ramp before the 1.1-V PLL rails.

1

Notice:

1.CPU_LDT_RST# msut be asserted a minimum of 1ms prior to the assertion of CPU_PWRGD

2.CPU_CLKP/N must be within specification a minimum of 1ms prior to the assertion of CPU_PWRGD

3.CPU_PWRGD remains deasserted at least 1ms after both CPU_CLKP/N and all voltages to the processor are within specification for operation

4.all NB power rails(1.8V/1.2V/1.1V) valid before NB_PWRGD at least 1ms

5.stable input clocks from CLKGEN(HT_REFCLKP/N) to NB before NB_PWRGD at least 1ms

A A

(SB_DA0)/(SB_CL0) (+3V)

Power Plane

MOS CKT (Level shift)

*Reserve: There is not SMBUS function in AVL

SB SMBUS Table

CLK GEN RAM Mini Card (WLAN)

+3V +3V

X X X*

5

V

VV

+3V

EC775 SDA1 / SCL1 (+3VPCU)
EC775 SDA2 / SCL2 (+3V)
EC775 SDA3 / SCL3 ()

Power Plane +3VPCU
MOS CKT (Level shift)

4

EC SMBUS Table

CPU thermal SensorBattery

V

X

3

V

+3V

X

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

POWER SEQUENCE

POWER SEQUENCE

POWER SEQUENCE

1

ZH9

ZH9

ZH9

4A

4A

4A

of

of

of

37 40Sunday, March 28, 2010

37 40Sunday, March 28, 2010

37 40Sunday, March 28, 2010

5

SLP_S3#(SUSB#):
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states.

SLP_S5#(SUSC#):
S5 Sleep Power plane control - Assertion of SLP_S5# shuts power off to non-critical components
when system transitions to S4 or S5 state.

AC Adapter

D D

BATT Charger

PU?

Battery

10

SUSON

13

MAINON

17

4

1

VIN

Always System power

Regulator

PU?

2

1b

+3VPCU

+5VPCU

NBSWON#

3

2

1

3

5

+3VPCU

MOS

PQ?

Regulator

7

+VIN

PU?

+3V_S5

+1.1V_S5

6

RSMRST#

8

PWRBTN#

9

SLP_S5#

SLP_S3#

LDT_RST#

26

CPU_LDT_RST#

RESET_L

EC

4

S5_ON

EC_RSMRST#

DNBSWON#

SUSC#

SUSB#

VRON

ECPWROK(SB_PWRGD)

VIN

Regulator

C C

PU?

CPU_VDDNB_CORE

CPU_CORE

CPU_COREPG

18

19

22

SB820

SB_PWRGD

A_RST#

LDT_PG

24

CPU_PWRGD

ASB2

U7

PWROK

5

CPU_VDDR

+NB_CORE

16

+1.1V

14
+2.5V

15

+1.8V

+3V
+5V

+1.1VSUS

+1.5VSUS

+SMDDR_VTERM

+SMDDR_VREF

+3VSUS

20

HWPG_SYS

CPU_COREPG

HWPG_VDDR

14

6

HWPG_NB_CORE

HWPG_1.1V

21

HWPG

25

NB_RST#_IN

HWPG_1.8V

HWPG_1.5V

U11

23

NB_PWRGD

PWRGOOD

SYSTEMSETb

RS880

14

12

14

MOS

PQ25

+1.5V

11

4

3

2

U9

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZH9

PROJECT :

ZH9

PROJECT :

Size Document Numb er R ev

Size Document Numb er R ev

Size Document Numb er R ev

power sequence block diagram

power sequence block diagram

power sequence block diagram

Date: Sheet

Date: Sheet

Date: Sheet

1

ZH9

4A

4A

4A

38

38

38

40Sunday, March 28, 2010

40Sunday, March 28, 2010

40Sunday, March 28, 2010

of

of

of

+5VPCU

Regulator

PU?

+VIN

Regulator

PU?

+1.1V_S5

MOS

PQ?

B B

A A

+3VPCU

LDO

PU?

+3VPCU

Regulator

PU?

+3VPCU/+5VPCU

MOS

PQ?

+1.1V_S5

MOS

PQ?

VIN

Regulator

PU?

+3VPCU

MOS

PQ?