Acer Aspire 5560 TravelMate 3240, TravelMate 3280 Schematics

Garda-D Block Diagram

(Discrete)

4 4

DDR2

533 MHz

3 3

Line In

MIC In

INT.MIC

Line Out (SPDIF)

2 2

INT.SPKR

1 1

CLK GEN.

IDT CV125PA (ICS 954206)

DDR2

RJ11

533/667MHz

11,12

533/667MHz

11,12

Codec

ALC883

AZALIA

OP AMP

G1421B

MODEM

MDC Card

New card

PWR SW TPS2231

PCI Express

Yonah 478

1.83G/2G/2.16G

Ver.:A3 :71.945PM.A0U / QK58

HDD

Mobile CPU

HOST BUS

400/533/667MHz

Calistoga

6,7,8,9,10

DMI I/F

100MHz

ICH7M

Ver. : B0, 71.ICH7M.A0U / QK65 KI.80101.017

15,16,17,18

PATA

SATA

CDROM

USB

3 PORT

MINI USB Blue-tooth

4, 5

G792

PCI Express x16

M56 Ver.: B24 M52 Ver.: A12 M54 Ver.: A12

PCI BUS

PCIEx1

SPI I/F

LPC BUS

ATI M54P / M52P

45,46,47,48,49

VRAM x4

128/256M

50,51

PCI 7412

CARDBUS

1394

CardReader

LAN

10/100 BCM4401-E

BIOS

SST25LF080A

SIO

NS87381

FIR

Project code: 91.4A901.001 PCB P/N : 55.4A901.XXX REVISION : 05217-1 (Hannstar, ACCL)

-1M-0111

LVDS

14"WSXGA+ LCD

RGB CRT

PCMCIA I/F

PWR SW

TSP2220A

24,25

Mini-PCI

802.11A/B/G

KBC

Renesas

RE144B

Touch Pad

33 33

1394 CONN

TXFM

Mini Card*1

802.11A/B/G

INT. KB

MS/MS Pro/xD/ MMC/SD/SDIO

RJ45

LPC

DEBUG CONN.

TVO

CRT

PCMCIA SLOT

Support TypeII

6 in 1

TOP

GND

VCC

GND

BOTTOM

BCM5787MKFBG-A1 BCM5789KFBG-C1 BCM4401EKFBG-B0

Giga LAN

BCM5789/5787M

SYSTEM DC/DC

TPS51120

PCB STACKUP

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DCBATOUT

TPS51100

APL5332KAC

3D3V_S0 2D5V_S0

APL5912-U

1D8V_S3 1D5V_S0

MAXIM CHARGER

MAX8725

DCBATOUT

CPU DC/DC

ISL6262

INPUTS

DCBATOUT

OUTPUTS

5V_S5

3D3V_S5

1D05V_S0

1D8V_S3

DDR_VREF_S01D8V_S3

OUTPUTSINPUTS

CHG_PWR

18V 4.0A

UP+5V

5V 100mA

OUTPUTS

VCC_CORE_S0

0~1.3V 44A

ATI M54 DC/DC

FAN5234

INPUTS

DCBATOUT

1D8V_S0 1D2V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

BLOCK DIAGRAM

AG1 -1M

OUTPUTS

VGA_CORE_S0

APL5331KAC

153Wednesday, January 11, 2006

38,39

ICH7M Integrated Pull-up and Pull-down Resistors

EE_DIN, EE_DOUT,

GNT[4]#/GPIO48,

LAD[3:0]#/FHW[3:0]#,

LDRQ[0], LDRQ[1]/GPIO[41],

4 4

PWRBTN#,

DDREQ

DD[7],

ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0],

EE_CS,

SPI_ARB, SPI_CLK,

USB[7:0][P,N]

LAN_CLK

GNT[3:0],

GNT[5]#/GPO17,

TP[3]

ACZ_SYNC,ACZ_SDOUT,

GPIO[25],

PME#,

LAN_RXD[2:0]

DPRSLPVR/GPIO16,

SPKR,

ICH7 internal 20K pull-ups

ICH7 internal 11.5K pull-downs

ICH7 internal 20K pull-downs

ICH7 internal 15K pull-downs

ICH7 internal 15K pull-upSATALED#

ICH7 internal 100K pull-down

ICH7-M EDS 17837 1.5V1

ICH7M IDE Integrated Series Termination Resistors

3 3

DD[15:0],

DDACK#,

DCS3#,

IORDY,

IDEIRQ

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

ICH7M Functional Strap Definitions

Signal

ACZ_SDOUT

ACZ_SYNC

EE_CS

EE_DOUT

2 2

GNT2#

GNT3#

GNT5#/ GPIO17#, GNT4#/ GPIO48

DPRSLPVR Reserved

GPIO25

INTVRMEN

LINKALERT#

REQ[4:1]#

1 1

SATALED#

SPKR

TP3

Usage/When Sampled

XOR Chain Entrance/ PCIE Port Config bit1, Rising Edge of PWROK

PCIE bit0, Rising Edge of PWROK.

Reserved

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection. Rising Edge of PWROK.

Reserved. Rising Edge of RSMRST#.

Integrated VccSus1_05 VRM Enable/Disable. Always sampled.

Reserved

XOR Chain Selection. Rising Edge of PWROK.

Reserved This signal should not be pull low.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h)

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal should not be pull high.

This signal should not be pull low.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.

This signal should not be pull high.

This signal should not be pull low.

Enables integrated VccSus1_05 VRM when sampled high

Requires an external pull-up resistor.

TBD, Chapter 8.

If sampled high, the system is strapped to the "No Reboot" mode(ICH7 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

This signal should not be pull low unless using XOR Chain testing.

Comment

954305D 27Mhz/LCDCLK Spread and Frequency Selection Table

SS3

SS2 Byte9 bit 7

000

0000

1 +-0.25 Center

SS1

bit6

bit5

001

PCI Routing

7412

page 16

MiniPCI

LAN

SS0 bit4

Spread Amount%

-0.50 Down

-1.00 Down

-1.50 Down

-2.00 Down

-0.75 Down

-1.25 Down

-1.75 Down

-2.25 Down

+-0.5 Center

+-0.75 Center

+-1.0 Center

+-0.25 Center

+-0.5 Center

+-0.75 Center

+-1.0 Center

page 16

INT -> PIRQ A->G, B->B,

C->F, D->G

A/C -> E B/D -> E

A -> H

Calistoga Strapping Signals and Configuration

page 3

REQ/GNTIDSEL

Pin Name

CFG[2:0]

CFG[4:3]

CFG5

CFG7

CFG8

CFG9

CFG[11:10] Reserved

CFG[13:12]

CFG[15:14]

CFG16

CFG17

CFG18

CFG19

CFG20

SDVOCRTL _DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Calistoga GMCH PWORK in signal.

Strap Description

FSB Frequency Select

Reserved

DMI x2 Select

ReservedCFG6

CPU Strap

Reserved

PCI Express Graphics Lane Reversal

XOR/ALL Z test straps

Reserved

FSB Dynamic ODT

Global R-comp Disable (All R-comps)

VCC Select

DMI Lane Reversal

SDVO/PCIE Concurrent

SDVO Present

EDS 17050 0.71

Configuration

001 = FSB533 011 = FSB667 others = Reserved

0 = DMI x2

1 = DMI x4

0 = Reserved

1 =Mobile CPU(Default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane Numbered in order

00 = Reserved 01 = XOR mode enabled 10 = All Z mode enabled

11 = Normal Operation

(Default)

Reserved

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = All R-comp Disable

1 = Normal Operation (Default)

0 = 1.05V

1 = 1.5V

0 = Normal operation (Default):lane Numbered in order

1 =Reverse Lane,4->0,3->1 ect...

0 = Only SDVO or PCIE x1 is operational (Default)

1 =SDVO and PCIE x1 are operating simultaneously via the PEG port

0 = No SDVO Card present

1= SDVO Card present

(Default)

page 7

(Default)

History

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet of

Date: Sheet

Reference

AG1 SD

253Tuesday, January 10, 2006

3D3V_S0

R155

0R0603-PAD

C258

C258 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16

CLK_PCIE_LAN 35 CLK_PCIE_LAN# 35

CLK_PCIE_SATA 15 CLK_PCIE_SATA# 15

CLK_PCIE_NEW 30 CLK_PCIE_NEW# 30

CLK_PCIE_MINI1 26 CLK_PCIE_MINI1# 26

CLK_PCIE_PEG 45 CLK_PCIE_PEG# 45

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 PM_STPCPU# 16

C508

C508 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CLK14_SIO32 CLK_ICH1416

3D3V_S0

R213

0R0603-PAD

R173 33R2J-2-GPR173 33R2J-2-GP

1 2

R176 33R2J-2-GPR176 33R2J-2-GP

1 2

R179 22R2J-2-GPR179 22R2J-2-GP R209 33R2J-2-GPR209 33R2J-2-GP

1 2

R214 22R2J-2-GPR214 22R2J-2-GP R210 33R2J-2-GP

R210 33R2J-2-GP

1 2

MINI

R211 33R2J-2-GPR211 33R2J-2-GP

1 2

H/L : CPU_ITP/SRC7

GEN_XTAL_IN

1 2

R154 470R2J-2-GPR154 470R2J-2-GP R177 22R2J-2-GPR177 22R2J-2-GP

1 2

R181 22R2J-2-GPR181 22R2J-2-GP

1 2

10KR2J-3-GP

3D3V_48MPWR_S0

C301

C301 SC1U6D3V2ZY-GP

SC1U6D3V2ZY-GP

1 2

R174 10KR2J-3-GPR174 10KR2J-3-GP

3D3V_S0

R212

PCLKCLK0 PCLKCLK1 PCLKCLK2

PCLKCLK2 PCLKCLK3

SS_SEL ITP_EN

GEN_XTAL_OUT

GEN_REF

GEN_IREF

R157475R2F-L1-GP R157475R2F-L1-GP

C226

C226 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

PCI0

PCI1

PCI2

PCI3

PCIF1/SEL100/96#

PCIF0/ITP_EN

PCI_STOP#

SCL

SDA

DOT96

DOT96#

XTAL_IN

XTAL_OUT

REF

IREF

VTT_PWRGD#/PD

VSS_PCI

VSS_REF

VSS_CPU

VSSA

VSS48

VSS_SRC

IDTCV125PAG-GP 71.00125.A0W

CPU2_ITP/SRC7

CPU2_ITP#/SRC7#

CPU_STOP#

FSC/TEST_SEL

FSB/TEST_MODE

USB48/FSA

3D3V_CLKGEN_S0

C257

C257 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U24

LVDS

LVDS#

SRC1

SRC1#

SRC2

SRC2#

SRC3

SRC3#

SRC4

SRC4#

SRC5

SRC5#

SRC6

SRC6#

36 35

CPU0

CPU0#

CPU1

CPU1#

54 53 16 12

VDD_SRC

VDD_PCI

VDD_REF

VDD_CPU

VDDA

VDD48

VDD_SRC

C254

C254 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

CLK_MCH_3GPLL_1

CLK_MCH_3GPLL_1# CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# CLK_PCIE_LAN_1 CLK_PCIE_LAN_1# CLK_PCIE_SATA_1 CLK_PCIE_SATA_1# CLK_PCIE_NEW_1 CLK_PCIE_NEW_1# CLK_PCIE_MINI1_1 CLK_PCIE_MINI1_1#

CLK_PCIE_PEG_1 CLK_PCIE_PEG_1#

CLK_CPU_BCLK_1 CLK_CPU_BCLK_1#

CLK_MCH_BCLK_1 CLK_MCH_BCLK_1#

CPU_SEL2 CPU_SEL1 CLK48

C230

C230 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_CLKGEN_S0

3D3V_CLKPLL_S0 3D3V_48MPWR_S0

C255

C255 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

RN35 SRN33J-5-GP-URN35 SRN33J-5-GP-U

RN21 SRN33J-5-GP-URN21 SRN33J-5-GP-U

RN40 SRN33J-5-GP-U

RN25 SRN33J-5-GP-U

RN29 SRN33J-5-GP-U

RN27 SRN33J-5-GP-U

RN28 SRN33J-5-GP-U

RN17 SRN33J-5-GP-URN17 SRN33J-5-GP-U

RN19 SRN33J-5-GP-URN19 SRN33J-5-GP-U

R60122R2J-2-GP R60122R2J-2-GP

1 2

R60022R2J-2-GP R60022R2J-2-GP

1 2

R602

1 2

2K2R2J-2-GP

1 2 3

2 3 1

GIGA

2 3

SATA

1 2 3

NEW

1 2 3

MINIC

1 2 3

VGA

C303

C303 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

23 1

CPU_SEL2 4,7 CPU_SEL1 4,7 CLK48_ICH 16 CLK48_CARDBUS 25 CPU_SEL0 4,7

Dummy when use UMA

3D3V_S0

3D3V_CLKPLL_S0

R158

0R0603-PAD

4 4

3 3

2 2

C228

C228 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_S0

R598

R598 10KR2J-3-GP

10KR2J-3-GP

SS_SEL

H/L: 100/96MHz

R597

R597 10KR2J-3-GP

10KR2J-3-GP

PCLK_FWH & PCLK_PCM need equal length

C229

C229 SC1U6D3V2ZY-GP

SC1U6D3V2ZY-GP

C256

1 2

SC20P50V2JN-1GP

C225

1 2

SC20P50V2JN-1GP

X-14D31818M-31GP

82.30005.831

PCLK_KBC31 PCLK_LAN22 PCLK_PCM25 PCLK_SIO32 PCLK_FWH34 PCLK_MINI30 CLK_ICHPCI16

PM_STPPCI#16

SMBC_ICH11,18

SMBD_ICH11,18

GEN_XTAL_OUT_R

CLK_EN#38

EMI capacitor

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

PCLK_MINI

RN34

CLK_PCIE_MINI1 CLK_PCIE_MINI1#

SRN49D9F-GP

CLK_PCIE_LAN CLK_PCIE_LAN#

SRN49D9F-GP

CLK_PCIE_SATA CLK_PCIE_SATA#

SRN49D9F-GP

1 1

SEL1

SEL2

0 0

0 1 1

0 1

1 100M

0 1

1 1

SEL0

01200M 1 00333M 1 0 1

CPU

266M 133M

166M

400M

Reserved

FSB

X 533M X 667M X X X X

SRN49D9F-GP

CLK_PCIE_ICH CLK_PCIE_ICH#

SRN49D9F-GP

CLK_PCIE_NEW CLK_PCIE_NEW#

SRN49D9F-GP

RN34

1 2 3

MINIC

RN42

2 3

GIGA

RN32

2 3

SATA

RN20

1 2 3

RN30

1 2 3

NEW

RN18

CLK_CPU_BCLK

CLK_CPU_BCLK#

SRN49D9F-GP

CLK_MCH_BCLK CLK_MCH_BCLK#

SRN49D9F-GP

CLK_PCIE_PEG CLK_PCIE_PEG#

SRN49D9F-GP

CLK_MCH_3GPLL CLK_MCH_3GPLL#

SRN49D9F-GP

RN18

1 2 3

RN16

1 2 3

RN31

1 2 3

VGA

RN36

1 2 3

CLK_ICH14

CLK_ICHPCI

CLK48_ICH

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet of

1 2

EC20 SC22P50V2JN-4GP

EC18 SC22P50V2JN-4GP

EC19 SC22P50V2JN-4GP

EC17 SC22P50V2JN-4GP

EC21 SC22P50V2JN-4GP

EC34 SC22P50V2JN-4GP

Clock Generator IDT CVT125PAG

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

AG1 -1

353Tuesday, January 10, 2006

H_RS#0 H_RS#1 H_RS#2

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK

XDP_TDI

XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

R605

1 2

0R0402-PAD

TP28 TPAD30TP28 TPAD30

TP20 TPAD30TP20 TPAD30 TP24 TPAD30TP24 TPAD30

TP45 TPAD30TP45 TPAD30 TP17 TPAD30TP17 TPAD30 TP16 TPAD30TP16 TPAD30 TP15 TPAD30TP15 TPAD30

TP27 TPAD30TP27 TPAD30

H_ADS# 6 H_BNR# 6

H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ#0 6

H_INIT# 15

H_LOCK# 6

H_CPURST# 6

H_TRDY# 6

H_HIT# 6 H_HITM# 6

TP41 TPAD30TP41 TPAD30 TP44 TPAD30TP44 TPAD30 TP46 TPAD30TP46 TPAD30 TP40 TPAD30TP40 TPAD30 TP43 TPAD30TP43 TPAD30 TP47 TPAD30TP47 TPAD30 TP39 TPAD30TP39 TPAD30 TP30 TPAD30TP30 TPAD30 TP33 TPAD30TP33 TPAD30 TP29 TPAD30TP29 TPAD30 TP42 TPAD30TP42 TPAD30 TP18 TPAD30TP18 TPAD30

H_THERMDA 19 H_THERMDC 19 PM_THRMTRIP-A# 7

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

1D05V_S0

3D3V_S0

U72A

4 4

3 3

2 2

1 1

H_A#[31..3]6

H_ADSTB#06 H_REQ#[4..0]6

H_ADSTB#16

H_A20M#15

H_FERR#15

H_IGNNE#15

H_STPCLK#15 H_INTR15 H_NMI15 H_SMI#15

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

TP37TPAD30 TP37TPAD30 TP31TPAD30 TP31TPAD30 TP36TPAD30 TP36TPAD30 TP35TPAD30 TP35TPAD30 TP26TPAD30 TP26TPAD30 TP25TPAD30 TP25TPAD30 TP34TPAD30 TP34TPAD30 TP32TPAD30 TP32TPAD30

TP19TPAD30 TP19TPAD30

TP14TPAD30 TP14TPAD30

U72A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

AA1

RSVD[01]

AA4

RSVD[02]

AB2

RSVD[03]

AA3

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

RSVD[08]

RSVD[09]

RSVD[10]

B25

RSVD[11]

BGA479-SKT6-GPU1

62.10079.001

2nd source: 62.10053.401

ADDR GROUP 0

DEFER#

DRDY#

DBSY#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

ADDR GROUP 1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TRST#

XDP/ITP SIGNALSH CLK

PROCHOT#

THERMDA THERMDC

THERM

THERMTRIP#

BCLK[0] BCLK[1]

RSVD[12]

RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17]

RESERVED

RSVD[18] RSVD[19] RSVD[20]

XDP_TDI

XDP_TMS

XDP_TDO

H_CPURST#

XDP_DBRESET#

ADS# BNR#

BPRI#

BR0#

IERR#

INIT#

HITM#

DBR#

H1 E2 G5

H5 F21 E1

D20 B3

B1 F3 F4 G3 G2

HIT#

AD4 AD3 AD1 AC4 AC2 AC1 AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6 C20

D21 A24 A25

A22 A21

T22

D2 F6 D3 C1 AF1 D22 C23 C24

R284 150R2F-1-GPR284 150R2F-1-GP

1 2

R282 39D2R3F-2-GPR282 39D2R3F-2-GP

1 2

R283 54D9R2F-L1-GP

1 2

R606 54D9R2F-L1-GP

1 2

R207 150R2F-1-GP

1 2

H_IERR#

H_RS#[2..0] 6

1D05V_S0

R613

R613 56R2J-4-GP

56R2J-4-GP

Place testpoint on H_IERR# with a GND

0.1" away

1D05V_S0

R595

R595 56R2J-4-GP

56R2J-4-GP

1 2

PM_THRMTRIP-I# 36

Layout Note:

0.5" max length.

2KR2F-3-GP

H_THERMDA

H_THERMDC

R596

0R2J-2-GP

1D05V_S0

R627

PM_THRMTRIP# should connect to ICH7 and Calistoga without T-ing

R628

R628 1KR2F-3-GP

1KR2F-3-GP

SC1KP16V2KX-GP

C675

C675 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

H_DSTBN#06 H_DSTBP#06 H_DINV#06

CPU_PROCHOT# 38

( No stub)

H_DSTBN#16 H_DSTBP#16 H_DINV#16

CPU_GTLREF0

C321

CPU_SEL03,7 CPU_SEL13,7 CPU_SEL23,7

R614 1KR2J-1-GP

1 2

R615 51R2F-2-GPR615 51R2F-2-GP

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

TEST2

U72B

E22

D[0]#

F24

D[1]#

E26

D[2]#

H22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H26

D[12]#

F26

D[13]#

K22

D[14]#

H25

D[15]#

H23

DSTBN[0]#

G22

DSTBP[0]#

J26

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L25

D[20]#

L22

D[21]#

L23

D[22]#

M23

D[23]#

P25

D[24]#

P22

D[25]#

P23

D[26]#

T24

D[27]#

R24

D[28]#

L26

D[29]#

T25

D[30]#

N24

D[31]#

M24

DSTBN[1]#

N25

DSTBP[1]#

M26

DINV[1]#

AD26

GTLREF

C26

TEST1

D25

TEST2

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

BGA479-SKT6-GPU1

MISC

DATA GRP 0 DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]#

DATA GRP 2

D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

DATA GRP 3

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23

AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20

R26 U26 U1 V1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3TEST1

H_DINV#[3..0] 6 H_DSTBN#[3..0] 6 H_DSTBP#[3..0] 6

H_D#[63..0] 6

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

R630 27D4R2F-L1-GPR630 27D4R2F-L1-GP

1 2

R629 54D9R2F-L1-GPR629 54D9R2F-L1-GP

1 2

R287 27D4R2F-L1-GPR287 27D4R2F-L1-GP

1 2

R286 54D9R2F-L1-GPR286 54D9R2F-L1-GP

1 2

H_DPRSLP# 15,38 H_DPSLP# 15 H_DPWR# 6

H_PWRGD 15,36

H_CPUSLP# 6,15 PSI# 38

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

Wistron Corporation

XDP_TCK

XDP_TRST#

R299 27D4R2F-L1-GPR299 27D4R2F-L1-GP

1 2

R301 680R3F-GPR301 680R3F-GP

1 2

All place within 2" to CPU

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

AG1 SC

453Tuesday, January 10, 2006

VCC_CORE_S0

4 4

3 3

2 2

1 1

U72C

VCC[001]

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

VCC[010]

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

VCC[033]

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

VCC[042]

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

BGA479-SKT6-GPU1

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCSENSE

VSSSENSE

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCA

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26

AD6 AF5 AE5 AF4 AE3 AF2 AE2

AF7

AE7

VCC_CORE_S0

CPU_V6

1 2

0R0402-PAD

C369

SCD1U10V2KX-4GP

H_VID0 38 H_VID1 38 H_VID2 38 H_VID3 38 H_VID4 38 H_VID5 38 H_VID6 38

H_VID[0..6] 38

R298

R298 100R2F-L1-GP-U

100R2F-L1-GP-U

1D05V_S0

R285

VCC_CORE_S0

Layout Note

1D5V_VCCA_S0

C674

SCD01U16V2KX-3GP

VCC_CORE_S0

R300

R300 100R2F-L1-GP-U

100R2F-L1-GP-U

Layout Note:

C715

SC10U10V5ZY-1GP

L22

1 2

HCB1608KF121T30-GP

VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

C346

SC10U10V5ZY-1GP

68.00230.041

C673

C673 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

VCC_SENSE 38

VSS_SENSE 38

C344

SC10U10V5ZY-1GP

C343

1D5V_S0

SC10U10V5ZY-1GP

1D05V_S0

SCD1U10V2KX-4GP

VCC_CORE_S0

SCD1U10V2KX-4GP

C701

C713

SC10U10V5ZY-1GP

C363

C364

SCD1U10V2KX-4GP

C716

C700

SCD1U10V2KX-4GP

C702

SC10U10V5ZY-1GP

C348

C348 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C365

SCD1U10V2KX-4GP

C703

C714

SC10U10V5ZY-1GP

C342

C347

SCD1U10V2KX-4GP

C676

C341

SC10U10V5ZY-1GP

C677

C370

SC10U10V5ZY-1GP

C340

SCD1U10V2KX-4GP

C680

C711

C711 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

C682

SC10U10V5ZY-1GP

C683

C712

SC10U10V5ZY-1GP

C368

SC4D7U6D3V3KX-GP

C678

C366

SC10U10V5ZY-1GP

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

U72D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

A26

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

BGA479-SKT6-GPU1

VSS[082]

P21

VSS[083]

P24

VSS[084]

VSS[085]

VSS[086]

R22

VSS[087]

R25

VSS[088]

VSS[089]

VSS[090]

T23

VSS[091]

T26

VSS[092]

VSS[093]

VSS[094]

U21

VSS[095]

U24

VSS[096]

VSS[097]

VSS[098]

V22

VSS[099]

V25

VSS[100]

VSS[101]

VSS[102]

W23

VSS[103]

W26

VSS[104]

VSS[105]

VSS[106]

Y21

VSS[107]

Y24

VSS[108]

AA2

VSS[109]

AA5

VSS[110]

AA8

VSS[111]

AA11

VSS[112]

AA14

VSS[113]

AA16

VSS[114]

AA19

VSS[115]

AA22

VSS[116]

AA25

VSS[117]

AB1

VSS[118]

AB4

VSS[119]

AB8

VSS[120]

AB11

VSS[121]

AB13

VSS[122]

AB16

VSS[123]

AB19

VSS[124]

AB23

VSS[125]

AB26

VSS[126]

AC3

VSS[127]

AC6

VSS[128]

AC8

VSS[129]

AC11

VSS[130]

AC14

VSS[131]

AC16

VSS[132]

AC19

VSS[133]

AC21

VSS[134]

AC24

VSS[135]

AD2

VSS[136]

AD5

VSS[137]

AD8

VSS[138]

AD11

VSS[139]

AD13

VSS[140]

AD16

VSS[141]

AD19

VSS[142]

AD22

VSS[143]

AD25

VSS[144]

AE1

VSS[145]

AE4

VSS[146]

AE8

VSS[147]

AE11

VSS[148]

AE14

VSS[149]

AE16

VSS[150]

AE19

VSS[151]

AE23

VSS[152]

AE26

VSS[153]

AF3

VSS[154]

AF6

VSS[155]

AF8

VSS[156]

AF11

VSS[157]

AF13

VSS[158]

AF16

VSS[159]

AF19

VSS[160]

AF21

VSS[161]

AF24

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

AG1 SA

553Tuesday, January 10, 2006

H_XRCOMP

R643

R643 24D9R2F-L-GP

24D9R2F-L-GP

4 4

1D05V_S0

R647

R647 54D9R2F-L1-GP

54D9R2F-L1-GP

1 2

H_XSCOMP

1D05V_S0

R645

R645 221R2F-2-GP

221R2F-2-GP

H_XSWING

3 3

2 2

1D05V_S0

1 2

1D05V_S0

R644

R644 100R2F-L1-GP-U

100R2F-L1-GP-U

H_YRCOMP

R639

R639 24D9R2F-L-GP

24D9R2F-L-GP

R642

R642 54D9R2F-L1-GP

54D9R2F-L1-GP

H_YSCOMP

R641

R641 221R2F-2-GP

221R2F-2-GP

H_YSWING

R640

R640 100R2F-L1-GP-U

100R2F-L1-GP-U

H_D#[63..0]4

C743

C743 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 2

C741

C741 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 2

U71A

W11

AB7 AA9

AB8

AA4 AA7 AA2 AA6

AA10

AA1 AB4

AC9 AB11 AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5 AD10

AD4

AC8

AG2

AG1

K11

T10

U11 T11

Y10

J6 H3 K2 G1 G2 K9 K1 K7

J8 H4

T3 U7 U9

T1 T8 T4

U5 T9

W4 W3

Y3 Y7

E1 E2 E4

Y1 U1

U71A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_XRCOMP H_XSCOMP H_XSWING

H_YRCOMP H_YSCOMP H_YSWING

H_CLKIN H_CLKIN#

CALISTOGA

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_XRCOMP H_XSCOMP H_XSWING

H_YRCOMP H_YSCOMP H_YSWING

CLK_MCH_BCLK3

CLK_MCH_BCLK#3

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31

H_ADS#

H_VREF_0

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_VREF_1

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_SLPCPU#

H_TRDY#

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13

J7 W8 U3 AB10

K4 T7 Y5 AC4

K3 T6 AA5 AC5

D3 D4 B3

D8 G8 B8 F8 A8

B4 E6 D6

E3 E7

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_VREF

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

R646

1 2

0R0402-PAD

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4

H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_CPURST# 4

H_DBSY# 4

H_DEFER# 4 H_DPWR# 4

H_DRDY# 4

H_HIT# 4 H_HITM# 4

H_LOCK# 4

H_CPUSLP# 4,15 H_TRDY# 4

H_A#[31..3] 4

C362

C362 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 2

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

1D05V_S0

H_RS#[2..0] 4

R274

R274 100R2F-L1-GP-U

100R2F-L1-GP-U

R246

R246 200R2F-L-GP

200R2F-L-GP

1 1

Place them near to the chip ( < 0.5")

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

GMCH (1 of 5)

AG1 SA

653Tuesday, January 10, 2006

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

AY35

AR1

AW7

AW40

AW35

AT1 AY7

AY40

AU20 AT20 BA29 AY29

AW13 AW12

AY21

AW21

AL20 AF10

BA13 BA12 AY20 AU21

AV9 AT9

AK1

AK41

AF33

AG33

AE35

AF39 AG35 AH39

AC35 AE39

AF35 AG39

AE37

AF41 AG37 AH41

AC37 AE41

AF37 AG41

A27 A26 C40 D41

SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3

SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3

SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_OCDCOMP_0 SM_OCDCOMP_1

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP# SM_RCOMP

SM_VREF_0 SM_VREF_1

G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

CALISTOGA

M_CLK_DDR011 M_CLK_DDR111 M_CLK_DDR211 M_CLK_DDR311

M_CLK_DDR#011 M_CLK_DDR#111 M_CLK_DDR#211 M_CLK_DDR#311

4 4

R244

R244 40D2R2F-GP

40D2R2F-GP

3 3

2 2

1 1

M_CKE011,12 M_CKE111,12 M_CKE211,12 M_CKE311,12

M_CS0#11,12 M_CS1#11,12 M_CS2#11,12 M_CS3#11,12

R273

R273 40D2R2F-GP

40D2R2F-GP

DDR_VREF_S3

C737

SCD1U16V2ZY-2GP

DMI_TXN[3..0]16

DMI_TXP[3..0]16

DMI_RXN[3..0]16

DMI_RXP[3..0]16

3D3V_S0

RN43

1 2 3

SRN10KJ-5-GP

1D8V_S3

R271

R271 80D6R2F-L-GP

80D6R2F-L-GP

R272

R272 80D6R2F-L-GP

80D6R2F-L-GP

M_OCDCOMP0 M_OCDCOMP1

M_ODT011,12 M_ODT111,12 M_ODT211,12 M_ODT311,12

CLK_MCH_3GPLL#3 CLK_MCH_3GPLL3

C667

C667 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

PM_EXTTS#0

PM_EXTTS#1

M_RCOMPN

M_RCOMPP

M_RCOMPN M_RCOMPP

DMI_TXP3

CFGRSVD

DDR MUXINGCLKDMI

PM_THRMTRIP#

MISC

SDVO_CTRLCLK

SDVO_CTRLDATA

3D3V_S0

RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8

RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8

CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1

PWROK

RSTIN#

LT_RESET#

NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

R254

1 2

DUMMY-R2

DUMMY-R2 R242

R242

1 2

DUMMY-R2

DUMMY-R2 R241

R241

1 2

DUMMY-R2

DUMMY-R2 R249

R249

1 2

DUMMY-R2

DUMMY-R2 R255

R255

1 2

DUMMY-R2

DUMMY-R2 R247

R247

1 2

DUMMY-R2

DUMMY-R2 R260

R260

1 2

DUMMY-R2

DUMMY-R2 R253

R253

1 2

DUMMY-R2

DUMMY-R2 R252

R252

1 2

DUMMY-R2

DUMMY-R2 R259

R259

1 2

DUMMY-R2

DUMMY-R2 R251

R251

1 2

DUMMY-R2

R256

1 2

2K2R2J-2-GP

2K2R2J-2-GP R277

R277

1 2

DUMMY-R2

DUMMY-R2 R275

R275

1 2

DUMMY-R2

DUMMY-R2 R248

R248

1 2

DUMMY-R2

DUMMY-R2 R258

R258

1 2

DUMMY-R2

DUMMY-R2 R250

R250

1 2

DUMMY-R2

DUMMY-R2 R276

R276

1 2

DUMMY-R2

NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

U71B

H32 T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41 A35 A34 D28 D27

K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26

G28 F25 H26 G6 AH33 AH34

H28 H27 K28

D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

PM_EXTTS#0 PM_EXTTS#1

1 2

CFG18

CFG19

CFG20

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

CFG16

CFG17

CPU_SEL0 3,4 CPU_SEL1 3,4 CPU_SEL2 3,4

SEL1

SEL2

0 0

0 1 1 100M 1 1

PM_BMBUSY# 16

PM_THRMTRIP-A# 4

R238

R238 100R2J-2-GP

100R2J-2-GP

TP13 TPAD30TP13 TPAD30 TP12 TPAD30TP12 TPAD30

MCH_ICH_SYNC# 16

When High 1K Ohm

CFG6:

0=Moby Dick ,1=Calistoga (default)

When Low choice lower than 3.5K Ohm

CPU

SEL0

266M

01200M 1 00333M 1 0 1

R237

1 2

0R2J-2-GP

R239

1 2

0R0402-PAD

RN97

RN97 SRN10KJ-5-GP

SRN10KJ-5-GP

2 3

133M

166M

400M

Reserved

1D05V_S03D3V_S0

VGATE_PWRGD 16,38,48

PWROK 16,19

0 1 1 0 0 1 1

PLT_RST1# 16,20,26,30,31,32,34,35,45

When PM replace to GM

1D5V_S0

GMCH_DDCCLK

GMCH_DDCDATA

D32

H30 H29 G26 G25 B38 C35 F32 C33 C32

A33 A32 E27 E26

C37 B35 A37

B37 B34 A36

G30 D30 F29

F30 D29 F28

A16 C18 A19

B16 B18 B19

E23 D23 C22 B22 A21 B21

C26 C25 G23

H23

J30

J20

J22

U71C

CALISTOGA

L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL

LA_CLK# LA_CLK LB_CLK# LB_CLK

LA_DATA#_0 LA_DATA#_1 LA_DATA#_2

LA_DATA_0 LA_DATA_1 LA_DATA_2

LB_DATA#_0 LB_DATA#_1 LB_DATA#_2

LB_DATA_0 LB_DATA_1 LB_DATA_2

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT

TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC

LVDS

VGA

1D5V_PCIE_S0

R594

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8

EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15

EXP_A_RXP_0

EXP_A_RXP_1

EXP_A_RXP_2

EXP_A_RXP_3

EXP_A_RXP_4

EXP_A_RXP_5

EXP_A_RXP_6

EXP_A_RXP_7

EXP_A_RXP_8

EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12

PCI-EXPRESS GRAPHICS

EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15

EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8

EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

D40 D38

PEG_RXN0

F34

PEG_RXN1

G38

PEG_RXN2

H34

PEG_RXN3

J38

PEG_RXN4

L34

PEG_RXN5

M38

PEG_RXN6

N34

PEG_RXN7

P38

PEG_RXN8

R34

PEG_RXN9

T38

PEG_RXN10

V34

PEG_RXN11

W38

PEG_RXN12

Y34

PEG_RXN13

AA38

PEG_RXN14

AB34

PEG_RXN15

AC38

PEG_RXP0

D34

PEG_RXP1

F38

PEG_RXP2

G34

PEG_RXP3

H38

PEG_RXP4

J34

PEG_RXP5

L38

PEG_RXP6

M34

PEG_RXP7

N38

PEG_RXP8

P34

PEG_RXP9

R38

PEG_RXP10

T34

PEG_RXP11

V38

PEG_RXP12

W34

PEG_RXP13

Y38

PEG_RXP14

AA34

PEG_RXP15

AB38

GTXN0 PEG_TXN0

F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40

D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40

1 2

GTXN1

C298 SCD1U16V2KX-3GPC298 SCD1U16V2KX-3GP

1 2

GTXN2

C297 SCD1U16V2KX-3GPC297 SCD1U16V2KX-3GP

1 2

GTXN3

C294 SCD1U16V2KX-3GPC294 SCD1U16V2KX-3GP

1 2

GTXN4

C293 SCD1U16V2KX-3GPC293 SCD1U16V2KX-3GP

1 2

GTXN5

C290 SCD1U16V2KX-3GPC290 SCD1U16V2KX-3GP

1 2

GTXN6

C289 SCD1U16V2KX-3GPC289 SCD1U16V2KX-3GP

1 2

GTXN7

C287 SCD1U16V2KX-3GPC287 SCD1U16V2KX-3GP

1 2

GTXN8

C284 SCD1U16V2KX-3GPC284 SCD1U16V2KX-3GP

1 2

GTXN9

C283 SCD1U16V2KX-3GPC283 SCD1U16V2KX-3GP

1 2

GTXN10

C280 SCD1U16V2KX-3GPC280 SCD1U16V2KX-3GP

1 2

GTXN11

C279 SCD1U16V2KX-3GPC279 SCD1U16V2KX-3GP

1 2

GTXN12

C248 SCD1U16V2KX-3GPC248 SCD1U16V2KX-3GP

1 2

GTXN13

C277 SCD1U16V2KX-3GPC277 SCD1U16V2KX-3GP

1 2

C245 SCD1U16V2KX-3GPC245 SCD1U16V2KX-3GP

1 2

GTXN15

C275 SCD1U16V2KX-3GPC275 SCD1U16V2KX-3GP

1 2

C273 SCD1U16V2KX-3GPC273 SCD1U16V2KX-3GP

GTXP0 PEG_TXP0

1 2

GTXP1

C300 SCD1U16V2KX-3GPC300 SCD1U16V2KX-3GP

1 2

GTXP2

C299 SCD1U16V2KX-3GPC299 SCD1U16V2KX-3GP

1 2

GTXP3

C296 SCD1U16V2KX-3GPC296 SCD1U16V2KX-3GP

1 2

GTXP4

C295 SCD1U16V2KX-3GPC295 SCD1U16V2KX-3GP

1 2

GTXP5

C292 SCD1U16V2KX-3GPC292 SCD1U16V2KX-3GP

1 2

GTXP6

C291 SCD1U16V2KX-3GPC291 SCD1U16V2KX-3GP

1 2

GTXP7

C288 SCD1U16V2KX-3GPC288 SCD1U16V2KX-3GP

1 2

GTXP8

C286 SCD1U16V2KX-3GPC286 SCD1U16V2KX-3GP

1 2

GTXP9

C285 SCD1U16V2KX-3GPC285 SCD1U16V2KX-3GP

1 2

GTXP10

C282 SCD1U16V2KX-3GPC282 SCD1U16V2KX-3GP

1 2

GTXP11

C281 SCD1U16V2KX-3GPC281 SCD1U16V2KX-3GP

1 2

GTXP12

C249 SCD1U16V2KX-3GPC249 SCD1U16V2KX-3GP

1 2

GTXP13

C278 SCD1U16V2KX-3GPC278 SCD1U16V2KX-3GP

1 2

GTXP14

C247 SCD1U16V2KX-3GPC247 SCD1U16V2KX-3GP

1 2

GTXP15 PEG_TXP15

C276 SCD1U16V2KX-3GPC276 SCD1U16V2KX-3GP

1 2

C274 SCD1U16V2KX-3GPC274 SCD1U16V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (2 of 5)

AG1 -1

24D9R2F-L-GP

PEG_RXN[15..0] 45

PEG_RXP[15..0] 45

PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14GTXN14 PEG_TXN15

PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14

753Tuesday, January 10, 2006

PEG_TXN[15..0]45

PEG_TXP[15..0]45

4 4

U71D

M_A_DQ[63..0]11

3 3

2 2

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AJ35

AJ34 AM31 AM33

AJ36 AK35

AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26

AL27 AM26 AN24 AK28

AL28 AM24 AP26 AP23

AL22 AP21 AN20

AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12

AL14

AL12

AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2

AW2

AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

U71D

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

CALISTOGA

M_B_DQ[63..0]11

AU12

SA_BS_0

AV14

SA_BS_1

BA20

SA_BS_2

AY13

SA_CAS#

AJ33

SA_DM_0

AM35

SA_DM_1

AL26

SA_DM_2

AN22

SA_DM_3

AM14

SA_DM_4

AL9

SA_DM_5

AR3

SA_DM_6

AH4

SA_DM_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

SA_RAS#

SA_WE#

AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5

AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12

AW14 AK23 AK24 AY14

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_10

SA_MA_11

SA_MA_12

SA_MA_13

SA_RCVENIN#

SA_RCVENOUT#

DDR SYSTEM MEMORY A

M_A_CAS# 11,12

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4

M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

SA_RCVENIN# SA_RCVENOUT#

Place Test PAD Near to Chip as could as possible

M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12

M_A_DM[7..0] 11

M_A_DQS[7..0] 11

M_A_DQS#[7..0] 11

M_A_A[13..0] 11,12

M_A_RAS# 11,12

TP23 TPAD30TP23 TPAD30 TP11 TPAD30TP11 TPAD30

M_A_WE# 11,12

U71E

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AK39

AJ37 AP39 AR41

AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40

AW38

AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31

AW31

AV29

AW29

AM19

AL19 AP14 AN14 AN17 AM16 AP15

AL15

AJ11 AH10

AN10 AK13 AH11 AK10

BA10

AW10

BA4

AW4 AY10

AY9

AW5

AY5 AV4 AR5 AK4 AK3 AT4 AK5

AJ9

AJ8

AJ5 AJ3

U71E

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

CALISTOGA

AT24

SB_BS_0

AV23

SB_BS_1

AY28

SB_BS_2

AR24

SB_CAS#

AK36

SB_DM_0

AR38

SB_DM_1

AT36

SB_DM_2

BA31

SB_DM_3

AL17

SB_DM_4

AH8

SB_DM_5

BA5

SB_DM_6

AN4

SB_DM_7

AM39

SB_DQS_0

AT39

SB_DQS_1

AU35

SB_DQS_2

AR29

SB_DQS_3

AR16

SB_DQS_4

AR10

SB_DQS_5

AR7

SB_DQS_6

AN5

SB_DQS_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_WE#

AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5

AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23

AU23 AK16 AK18 AR27

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_RCVENIN#

SB_RCVENOUT#

DDR SYSTEM MEMORY B

M_B_CAS# 11,12

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7M_A_DQS5 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

SB_RCVENIN# SB_RCVENOUT#

Place Test PAD Near to Chip ascould as possible

M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12

M_B_DM[7..0] 11

M_B_DQS[7..0] 11

M_B_DQS#[7..0] 11

M_B_A[13..0] 11,12

M_B_RAS# 11,12

M_B_WE# 11,12

TP22 TPAD30TP22 TPAD30 TP21 TPAD30TP21 TPAD30

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

GMCH (3 of 5)

AG1 SA

853Tuesday, January 10, 2006

R593

2D5V_S0

C401

SC10U10V5ZY-1GP

C738

C738 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

1D5V_HPLL_S0

C400

1D5V_MPLL_S0

SCD1U10V2KX-4GP

C739

C739 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2D5V_3GBG_S0

4 4

SCD1U10V2KX-4GP

1D5V_S0

3 3

2 2

1 1

C672

1 2

HCB1608KF121T30-GP

68.00230.041

1 2

HCB1608KF121T30-GP

68.00230.041

0R0603-PAD

L11

L30

1D5V_S0

1D5V_S0 1D5V_PCIE_S0

R592

0R0805-PAD

1D5V_3GPLL_S0

1 2

R240 0R0603-PADR240 0R0603-PAD

SC4D7U6D3V3KX-GP

3D3V_S0

0R0603-PAD

0R0805-PAD

C316

R619

1D5V_S0

SC4D7U6D3V3KX-GP

1D5V_S0

1 2

0R0805-PAD

C670

0R0603-PAD

R245

C669

C315

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

C698

SC10U10V5ZY-1GP

1D5V_QTVDAC_S0

R620

SCD1U10V2KX-4GP

C336

C668

SC4D7U6D3V3KX-GP

1D5V_S0

SCD1U10V2KX-4GP

C697

C697 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C338

C314

SCD1U10V2KX-4GP

C671

SCD1U10V2KX-4GP

1D05V_S0

1D5V_S0

R257

0R0603-PAD

1D5V_AUX

C330

SCD1U10V2KX-4GP

2D5V_3GBG_S0

1D5V_TVDAC_S0

C339

1D5V_HPLL_S0

1D5V_MPLL_S0

C334

SCD1U10V2KX-4GP

1D5V_S0

U71H

H22

VCCSYNC

C30

VCC_TXLVDS0

B30

VCC_TXLVDS1

A30

VCC_TXLVDS2

AJ41

VCC3G0

AB41

VCC3G1

Y41

VCC3G2

V41

VCC3G3

R41

VCC3G4

N41

VCC3G5

L41

VCC3G6

AC33

VCCA_3GPLL

G41

VCCA_3GBG

H41

VSSA_3GBG

F21

VCCA_CRTDAC0

E21

VCCA_CRTDAC1

G21

VSSA_CRTDAC

B26

VCCA_DPLLA

C39

VCCA_DPLLB

AF1

VCCA_HPLL

A38

VCCA_LVDS

B39

VSSA_LVDS

AF2

VCCA_MPLL

H20

VCCA_TVBG

G20

VSSA_TVBG

E19

VCCA_TVDACA0

F19

VCCA_TVDACA1

C20

VCCA_TVDACB0

D20

VCCA_TVDACB1

E20

VCCA_TVDACC0

F20

VCCA_TVDACC1

AH1

VCCD_HMPLL0

AH2

VCCD_HMPLL1

A28

VCCD_LVDS0

B28

VCCD_LVDS1

C28

VCCD_LVDS2

D21

VCCD_TVDAC

A23

VCC_HV0

B23

VCC_HV1

B25

VCC_HV2

H19

VCCD_QTVDAC

AK31

VCCAUX0

AF31

VCCAUX1

AE31

VCCAUX2

AC31

VCCAUX3

AL30

VCCAUX4

AK30

VCCAUX5

AJ30

VCCAUX6

AH30

VCCAUX7

AG30

VCCAUX8

AF30

VCCAUX9

AE30

VCCAUX10

AD30

VCCAUX11

AC30

VCCAUX12

AG29

VCCAUX13

AF29

VCCAUX14

AE29

VCCAUX15

AD29

VCCAUX16

AC29

VCCAUX17

AG28

VCCAUX18

AF28

VCCAUX19

AE28

VCCAUX20

AH22

VCCAUX21

AJ21

VCCAUX22

AH21

VCCAUX23

AJ20

VCCAUX24

AH20

VCCAUX25

AH19

VCCAUX26

P19

VCCAUX27

P16

VCCAUX28

AH15

VCCAUX29

P15

VCCAUX30

AH14

VCCAUX31

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12 AD12

VCCAUX39 VCCAUX40

SCD1U10V2KX-4GP

POWER

CALISTOGA

VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76

AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1

SCD1U10V2KX-4GP

VCCP_GMCH_CAP3

VCCP_GMCH_CAP2 VCCP_GMCH_CAP1

C740

SCD47U10V3ZY-GP

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

C361

SC2D2U6D3V3MX-1-GP

C710

C710 SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

GMCH (4 of 5)

AG1 SA

1D05V_S0

C332

C744

C744 SCD47U10V3ZY-GP

SCD47U10V3ZY-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

953Tuesday, January 10, 2006

C742

SC4D7U10V5ZY-3GP

U71G

1D05V_S0

4 4

3 3

2 2

1 1

AA33

W33

AA32

W32

M32

AA31

W31

M31

AA30

W30

M30

AA29

W29

M29

AB28 AA28

M28

M27

M25

M24 AB23 AA23

M23

AC22 AB22

W22

M22

AC21 AA21

W21

M21

AC20 AB20

W20

M20

AB19 AA19

M19

M18

M17

M16

P33 N33 L33

Y32

V32 P32 N32

L32

V31 T31 R31 P31 N31

Y30

V30 U30 T30 R30 P30 N30

L30

Y29

V29 U29 R29 P29

L29

Y28 V28 U28 T28 R28 P28 N28

L28 P27 N27

L27 P26 N26 L26 N25

L25 P24 N24

Y23 P23 N23

L23

Y22

P22 N22

L22

N21

L21

Y20

P20 N20

L20

Y19 N19

L19 N18

L18 P17 N17

N16

L16

U71G

VCC_0 VCC_1 VCC_2 VCC_3 VCC_4

J33

VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13

J32

VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110

VCC

VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98

VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107

VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9

AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1

SC10U10V5ZY-1GP

CALISTOGA

ST220U2VBM-3GP

1D05V_S0

C320

SC10U10V5ZY-1GP

TC21

U71F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21 U21 T21 R21

AD20

V20 U20 T20 R20

AD19

V19 U19

T19 AD18 AC18 AB18 AA18

Y18

W18

V18

U18

T18

C337

VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72

SCD1U10V2KX-4GP

NCTF

CALISTOGA

C317

SCD1U10V2KX-4GP

C319

SCD1U10V2KX-4GP

Place these Caps close VCC_0 ~ VCC_110

1D8V_S3

SC10U10V5ZY-1GP

C708

C360

SCD1U10V2KX-4GP

C736

SCD1U10V2KX-4GP

VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8

VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12

VCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8

VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57

C333

SCD1U10V2KX-4GP

C331

SCD1U10V2KX-4GP

U71I

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

AV40 AP40 AN40 AK40

AJ40 AH40 AG40

AF40 AE40

AY39

AW39

AV39 AR39 AN39

AJ39 AC39 AB39 AA39

W39

AT38 AM38 AH38 AG38

AF38 AE38

AK37 AH37 AB37 AA37

W37

AY36

AW36

AN36 AH36 AG36

AF36 AE36 AC36

BA35 AV35 AR35 AH35 AB35 AA35

W35

AN34

P41 M41

J41 F41

B40

Y39

V39

T39 R39 P39 N39 M39

L39

J39 H39 G39

F39 D39

C38

Y37

V37

T37 R37 P37 N37 M37

L37

J37 H37 G37

F37 D37

C36 B36

Y35

V35

T35 R35 P35 N35 M35

L35

J35 H35 G35

F35 D35

SCD1U16V2ZY-2GP

VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96

CALISTOGA

C709

SCD1U16V2ZY-2GP

C686

VSS

SCD1U16V2ZY-2GP

C313

AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17

AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15

C335

C359

SCD1U10V2KX-4GP

1D5V_AUX

C318

SCD1U10V2KX-4GP

C399

SCD1U10V2KX-4GP

TC20

TC20 ST220U2VBM-3GP

ST220U2VBM-3GP

C695

SCD1U16V2ZY-2GP

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

AT23 AN23 AM23 AH23 AC23

W23

K23

C23

AA22

K22 G22

E22 D22

A22 BA21 AV21 AR21 AN21

AL21

AB21

Y21

P21

K21

H21

C21

AW20

AR20 AM20 AA20

K20

B20

A20 AN19 AC19

W19

K19

G19

C19 AH18

P18

H18

D18

A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16

AL16

C16 AN15 AM15 AK15

N15

M15

B15

A15 BA14

AT14 AK14 AD14 AA14

U14 K14 H14

E14 AV13 AR13 AN13 AM13

AL13

AG13

P13

D13

B13 AY12 AC12

K12

H12

E12 AD11 AA11

Y11

U71J

VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186

J23

VSS_187

F23

VSS_188 VSS_189 VSS_190 VSS_191 VSS_192

F22

VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205

J21

VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234

J16

VSS_235

F16

VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242

L15

VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261

F13

VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272

VSS

CALISTOGA

GMCH (5 of 5)

AG1

J11

VSS_273

D11

VSS_274

B11

VSS_275

AV10

VSS_276

AP10

VSS_277

AL10

VSS_278

AJ10

VSS_279

AG10

VSS_280

AC10

VSS_281

W10

VSS_282

U10

VSS_283

BA9

VSS_284

AW9

VSS_285

AR9

VSS_286

AH9

VSS_287

AB9

VSS_288

VSS_289

VSS_290

VSS_291

VSS_292

VSS_293

AG8

VSS_294

AD8

VSS_295

AA8

VSS_296

VSS_297

VSS_298

VSS_299

BA7

VSS_300

AV7

VSS_301

AP7

VSS_302

AL7

VSS_303

AJ7

VSS_304

AH7

VSS_305

AF7

VSS_306

AC7

VSS_307

VSS_308

VSS_309

VSS_310

AG6

VSS_311

AD6

VSS_312

AB6

VSS_313

VSS_314

VSS_315

VSS_316

VSS_317

VSS_318

VSS_319

AV5

VSS_320

AF5

VSS_321

AD5

VSS_322

AY4

VSS_323

AR4

VSS_324

AP4

VSS_325

AL4

VSS_326

AJ4

VSS_327

VSS_328

VSS_329

VSS_330

VSS_331

VSS_332

VSS_333

AY3

VSS_334

AW3

VSS_335

AV3

VSS_336

AL3

VSS_337

AH3

VSS_338

AG3

VSS_339

AF3

VSS_340

AD3

VSS_341

AC3

VSS_342

AA3

VSS_343

VSS_344

AT2

VSS_345

AR2

VSS_346

AP2

VSS_347

AK2

VSS_348

AJ2

VSS_349

AD2

VSS_350

AB2

VSS_351

VSS_352

VSS_353

VSS_354

VSS_355

VSS_356

VSS_357

VSS_358

VSS_359

AL1

VSS_360

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 53Tuesday, January 10, 2006

DM1

M_B_A[13..0]8,12

4 4

M_B_BS#28,12

M_B_BS#08,12 M_B_BS#18,12

M_B_DQ[63..0]8

3 3

2 2

M_B_DQS#[7..0]8

M_B_DQS[7..0]8

1 1

M_ODT27,12 M_ODT37,12

DDR_VREF_S3

SC2D2U6D3V3MX-1-GP

C328

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

BC4

SCD1U16V2ZY-2GP

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

DM1

102

101

100

105

A10/AP

A11

A12

116

A13

A14

A15

A16/BA2

107

BA0

106

BA1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

/DQS0

/DQS1

/DQS2

/DQS3

129

/DQS4

146

/DQS5

167

/DQS6

186

/DQS7

DQS0

DQS1

DQS2

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

ODT0

119

ODT1

VREF

VSS

202

GND

DDR2-200P-5-GP 62.10017.771

High 5.2mm 2nd source:62.10017.661

/RAS

/WE

/CAS

/CS0 /CS1

CKE0 CKE1

CK0

/CK0

CK1

/CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

VDDSPD

SA0 SA1

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NORMAL TYPE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

108 109 113

110 115

79 80

30 32

164 166

10 26 52 67 130 147 170 185

195 197

199

198 200

SCD1U16V2ZY-2GP

69 83 120 163

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

BC6

1D8V_S3

M_B_RAS# 8,12

M_B_WE# 8,12

M_B_CAS# 8,12

M_CS2# 7,12 M_CS3# 7,12

M_CKE2 7,12 M_CKE3 7,12

M_CLK_DDR3 7 M_CLK_DDR#3 7

M_CLK_DDR2 7 M_CLK_DDR#2 7

M_B_DM[7..0] 8

SMBD_ICH 3,18 SMBC_ICH 3,18

R363

1 2

10KR2J-3-GP

Place near DM2

3D3V_S0

M_CLK_DDR3

C326

C326 SC10P50V2JN-4GP

SC10P50V2JN-4GP

M_CLK_DDR#3

M_CLK_DDR2

C448

C448 SC10P50V2JN-4GP

SC10P50V2JN-4GP

M_CLK_DDR#2

M_A_A[13..0]8,12

M_A_BS#28,12

M_A_BS#08,12 M_A_BS#18,12

M_A_DQ[63..0]8

M_A_DQS#[7..0]8

M_A_DQS[7..0]8

M_ODT07,12 M_ODT17,12

DDR_VREF_S3

SC2D2U6D3V3MX-1-GP

C696

DDR_VREF_S3

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

BC10

SCD1U16V2ZY-2GP

DM2

102

101

100

105

A10/AP

A11

A12

116

A13

A14

A15

A16/BA2

107

BA0

106

BA1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

/DQS0

/DQS1

/DQS2

/DQS3

129

/DQS4

146

/DQS5

167

/DQS6

186

/DQS7

DQS0

DQS1

DQS2

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

ODT0

119

ODT1

VREF

VSS

202

GND

DDR2-200P-4-GP 62.10017.761

High 9.2mm 2nd source:62.10017.A61

/RAS

/WE

/CAS

/CS0 /CS1

CKE0 CKE1

CK0

/CK0

CK1

/CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

VDDSPD

SA0 SA1

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NORMAL TYPE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GND

108 109 113

110 115

79 80

30 32

164 166

M_A_DM0

M_A_DM1

M_A_DM2

M_A_DM3

M_A_DM4

130

M_A_DM5

147

M_A_DM6

170

M_A_DM7

185

SMBD_ICH

195

SMBC_ICH

197

199

198 200

50 69 83 120 163

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201

1D8V_S3

Title

Size Document Number Rev

Custom

Date: Sheet

M_A_RAS# 8,12 M_A_WE# 8,12 M_A_CAS# 8,12

M_CS0# 7,12 M_CS1# 7,12

M_CKE0 7,12 M_CKE1 7,12

M_CLK_DDR0 7 M_CLK_DDR#0 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

M_A_DM[7..0] 8

BC7

SCD1U16V2ZY-2GP

DDR2 Socket

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

AG1 SB

Place near DM1

M_CLK_DDR0

C329

C329 SC10P50V2JN-4GP

SC10P50V2JN-4GP

M_CLK_DDR#0

M_CLK_DDR1

C449

C449 SC10P50V2JN-4GP

SC10P50V2JN-4GP

M_CLK_DDR#1

3D3V_S0

11 53Tuesday, January 10, 2006

PARALLEL TERMINATION Decoupling Capacitor

DDR_VREF_S0

4 4

3 3

2 2

1 1

Put decap near power(0.9V) and pull-up resistor

RN55

8 7 6

SRN56J-2-GP

1 2 1 2 1 2 1 2

RN62

8 7 6

SRN56J-2-GP

RN60

8 7 6

SRN56J-2-GP

RN59

8 7 6

SRN56J-2-GP

RN54

8 7 6

SRN56J-2-GP

RN61

8 7 6

SRN56J-2-GP

RN63

8 7 6

SRN56J-2-GP

RN65

8 7 6

SRN56J-2-GP

RN66

8 7 6

SRN56J-2-GP

RN56

8 7 6

SRN56J-2-GP

RN64

8 7 6

SRN56J-2-GP

RN67

8 7 6

SRN56J-2-GP

M_B_A12

M_B_A9

R314 56R2J-4-GPR314 56R2J-4-GP R312 56R2J-4-GPR312 56R2J-4-GP R315 56R2J-4-GPR315 56R2J-4-GP R313 56R2J-4-GPR313 56R2J-4-GP

M_B_A5

M_B_A3

M_B_A1

M_B_A10

M_B_A13

1 2 3 45

M_B_A0

M_B_A2

M_B_A4

M_B_A6

M_B_A7

M_B_A11

3 45

1 2 3 45

M_A_A13

1 2 3 45

M_A_A0

M_A_A2

M_A_A4

1 2 3 45

1 2

M_A_A12

M_A_A8

M_A_A6

M_A_A7

M_A_A11

3 45

M_A_A5

M_A_A3

M_A_A1

M_A_A10

M_A_A9 M_B_A8

M_CKE2 7,11 M_B_BS#2 8,11

M_ODT2 7,11 M_CS2# 7,11 M_B_RAS# 8,11

M_B_BS#1 8,11

M_CKE3 7,11

M_B_BS#0 8,11 M_B_WE# 8,11 M_CS3# 7,11 M_B_CAS# 8,11

M_ODT0 7,11 M_CS0# 7,11 M_A_RAS# 8,11

M_A_BS#1 8,11

M_A_BS#0 8,11 M_A_WE# 8,11 M_A_CAS# 8,11 M_CS1# 7,11

M_CKE0 7,11 M_A_BS#2 8,11

M_CKE1 7,11

M_ODT1 7,11 M_ODT3 7,11

M_A_A[13..0] 8,11

M_B_A[13..0] 8,11

DDR_VREF_S0

1D8V_S3

C435

C435 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C418

C418 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C733

C733 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C382

C382 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Put decap near power(0.9V) and pull-up resistor

C419

C419 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C396

C396 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C734

C734 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C389

C389 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C383

C383 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C387

C413

C413 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C415

C415 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C387 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C434

C434 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Place these Caps near DM1

C735

C735 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C414

C388

SCD1U16V2ZY-2GP

Place these Caps near DM2

C392

C392 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C416

C393

SCD1U16V2ZY-2GP

C386

C386 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C436

C436 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C410

C410 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C390

C390 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C384

C411

C411 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C398

C398 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C394

C394 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C384 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C397

C397 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C759

C759 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C412

C412 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C409

C409 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C395

C395 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C761

C761 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C438

C438 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C408

C408 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C417

C417 SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

C385

C385 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C407

C407 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C391

C391 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C437

C437 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR2 Termination Resistor

AG1 SA

12 53Tuesday, January 10, 2006

3D3V_S0

LAUNCH1

14 12 11 10 9 8 7 6 5 4 3 2

20.K0174.012

ACES-CON12-GP

2nd source: 20.K0185.012

CAP_LED31

NUM_LED31

EMAIL_LED31

STDBY_LED31

PWRLED31

1 2

EC52 SCD01U16V2KX-3GPEC52 SCD01U16V2KX-3GP

EMAIL_LED#

1 2

EC15 SC100P50V2JN-3GPEC15 SC100P50V2JN-3GP

MAIL# INTERNET# EBUTTON# PROGRAM# PWRBTN#

EC16

GND

SRC100P50V-2-GP

SCD1U10V2KX-4GP

Q12

CHDTC124EU-1GP

CHDTC124EU-1GP Q13

Q13

CHDTC124EU-1GP

CHDTC124EU-1GP Q40

Q40

CHDTC124EU-1GP

CHDTC124EU-1GP Q42

Q42

CHDTC124EU-1GP

CHDTC124EU-1GP Q41

Q41

CHDTC124EU-1GP

RC1

OUT

CAP_LED#

84.00124.F1K

OUT

NUM_LED#

84.00124.F1K

OUT

EMAIL_LED#

84.00124.F1K

OUT

STDBY_LED#

84.00124.F1K

OUT

PWRLED#

84.00124.F1K

678

ATI_LCDVDD_ON48

1 2

100R2J-2-GP

1 2

100R2J-2-GP

123

SC1U10V3KX-3GP

R709

R708

INT_MICP 29

MAIL# 31 INTERNET# 31 EBUTTON# 31 PROGRAM# 31

Layout 40 mil

LED6

LED-Y-47-GP

83.00190.D7A

SCD1U10V2KX-4GP

LED5

LED-G-62-GP

83.00190.Q70

SCD1U10V2KX-4GP

LAUNCH BD CONN

3D3V_AUX_S5

Launch

12 1

EC_PWRBTN# 31

3D3V_S0LCDVDD_S0

6 5 4

EC53

1 2

EC54

1 2

R72

R72 100KR2J-1-GP

100KR2J-1-GP

1 2

R120

1 2

470R2J-2-GP

SCD1U16V2ZY-2GP

OUT

GND ON/OFF#3IN

AAT4280IGU-3-T1GP

SCD1U50V3KX-GP

74.04280.B9P

3D3V_S5

on Front Panel

3D3V_S0

on Front Panel

C127

Layout 40 mil

GND

C20

C20 SC1U10V3KX-3GP

SC1U10V3KX-3GP

CCD Pin

Symbol

USB-

USB+

GND

Inverter Pin

Symbol

Vin

PWM

BLON

GND

Launch BD

Symbol

3V_S0

PWRBTN#

PROGRAM#

EBUTTON#

INTERNET#

MAIL#

79NC

MAIL_LED#

PWR_B_LED#

10 NC

INT_MICP

12 INT_MICN

LCD/INVERTER/CCD CONN

5V_S0

LCD1

MH1

MH2

44 42

IPEX-CON40-2-GP

20.F0763.040

D41

1N4148W-7-F-GP

4143

VCC_CCD

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

5VCCD

R169

1 2

0R2J-2-GP

3VCCD

BRIGHTNESS

1 2

R475 0R2J-2-GPR475 0R2J-2-GP

1 2

R474 0R2J-2-GPR474 0R2J-2-GP

SC modify

Layout 60 mil

L29

FILTER-79-GP

69.10084.071

3D3V_S0

EC3

1 2

SCD1U10V2KX-4GP

EC4

1 2

SCD1U10V2KX-4GP

ATI_TXACLK- 48 ATI_TXACLK+ 48

ATI_TXAOUT2- 48

ATI_TXAOUT2+ 48

ATI_TXAOUT1- 48

ATI_TXAOUT1+ 48

ATI_TXAOUT0- 48

ATI_TXAOUT0+ 48

ATI_TXBOUT0- 48

ATI_TXBOUT0+ 48

ATI_TXBOUT1- 48

ATI_TXBOUT1+ 48

ATI_TXBOUT2- 48

ATI_TXBOUT2+ 48

ATI_TXBCLK- 48 ATI_TXBCLK+ 48

C554

SC1U50V5ZY-1-GP

EC6

SC1KP16V2KX-GP

USB_PN5 16 USB_PP5 16

DCBATOUT

C553

SCD1U25V3KX-GP

EC5

SC1KP16V2KX-GP

EVEN CHANNEL

ODD CHANNEL

EC31

EDID_CLK 46 EDID_DAT 46

EC32

SC1KP16V2KX-GP

TOP VIEW

LCDVDD_S0

C12

C19

SC10U10V5ZY-1GP

BRIGHTNESS 31 BLON_OUT 31

R9 100KR2J-1-GP

100KR2J-1-GP

1 2

SC1KP16V2KX-GP

LCD

SCD1U16V2ZY-2GP

GND

CHRGER_LED31

DC_BATFULL31

BLUETOOTH_LED31

WLAN_LED#26

GND

Front panel

LED

ButtonVV

BlutTooth Wireless Charger Power2

Q20

CHDTC124EU-1GP

CHDTC124EU-1GP Q24

Q24

CHDTC124EU-1GP

CHDTC124EU-1GP Q26

Q26

CHDTC124EU-1GP

OUT

CHRGER_LED#

84.00124.F1K

OUT

DC_BATFULL#

84.00124.F1K

OUT

BT_LED#

84.00124.F1K

1 2

100R2J-2-GP

2nd source: 62.40066.001

R445

100R2J-2-GP

R444

100R2J-2-GP

R430

330R2J-3-GP

R431

LED4

83.00190.D7A

LED3

83.00190.Q70

LED1 LED-B-27-U-GP

LED2

83.00190.D7A

BT_BTN#31

WIRELESS_BTN#31

BTBTN1

SW-SLIDE47-GP

62.40018.251

LED-Y-47-GP

LED-G-62-GP

83.00190.P70

LED-Y-47-GP

2 3

3D3V_S5

5V_S0

3D3V_S0

on Front Panel

3D3V_S0

RN78

1 2 3

SRN10KJ-5-GP

WLBTN1

2 3

SW-SLIDE47-GP

62.40018.251

Charger: OFF : Battery or DC only Orange : Charging Orange Blink : Battery low

Power: Green : S0 Orange : S3 Orange Blinking : Enter S4

1st source: 20.K0228.008

Edge Trigger

LED BD CONN

LEDB1

MLX-CON8-7-GP-U

20.K0185.008

10 8 7 6 5 4 3 2

1 9

CHRGER_LED# DC_BATFULL# PWRLED# STDBY_LED#

MEDIA_LED# NUM_LED CAP_LED

BT_LED#

WLAN_LED#

3D3V_S0

MEDIA_LED#

NUM_LED#

CAP_LED#

-1 modify

SRC100P50V-2-GP

EC33

SCD1U10V2KX-4GP

RC9

1 2 3 4 5

RC2

1 2 3 4 5

EC29

1 2

SC100P50V2JN-3GP

EC30

1 2

SC100P50V2JN-3GP

R236

4K7R2J-2-GP

D22

BAW56PT-U

83.00056.E11

8 7 6

5V_S0

SATA

HDLED#

Dummy when use IDE

CDROM_LED# 20

R798

0R2J-2-GP

PATA

SATA

R233

0R2J-2-GP

R234

0R2J-2-GP

PATA

3D3V_S0

R235

R235 10KR2J-3-GP

10KR2J-3-GP

Dummy when use SATA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD / LAUNCH / LEDs

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet

LCD / LAUNCH / LEDs

AG1 -1

13 53Tuesday, January 10, 2006

SATA_LED# 15

HDD_LED# 20

Layout Note: Place these resistors close to the CRT-out connector

ATI_RED46

4 4

ATI_GREEN46

ATI_BLUE46

R457

R456

150R2F-1-GP

R458

R458 150R2F-1-GP

150R2F-1-GP

C541

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

3 3

Ferrite bead impedance: 10 ohm@100MHz

C543

SC3P50V2CN-1-GP

C545

1 2

SC3P50V2CN-1-GP

L17

FCB1608CF-GP

L18

FCB1608CF-GP

L19

FCB1608CF-GP

C542

-1 for CRT SIV Fail

C544

SC6D8P50V2DN-GP

CRT_R

CRT_G

CRT_B

3D3V_S0

10KR2J-3-GP

C546

CRT_IN#31

DAT_DDC1_5

SC6D8P50V2DN-GP

JVGA_HS

JVGA_VS

CLK_DDC1_5

SC100P50V2JN-3GP

Hsync & Vsync level shift

5V_S0

C539

C539 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U59A

R451

ATI_HSY46

ATI_VSY46

2 2

1 2

47R2J-2-GP

R449

1 2

47R2J-2-GP

HSYNC_4 JVGA_HS

VSYNC_4

5 6

2 3

U59B

TSAHCT125PW-GP

For System CRT

JVGA_VS

DDC_CLK & DATA level shift

ATI_DDCDAT46

ATI_DDCCLK46

CRT I/F & CONNECTOR

5V_S0

D2 CH751H-40PT

CH751H-40PT

RN3

RN3 SRN10KJ-5-GP

SRN10KJ-5-GP

RN4

RN4 SRN2K2J-1-GP

SRN2K2J-1-GP

2 3

2N7002-8-GP

VIDEO-15-42-GP-U

2 3

SC100P50V2JN-3GP

C5 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

-1 for CRT SIV Fail

C6 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

3D3V_S0

CRT1

20.20378.015

2 3

Q4 2N7002-8-GP

2N7002-8-GP

6 1

7 2 8 3 9 4 10 5

DAT_DDC1_5

CLK_DDC1_5

CRT_R

CRT_G

CRT_B

1 2

R461

R461 0R2J-2-GP

0R2J-2-GP

1 2

R455

R455 0R2J-2-GP

0R2J-2-GP

5V_CRT_S0

C2 SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

CRT_IN#

TVOUT1

C705

1 2

SC33P50V3JN-GP

L26

1 2

IND-1D2UH-5-GP

C704

C704 SC150P-GP

SC150P-GP

1 2

L24

1 2

IND-1D2UH-5-GP

C689

C689 SC150P-GP

SC150P-GP

1 2

L25

1 2

IND-1D2UH-5-GP

C688

C688 SC150P-GP

SC150P-GP

C690

C690 SC33P50V3JN-GP

SC33P50V3JN-GP

C691

C691 SC33P50V3JN-GP

SC33P50V3JN-GP

CRMA_1

C706

C706 SC270P50V2JN-2GP

SC270P50V2JN-2GP

LUMA_1

C693

C693 SC270P50V2JN-2GP

SC270P50V2JN-2GP

COMP_1

C692

C692 SC270P50V2JN-2GP

SC270P50V2JN-2GP

TV OUT CONN

ATI_TV_CRMA46

ATI_TV_LUMA46

1 1

ATI_TV_COMP46

R621

R621 150R2F-1-GP

150R2F-1-GP

R617

R617 150R2F-1-GP

150R2F-1-GP

R616

R616 150R2F-1-GP

150R2F-1-GP

TVOUT1

22.10021.D81

3 6 7 5 2 4

MINDIN7-11-U1-GP

Reverse type

LUMA_1

CRMA_1

COMP_1

D23

BAV99PT-GP-U

D25

BAV99PT-GP-U

D24

BAV99PT-GP-U

5V_S0

CRT_R

CRT_G

CRT_B

D32

BAV99PT-GP-U

D33

BAV99PT-GP-U

D34

BAV99PT-GP-U

5V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

CRT/TV Connector

AG1 -1

14 53Tuesday, January 10, 2006

4 4

3D3V_AUX_S5

D19

2 1

CH751H-40PT

RTC_AUX_S5

C135

C135 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

RTC circuitry

1KR2J-1-GP

RTC1

2 3

ACES-CON3-GP

20.F0714.003

2nd source: 20.D0198.103

3 3

2 2

1 1

R123

BAT

1 2

C133

C133 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 2

RTC_AUX_S5

1KR2J-1-GP

D20

BAT_D RTC_RST#

2 1

CH751H-40PT

R543

R543 300KR2J-GP

300KR2J-GP

P.H. for internal VCCSUS1_05

INTVRMEN

R549

R549 0R2J-2-GP

0R2J-2-GP

1 2

INTVRMEN

Enable

Disable10

R540 20KR2J-L2-GPR540 20KR2J-L2-GP

1MR2J-1-GP

R541

C178

SC1U10V3ZY-6GP

AC97_BTCLK28

ACZ_BTCLK_MDC21

ACZ_SYNC21,28

ACZ_RST#21,28

ACZ_SDATAOUT21,28

Place within 500 mils of ICH7ball

Change to 24.9 1% ohm when use SATA HD

1 2

C234 SC4D7P50V3DN-1GPC234 SC4D7P50V3DN-1GP

X-32D768KHZ-41GP

82.30001.731

1 2

C236 SC4D7P50V3DN-1GPC236 SC4D7P50V3DN-1GP

AC97_BTCLK

R124

22R2J-2-GP

R126

22R2J-2-GP

R547 39R2J-L-GPR547 39R2J-L-GP

R545 39R2J-L-GPR545 39R2J-L-GP

R544

2 3

1 2

ACZ_SDATAIN028 ACZ_SDATAIN121

1 2

39R2J-L-GP

SATA_LED#13

SATA_RXN020 SATA_RXP020

SATA_TXN020 SATA_TXP020

CLK_PCIE_SATA#3 CLK_PCIE_SATA3

1 2

R569 24D9R2F-L-GPR569 24D9R2F-L-GP

IDE_PDIOR#20 IDE_PDIOW#20 IDE_PDDACK#20

INT_IRQ1420 IDE_PDIORDY20

TP5TPAD30 TP5TPAD30

R164

R164 10MR2J-L-GP

10MR2J-L-GP

RCT_X1

RCT_X2

INTRUDER# INTVRMEN

ACZ_BIT_CLK ACZ_SYNC_R

ACZ_RST#_R

ACZ_SDATAOUT_R

SATARBIAS

AB1 AB2

AA3

AF18

AF3 AE3 AG2 AH2

AF7 AE7 AG6 AH6

AF1 AE1

AH10 AG10

AF15

AH15

AF16 AH16 AG16 AE15

Y1 Y2

U5 V4 T5

U7 V6 V7

U1 R6

T2 T3 T1

U20A

RTXC1 RTCX2

RTCRST#

INTRUDER# INTVRMEN

EE_CS EE_SHCLK EE_DOUT EE_DIN

LAN_CLK

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

LAN_TXD0 LAN_TXD1 LAN_TXD2

ACZ_BIT_CLK ACZ_SYNC

ACZ_RST#

ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA_CLKN SATA_CLKP

SATARBIASN SATARBIASP

DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ

ICH7-M-GP

LPCCPU

RTCLAN

AC-97/AZALIA

SATA

IDE

LAD0 LAD1 LAD2 LAD3

LDRQ0#

LDRQ1#/GPIO23

LFRAME#

A20GATE

A20M#

CPUSLP#

TP1/DPRSTP#

TP2/DPSLP#

FERR#

GPIO49/CPUPWRGD

IGNNE#

INIT3_3V#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THERMTRIP#

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8

DD9 DD10 DD11 DD12 DD13 DD14 DD15

DA0

DA1

DA2

DCS1# DCS3#

71.ICH7M.00U

AA6 AB5 AC4 Y6

AC3 AA5

AB3

AE22 AH28

AG27

AF24 AH25

AG26

AG24

AG22 AG21 AF22 AF25

AG23

AH24 AF23

AH22

AF26

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15

AH17 AE17 AF17

AE16 AD16

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

1 2

H_CPUSLP#_2

H_DPRSLP#_2

H_THERMTRIP_R

3D3V_S0

LPC_LDRQ0# 32

R559

R559 10KR2J-3-GP

10KR2J-3-GP

LPC_LFRAME# 31

K_A20GATE 31 H_A20M# 4

H_DPSLP# 4

H_PWRGD 4,36

H_IGNNE# 4 FWH_INIT# 34 H_INIT# 4 H_INTR 4

H_RCIN# 31

H_NMI 4 H_SMI# 4

H_STPCLK# 4

IDE_PDD0 20 IDE_PDD1 20 IDE_PDD2 20 IDE_PDD3 20 IDE_PDD4 20 IDE_PDD5 20 IDE_PDD6 20 IDE_PDD7 20 IDE_PDD8 20 IDE_PDD9 20 IDE_PDD10 20 IDE_PDD11 20 IDE_PDD12 20 IDE_PDD13 20 IDE_PDD14 20 IDE_PDD15 20

IDE_PDA0 20 IDE_PDA1 20 IDE_PDA2 20

IDE_PDCS1# 20 IDE_PDCS3# 20IDE_PDDREQ20

LPC_LAD[0..3] 31

Open R168 for Dothan A step Shunt for Dothan B step & all Yonah

R170

1 2

0R2J-2-GP

0R2J-2-GP R168

R168

1 2

0R0402-PAD

1D05V_S0

R567

R567 56R2J-4-GP

56R2J-4-GP

H_DPSLP#

H_PWRGD

1 2

200R2F-L-GP

-1 Modify

Layout Note: R568 needs to placed within 2" of ICH7, R568 must be placed within 2" of R169 w/o stub.

H_CPUSLP# 4,6

H_DPRSLP# 4,38

R563

1D05V_S0

R565

R565 56R2J-4-GP

56R2J-4-GP

R568

R568 56R2J-4-GP

56R2J-4-GP

H_FERR# 4

Placement Note: Diatance between the ICH-7 M and cap on the "P" signal should be identical distance between the ICH-7 M and cap on the "N" signal for same pair.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ICH7-M (1 of 4)

AG1 -1

15 53Tuesday, January 10, 2006

PCI_AD[0..31]22,24,25,30

4 4

INT_PIRQB#25

3 3

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

U20B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

Interrupt I/F

PIRQA#

PIRQB#

PIRQC#

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7-M-GP

PCI

MISC

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3#

GNT3# REQ4#/GPIO22 GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2/PIRQE#

GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#

RSVD[6] RSVD[7] RSVD[8] RSVD[9]

MCH_SYNC#

D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8

B15 C12 D12 C15

A7 E10

R511 47R2J-2-GPR511 47R2J-2-GP

B18 A12 C9 E11 B10 F15 F14 F16

C26 A9 B19

G8 F7 F8 G7

AE9 AG8 AH8 F21 AH20

ICH7 Pullups

RP5

PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP#

3D3V_S0

MCH_ICH_SYNC#

PCI_REQ#1

2 2

1 1

PCI_REQ#5

3D3V_S0

INT_PIRQD# INT_PIRQG# INT_PIRQB# INT_PIRQF# INT_PIRQC#

3D3V_S0

PM_CLKRUN#

ACZ_SPKR

ECSCI#

EXT_FWH#

1 2

1KR2J-1-GP

R562

R532

1 2

10KR2J-3-GP

SPI

1 2

1KR2J-1-GP

R42

R557

1 2

10KR2J-3-GP

RP5

1 2 3 4 5 6

SRN8K2J-2-GP

RP6

1 2 3 4 5 6

SRN8K2J-2-GP

RP4

1 2 3 4 5 6

SRN8K2J-2-GP

1 2

R625

R513 1KR2J-1-GP

1 2

PCI_GNT#5

SPI_WP#

PCI_GNT#4

PWROK

8K2R2J-3-GP

R560

R561

2N7002-8-GP

2 3

84.27002.L04

Boot from various source

PCI_SERR#

PCI_LOCK#

PCI_PERR#

PCI_DEVSEL#

PCI_REQ#3

INT_SERIRQPCI_REQ#2

PCI_REQ#4

PCI_REQ#0

10 9

INT_PIRQH#

INT_PIRQE#

INT_PIRQA#

3D3V_S0

10KR2J-3-GP

Q43

EXT_FWH#

Default:H

LPC H H

PCI H L

SPI L H

3D3V_S0

GNT5# GNT4#

SMB_LINK_ALERT#

3D3V_S5

EXT_FWH# 34

4K7R2J-2-GP

T=22ms

ICH7_GPI12 PM_BATLOW#_R

PCI_REQ#0

PCI_REQ#1

PCI_REQ#2

PCI_REQ#3 PCI_GNT#3 PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5

1 2

PCI_LOCK#

R516

ICH_PME#_1

1 2

R512 0R0402-PADR512 0R0402-PAD

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

USB_OC#2 USB_OC#1 USB_OC#3 USB_OC#0

ECSWI# ECSMI#

SMLINK0 SMLINK1

3D3V_S5

R587

TP69 TPAD30TP69 TPAD30

TP2 TPAD30TP2 TPAD30

TP68 TPAD30TP68 TPAD30

PCI_C/BE#0 22,24,30 PCI_C/BE#1 22,24,30 PCI_C/BE#2 22,24,30 PCI_C/BE#3 22,24,30

PCI_IRDY# 22,25,30 PCI_PAR 22,24,30

PCI_DEVSEL# 22,25,30 PCI_PERR# 22,25,30

PCI_SERR# 22,25,30 PCI_STOP# 22,25,30 PCI_TRDY# 22,25,30

PCI_FRAME# 22,25,30

0R0402-PAD

CLK_ICHPCI 3

RP7

1 2 3 4 5 6

SRN10KJ-L3-GP

SRN10KJ-L3-GP RP9

RP9

1 2 3 4 5 6

SRN10KJ-L3-GP

SRN100KJ-6-GP

SRN10KJ-5-GP

1 2

R588

R588 100KR2J-1-GP

100KR2J-1-GP

PCI_REQ#0 25 PCI_GNT#0 25 PCI_REQ#1 30 PCI_GNT#1 30 PCI_REQ#2 22 PCI_GNT#2 22

PCIRST1# 22,25,27,30

PLT_RST1# 7,20,26,30,31,32,34,35,45

ICH_PME# 22

INT_PIRQE# 30 INT_PIRQF# 25 INT_PIRQG# 25 INT_PIRQH# 22

MCH_ICH_SYNC# 7

3D3V_S5

PCIE_WAKE#

PSW_CLR#DBRESET#

SMB_ALERT#

PM_RI#

3D3V_S5

USB_OC#5

USB_OC#7

USB_OC#4

USB_OC#6

3D3V_S5

RN90

23 1

RN88

23 1

D40

D40 BAT54PT-GP

BAT54PT-GP

RSMRST#_TO_KBC 31

C659

C659 SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

LAN

MiniC

NEW

U20C

PSW_CLR#

ECSMI#

R125

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0/BM_BUSY#

B23

GPIO11/SMBALERT#

AC20

GPIO18/STPPCI#

AF21

GPIO20/STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32/CLKRUN#

AC19

GPIO33/AZ_DOCK_EN#

GPIO34/AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7-M-GP

C602SCD1U16V2KX-3GP C602SCD1U16V2KX-3GP

C601SCD1U16V2KX-3GP C601SCD1U16V2KX-3GP

C574SCD1U16V2KX-3GP C574SCD1U16V2KX-3GP

C575SCD1U16V2KX-3GP C575SCD1U16V2KX-3GP

C625SCD1U16V2KX-3GP

C626SCD1U16V2KX-3GP

SPI_CLK_1 SPI_CS# SPI_ARB

SPI_MOSI SPI_MISO

USB_OC#0

USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7

F26 F25 E28 E27

H26 H25 G28 G27

K26 K25

NEW

J28

NEW

J27

M26 M25

L28 L27

P26 P25 N28 N27

T25 T24 R28 R27

R2 P6 P1

P5 P2

D3 C4 D5 D4 E5 C3 A2 B3

U20D

PERn1 PERp1 PETn1 PETp1

PERn2 PERp2 PETn2 PETp2

PERn3 PERp3 PETn3 PETp3

PERn4 PERp4 PETn4 PETp4

PERn5 PERp5 PETn5 PETp5

PERn6 PERp6 PETn6 PETp6

SPI_CLK SPI_CS# SPI_ARB

SPI_MOSI SPI_MISO

OC0# OC1# OC2# OC3# OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31

ICH7-M-GP

SMB_CLK18,26,30,35 SMB_DATA18,26,30,35

ACZ_SPKR28 PM_SUS_STAT#31,32

PM_BMBUSY#7

PM_STPPCI#3 PM_STPCPU#3

PSW_CLR#33

PM_CLKRUN#22,25,30,31,32

PCIE_WAKE#30,31,35

VGATE_PWRGD7,38,48

PCIE_RXN135

PCIE_RXP135 PCIE_TXN135 PCIE_TXP135

PCIE_RXN226

PCIE_RXP226 PCIE_TXN226 PCIE_TXP226

PCIE_RXN3N30

PCIE_RXP3N30 PCIE_TXN3N30 PCIE_TXP3N30

SPI_CLK34

INT_SERIRQ25,30,31,32

SPI_WP#34

ECSCI#31

USB_OC#221

USB_OC#421

SMB_LINK_ALERT#

SMLINK0 SMLINK1

PM_RI#

DBRESET#

SMB_ALERT#

PCIE_WAKE#

THRM#19

1 2

47R2J-2-GP

47R2J-2-GP TP4TPAD30 TP4TPAD30

SPI_CS#34

SPI_MOSI34 SPI_MISO34

GPIO

SATA

SMB

Clocks

GPIO16/DPRSLPVR

SYS

GPIO

SYS

GPIO

Power MGT

GPIO

PCI-Express

DMI_CLKN DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

SPI

USB

USBRBIAS#

USBRBIAS

1 2

R542 10KR2J-3-GPR542 10KR2J-3-GP

RN91

23 1

SRN10KJ-5-GP

GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/SATA3GP

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

TP0/BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39

V26

DMI0RXN

V25

DMI0RXP

U28

DMI0TXN

U27

DMI0TXP

Y26

DMI1RXN

Y25

DMI1RXP

W28

DMI1TXN

W27

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA28

DMI2TXN

AA27

DMI2TXP

AD25

DMI3RXN

AD24

DMI3RXP

AC28

DMI3TXN

AC27

DMI3TXP

AE28

AE27

C25

D25

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

3D3V_S5

RN24

SATA0_R0

AF19

SATA0_R1

AH18

SATA0_R2

AH19

SATA0_R3

AE19

AC1 B2

C20

B24 D23 F22

AA4

PM_DPRSLPVR_R

AC22

PM_BATLOW#_R

C21

PWRBTN#_ICH

C23

C19

E20 A20

ICH7_GPI12

F19 E19 R4 E22 R3 D20 AD21 AD20 AE20

USB_PN0 21 USB_PP0 21 USB_PN1 21 USB_PP1 21 USB_PN2 21 USB_PP2 21 USB_PN3 30 USB_PP3 30 USB_PN4 21 USB_PP4 21 USB_PN5 13 USB_PP5 13 USB_PN6 26 USB_PP6 26 USB_PN7 21 USB_PP7 21

USB_RBIAS_PN

1 2

DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7

DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7

DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7

DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7

CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3

DMI_IRCOMP_R

SATA0_R2 SATA0_R0 SATA0_R3 SATA0_R1

SRN10KJ-4-GP

PM_SUS_CLK 18

PM_SLP_S3# 18,30,31,36,41,43,52

PM_SLP_S5# 31,41,43

R564 100R2J-2-GPR564 100R2J-2-GP

1 2

D16

BAS16-1-GP

R510

R510 10KR2J-3-GP

10KR2J-3-GP

ECSWI# 31

NEWCARD_RST# 30

Layout Note: PCIE AC coupling caps need to be within 250 mils of the driver.

1 2

R80

RN24

1 2 3 4 5

CLK_ICH14 3 CLK48_ICH 3

PWROK 7,19

R566100KR2J-1-GPDYR566100KR2J-1-GP

R546

100KR2J-1-GP

DMI_TXN[3..0]7 DMI_TXP[3..0]7

DMI_RXN[3..0]7 DMI_RXP[3..0]7

1D5V_S0

Place within 500 mils of ICH

R535

R535 24D9R2F-L-GP

24D9R2F-L-GP

Pair

4 USB3

22D6R2F-L1-GP

67MINIC1

SC Modify

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

ICH7-M (2 of 4)

AG1 -1M

16 53Tuesday, January 10, 2006

3D3V_S0

8 7 6

PM_DPRSLPVR 38

SB_PWRBTN# 31

SB_RSMRST# 31

USB

Device

USB1

USB2

NEW C

CCD

BT2

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