Acer Aspire 5220G, Aspire 5520G Schematic

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Compal Confidential

ICW50 Schematics Document

AMD Turion/Sempron + Nvidia MCP67-MV

2007 / 07 / 03 FOR MP

3 3

4 4

Rev:2.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Compal Secret Data

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet of

143Tuesday, November 27, 2007

143Tuesday, November 27, 2007

143Tuesday, November 27, 2007

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Compal confidential

Project Code: ICW50
File Name : LA-3581P

D D

DVI-D Conn. LCD Conn.

page 20page 20

Thermal Sensor
ADM1032ARM

page 6

CRT & TV-out

page 19

AMD Turion/Sempron CPU

Socket S1 638P

page 4,5,6,7

HT LINK

200-800MHz

DDRII DDRII-SO-DIMM X2

Nvidia

LVDS

LVDSDVI

PCI-Express

MXM II VGA/B

page 18

C C

PCI-Express

MCP67-MV

836 BGA

USB 2.0 BUS
HD Audio

IDE BUS
SATA BUS

533/667/800

Dual Channel

3.3V 24.576MHz/48Mhz

3.3V ATA-100

port 1

USB conn x4

CDROM
Conn.

page 08,09

page 21

Bluetooth
Conn

MDC 1.5
Conn

CMOS
Camera

page 20page 29page 25,26

HDA Codec

page 29 page 31

ALC268

New Card
Socket

MINI Card x2

WLAN, TV-Tuner

PHY(GbE)

RTL8211B

page 22

IDSEL:AD20
(PIRQE#,
GNT#0,
REQ#0)

PCI BUS

3.3V 33 MHz

page 10,11,12,13,14,15,16,17

S-ATA HDD
Conn.

page 21

Audio AMP

page 32

Card Reader

RJ45

RICOH R5C833

page 22

1394

B B

Conn.

page 23

page 23

6 in 1
socket

page 24

LPC BUS

ENE KB926

page 27,28

Power On/Off CKT / LID switch / Power OK CKT

DC/DC Interface CKT.

page 33

CIR/LED

page 29

page 30

RTC CKT.

page 16

Touch Pad

page 29

EC I/O Buffer BIOS

page 29

Int.KBD

page 29

page 29

Power Circuit DC/DC

page 35~41

CIR

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 30

3

Compal Secret Data

Compal Secret Data

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Phone Jack x3

page 32

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

401474

401474

401474

1

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243Tuesday, November 27, 2007

243Tuesday, November 27, 2007

243Tuesday, November 27, 2007

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Voltage Rails

Power Plane Description

D D

C C

VIN
B+
+CPU_CORE
+0.9V 0.9V switched power rail for DDR terminator
+1.5VS
+1.2VALW ON ON ON*
+1.2VS ON OFF OFF
+1.2V_HT
+1.8V 1.8V power rail for DDR
+1.8VS 1.8V switched power rail
+2.5VS

+3VALW/+3V/+3VAUX

+3VS
+5VALW
+5VS

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.5V switched power rail

1.2V always on power rail

1.2V switched power rail

1.2V switched power rail ON OFF OFF

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

S1 S3 S5
N/A N/A N/A

ON OFF
ON ON
ON OFFOFF

ON
ON OFF
ON
ON
ON
ON
ON OFF
ON
ON+RTCVCC

ON
OFF
OFF
ON
OFF
ON
OFF

ONRTC power

N/AN/AN/A
OFF
OFF

OFF

OFF
ON*
OFF
ON*

ON*ONVSB always on power rail+VSB
ON

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7NC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

1394

AD20 0

PIRQE

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

B B

EC SM Bus1 address

Device

Smart Battery

Address Address

EC SM Bus2 address

Device

ADM1032

1001 100X b0001 011X b

SKU ID Table

SKU ID

0
1
2

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW

SLP_S5# +VALW +V +VS Clock

HIGHHIGH

HIGH

LOW

HIGH

LOWLOW

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

PCB Revision

UMA (0V)
DISCRETE (3.3V)

SKU

B - PHASE
C - PHASE

ON

ON

ON ON

ON

ON

ON

ON

ON

OFF

ON

ON

V typ

AD_BID

OFF

OFF

OFF

OFF

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

BTO Option Table

BTO Item BOM Structure

UMA UMA@
VGA VGA@

UMA & TV-OUT UMA&TV@

2 SATA HDD SATA2@

CAMERA CMOS@

BLUETOOTH BT@

MINI CARD 1(TV) MINI1@

MINI CARD 2(WLAN) MINI2@

NEW CARD EXPRESS@

TV-OUT

DVI DVI@

1394

CARD READER

HT Debug Port

LOW

OFF

OFF

OFF

max

45@DIP CAP & RTC

TV@

1394@
5IN1@

HT@

3
4
5

MCP67 SM Bus address

Device Address

DDR DIMM0
DDR DIMM2

A A

1001 000Xb
1001 001Xb

6
7

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet of

343Tuesday, November 27, 2007

343Tuesday, November 27, 2007

343Tuesday, November 27, 2007

1

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C

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PROCESSOR HYPERTRANSPORT INTERFACE

D D

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.2V_HT

JP22A

JP22A

D4

VLDT_A3

D3

VLDT_A2

D2

VLDT_A1

D1

VLDT_A0

H_CADIP15(10) H_CADOP15 (10)
H_CADIN15(10)
H_CADIP14(10)
H_CADIN14(10)
H_CADIP13(10)
H_CADIN13(10)
H_CADIP12(10)
H_CADIN12(10)
H_CADIP11(10)
H_CADIN11(10)
H_CADIP10(10)
H_CADIN10(10)
H_CADIP9(10)
H_CADIN9(10)
H_CADIP8(10)

C C

+1.2V_HT

B B

H_CADIN8(10)
H_CADIP7(10)
H_CADIN7(10)
H_CADIP6(10)
H_CADIN6(10)
H_CADIP5(10)
H_CADIN5(10)
H_CADIP4(10)
H_CADIN4(10)
H_CADIP3(10)
H_CADIN3(10)
H_CADIP2(10)
H_CADIN2(10)
H_CADIP1(10)
H_CADIN1(10)
H_CADIP0(10)
H_CADIN0(10)

H_CLKIP1(10)
H_CLKIN1(10)
H_CLKIP0(10)
H_CLKIN0(10)

R143 51_0402_1%

R143 51_0402_1%

1 2

R142 51_0402_1%

R142 51_0402_1%

1 2

H_CTLIP0(10)
H_CTLIN0(10)

H_CADIP15
H_CADIP14

H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

H_CTLIP1
H_CTLIN1

H_CTLIP0
H_CTLIN0

N5

L0_CADIN_H15

P5

L0_CADIN_L15

M3

L0_CADIN_H14

M4

L0_CADIN_L14

L5

L0_CADIN_H13

M5

L0_CADIN_L13

K3

L0_CADIN_H12

K4

L0_CADIN_L12

H3

L0_CADIN_H11

H4

L0_CADIN_L11

G5

L0_CADIN_H10

H5

L0_CADIN_L10

F3

L0_CADIN_H9

F4

L0_CADIN_L9

E5

L0_CADIN_H8

F5

L0_CADIN_L8

N3

L0_CADIN_H7

N2

L0_CADIN_L7

L1

L0_CADIN_H6

M1

L0_CADIN_L6

L3

L0_CADIN_H5

L2

L0_CADIN_L5

J1

L0_CADIN_H4

K1

L0_CADIN_L4

G1

L0_CADIN_H3

H1

L0_CADIN_L3

G3

L0_CADIN_H2

G2

L0_CADIN_L2

E1

L0_CADIN_H1

F1

L0_CADIN_L1

E3

L0_CADIN_H0

E2

L0_CADIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0

HTT Interface

HTT Interface

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

Athlon 64 S1
Processor Socket

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

1 2

H_CADOP15
H_CADON15H_CADIN15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CTLOP0
H_CTLON0

C533

C533

4.7U_0805_10V4Z

4.7U_0805_10V4Z

H_CADON15 (10)
H_CADOP14 (10)
H_CADON14 (10)
H_CADOP13 (10)
H_CADON13 (10)
H_CADOP12 (10)
H_CADON12 (10)
H_CADOP11 (10)
H_CADON11 (10)
H_CADOP10 (10)
H_CADON10 (10)
H_CADOP9 (10)
H_CADON9 (10)
H_CADOP8 (10)
H_CADON8 (10)
H_CADOP7 (10)
H_CADON7 (10)
H_CADOP6 (10)
H_CADON6 (10)
H_CADOP5 (10)
H_CADON5 (10)
H_CADOP4 (10)
H_CADON4 (10)
H_CADOP3 (10)
H_CADON3 (10)
H_CADOP2 (10)
H_CADON2 (10)
H_CADOP1 (10)
H_CADON1 (10)
H_CADOP0 (10)
H_CADON0 (10)

H_CLKOP1 (10)
H_CLKON1 (10)
H_CLKOP0 (10)
H_CLKON0 (10)

H_CTLOP0 (10)
H_CTLON0 (10)

+3VS

12

R88

R88
10K_0402_5%

10K_0402_5%

FAN_SPEED1(27,28)

+5VS

+VCC_FAN1

EN_DFAN1(27,28)

FAN Conn

+5VS

12

D20

D20
1SS355_SOD323-2

1SS355_SOD323-2

12

D21

D21
BAS16_SOT23-3

BAS16_SOT23-3

Update Footprint

EN_DFAN1

1

C310

C310
10U_0805_10V4Z

10U_0805_10V4Z

2

W=40mils

+VCC_FAN1

FAN1

1

C52

C52
1000P_0402_50V7K

1000P_0402_50V7K

2

U11

U11

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

G993P1UF_SOP8

FAN1 Conn

1 2

C510 10U_0805_10V4Z

C510 10U_0805_10V4Z

1 2

C509 1000P_0402_50V7K

C509 1000P_0402_50V7K

ACES_85205-03001

ACES_85205-03001

8

GND

7

GND

6

GND

5

GND

JP16

JP16

1
2
3

+1.2V_HT

1

2

C542

C542

4.7U_0805_10V4Z

4.7U_0805_10V4Z

LAYOUT: Place bypass cap on topside of board

A A

5

C541

C541

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

1

2

C540

C540

0.22U_0402_10V4Z

0.22U_0402_10V4Z

C536

C536

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

2

C538

C538
180P_0402_50V8J

180P_0402_50V8J

C539

C539
180P_0402_50V8J

180P_0402_50V8J

1

1

2

2

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

443Tuesday, November 27, 2007

443Tuesday, November 27, 2007

443Tuesday, November 27, 2007

1

C

C

C

A

Dr-Bios.com

B

C

D

E

Processor DDR2 Memory Interface

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.8V

4 4

3 3

2 2

1 1

12

R386

R386

39.2_0402_1%~D

39.2_0402_1%~D

R388

R388

12

39.2_0402_1%~D

39.2_0402_1%~D

PLACE THEM CLOSE TO
CPU WITHIN 1"

DDR_CS3_DIMMA#(8)
DDR_CS2_DIMMA#(8)
DDR_CS1_DIMMA#(8)
DDR_CS0_DIMMA#(8)

DDR_CS3_DIMMB#(9)
DDR_CS2_DIMMB#(9)
DDR_CS1_DIMMB#(9)
DDR_CS0_DIMMB#(9)

DDR_CKE1_DIMMB(9)
DDR_CKE0_DIMMB(9)
DDR_CKE1_DIMMA(8)
DDR_CKE0_DIMMA(8)

DDR_A_MA[15..0](8)

DDR_A_BS#2(8)
DDR_A_BS#1(8)
DDR_A_BS#0(8)

DDR_A_RAS#(8)
DDR_A_CAS#(8)
DDR_A_WE#(8)

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH

+1.8V

R228

R228

1K_0402_1%

1K_0402_1%

R222

R222

1K_0402_1%

1K_0402_1%

TP2PAD TP2PAD

M_ZN
M_ZP

10:8:10:8:10

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

1

C336

C336

1.5P_0402_50V8C

1.5P_0402_50V8C

2

1

C344

C344

1.5P_0402_50V8C

1.5P_0402_50V8C

2

12

1

12

2

1000P_0402_50V7K

1000P_0402_50V7K

+0.9VREF_CPU

W17

VTT_SENSE

Y10

AE10
AF10

V19
J22
V22
T19

Y26
J24

W24

U23
H26

J23
J20

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

C358

C358

J21
K19

K20
V24
K24
L20
R19
L19
L22

L21
M19
M20
M24
M22

N22

N21

R21

K22

R20

T22

T20

U20

U21

1

C363

C363
1000P_0402_50V7K

1000P_0402_50V7K

2

VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU

JP22B

JP22B

M_VREF
VTT_SENSE

M_ZN
M_ZP

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MA_BANK2
MA_BANK1
MA_BANK0

MA_RAS_L
MA_CAS_L
MA_WE_L

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F
Athlon 64 S1
Processor
Socket

CPU_VREF_REF

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9V

D10

VTT1

C10

VTT2

B10

VTT3

AD10

VTT4

W10

VTT5

AC10

VTT6

AB10

VTT7

AA10

VTT8

A10

VTT9

DDR_A_CLK2

Y16

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9
MB_ADD8

DDRII Cmd/Ctrl//Clk

DDRII Cmd/Ctrl//Clk

MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

1

C345

C345

2

1000P_0402_50V7K

1000P_0402_50V7K

DDR_A_CLK#2

AA16

DDR_A_CLK1

E16

DDR_A_CLK#1

F16

DDR_B_CLK2

AF18

DDR_B_CLK#2

AF17

DDR_B_CLK1

A17

DDR_B_CLK#1

A18

DDR_B_ODT1

W23

DDR_B_ODT0

W26

DDR_A_ODT1

V20

DDR_A_ODT0

U19

DDR_B_MA15

J25

DDR_B_MA14

J26

DDR_B_MA13

W25

DDR_B_MA12

L23

DDR_B_MA11

L25

DDR_B_MA10

U25

DDR_B_MA9

L24

DDR_B_MA8

M26

DDR_B_MA7

L26

DDR_B_MA6

N23

DDR_B_MA5

N24

DDR_B_MA4

N25

DDR_B_MA3

N26

DDR_B_MA2

P24

DDR_B_MA1

P26

DDR_B_MA0

T24

DDR_B_BS#2

K26

DDR_B_BS#1

T26

DDR_B_BS#0

U26

DDR_B_RAS#

U24

DDR_B_CAS#

V26

DDR_B_WE#

U22

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH

1

2

C357

C357

1

2

1

2

+0.9VREF_CPU

1

C350

C350
1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

C349

C349

1.5P_0402_50V8C

1.5P_0402_50V8C

C348

C348

1.5P_0402_50V8C

1.5P_0402_50V8C

DDR_A_CLK2 (8)
DDR_A_CLK#2 (8)
DDR_A_CLK1 (8)
DDR_A_CLK#1 (8)

DDR_B_CLK2 (9)
DDR_B_CLK#2 (9)
DDR_B_CLK1 (9)
DDR_B_CLK#1 (9)

DDR_B_ODT1 (9)
DDR_B_ODT0 (9)
DDR_A_ODT1 (8)
DDR_A_ODT0 (8)

DDR_B_MA[15..0] (9)

DDR_B_BS#2 (9)
DDR_B_BS#1 (9)
DDR_B_BS#0 (9)

DDR_B_RAS# (9)
DDR_B_CAS# (9)
DDR_B_WE# (9)

DDR_B_D[63..0](9)

To reverse SODIMM socket

DDR_B_DM[7..0](9) DDR_A_DM[7..0] (8)

DDR_B_DQS7(9)
DDR_B_DQS#7(9)
DDR_B_DQS6(9)
DDR_B_DQS#6(9)
DDR_B_DQS5(9)
DDR_B_DQS#5(9)
DDR_B_DQS4(9)
DDR_B_DQS#4(9)
DDR_B_DQS3(9)
DDR_B_DQS#3(9)
DDR_B_DQS2(9)
DDR_B_DQS#2(9)
DDR_B_DQS1(9)
DDR_B_DQS#1(9)
DDR_B_DQS0(9)
DDR_B_DQS#0(9)

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

JP22C

JP22C

AD11

MB_DATA63

AF11

MB_DATA62

AF14

MB_DATA61

AE14

MB_DATA60

Y11

MB_DATA59

AB11

MB_DATA58

AC12

MB_DATA57

AF13

MB_DATA56

AF15

MB_DATA55

AF16

MB_DATA54

AC18

MB_DATA53

AF19

MB_DATA52

AD14

MB_DATA51

AC14

MB_DATA50

AE18

MB_DATA49

AD18

MB_DATA48

AD20

MB_DATA47

AC20

MB_DATA46

AF23

MB_DATA45

AF24

MB_DATA44

AF20

MB_DATA43

AE20

MB_DATA42

AD22

MB_DATA41

AC22

MB_DATA40

AE25

MB_DATA39

AD26

MB_DATA38

AA25

MB_DATA37

AA26

MB_DATA36

AE24

MB_DATA35

AD24

MB_DATA34

AA23

MB_DATA33

AA24

MB_DATA32

G24

MB_DATA31

G23

MB_DATA30

D26

MB_DATA29

C26

MB_DATA28

G26

MB_DATA27

G25

MB_DATA26

E24

MB_DATA25

E23

MB_DATA24

C24

MB_DATA23

B24

MB_DATA22

C20

MB_DATA21

B20

MB_DATA20

C25

MB_DATA19

D24

MB_DATA18

A21

MB_DATA17

D20

MB_DATA16

D18

MB_DATA15

C18

MB_DATA14

D14

MB_DATA13

C14

MB_DATA12

A20

MB_DATA11

A19

MB_DATA10

A16

MB_DATA9

A15

MB_DATA8

A13

MB_DATA7

D12

MB_DATA6

E11

MB_DATA5

G11

MB_DATA4

B14

MB_DATA3

A14

MB_DATA2

A11

MB_DATA1

C11

MB_DATA0

AD12

MB_DM7

AC16

MB_DM6

AE22

MB_DM5

AB26

MB_DM4

E25

MB_DM3

A22

MB_DM2

B16

MB_DM1

A12

MB_DM0

AF12

MB_DQS_H7

AE12

MB_DQS_L7

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AC25

MB_DQS_H4

AC26

MB_DQS_L4

F26

MB_DQS_H3

E26

MB_DQS_L3

A24

MB_DQS_H2

A23

MB_DQS_L2

D16

MB_DQS_H1

C16

MB_DQS_L1

C12

MB_DQS_H0

B12

MB_DQS_L0

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

DDRII Data

DDRII Data

Athlon 64 S1
Processor Socket

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] (8)

DDR_A_DQS7 (8)
DDR_A_DQS#7 (8)
DDR_A_DQS6 (8)
DDR_A_DQS#6 (8)
DDR_A_DQS5 (8)
DDR_A_DQS#5 (8)
DDR_A_DQS4 (8)
DDR_A_DQS#4 (8)
DDR_A_DQS3 (8)
DDR_A_DQS#3 (8)
DDR_A_DQS2 (8)
DDR_A_DQS#2 (8)
DDR_A_DQS1 (8)
DDR_A_DQS#1 (8)
DDR_A_DQS0 (8)
DDR_A_DQS#0 (8)

To normal SODIMM socket

A1

AF1

A26

Athlon 64 S1g1

uPGA638
Top View

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Issued Date

Issued Date

Issued Date

Compal Secret Data

Compal Secret Data

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

543Tuesday, November 27, 2007

543Tuesday, November 27, 2007

543Tuesday, November 27, 2007

C

C

C

5

Dr-Bios.com

+2.5VS

1

C266

C266

FCM2012C-800_0805

FCM2012C-800_0805

22U_0805_6.3V6M

22U_0805_6.3V6M

D D

C C

2

HTCPU_PWRGD(10)

HTCPU_STOP#(10)

MCP_PWRGD(15,18,27,28)

HTCPU_RST#(10)

1 2

R375

R375
0_0402_5% @

0_0402_5% @

1 2

+1.8V

L28

L28

MCP_PWRGD_R

1

C276

C276

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.8V

12

R379

R379
300_0402_5%

300_0402_5%

+1.8V

12

R184

R184
300_0402_5%

300_0402_5%

+1.8V

12

R373

R373
300_0402_5%

300_0402_5%

1

C271

C271

2

0.22U_0603_16V7K

0.22U_0603_16V7K

+1.8V+3VS

12

R381

R381

4.7K_0402_5%

4.7K_0402_5%
@

@

5

U26

U26

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

@

@

1 2

R380 0_0402_5%

R380 0_0402_5%

+1.8V

5

U9

U9

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

@

@

1 2

R183 0_0402_5%

R183 0_0402_5%

+1.8V

5

U25

U25

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

@

@

1 2

R374 0_0402_5%

R374 0_0402_5%

1

C277

C277
3300P_0402_50V7K

3300P_0402_50V7K

2

C543 0.1U_0402_16V4Z

C543 0.1U_0402_16V4Z

1 2

4

1 2

Y

R383 0_0402_5%

R383 0_0402_5%

4

1 2

Y

R189 0_0402_5%

R189 0_0402_5%

4

1 2

Y

R377 0_0402_5%

R377 0_0402_5%

4

W=50mils

place them to CPU within 1"

@

@

@

@

@

@

+1.8V

CPU_SIC(15)
CPU_SID(15)

+1.2V_HT

CPU_ALL_PWROK

CPU_LDTSTOP#

CPU_HT_RESET#

R370 300_0402_5%R370 300_0402_5%

1 2

R371 300_0402_5%R371 300_0402_5%

1 2

R369 0_0402_5%R369 0_0402_5%

1 2

R368 0_0402_5%R368 0_0402_5%

1 2

R378 44.2_0603_1%R378 44.2_0603_1%

1 2

R376 44.2_0603_1%R376 44.2_0603_1%

1 2

CPUCLK(10)

CPUCLK#(10)

3

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

+2.5VS_VDDA

CPU_SIC_R
CPU_SID_R

CPU_HTREF1
CPU_HTREF0 VID0

5:10

CPU_VCC_SENSE(41)
CPU_VSS_SENSE(41)

C545

C545

1 2

3900P_0402_50V7K

3900P_0402_50V7K

C544

C544

1 2

3900P_0402_50V7K

3900P_0402_50V7K

CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST21_SCANEN
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

169_0402_1%

169_0402_1%

12

R382

R382

R199 300_0402_5%R199 300_0402_5%
R198 1K_0402_5%

R198 1K_0402_5%
R188 510_0402_5%

R188 510_0402_5%

R197 300_0402_5%R197 300_0402_5%
R387 510_0402_5%R387 510_0402_5%
R385 300_0402_5%R385 300_0402_5%
R215 300_0402_5%R215 300_0402_5%

TP3PAD TP3PAD
TP1PAD TP1PAD

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_THERMDC
CPU_THERMDA

10:10

1 2
1 2
1 2

1 2
1 2
1 2
1 2

2

ATHLON Control and Debug

JP22D

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

CPU_VCC_SENSE
CPU_VSS_SENSE

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

+1.8V

JP22D

F8

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI
TEST25_HE9TEST29_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

AMD NPT S1 SOCKET
Processor Socket

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

DBREQ_L

TEST29_L

MISC

MISC

TEST28_H

TEST28_L

PSI_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

VID5
VID4
VID3
VID2
VID1
VID0

TDO

H_THERMTRIP_S#

AF6

CPU_PROCHOT#_1.8

AC7

VID5

A5

VID4

C6

VID3

A6

VID2

A4

VID1

C5
B5

CPU_PRESENT#

AC6

PSI#

A3

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

5:5:5

AE7
AD7
AE8

CPU_TEST21_SCANEN

AB8
AF7

J7
H8
AF8

CPU_TEST26_BURNIN#

AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

R155

R155
300_0402_5%

300_0402_5%

+1.8V

12

PSI# (41)

80.6_0402_1%

80.6_0402_1%

1

12

R156

R156
300_0402_5%

300_0402_5%

VID5 (41)
VID4 (41)
VID3 (41)
VID2 (41)
VID1 (41)
VID0 (41)

R384

R384

1 2

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

HDT Connector

12

12

CPU_DBREQ#
CPU_DBRDY
CPU_TCK

CPU_TDI
CPU_TRST#
CPU_TDO

1

2

12

R163 220_0402_5%HT@R163 220_0402_5%HT@

EC_SMB_CK2
EC_SMB_DA2

B B

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

C275

C275

2200P_0402_50V7K

A A

2200P_0402_50V7K

EC_SMB_CK2(27,28)
EC_SMB_DA2(27,28)

5

12

12

+1.8V

R160 220_0402_5%HT@R160 220_0402_5%HT@

R162 220_0402_5% HT@R162 220_0402_5% HT@

R159 220_0402_5%HT@R159 220_0402_5%HT@

R161 220_0402_5%HT@R161 220_0402_5%HT@

U4

CPU_THERMDA
CPU_THERMDC

U4

2

D+

3

D-

8

SCLK

7

SDATA

U2 CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE
CLOSE TO PROCESSOR WITHIN 1" INCH

+3VS

1

C269

C269

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

VDD1
ALERT#
THERM#

GND

ADM1032ARM_RM8

ADM1032ARM_RM8

JP7

JP7

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

SAMTEC_ASP-68200-07
@

@

1
6
4
5

R113

R113
220_0402_5%

220_0402_5%
HT@

HT@

3V_LDT_RST#

+3VS

12

1 2

R535 0_0402_5%

R535 0_0402_5%

+3V

2

G

G

CPU_HT_RESET#

1 3

D

S

D

@

@

S

Q14

Q14

2N7002_SOT23

2N7002_SOT23
HT@

HT@

H_THERMTRIP_S# H_THERMTRIP#CPU_TMS

PVT Modify 2007/03/22

12

R186

R186

10K_0402_5%@

10K_0402_5%@

PROCHOT#(10)

R141 0_0402_5%

R141 0_0402_5%

Connect to MCP67

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V +1.8V +3V +3V

12

R114

R114
300_0402_5%

300_0402_5%

CPU_PROCHOT#_1.8

1 2

@

@

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

12

R127

R127
1K_0402_5%

1K_0402_5%

2

Q16

Q16

3 1

MMBT3904_SOT23

MMBT3904_SOT23

1 2

R115 0_0402_5%

R115 0_0402_5%

10K_0402_5%

10K_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

@

@

+1.8V +3VS

12

R133

R133

CPU_PH_G

B

B

2

Q19

Q19

E

E

3 1

MMBT3904_SOT23

MMBT3904_SOT23

C

C

12

R116

R116
10K_0402_5%

10K_0402_5%

12

R130

R130

4.7K_0402_5%

4.7K_0402_5%

12

2

3 1

R117

R117

1K_0402_5%@

1K_0402_5%@

Q15

Q15
MMBT3904_SOT23

MMBT3904_SOT23
@

@

MAINPWON (35,36,37)

H_THERMTRIP# (10)

EC_THERM# (15,27,28)

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet

1

of

643Tuesday, November 27, 2007

643Tuesday, November 27, 2007

643Tuesday, November 27, 2007

C

C

C

5

Dr-Bios.com

D D

PROCESSOR POWER AND GROUND

JP22E

JP22E

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

C C

B B

M6
M8

M10

N7
N9

N11

P8

P10

R4
R7
R9

R11

T2
T6

T8
T10
T12
T14

U7

U9
U11
U13

V6
V8

V10

A1

VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25

Power

Power

VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

Athlon 64 S1g1

uPGA638
Top View

AF1

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

+CPU_CORE+CPU_CORE

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

+1.8V

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

A26

4

JP22F

JP22F

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_PZ63823-284S-41F

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101

Ground

Ground

VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

3

+CPU_CORE

1

+

+

2

+CPU_CORE

1

2
C279

C279
10U_0805_10V6M

10U_0805_10V6M

C548

C548
470U_D2E_2VM_R9

470U_D2E_2VM_R9

C287

C287
10U_0805_10V6M

10U_0805_10V6M

1

1

2

2

C280

C280
10U_0805_10V6M

10U_0805_10V6M

1

+

+

C550

C550
470U_D2E_2VM_R9

470U_D2E_2VM_R9

2

C288

C288
10U_0805_10V6M

10U_0805_10V6M
1

2

1

+

+

2

1

2
C282

C282
10U_0805_10V6M

10U_0805_10V6M

C546

C546
470U_D2E_2VM_R9

470U_D2E_2VM_R9

C289

C289
10U_0805_10V6M

10U_0805_10V6M
1

2

2

1

+

+

C547

C547
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

2

1

2

C281

C281
10U_0805_10V6M

10U_0805_10V6M

+CPU_CORE

1

+

+

2

C551

C551
820U_E9_2.5V_M_R7

820U_E9_2.5V_M_R7
45@

45@

1

10/2 Modify

CPU SOCKET S1 DECOUPLING

+CPU_CORE

1

C319

C319

180P_0402_50V8J

180P_0402_50V8J

2

1

C333

C333
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

2

1

C327

C327
10U_0805_10V6M

10U_0805_10V6M

2

C309

C309

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C328

C328
10U_0805_10V6M

10U_0805_10V6M

2

1

C353

C353
10U_0805_10V6M

10U_0805_10V6M

2

1

C324

C324
10U_0805_10V6M

10U_0805_10V6M

2

1

C343

C343
10U_0805_10V6M

10U_0805_10V6M

2

1

C316

C316
10U_0805_10V6M

10U_0805_10V6M

2

1

C361

C361

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C334

C334
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C356

C356

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

C308

C308

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

C332

C332
10U_0805_10V6M

10U_0805_10V6M

2

1

C315

C315
22U_0805_6.3V6M

22U_0805_6.3V6M

2

+CPU_CORE +1.8V

1

C318

C318

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C326

C326
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

2

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8V

1

C352

C352

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C381

C381

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

+0.9V

1

C304

C304

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C342

C342

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

2

1

C320

C320

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

C385

C385

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C351

C351

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C382

C382

0.01U_0402_16V7K

0.01U_0402_16V7K

2

1

C303

C303

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C388

C388

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

2

1

C302

C302

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C362

C362

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

C340

C340
180P_0402_50V8J

180P_0402_50V8J

1

C313

C313

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C360

C360
180P_0402_50V8J

180P_0402_50V8J

2

1

C386

C386

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C312

C312

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C383

C383

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C314

C314

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C298

C298

0.22U_0402_10V4Z

0.22U_0402_10V4Z

2

1

C299

C299
1000P_0402_50V7K

1000P_0402_50V7K

2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C300

C300
1000P_0402_50V7K

1000P_0402_50V7K

2

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

1

C307

C307
1000P_0402_50V7K

1000P_0402_50V7K

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

C306

C306
1000P_0402_50V7K

1000P_0402_50V7K

2

1

2

C305

C305
180P_0402_50V8J

180P_0402_50V8J

1

2

1

C297

C297
180P_0402_50V8J

180P_0402_50V8J

2

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet of

C296

C296
180P_0402_50V8J

180P_0402_50V8J

1

C295

C295

180P_0402_50V8J

180P_0402_50V8J

2

1

743Tuesday, November 27, 2007

743Tuesday, November 27, 2007

743Tuesday, November 27, 2007

C

C

C

5

Dr-Bios.com

4

3

2

1

+1.8V+DIMM_VREF+1.8V+1.8V

C579 4.7U_0805_10V4ZC579 4.7U_0805_10V4Z

C428 0.1U_0402_16V4Z C428 0.1U_0402_16V4Z

JP28

JP28

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA(5)
DDR_CS2_DIMMA#(5)

DDR_A_BS#2(5)

DDR_A_BS#0(5)
DDR_A_WE#(5)

DDR_A_CAS#(5)
DDR_CS1_DIMMA#(5)

DDR_A_ODT1(5)

B B

A A

MEM_SMBDATA(9,15)
MEM_SMBCLK(9,15)

DDR_A_D1
DDR_A_DQS#0

DDR_A_DQS0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18 DDR_A_D22
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43 DDR_A_D47
DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51 DDR_A_D55

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59
MEM_SMBDATA

MEM_SMBCLK

+3VS

5

1

C429

C429

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

DIMM1 REV H:5.2mm (BOT)

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-M2RN-7F

FOX_AS0A426-M2RN-7F
<BOM Structure>

<BOM Structure>

DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

VSS
DQ4
DQ5
VSS

CK0

A11

BA1
S0#

CK1

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
DDR_A_CLK1

DDR_A_CLK#1
DDR_A_D14

DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6DDR_A_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D52

DDR_A_CLK2
DDR_A_CLK#2

DDR_A_DM6
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R281 10K_0402_5%R281 10K_0402_5%

1 2

R282 10K_0402_5%R282 10K_0402_5%

1 2

1

2

DDR_A_CLK1 (5)
DDR_A_CLK#1 (5)

DDR_A_D[0..63](5)
DDR_A_DM[0..7](5)

DDR_A_DQS[0..7](5)
DDR_A_MA[0..15](5)

DDR_A_DQS#[0..7](5)

DDR_CKE1_DIMMA (5)

DDR_A_BS#1 (5)
DDR_A_RAS# (5)
DDR_CS0_DIMMA# (5)

DDR_A_ODT0 (5)

DDR_CS3_DIMMA# (5)

DDR_A_CLK2 (5)
DDR_A_CLK#2 (5)

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

Issued Date

Issued Date

Issued Date

3

12

R275

R275

1K_0402_1%

1K_0402_1%

12

R274

R274

1K_0402_1%

1K_0402_1%

DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

+1.8V

C399

C399

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

1

1

2

2

C413

C413

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C407

C407

2

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C436

C436

C437

C437

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
DDR_A_MA10

DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_CS3_DIMMA#

+0.9V

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C427

1

2
C424

C424

0.01U_0402_16V7K

0.01U_0402_16V7K

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

C409

C409

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C434

C434

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C438

C438

C427

0.01U_0402_16V7K

0.01U_0402_16V7K
1

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

C410

C410

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C433

C433

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C439

C439

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C414

C414

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

1

1

2

2

C398

C398

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

C408

C408

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C435

C435

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

RP10 47_0404_4P2R_5%RP10 47_0404_4P2R_5%

RP11 47_0404_4P2R_5%RP11 47_0404_4P2R_5%

RP12 47_0404_4P2R_5%RP12 47_0404_4P2R_5%

RP13 47_0404_4P2R_5%RP13 47_0404_4P2R_5%

RP14 47_0404_4P2R_5%RP14 47_0404_4P2R_5%

RP9 47_0404_4P2R_5%RP9 47_0404_4P2R_5%

RP8 47_0404_4P2R_5%RP8 47_0404_4P2R_5%

R277 47_0402_1%R277 47_0402_1%

1 2

R280 47_0402_1%R280 47_0402_1%

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C443

C443

Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V

2

1

2
C426

C426
10P_0402_50V8K

10P_0402_50V8K

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C411

C411

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C431

C431

1

2

C445

C445

C425

C425
10P_0402_50V8K

10P_0402_50V8K
1

2

1

C412

C412

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C432

C432

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C446

C446

C577

C577

0.22U_0603_16V7K

0.22U_0603_16V7K
1

1

2

2
C578

C578

0.22U_0603_16V7K

0.22U_0603_16V7K

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

C415

C415

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C453

C453

C452

C452

RP15 47_0404_4P2R_5%RP15 47_0404_4P2R_5%

RP16 47_0404_4P2R_5%RP16 47_0404_4P2R_5%

RP17 47_0404_4P2R_5%RP17 47_0404_4P2R_5%

RP20 47_0404_4P2R_5%RP20 47_0404_4P2R_5%

RP18 47_0404_4P2R_5%RP18 47_0404_4P2R_5%

RP19 47_0404_4P2R_5%RP19 47_0404_4P2R_5%

RP21 47_0404_4P2R_5%RP21 47_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C440

C440

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet

1

2
C576

C576

0.22U_0603_16V7K

0.22U_0603_16V7K

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C416

C416

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C451

C451

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C441

C441

C575

C575

0.22U_0603_16V7K

0.22U_0603_16V7K
1

2

1

C417

C417

2

1

2

C450

C450

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C442

C442

1

2
C574

C574

0.22U_0603_16V7K

0.22U_0603_16V7K

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C449

C449

DDR_A_MA14
DDR_A_MA15

DDR_A_MA7
DDR_CKE1_DIMMA

DDR_A_MA6
DDR_A_MA11

DDR_A_MA2
DDR_A_MA4

DDR_A_BS#1
DDR_A_MA0

DDR_CS0_DIMMA#
DDR_A_RAS#

DDR_A_MA13DDR_A_ODT1
DDR_A_ODT0

1

2

C444

C444

1

C418

C418

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

1

2

C448

C448

1

C573

C573

0.22U_0603_16V7K

0.22U_0603_16V7K

2

+

+

C628

C628
220U_D2_4VM_R15

220U_D2_4VM_R15

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1

2

2

C447

C447

+1.8V

843Tuesday, November 27, 2007

843Tuesday, November 27, 2007

843Tuesday, November 27, 2007

C422

C422

+

+

150U_D2_6.3VM

150U_D2_6.3VM

of

C

C

C

5

Dr-Bios.com

4

3

2

1

1

2

1

2

2

C472

C472

1

2

C622

C622

C479

C479

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C471

C471

DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

1

C627

C627

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C478

C478

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C470

C470

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

C632

C632

C626

C626

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C466

C466

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C457

C457

C469

C469

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

C464

C464

4.7U_0805_10V4Z

1

2

C458

C458

1

1

C633

C633

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C463

C463

C465

C465

1 4
2 3

RP30 47_0404_4P2R_5%RP30 47_0404_4P2R_5%

1 4
2 3

RP31 47_0404_4P2R_5%RP31 47_0404_4P2R_5%

1 4
2 3

RP32 47_0404_4P2R_5%RP32 47_0404_4P2R_5%

1 4
2 3

RP33 47_0404_4P2R_5%RP33 47_0404_4P2R_5%

1 4
2 3

RP34 47_0404_4P2R_5%RP34 47_0404_4P2R_5%

1 4
2 3

RP28 47_0404_4P2R_5%RP28 47_0404_4P2R_5%

1 4
2 3

RP35 47_0404_4P2R_5%RP35 47_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C477

C477

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet of

C654

C654
1000P_0402_50V7K

1000P_0402_50V7K

1

1

2

2

C653

C653
1000P_0402_50V7K

1000P_0402_50V7K

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

C630

C630

C631

C631

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C462

C462

DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
DDR_B_BS#1

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT0
DDR_B_MA13

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C485

C485

C486

C486

1

+

+

C629

C629
220U_D2_4VM_R15

220U_D2_4VM_R15

2

1

2

C461

C461

1

2

C484

C484

1

C656

C656
1000P_0402_50V7K

1000P_0402_50V7K

1

1

2

2

C655

C655
1000P_0402_50V7K

1000P_0402_50V7K

+1.8V

943Tuesday, November 27, 2007

943Tuesday, November 27, 2007

943Tuesday, November 27, 2007

C

C

C

+DIMM_VREF+1.8V+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C459

C459

C455

4.7U_0805_10V4Z

C455

JP29

JP29

1

VREF

3

DDR_B_D0

D D

C C

DDR_CKE0_DIMMB(5)
DDR_CS2_DIMMB#(5)

DDR_B_BS#2(5)

DDR_B_BS#0(5)
DDR_B_WE#(5)

DDR_B_CAS#(5)
DDR_CS1_DIMMB#(5)

DDR_B_ODT1(5)

B B

A A

MEM_SMBDATA(8,15)

MEM_SMBCLK(8,15)

DDR_B_D1
DDR_B_DQS#0

DDR_B_DQS0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59

MEM_SMBDATA
MEM_SMBCLK

+3VS

5

1

C456

C456

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

DIMM0 REV H:9.2mm (BOT)

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-MARG-7F

FOX_AS0A426-MARG-7F

Change PCB Footprint

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

4

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
DDR_B_CLK1

DDR_B_CLK#1
DDR_B_D14

DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_ODT0
DDR_B_MA13

DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_CLK2
DDR_B_CLK#2

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R289 10K_0402_5%R289 10K_0402_5%

1 2

R288 10K_0402_5%R288 10K_0402_5%

1 2

4.7U_0805_10V4Z
1

2

DDR_B_CLK1 (5)
DDR_B_CLK#1 (5)

DDR_CKE1_DIMMB (5)

DDR_B_BS#1 (5)
DDR_B_RAS# (5)
DDR_CS0_DIMMB# (5)

DDR_B_ODT0 (5)

DDR_CS3_DIMMB# (5)

DDR_B_CLK2 (5)
DDR_B_CLK#2 (5)

+3VS

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

Issued Date

Issued Date

Issued Date

3

+1.8V

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1

2

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

DDR_B_D[0..63](5)

DDR_B_DM[0..7](5)

DDR_B_DQS[0..7](5)

DDR_B_MA[0..15](5)

DDR_B_DQS#[0..7](5)

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C624

C624

C625

C625

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C481

C483

C483

DDR_CS2_DIMMB#
DDR_CKE0_DIMMB

DDR_B_MA12
DDR_B_BS#2

DDR_B_MA8
DDR_B_MA9

DDR_B_MA3
DDR_B_MA5

DDR_B_MA10
DDR_B_MA1

DDR_B_WE#
DDR_B_BS#0

DDR_CS0_DIMMB#
DDR_B_RAS#

DDR_B_ODT1
DDR_CS3_DIMMB#

+0.9V

Compal Secret Data

Compal Secret Data

Compal Secret Data

C481

C482

C482

Deciphered Date

Deciphered Date

Deciphered Date

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C623

C623

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C480

C480

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

1 4
2 3

RP22 47_0404_4P2R_5%RP22 47_0404_4P2R_5%

1 4
2 3

RP23 47_0404_4P2R_5%RP23 47_0404_4P2R_5%

1 4
2 3

RP24 47_0404_4P2R_5%RP24 47_0404_4P2R_5%

1 4
2 3

RP25 47_0404_4P2R_5%RP25 47_0404_4P2R_5%

1 4
2 3

RP26 47_0404_4P2R_5%RP26 47_0404_4P2R_5%

1 4
2 3

RP27 47_0404_4P2R_5%RP27 47_0404_4P2R_5%

1 4
2 3

RP29 47_0404_4P2R_5%RP29 47_0404_4P2R_5%

R286 47_0402_1%R286 47_0402_1%

1 2

R287 47_0402_1%R287 47_0402_1%

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C476

C476

Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V

5

Dr-Bios.com

H_CADOP0(4)
H_CADON0(4)
H_CADOP1(4)

D D

C C

C46

L7

+3VS

B B

+1.2V_HT

1 2

MBK1608121YZF_0603 L7MBK1608121YZF_0603

L13

L13

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

C46

4.7U_0805_10V4Z

4.7U_0805_10V4Z

H_CADON1(4)
H_CADOP2(4)
H_CADON2(4)
H_CADOP3(4)
H_CADON3(4)
H_CADOP4(4)
H_CADON4(4)
H_CADOP5(4)
H_CADON5(4)
H_CADOP6(4)
H_CADON6(4)
H_CADOP7(4)
H_CADON7(4)

H_CADOP8(4)
H_CADON8(4)
H_CADOP9(4)
H_CADON9(4)
H_CADOP10(4)
H_CADON10(4)
H_CADOP11(4)
H_CADON11(4)
H_CADOP12(4)
H_CADON12(4)
H_CADOP13(4)
H_CADON13(4)
H_CADOP14(4)
H_CADON14(4)
H_CADOP15(4)
H_CADON15(4)

H_CLKOP0(4)
H_CLKON0(4)
H_CLKOP1(4)
H_CLKON1(4)

H_CTLOP0(4)
H_CTLON0(4)

H_THERMTRIP#(6)

PROCHOT#(6)

1

2

C141

C141
10U_0805_10V4Z

10U_0805_10V4Z

1

2

C43

C43

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C101

C101

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

4

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

H_CTLOP0
H_CTLON0

+3.3V_PLL_CPU

+1.2V_PLL_CPU_HT

+1.2V_HT

AF16
AG16
AH16

AJ16

AJ15
AK15
AK16
AL16

AG17

AF17
AL17
AK17
AL18
AK18

AJ19
AK19

AD14

AE14
AF14

AG14
AH14

AJ14
AL13
AK13

AC15
AD15
AD16

AE16
AE17

AD17

AB17

AC17

AJ17

AH17

AL14
AK14

AH19
AG19
AC18
AD18

AC13

AB13

AB16

AB15

1 2

R364 150_0402_1%

R364 150_0402_1%

1 2

R366 150_0402_1%

R366 150_0402_1%

AM12

AL12

U23A

U23A

HT_MCP_RXD0_P
HT_MCP_RXD0_N
HT_MCP_RXD1_P
HT_MCP_RXD1_N
HT_MCP_RXD2_P
HT_MCP_RXD2_N
HT_MCP_RXD3_P
HT_MCP_RXD3_N
HT_MCP_RXD4_P
HT_MCP_RXD4_N
HT_MCP_RXD5_P
HT_MCP_RXD5_N
HT_MCP_RXD6_P
HT_MCP_RXD6_N
HT_MCP_RXD7_P
HT_MCP_RXD7_N

HT_MCP_RXD8_P
HT_MCP_RXD8_N
HT_MCP_RXD9_P
HT_MCP_RXD9_N
HT_MCP_RXD10_P
HT_MCP_RXD10_N
HT_MCP_RXD11_P
HT_MCP_RXD11_N
HT_MCP_RXD12_P
HT_MCP_RXD12_N
HT_MCP_RXD13_P
HT_MCP_RXD13_N
HT_MCP_RXD14_P
HT_MCP_RXD14_N
HT_MCP_RXD15_P
HT_MCP_RXD15_N

HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N

HT_MCP_RXCTL0_P
HT_MCP_RXCTL0_N
HT_MCP_RXCTL1_P/RESERVED
HT_MCP_RXCTL1_N/RESERVED

THERMTRIP#/GPIO_58
PROCHOT#/GPIO_20

+3.3V_PLL_CPU

+1.2V_PLL_CPU_HT

HT_MCP_COMP_VDD

HT_MCP_COMP_GND

MCP67-MV_PBGA836

MCP67-MV_PBGA836

3

MCP67

MCP67
PART 1 OF 8

PART 1 OF 8

HT

HT

RESERVED/HT_MCP_TXCTL1_P

RESERVED/HT_MCP_TXCTL1_N

HT_MCP_TXD0_P
HT_MCP_TXD0_N
HT_MCP_TXD1_P
HT_MCP_TXD1_N
HT_MCP_TXD2_P
HT_MCP_TXD2_N
HT_MCP_TXD3_P
HT_MCP_TXD3_N
HT_MCP_TXD4_P
HT_MCP_TXD4_N
HT_MCP_TXD5_P
HT_MCP_TXD5_N
HT_MCP_TXD6_P
HT_MCP_TXD6_N
HT_MCP_TXD7_P
HT_MCP_TXD7_N

HT_MCP_TXD8_P
HT_MCP_TXD8_N
HT_MCP_TXD9_P
HT_MCP_TXD9_N

HT_MCP_TXD10_P

HT_MCP_TXD10_N

HT_MCP_TXD11_P

HT_MCP_TXD11_N

HT_MCP_TXD12_P

HT_MCP_TXD12_N

HT_MCP_TXD13_P

HT_MCP_TXD13_N

HT_MCP_TXD14_P

HT_MCP_TXD14_N

HT_MCP_TXD15_P

HT_MCP_TXD15_N

HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N

HT_MCP_TXCTL0_P
HT_MCP_TXCTL0_N

HT_MCP_REQ#

HT_MCP_STOP#

HT_MCP_RST#

HT_MCP_PWRGD

CLKOUT_200MHZ_P
CLKOUT_200MHZ_N

CLKOUT_25MHZ

CPU_SBVREF

CLK200_TERM_GND

AK27
AJ27
AK26
AL26
AK25
AL25
AL24
AK24
AK22
AL22
AK21
AL21
AH21
AJ21
AL20
AM20

AG27
AH27
AF25
AG25
AH25
AJ25
AE23
AF23
AD21
AE21
AF21
AG21
AC20
AD20
AE19
AF19

AK23
AJ23
AG23
AH23

AK20
AJ20
AD19
AC19

AD23
AB20
AC21
AD22

AL28
AM28

AK28
AG28
AJ28

R123

R123

2.37K_0402_1%

2.37K_0402_1%

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

H_CTLIP0
H_CTLIN0

HTCPU_REQ#
HTCPU_STOP#
HTCPU_RST#
HTCPU_PWRGD

12

TP4 PADTP4 PAD

1

C136

C136

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

H_CADIP0 (4)
H_CADIN0 (4)
H_CADIP1 (4)
H_CADIN1 (4)
H_CADIP2 (4)
H_CADIN2 (4)
H_CADIP3 (4)
H_CADIN3 (4)
H_CADIP4 (4)
H_CADIN4 (4)
H_CADIP5 (4)
H_CADIN5 (4)
H_CADIP6 (4)
H_CADIN6 (4)
H_CADIP7 (4)
H_CADIN7 (4)

H_CADIP8 (4)
H_CADIN8 (4)
H_CADIP9 (4)
H_CADIN9 (4)
H_CADIP10 (4)
H_CADIN10 (4)
H_CADIP11 (4)
H_CADIN11 (4)
H_CADIP12 (4)
H_CADIN12 (4)
H_CADIP13 (4)
H_CADIN13 (4)
H_CADIP14 (4)
H_CADIN14 (4)
H_CADIP15 (4)
H_CADIN15 (4)

H_CLKIP0 (4)
H_CLKIN0 (4)
H_CLKIP1 (4)
H_CLKIN1 (4)

H_CTLIP0 (4)
H_CTLIN0 (4)

HTCPU_STOP# (6)
HTCPU_RST# (6)
HTCPU_PWRGD (6)

CPUCLK (6)
CPUCLK# (6)

9/25 Modify TO +3VS

+3VS

12

R164

R164
22K_0402_5%

22K_0402_5%

+1.2V_HT

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

10 43Tuesday, November 27, 2007

10 43Tuesday, November 27, 2007

10 43Tuesday, November 27, 2007

1

C

C

C

5

Dr-Bios.com

PCIE_GTX_C_MRX_P[0..15](18) PCIE_MTX_C_GRX_P[0..15](18)
PCIE_GTX_C_MRX_N[0..15](18)

D D

+3V

12

R45

R45
10K_0402_5%

10K_0402_5%
@

C C

B B

MP 2007/5/10 Modify

R550 0_0402_5%

R550 0_0402_5%

A A

R551 0_0402_5% MINI2@R551 0_0402_5% MINI2@

R552 0_0402_5% MINI1@R552 0_0402_5% MINI1@

12

12

12

MCP_PCIE_WAKE#(25,26,27)

PE_PRSNTX16#(18)

PCIE_MRX_PTX_P1(26)
PCIE_MRX_PTX_N1(26)

EXP_CLKREQ#(26)

PCIE_MRX_PTX_P2(25)
PCIE_MRX_PTX_N2(25)

MINI2_CLKREQ#(25)

PCIE_MRX_PTX_P3(25)
PCIE_MRX_PTX_N3(25)

MINI1_CLKREQ#(25)

L19

L19

+1.2VS

+1.2VS

+3VS

@

@

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

L5

1 2

MBK1608121YZF_0603 L5MBK1608121YZF_0603

L6

1 2

MBK1608121YZF_0603 L6MBK1608121YZF_0603

PEA_PRSNT#

PEB_PRSNT#

PEC_PRSNT#

C18

C18

4.7U_0805_10V4Z

4.7U_0805_10V4Z

@

R146 0_0402_5%

R146 0_0402_5%

1 2

R147 0_0402_5%

R147 0_0402_5%

1 2

+3VS

R139 0_0402_5% MINI2@R139 0_0402_5% MINI2@

1 2

R140 0_0402_5% MINI2@R140 0_0402_5% MINI2@

1 2

+3VS

R134 0_0402_5%

R134 0_0402_5%

1 2

R135 0_0402_5%

R135 0_0402_5%

1 2

+3VS

C115

C115

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

EXPRESS@

EXPRESS@

EXPRESS@

EXPRESS@

PEA_PRSNT#

PEB_PRSNT#

MINI1@

MINI1@

MINI1@

MINI1@

PEC_PRSNT#

1

2

C104

C104

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C25

C25

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

MCP_PCIE_WAKE#
R365 10K_0402_5%@R365 10K_0402_5%@
R367 10K_0402_5%@R367 10K_0402_5%@
R149 10K_0402_5%@R149 10K_0402_5%@

R152 10K_0402_5%

R152 10K_0402_5%

R118 10K_0402_5%

R118 10K_0402_5%

R148 10K_0402_5%

R148 10K_0402_5%

C105

C105

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

1

2

12
12
12

PCIE_MRX_PTX_P1_R

PCIE_MRX_PTX_N1_R

12

EXPRESS@

EXPRESS@

PCIE_MRX_PTX_P2_R

PCIE_MRX_PTX_N2_R PCIE_MTX_C_PRX_N2

12

MINI2@

MINI2@

PCIE_MRX_PTX_P3_R

PCIE_MRX_PTX_N3_R

12

MINI1@

MINI1@

+1.2V_PLL_PE_SS1

+1.2V_PLL_PE1

+3.3V_PLL_PE_SS1

1

2

C26

C26

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

R145

R145

2.37K_0402_1%

2.37K_0402_1%
@

@

U23B

U23B

F23

PE0_RX0_P

G23

PE0_RX0_N

F24

PE0_RX1_P

F25

PE0_RX1_N

D25

PE0_RX2_P

D26

PE0_RX2_N

C28

PE0_RX3_P

D28

PE0_RX3_N

C29

PE0_RX4_P

C30

PE0_RX4_N

D29

PE0_RX5_P

D30

PE0_RX5_N

F26

PE0_RX6_P

F27

PE0_RX6_N

F28

PE0_RX7_P

F29

PE0_RX7_N

H23

PE0_RX8_P

H24

PE0_RX8_N

H25

PE0_RX9_P

H26

PE0_RX9_N

H27

PE0_RX10_P

H28

PE0_RX10_N

K24

PE0_RX11_P

K25

PE0_RX11_N

K27

PE0_RX12_P

K26

PE0_RX12_N

K28

PE0_RX13_P

K29

PE0_RX13_N

J31

PE0_RX14_P

J30

PE0_RX14_N

K31

PE0_RX15_P

K30

PE0_RX15_N

H17

PE_WAKE#/GPIO_21

U31

PE0_PRSNTX1#/DDC_CLK1

U30

PE0_PRSNTX4#/DDC_DATA1

U29

PE0_PRSNTX8#/EXP_EN

U28

PE0_PRSNTX16#

L29

PE1_RX_P

L30

PE1_RX_N

W27

PEA_CLKREQ#

W28

PEA_PRSNT#

M26

PE2_RX_P

M27

PE2_RX_N

U26

PEB_CLKREQ#

U27

PEB_PRSNT#

N23

PE3_RX_P

N22

PE3_RX_N

U25

PEC_CLKREQ#

U24

PEC_PRSNT#

N30

PE4_RX_P

N31

PE4_RX_N

R22

PED_CLKREQ#/GPIO_16

U23

PED_PRSNT#

P31

PE5_RX_P

P30

PE5_RX_N

T22

PEE_CLKREQ#/GPIO_17

V31

PEE_PRSNT#

P26

PE6_RX_P

P27

PE6_RX_N

U22

PEF_CLKREQ#/GPIO_18

V30

PEF_PRSNT#

U19

+1.2V_PLL_PE_SS1

U20

+1.2V_PLL_PE_SS2

R20

+1.2V_PLL_PE1

R19

+1.2V_PLL_PE2

P19

+3.3V_PLL_PE_SS1

P20

+3.3V_PLL_PE_SS2

V24

PE_CLK_COMP

MCP67-MV_PBGA836

MCP67-MV_PBGA836

3

MVP67

MVP67
PART 2 OF 8

PART 2 OF 8

PCIE GFX I/F

PCIE GFX I/F

PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P

PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

PE0_REFCLK_P
PE0_REFCLK_N

PE1_TX_P

PE1_TX_N
PE1_REFCLK_P
PE1_REFCLK_N

PE2_TX_P

PE2_TX_N
PE2_REFCLK_P
PE2_REFCLK_N

PE3_TX_P

PE3_TX_N
PE3_REFCLK_P
PE3_REFCLK_N

PE4_TX_P

PE4_TX_N
PE4_REFCLK_P
PE4_REFCLK_N

PE5_TX_P

PE5_TX_N
PE5_REFCLK_P
PE5_REFCLK_N

PE6_TX_P

PE6_TX_N
PE6_REFCLK_P
PE6_REFCLK_N

PEX_RST#

PEX_RST1#

PCIE_MTX_GRX_P0

D24

PCIE_MTX_GRX_N0

C24

PCIE_MTX_GRX_P1

A24

PCIE_MTX_GRX_N1

B24

PCIE_MTX_GRX_P2

B25

PCIE_MTX_GRX_N2

C25

PCIE_MTX_GRX_P3

B26

PCIE_MTX_GRX_N3

C26

PCIE_MTX_GRX_P4

C27

PCIE_MTX_GRX_N4

D27

PCIE_MTX_GRX_P5

A28

PCIE_MTX_GRX_N5

B28

PCIE_MTX_GRX_P6

A29

PCIE_MTX_GRX_N6

B29

PCIE_MTX_GRX_P7

A30

PCIE_MTX_GRX_N7

B30

PCIE_MTX_GRX_P8

B31

PCIE_MTX_GRX_N8

B32

PCIE_MTX_GRX_P9

C31

PCIE_MTX_GRX_N9

C32

PCIE_MTX_GRX_P10

D31

PCIE_MTX_GRX_N10

D32

PCIE_MTX_GRX_P11

E31

PCIE_MTX_GRX_N11

E30

PCIE_MTX_GRX_P12

F31

PCIE_MTX_GRX_N12

F30

PCIE_MTX_GRX_P13

G29

PCIE_MTX_GRX_N13

G30

PCIE_MTX_GRX_P14

H29

PCIE_MTX_GRX_N14

H30

PCIE_MTX_GRX_P15

H32

PCIE_MTX_GRX_N15

H31

CLK_PCIE_VGA

R29

CLK_PCIE_VGA#

R30

PCIE_MTX_PRX_P1

M28

PCIE_MTX_PRX_N1

M29
T32
T31

M24

PCIE_MTX_PRX_N2

M25
T29
T30

M22

PCIE_MTX_PRX_N3

M23
T27
T28

M30
M31
T25
T26

P29
P28
T23
T24

P24
P25
P23
R23

W30

W29

R165 0_0402_5% R165 0_0402_5%

PCIE_MTX_C_GRX_N[0..15](18)

C194 0.1U_0402_16V7K VGA@C194 0.1U_0402_16V7K VGA@

1 2

C167 0.1U_0402_16V7K VGA@C167 0.1U_0402_16V7K VGA@

1 2

C196 0.1U_0402_16V7K VGA@C196 0.1U_0402_16V7K VGA@

1 2

C169 0.1U_0402_16V7K VGA@C169 0.1U_0402_16V7K VGA@

1 2

C198 0.1U_0402_16V7K VGA@C198 0.1U_0402_16V7K VGA@

1 2

C171 0.1U_0402_16V7K VGA@C171 0.1U_0402_16V7K VGA@

1 2

C200 0.1U_0402_16V7K VGA@C200 0.1U_0402_16V7K VGA@

1 2

C173 0.1U_0402_16V7K VGA@C173 0.1U_0402_16V7K VGA@

1 2

C202 0.1U_0402_16V7K VGA@C202 0.1U_0402_16V7K VGA@

1 2

C175 0.1U_0402_16V7K VGA@C175 0.1U_0402_16V7K VGA@

1 2

C204 0.1U_0402_16V7K VGA@C204 0.1U_0402_16V7K VGA@

1 2

C177 0.1U_0402_16V7K VGA@C177 0.1U_0402_16V7K VGA@

1 2

C229 0.1U_0402_16V7K VGA@C229 0.1U_0402_16V7K VGA@

1 2

C238 0.1U_0402_16V7K VGA@C238 0.1U_0402_16V7K VGA@

1 2

C231 0.1U_0402_16V7K VGA@C231 0.1U_0402_16V7K VGA@

1 2

C240 0.1U_0402_16V7K VGA@C240 0.1U_0402_16V7K VGA@

1 2

EXPRESS@

EXPRESS@

C249 0.1U_0402_16V7K

C249 0.1U_0402_16V7K

1 2

C248 0.1U_0402_16V7K

C248 0.1U_0402_16V7K

EXPRESS@

EXPRESS@
MINI2@

MINI2@

C220 0.1U_0402_16V7K

C220 0.1U_0402_16V7K

1 2

C219 0.1U_0402_16V7K

C219 0.1U_0402_16V7K

MINI2@

MINI2@
MINI1@

MINI1@

C235 0.1U_0402_16V7K

C235 0.1U_0402_16V7K

1 2

C234 0.1U_0402_16V7K

C234 0.1U_0402_16V7K

MINI1@

MINI1@

1 2

1 2

1 2

1 2

2

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

HT_VLD(15,31)

PE_RST0#

PCIE_RST1#

CLOSE TO CONNECT

C193 0.1U_0402_16V7KVGA@ C193 0.1U_0402_16V7KVGA@

1 2

C166 0.1U_0402_16V7KVGA@ C166 0.1U_0402_16V7KVGA@

1 2

C195 0.1U_0402_16V7KVGA@ C195 0.1U_0402_16V7KVGA@

1 2

C168 0.1U_0402_16V7KVGA@ C168 0.1U_0402_16V7KVGA@

1 2

C197 0.1U_0402_16V7KVGA@ C197 0.1U_0402_16V7KVGA@

1 2

C170 0.1U_0402_16V7KVGA@ C170 0.1U_0402_16V7KVGA@

1 2

C199 0.1U_0402_16V7KVGA@ C199 0.1U_0402_16V7KVGA@

1 2

C172 0.1U_0402_16V7KVGA@ C172 0.1U_0402_16V7KVGA@

1 2

C201 0.1U_0402_16V7KVGA@ C201 0.1U_0402_16V7KVGA@

1 2

C174 0.1U_0402_16V7KVGA@ C174 0.1U_0402_16V7KVGA@

1 2

C203 0.1U_0402_16V7KVGA@ C203 0.1U_0402_16V7KVGA@

1 2

C176 0.1U_0402_16V7KVGA@ C176 0.1U_0402_16V7KVGA@

1 2

C228 0.1U_0402_16V7KVGA@ C228 0.1U_0402_16V7KVGA@

1 2

C237 0.1U_0402_16V7KVGA@ C237 0.1U_0402_16V7KVGA@

1 2

C230 0.1U_0402_16V7KVGA@ C230 0.1U_0402_16V7KVGA@

1 2

C239 0.1U_0402_16V7KVGA@ C239 0.1U_0402_16V7KVGA@

1 2

PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1
CLK_PCIE_CARD
CLK_PCIE_CARD#

PCIE_MTX_C_PRX_P2PCIE_MTX_PRX_P2
CLK_PCIE_MINI2

CLK_PCIE_MINI2#

PCIE_MTX_C_PRX_P3PCIE_MTX_PRX_P3
PCIE_MTX_C_PRX_N3
CLK_PCIE_MINI1
CLK_PCIE_MINI1#

+3V

HT_VLD
PE_RST0#

PCIE_RST1# (25)

FOR MINI CARD

2

B

1

A

R170 0_0402_5%

R170 0_0402_5%

1 2

R169 0_0402_5%@ R169 0_0402_5%@

PCIE_RST1# PCIE_RST#

1 2

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

CLK_PCIE_VGA (18)
CLK_PCIE_VGA# (18)

PCIE_MTX_C_PRX_P1 (26)
PCIE_MTX_C_PRX_N1 (26)
CLK_PCIE_CARD (26)
CLK_PCIE_CARD# (26)

PCIE_MTX_C_PRX_P2 (25)
PCIE_MTX_C_PRX_N2 (25)
CLK_PCIE_MINI2 (25)
CLK_PCIE_MINI2# (25)

PCIE_MTX_C_PRX_P3 (25)
PCIE_MTX_C_PRX_N3 (25)
CLK_PCIE_MINI1 (25)
CLK_PCIE_MINI1# (25)

1

C267

C267

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5
U5

U5

P

G

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

3

2

4

Y

@

@

PCIE_RST#

1

NEW CARD

MINI_CARD(WLAN)

MINI_CARD(TV)

PCIE_RST# (18,26)

FOR VGA,LAN,NEW CARD

PEA_PRSNT#
PEB_PRSNT#
PEC_PRSNT#

1 2

R553 0_0402_5% @R553 0_0402_5% @

1 2

R554 0_0402_5% @R554 0_0402_5% @

1 2

R555 0_0402_5% @R555 0_0402_5% @

5

EXP_CLKREQ#
MINI2_CLKREQ#
MINI1_CLKREQ#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

CP_PE#(14,26)

4

1 2

R563 0_0402_5% EXPRESS@R563 0_0402_5% EXPRESS@

PEA_PRSNT#

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

Date: Sheet of

11 43Tuesday, November 27, 2007

11 43Tuesday, November 27, 2007

11 43Tuesday, November 27, 2007

1

C

C

C

5

Dr-Bios.com

4

3

2

1

+3VMAC+3V

U23C

1 2

R556 0_0805_5%@R556 0_0805_5%@

+3VAUX

1 2

D D

R557 0_0805_5%R557 0_0805_5%

40 mil

MP Modify 2007/04/13

C51

C51

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

MP Modify 2007/07/03

LINK10 LINK10_R

LINK10(22)

+3V +3V

C C

12

R526

R526
10K_0402_5%

10K_0402_5%

@

@

12

R527

R527
10K_0402_5%

10K_0402_5%

B B

R567 0_0402_5%R567 0_0402_5%

TXCLK

LINK10_R

12

L25

L25
MBK1608121YZF_0603

MBK1608121YZF_0603

1 2

+3V

12

R525

R525
10K_0402_5%

10K_0402_5%

2
3
4

TXCLK TXCLK_PHY_RTXCLK_R_

12

L24

L24
MBK1608121YZF_0603

MBK1608121YZF_0603
@

@

C210

C210

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

2

+3.3V_PLL

U40

U40

CLKIN1NC
SS%
GND
SSON

S IC PCS3P23Z01DG-08-TR TSSOP 8P

S IC PCS3P23Z01DG-08-TR TSSOP 8P

R529 0_0402_5% @R529 0_0402_5% @

NC

VDD

CLKOUT

1 2

1

2

C148

C148

0.1U_0402_16V4Z

0.1U_0402_16V4Z

8
7
6
5

MP Modify 2007/04/13

A A

SLP_RMGT#(15,22)

5

R559

R559
20K_0402_1%

20K_0402_1%

1 2

R560

R560
0_0402_5%

0_0402_5%

+3VMAC

+3VMAC

12

1

2

49.9_0402_1%

49.9_0402_1%

C190

C190
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

2

12

+3VMAC

12

L9

L9
MBK1608121YZF_0603

MBK1608121YZF_0603

R349

R349

49.9_0402_1%

49.9_0402_1%

C53

C53

0.1U_0402_16V4Z

0.1U_0402_16V4Z
12

R68

R68

R67

R67
124_0402_1%

124_0402_1%

27MHZ_20P_7A27000010

27MHZ_20P_7A27000010

1

C508

C508
22P_0402_50V8J

22P_0402_50V8J

2

UMA&TV@

UMA&TV@

C682

C682

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

R528 22_0402_5%

R528 22_0402_5%

1 2

R530 0_0402_5% @R530 0_0402_5% @

+3VS+3VS+3VS+1.8VS

12

12

L20

L20
MBK1608121YZF_0603

MBK1608121YZF_0603

L22

L22
MBK1608121YZF_0603

MBK1608121YZF_0603

+3V+3V

12

R558

R558
10K_0402_5%

10K_0402_5%

13

D

D

Q63

Q63

2

2N7002_SOT23

2N7002_SOT23

G

G

S

S

R479 10K_0402_5%@R479 10K_0402_5%@
R321 10K_0402_5%@R321 10K_0402_5%@

RGMII_INTR(22)

12

Y3

Y3

1 2

UMA&TV@

UMA&TV@

UMA_ENVDD(20)

TXCLK_PHYTXCLK_PHY_R

1

2
C211

C211

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.2VALW

S

S

G

G

Q62

Q62

2

AO3413_SOT23-3

AO3413_SOT23-3

D

D

1 3

+1.2VALW_MAC

6 mil

RXD0(22)
RXD1(22)
RXD2(22)
RXD3(22)
RXCLK(22)
RXCTL(22)

12

RGMII_INTR_R

12

RGMII_INTR

R514 0_0402_5%R514 0_0402_5%

12

1

2

R66

C55

C55

0.01U_0402_16V7K

0.01U_0402_16V7K

1

2

DPST_PWM(20,27,28)

ENBKL(18,27,28)

R66
124_0402_1%

124_0402_1%

NB_XTALIN
NB_XTALOUT

C507

C507
22P_0402_50V8J

22P_0402_50V8J
UMA&TV@

UMA&TV@

R121 0_0402_5% UMA@R121 0_0402_5%UMA@

TXCLK_PHY (22)

PVT Modify 2007/03/12

MP Modify 2007/07/03

R24 22K_0402_5%

R24 22K_0402_5%

1 2

R138 6.2K_0402_5%R138 6.2K_0402_5%

1 2

R136 10K_0402_5%R136 10K_0402_5%

+3VS

C221

C221

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

1 2

1

2

C212

C212

0.01U_0402_16V7K

0.01U_0402_16V7K

C178

C178

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

2

2

4

1 2

1 2

RXD0
RXD1
RXD2
RXD3
RXCLK
RXCTL

RGMII_INTR_R

1

2

C103

C103

0.01U_0402_16V7K

0.01U_0402_16V7K

1

1

2

2

C66

C66

4.7U_0805_10V4Z

4.7U_0805_10V4Z

+1.8V_IFP_MCP
+3.3V_PLL_IFPP

+3.3V_HDMI

C163

C163

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

R144

R144
1K_0402_1%

1K_0402_1%
@

@

C61

C61

0.1U_0402_16V4Z

0.1U_0402_16V4Z

LCD_BKLT_EN

1

2

PVT Modify 2007/03/12

C691

C691

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

B20
C20
E19
F19
G19

J20

C19

J18

D19

B18
N13
B17

C17

K21
D21

E23
H22

N15
E17
F17

U11
T11

AD24
AE25
AE27

AL29

AM29

AK29

AJ29

AM30

AL30

AK30

AJ30

AE26

AL32

AD25
AC26

AC24
AC25

AC23
AC22

AH29

AK31
AK32

C160

C160

0.1U_0402_16V4Z

0.1U_0402_16V4Z
@

@

U23C

RGMII_RXD0/MII_RXD0
RGMII_RXD1/MII_RXD1
RGMII_RXD2/MII_RXD2
RGMII_RXD3/MII_RXD3
RGMII_RXC/MII_RXCLK
RGMII_RXCTL/MII_RXDV

MII_RXER/GPIO_36
MII_COL/MI2C_DATA
MII_CRS/MI2C_CLK

RGMII/MII_INTR/GPIO35
+3.3V_PLL_MAC_DUAL
MII_COMP_3P3V

MII_COMP_GND

MCP67

MCP67
PART 3 OF 8

PART 3 OF 8

LAN

LAN

RGMII/MII_PWRDWN#/GPIO_37

+3.3V_DUAL_RMGT

+1.2V_DUAL_RMGT

RGMII_TXD0/MII_TXD0
RGMII_TXD1/MII_TXD1
RGMII_TXD2/MII_TXD2
RGMII_TXD3/MII_TXD3

RGMII_TXCLK/MII_TXCLK

RGMII_TXCTL/MII_TXEN

RGMII/MII_MDC

RGMII/MII_MDIO

BUF_25MHZ
MII_RESET#

MII_VREF

L14

+1.2VALW_MAC

N18

TXD0_R

J19

TXD1_R

K19

TXD2_R

L19

TXD3_R

L18

TXCLK_R TXCLK

H19

TXCTL_R

K18
K20

L20

RGMII_PWRDWN#

D17

R94 10K_0402_5%R94 10K_0402_5%

G17
C18

H20

MP Modify 2007/04/28

DDC_CLK0

DDC_CLK2

DDC_CLK3

B21
C21
B22

G21
H21

G8
H8

E21

F21
C23

C22
D23

AE30
AE31

AC30
AC29
AC27
AC28
AD30
AD29
AD31
AD32

AJ31
AJ32

AE28
AE29
AF30
AF31
AG30
AG29
AH31
AH30

L21
J22

L22
K22

AB31
AB30

C42

C42

0.1U_0402_16V4Z

0.1U_0402_16V4Z

IFPAB_RSET
IFPAB_PROBE

RGB_DAC_RSET
RGB_DAC_VREF

TV_DAC_RSET
TV_DAC_VREF

+3.3V_PLL_DISP
TV_XTALIN
TV_XTALOUT

GPIO_6/FERR//SYS_SERR/IGPU_GPIO_6*
GPIO_7/NFERR//SYS_PERR/IGPU_GPIO_7*

LCD_BKL_CTL
LCD_BKL_ON
LCD_PANEL_PWR

HDMI_TXC_P
HDMI_TXC_N

HDMI_TXD0_P
HDMI_TXD0_N
HDMI_TXD1_P
HDMI_TXD1_N
HDMI_TXD2_P
HDMI_TXD2_N

HPLUG_DET3
HPLUG_DET2

HDCP_ROM_SCLK
HDCP_ROM_SDATA

+1.8V_IFPA
+1.8V_IFPB

+3.3V_IFPAB_HVDD
+3.3V_HDMI_PLL_HVDD

+3.3V_HDMI

HDMI_RSET
HDMI_VPROBE

MCP67-MV_PBGA836

MCP67-MV_PBGA836

DACS

DACS

FLAT PANEL

FLAT PANEL

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC

DDC_DATA0

+3.3V_RGB_DAC

+3.3V_TV_DAC

TV_DAC_RED

TV_DAC_GREEN

TV_DAC_BLUE

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P

IFPA_TXD0_N

IFPA_TXD1_P

IFPA_TXD1_N

IFPA_TXD2_P

IFPA_TXD2_N

IFPA_TXD3_P

IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P

IFPB_TXD4_N

IFPB_TXD5_P

IFPB_TXD5_N

IFPB_TXD6_P

IFPB_TXD6_N

IFPB_TXD7_P

IFPB_TXD7_N

DDC_DATA2

DDC_DATA3

IFPAB_RSET

IFPAB_VPROBE

PVT Modify 2007/03/12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

R52 0_0603_5%

R52 0_0603_5%

1 2

R79 0_0603_5% @R79 0_0603_5% @

1 2

R473 22_0402_5% R473 22_0402_5%

1 2

R471 22_0402_5% R471 22_0402_5%

1 2

R474 22_0402_5% R474 22_0402_5%

1 2

R475 22_0402_5% R475 22_0402_5%

1 2

R476 33_0402_5%R476 33_0402_5%

1 2

R477 22_0402_5% R477 22_0402_5%

1 2

1 2

UMA_CRT_R
UMA_CRT_G
UMA_CRT_B

1

1

2

2

UMA_TV_CRMA
UMA_TV_LUMA
UMA_TV_COMPS

UMA_TXCLK+
UMA_TXCLK-

UMA_TXOUT0+
UMA_TXOUT0­UMA_TXOUT1+
UMA_TXOUT1­UMA_TXOUT2+
UMA_TXOUT2-

UMA_TZCLK+
UMA_TZCLK-

UMA_TZOUT0+
UMA_TZOUT0­UMA_TZOUT1+
UMA_TZOUT1­UMA_TZOUT2+
UMA_TZOUT2-

UMA_LCD_CLK
UMA_LCD_DATA

DDC_DATA3 DDC_DATA3

1

2

C528

C528

0.01U_0402_16V7K

0.01U_0402_16V7K
@

@

UMA_CRT_R (19)
UMA_CRT_G (19)
UMA_CRT_B (19)

UMA_CRT_HSYNC (19)
UMA_CRT_VSYNC (19)

UMA_CRT_CLK (19)

UMA_CRT_DATA (19)

C36

C36

4.7U_0805_10V4Z

4.7U_0805_10V4Z

UMA_TV_CRMA (19)

UMA_TV_LUMA (19)

UMA_TXCLK+ (20)
UMA_TXCLK- (20)

UMA_TXOUT0+ (20)
UMA_TXOUT0- (20)
UMA_TXOUT1+ (20)
UMA_TXOUT1- (20)
UMA_TXOUT2+ (20)
UMA_TXOUT2- (20)

UMA_TZOUT0+ (20)

UMA_TZOUT0- (20)

UMA_TZOUT1+ (20)

UMA_TZOUT1- (20)

UMA_TZOUT2+ (20)

UMA_TZOUT2- (20)

12

R372

R372
1K_0402_1%

1K_0402_1%
@

@

2

UMA_TV_COMPS (19)

UMA_TZCLK+ (20)

UMA_TZCLK- (20)

UMA_LCD_CLK (20)
UMA_LCD_DATA (20)

+3VMAC +1.2VALW

C44

C44

1

0.1U_0402_16V4Z

TXD0 (22)
TXD1 (22)
TXD2 (22)
TXD3 (22)

TXCTL (22)

RGMII_MDC (22)
RGMII_MDIO (22)

MII_RST (22)

C58

C58

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

0.1U_0402_16V4Z

2

+3VMAC

12

R69

R69

1.47K_0402_1%

1.47K_0402_1%

C40

C40

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C38

C38

1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+3VS

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

401474

401474

401474

12

R61

R61

1.47K_0402_1%

1.47K_0402_1%

L8

L8

1 2

MBK2012121YZF_0805

MBK2012121YZF_0805

UMA_CRT_R
UMA_CRT_G
UMA_CRT_B

UMA_TV_CRMA
UMA_TV_LUMA
UMA_TV_COMPS

UMA@

UMA@
R361 2.7K_0402_5%

R361 2.7K_0402_5%
R359 2.7K_0402_5%

R359 2.7K_0402_5%

R57 10K_0402_5%

R57 10K_0402_5%

R63 150_0402_1%

R63 150_0402_1%
R62 150_0402_1%

R62 150_0402_1%
R64 150_0402_1%

R64 150_0402_1%

R332 150_0402_1%

R332 150_0402_1%
R324 150_0402_1%

R324 150_0402_1%
R325 150_0402_1%

R325 150_0402_1%

1 2
1 2

1 2

1 2
1 2
1 2

1 2
1 2
1 2

RGMII_PWRDWN#

TXCLK_R

+3VS

TXCLK

UMA@

UMA@
UMA@

UMA@
UMA@

UMA@

UMA&TV@

UMA&TV@
UMA&TV@

UMA&TV@
UMA&TV@

UMA&TV@

UMA_LCD_CLK

UMA_LCD_DATA

1

12 43Tuesday, November 27, 2007

12 43Tuesday, November 27, 2007

12 43Tuesday, November 27, 2007

+3VMAC

12

R472

R472
10K_0402_5%

10K_0402_5%
@

@

12

R478

R478
10K_0402_5%

10K_0402_5%

12

C658

C658
33P_0402_50V8K

33P_0402_50V8K
@

@

12

C681

C681
33P_0402_50V8K

33P_0402_50V8K
@

@

C

C

C

5

Dr-Bios.com

4

3

2

1

RP3

RP3

+3VS

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

D D

+3VS

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

+3VS

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

+3VS

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

C C

+3VS

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%

B B

2 7
3 6
4 5

RP6

RP6

1 8
2 7
3 6
4 5

RP5

RP5

1 8
2 7
3 6
4 5

RP4

RP4

1 8
2 7
3 6
4 5

RP1

RP1

1 8
2 7
3 6
4 5

PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_SERR#
PCI_TRDY#
PCI_FRAME#
PCI_STOP#

PCI_IRDY#
PCI_PERR#
PCI_DEVSEL#

PCI_REQ#4
PM_CLKRUN#

LPC_DRQ#0
SERIRQ

PM_CLKRUN#

1 2

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8

PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQE#

PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_TRDY#

IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8

IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15

IDE_DREQ
IDE_IRQ
IDE_IORDY

12

PCI_REQ#0(23)

PCI_AD[31..0](23)

PCI_AD[31..0]

PCI_PIRQE#(23)
PCI_PIRQF#(23)

PCI_TRDY#(23)

LPC_DRQ#0

SERIRQ(23,27,28)

PM_CLKRUN#(23,27,28)

IDE_D[15..0](21)

IDE_DREQ(21)

IDE_IRQ(21)

IDE_IORDY(21)

IDE_IOR#(21)

IDE_D[15..0]

IDE_IOR#

R362 33_0402_5%R362 33_0402_5%
R43 15K_0402_5%

R43 15K_0402_5%

PCI_REQ#0

1 8

9/21 Add 33ohm for IDE_IOR#

U23D

U23D

E10

PCI_REQ0#

G10

PCI_REQ1#

J10

PCI_REQ2#/GPIO_40/RS232_DSR#

M11

PCI_REQ3#/GPIO_38/RS232_CTS#

E8

PCI_REQ4#/GPIO_52/RS232_SIN#

D10

PCI_AD0

B10

PCI_AD1

C10

PCI_AD2

L12

PCI_AD3

K11

PCI_AD4

J11

PCI_AD5

D11

PCI_AD6

C11

PCI_AD7

J12

PCI_AD8

H12

PCI_AD9

G12

PCI_AD10

F12

PCI_AD11

E12

PCI_AD12

D12

PCI_AD13

C12

PCI_AD14

B12

PCI_AD15

G14

PCI_AD16

E14

PCI_AD17

D14

PCI_AD18

J15

PCI_AD19

C14

PCI_AD20

D15

PCI_AD21

K15

PCI_AD22

C15

PCI_AD23

L16

PCI_AD24

G16

PCI_AD25

J16

PCI_AD26

E16

PCI_AD27

H16

PCI_AD28

D16

PCI_AD29

F16

PCI_AD30

A16

PCI_AD31

L17

PCI_INTW#

J17

PCI_INTX#

B16

PCI_INTY#

K17

PCI_INTZ#

K14

PCI_TRDY#

C6

LPC_DRQ1#/GPIO19/FANRPM1

B6

LPC_DRQ0#/GPIO_50

D6

LPC_SERIRQ

D5

LPC_CLKRUN/GPIO_42

AF10

IDE_DATA_P0

AL9

IDE_DATA_P1

AK8

IDE_DATA_P2

AK7

IDE_DATA_P3

AK6

IDE_DATA_P4

AJ6

IDE_DATA_P5

AL5

IDE_DATA_P6

AL4

IDE_DATA_P7

AJ5

IDE_DATA_P8

AK5

IDE_DATA_P9

AL6

IDE_DATA_P10

AJ7

IDE_DATA_P11

AJ8

IDE_DATA_P12

AL8

IDE_DATA_P13

AK9

IDE_DATA_P14

AG10

IDE_DATA_P15

AK11

IDE_DREQ_P

AH10

IDE_INTR_P

AK10

IDE_RDY_P

AL10

IDE_IOR_P#

AF12

CABLE_DET_P/GPIO_63

MCP67-MV_PBGA836

MCP67-MV_PBGA836

MCP67

MCP67
PART 4 OF 8

PART 4 OF 8

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI

PCI

PCI_PERR#/GPIO_43/RS232_DCD#

LPC_PWRDWN#/GPIO_54/EXT_NMI#

LPC

LPC

IDE

IDE

PCI_GNT0#

PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT1#

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR

PCI_SERR#
PCI_STOP#

PCI_PME#/GPIO_30

PCI_RESET0#
PCI_RESET1#
PCI_RESET2#
PCI_RESET3#

PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

PCI_CLKIN

LPC_FRAME#

LPC_RESET#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLK0
LPC_CLK1

IDE_ADDR_P0
IDE_ADDR_P1
IDE_ADDR_P2

IDE_CS1_P#
IDE_CS3_P#

IDE_DACK_P#

IDE_IOW_P#

IDE_COMP_3P3V
IDE_COMP_GND

PCI_GNT#0

F10
H10
K10
L10
F8

PCI_CBE#0

K12

PCI_CBE#1

K13

PCI_CBE#2

F14

PCI_CBE#3

K16

PCI_DEVSEL#

L13

PCI_FRAME#

J14

PCI_IRDY#

H14

PCI_PAR

B14

PCI_PERR#

J13

PCI_SERR#

C13

PCI_STOP#

B13

PCI_PME#

C16

R30 33_0402_5%R30 33_0402_5%

J9
K9
K8
L9

C9
B9
B8
A8
C8
D8

D7
B3

C7

A4
B4
C4
A3
B5

C5

AG12
AE12
AH12

AJ12
AK12
AJ11

AJ10

AM4
AK4

1 2

R33 33_0402_5%R33 33_0402_5%

1 2

CLK_PCI_1394_R

PCI_CLK4
PCI_CLKIN

CLK_PCI_LPC_R

IDE_A0
IDE_A1
IDE_A2

IDE_CS1#
IDE_CS3#
IDE_DACK#

IDE_IOW#

PCI_CBE#[3..0]

PCI_DEVSEL# (23)
PCI_FRAME# (23)
PCI_IRDY# (23)
PCI_PAR (23)
PCI_PERR# (23)
PCI_SERR# (23)
PCI_STOP# (23)

T4PAD T4PAD
T5PAD T5PAD

R40 22_0402_5% R40 22_0402_5%

R46 22_0402_5% R46 22_0402_5%

C31

C31

1

1

10P_0402_50V8J

10P_0402_50V8J

C30

C30
10P_0402_50V8J

10P_0402_50V8J

2

2

R329 22_0402_5% R329 22_0402_5%

1 2

T6PAD T6PAD

R54 33_0402_5%R54 33_0402_5%

1 2

R333 22_0402_5% R333 22_0402_5%

1 2

R328 22_0402_5% R328 22_0402_5%

1 2

R335 22_0402_5% R335 22_0402_5%

1 2

R311 22_0402_5% R311 22_0402_5%

1 2

R59 22_0402_5% R59 22_0402_5%

1 2

IDE_A0 (21)
IDE_A1 (21)
IDE_A2 (21)

IDE_CS1# (21)
IDE_CS3# (21)
IDE_DACK# (21)

IDE_IOW# (21)

PCI_GNT#0 (23)

PCI_CBE#[3..0] (23)

1 2

1 2

LPC_FRAME#LPC_DRQ#1

PCI_RST1394# (23)
PCIRST_IDE# (21)

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME# (14,27,28)

PLT_RST# (27,28)

LPC_AD0 (27,28)
LPC_AD1 (27,28)
LPC_AD2 (27,28)
LPC_AD3 (27,28)

CLK_PCI_LPC (27,28)

+3VS

12

R29

R29
121_0402_1%

121_0402_1%

12

R51

R51
121_0402_1%

121_0402_1%

PCI_PME# EC_PME#

Internal PU

CLK_PCI_1394 (23)

9/20 Added

+3V

5

A2Y

3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ#0
LPC_DRQ#1
SERIRQ

CLK_PCI_LPC_R

PCI_CBE#0

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

1

P

OE#

G

U32

U32

4

SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5
@

@

R38 8.2K_0402_5% @R38 8.2K_0402_5% @
R72 8.2K_0402_5% @R72 8.2K_0402_5% @
R36 10K_0402_5% @R36 10K_0402_5% @

JP35

JP35

1
3

39
40
41
42
43

S W-CONN AMP 2-767004-2 38P

S W-CONN AMP 2-767004-2 38P
@

@

SBPWR_EN# (34)

RP2

RP2

1 8
2 7
3 6
4 5

8.2K_1206_8P4R_5%

8.2K_1206_8P4R_5%
@

@

1 2
1 2
1 2

NC
NC

Debug Port

Debug Port

CLK05CLK1
A3<7>7A1<7>

A3<6>9A1<6>
A3<5>11A1<5>
A3<4>13A1<4>
A3<3>15A1<3>
A3<2>17A1<2>
A3<1>19A1<1>
A3<0>21A1<0>

A2<7>23A0<7>
A2<6>25A0<6>
A2<5>27A0<5>
A2<4>29A0<4>
A2<3>31A0<3>
A2<2>33A0<2>
A2<1>35A0<1>
A2<0>37A0<0>

GND
GND
GND
GND
GND

EC_PME# (27,28)

+3VS

@

@

2

NC

4

NC

6
8

10
12
14
16
18
20
22

24
26
28
30
32
34
36
38

C37

C37

1

10P_0402_50V8J

10P_0402_50V8J

2

PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10

PCI_AD9
PCI_AD8

PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

2006/08/18 2007/8/18

2006/08/18 2007/8/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

SCHEMATIC, M/B LA-3581P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

401474

401474

401474

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

13 43Tuesday, November 27, 2007

13 43Tuesday, November 27, 2007

13 43Tuesday, November 27, 2007

C

C

C