Acer Aspire 5515, eMachines E620 Schematics
A
1 1
B
C
D
E
2 2
Compal Confidential
KAW60 Schematics Document
AMD AM2 / RS690MC / SB600
2008 / 08 / 08 FOR Pre-MP
3 3
4 4
Rev:1.0
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/05/09 2006/03/08
2005/05/09 2006/03/08
2005/05/09 2006/03/08
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
D
Date: Sheet
150Friday, August 08, 2008
150Friday, August 08, 2008
150Friday, August 08, 2008
of
of
E
of
2.0
2.0
2.0
5
4
3
2
1
Compal confidential
Project Code: KAW60
File Name : LA-4661P
D D
Thermal Sensor
ADM1032ARM
page 8 page 17
Clock Generator
ICS951462
CRT & TV-OUT
page 24
Mini card
page 31
LCD CONN
page 25
PCIE X1
AMD AM2 CPU
940P PGA
H_A#(3..31)
ATI-RS690MC
465 BGA
page 12,13,14,15,16
page 6,7,8,9
H_D#(0..63)
HT 16x16 1000MHZ
A-Link Express
4 x PCIE
DDRII DDRII-SO-DIMM X2
533/667
page 10,11
Dual Channel
SIG1 : 35mm x 35mm x (2.20mm+2.11mm) 638pin
AM2 : 40mm x 40mm x (4.56mm+2.11mm) 940pin
RS485 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin
RS690 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin
SB460 : 27mm x 27mm (21.6mm x 21.6mm) x2.33mm 549pin
SB600 : 23mm x 23mm (21.6mm x 21.6mm) x2.33mm 549pin
C C
PCIE X1
ATI-SB600
PCI BUS
549 BGA
USB 2.0
USB 2.0
HD Audio
Mini PCI Socket
Mini card RTL8110SCL
page 31
Realtek
RTL8100CL
page 26
ENE Controller
CB714
page 32
1394 Controller
VT6311S
page 35
page 18,19,20,21,22
SATA
Realtek
B B
RTL8102EL
page 26
RJ45 CONN
page 27
Slot 0
page 33
6in1 CardReader
Slot
page 33
1394
Conn.
page 35
LPC BUS
SATA
USB conn x 2 / New card / Camera
page 34
BT Conn
page 38
HDA Codec
ALC268
page 39
MDC Conn.
page 41
AMP & Audio Jack
APA2057
page 31
page 40
HDD Conn.
page 23
CDROM Conn.
page 23
Power On/Off CKT / LID switch / Power OK CKT
page 37
DC/DC Interface CKT.
page 41
CIR/LED
page 38
RTC CKT.
page 18
Power Circuit DC/DC
page 42~48
A A
SMsC LPC47N207
page 36
FIR module
page 36
ENE KB926
Touch Pad
CONN.
page 29
page 28
Int. KBD
page 29
SPI BIOS
page 30
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
2
Date: Sheet
250Sunday, July 20, 2008
250Sunday, July 20, 2008
250Sunday, July 20, 2008
1
2.0
2.0
2.0
of
of
of
5
Voltage Rails
Power Plane
D D
C C
VIN
B+
+CPU_CORE
+0.9V
+1.2V_HT
+1.5VS
+1.8VALW
+1.8V
+1.8VS
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
+VSB
+RTCVCC
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator
1.2V switched power rail
1.5V switched power rail
1.8V always on power rail
1.8V power rail for DDR
1.8V switched power rail
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
4
S1 S3 S5
N/A N/A N/A
ON
ON ON
ON
ON
ON ON ON*
ON
ON
ON
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
OFF
OFF OFF
OFF OFF
OFF
ON
OFF
OFF
OFF
OFF
ON*
ON
OFF
OFF
ON
ON*
OFF
OFF
ON*ON
ON
ON
3
SIGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
SLP_S1# SLP_S3#
SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
HIGH
LOW
S4 (Suspend to Disk)
S5 (Soft OFF)
LOW LOW LOW LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2
LOWLOWLOW
ON
ON
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
OFF
ON
OFF
ON
V
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
ON ON
ON
OFF
OFF
OFF
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
1
LOW
OFF
OFF
OFF
max
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
Device
B B
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
(24C04)
IDSEL#
REQ#/GNT#
Interrupts
EC SM Bus2 address
Address Address
1010 000X b
1011 000X b
Device
ADM1032
1001 100X b0001 011X b
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
SKU ID Table
SKU ID
0
1
2
PCB Revision
SKU
BTO Option Table
BTO Item BOM Structure
WITH AMD HDT Debug port HDT@
WITH USBx2 USB2@
USBX1 WITH CHOKE
USBX1 WITHOUT CHOKE
USBx2 WITH CHOKE
USBx2 WITHOUT CHOKE
SPI ROM under SB600 SB600SPI@
EMI@
WOEMI@
USB2EMI@
USB2WOEMI@
MDC@WITH MODEM
3
4
5
SB600 SM Bus address
Device
Clock Generator
A A
(ICS951462)
DDR DIMM0
DDR DIMM2
5
Address
1101 001Xb
1001 000Xb
1001 010Xb
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
6
7
Compal Secret Data
Compal Secret Data
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
TABLE OF CONTENTS
TABLE OF CONTENTS
TABLE OF CONTENTS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
HCW51 LA-3121P
HCW51 LA-3121P
HCW51 LA-3121P
Date: Sheet
Date: Sheet
Date: Sheet
350Thursday, July 24, 2008
350Thursday, July 24, 2008
350Thursday, July 24, 2008
of
of
1
of
2.0
2.0
2.0
5
D D
DIMM3 DIMM4
DIMM1 DIMM2
3 PAIR MEM CLK
3 PAIR MEM CLK
M2 CPU
C C
M2 SOCKET
3 PAIR MEM CLK
3 PAIR MEM CLK
1 PAIR CPU CLK
200MHZ
EXTERNAL
CLK GEN.
B B
4
HTREFCLK
66MHZ
NB-OSC
14.318MHZ
NB PCIE CLK
100MHZ
SB PCIE CLK
100MHZ
SB-OSCIN
14.318MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
ATI NB -RS690
TVCLKIN
PCIE GFX SLOT - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 1 LANE
PCIE GBE
PCIE STAT
SB-OSCIN
3
14.318MHZ OSC INPUT
14.318MHZ
48MHZ OSC INPUT FOR USB
(OPTION)
SB-OSCIN
14.318MHZ
PCIE CLK
100MHZ
USB CLK
48MHZ
(OPTION)
ATI SB
SB600
PCI CLKFB
PCI CLK
33MHZ
AZ_BITCLK
2
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK1
33MHZ
PCI CLK6
33MHZ
PCI CLK5
33MHZ
SIO_CLK
24/48MHZ
25M Hz32.768K Hz
PCI SLOT0
PCI SLOT1
PCI SLOT2
LPC BIOS
SUPER IO
IT8712F
AC97 CODEC
AZALIA
KB_CLK
KEYBOARD
MS_CLK
24.576MHZ OSC INPUT
1
MOUSE
14.31818MHz
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/10 2006/10/10
2005/10/10 2006/10/10
2005/10/10 2006/10/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
2
Date: Sheet
450Tuesday, June 17, 2008
450Tuesday, June 17, 2008
450Tuesday, June 17, 2008
1
2.0
2.0
2.0
of
of
of
5
ATX P/S WITH 1A STBY CURRENT
-12V
3.3V
+/-5%
12V
+/-5%
+/-5%
5V
5VSB
+/-5%
+/-5%
D D
CPU
PW
12V
+/-5%
+5VDUAL_MEM (S0,S5)
4
2.5V SHUNT
REGULATOR
VRM SW
REGULATOR
1.8V VDD SW
REGULATOR
1.8V LINEAR
REGULATOR
VCC 1.2V SW
REGULATOR
0.9V VTT_DDR
REGULATOR
+1.8V(S0, S1)
VCC_NB (S0, S1)
3
CPU_VDDA_RUN (S0, S1)
CPU_VDD_RUN (S0, S1)
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
2
M2
VDDA 2.5V 0.1A
VDDCORE
0.8-1.55V 80A
DDRII MEM I/F VTT
0.125A, VDD 3A
VLDT 1.2V 0.5A
1
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
RS690
VDDHT 1.2V 0.5A
PCI-E CORE&VCO
& I/O &PLL 2.25A
NB CORE VDDC
1.2V 5A
DAC 200mA LVDS
1.8V 300mA
PLL & DAC-Q 0.1A
PCI-E PLL
+3.3VSB (S0, S1, S3, S4, S5)
+3.3VSB REGULATOR
ACPI CONTROLLER
C C
+3.3VDUAL (S0, S1, S3, S4, S5)
+5VDUAL (S0, S1, S3, S4, S5)
1.2V STB LDO
REGULATOR
+1.2VSB (S5)
SB600
X4 PCI-E 0.8A
ATA I/O 0.2A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
AZALIA CODEC
3.3V CORE 0.3A
B B
5V ANALOG 0.1A
SUPER I/O
+5V SD 0.01A
+5V 0.1A
3.0A3.0A
5.5A
CNR CONNECTOR
5V
3.3V
12V
3.3Vaux
-12V
0.5A
0.1A
X16 PCIEX1 PCIE per
3.3V
12V
PCI Slot (per slot)
5.0A
5V
3.3V
A A
12V
3.3Vaux
-12V
7.6A
0.5A
0.375A
0.1A
3.3V
12V
3.3Vaux
5VDual
+3.3VDUAL (S0, S1, S3)
5
4
1.0A
1.0A
0.5A
1.0A
0.1A
0.5A
USB X4 FR
VDD
5VDual
2.0A
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
USB X6 RL 2XPS/2
Issued Date
Issued Date
Issued Date
VDD
5VDual
2.0A
3
GBE
5VDual
1.0A
2005/10/10 2006/10/10
2005/10/10 2006/10/10
2005/10/10 2006/10/10
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
SATA
3.3V 0.3A (S0, S1)
2
Title
Title
Title
POWER DELIVERY CHART
POWER DELIVERY CHART
POWER DELIVERY CHART
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
Date: Sheet
550Tuesday, June 17, 2008
550Tuesday, June 17, 2008
550Tuesday, June 17, 2008
of
of
1
of
2.0
2.0
2.0
5
4
3
2
1
PROCESSOR HYPERTRANSPORT INTERFACE
D D
H_CADIP1512
H_CADIN1512
H_CADIP1412
H_CADIN1412
H_CADIP1312
H_CADIN1312
H_CADIP1212
H_CADIN1212
H_CADIP1112
H_CADIN1112
H_CADIP1012
H_CADIN1012
H_CADIP912
H_CADIN912
H_CADIP812
C C
+1.2V_HT
B B
H_CADIN812
H_CADIP712
H_CADIN712
H_CADIP612
H_CADIN612
H_CADIP512
H_CADIN512
H_CADIP412
H_CADIN412
H_CADIP312
H_CADIN312
H_CADIP212
H_CADIN212
H_CADIP112
H_CADIN112
H_CADIP012
H_CADIN012
H_CLKIP112
H_CLKIN112
H_CLKIP012
1 2
1 2
H_CLKIN012
H_CTLIP012
H_CTLIN012
R38 51_0402_1%R38 51_0402_1%
R37 51_0402_1%R37 51_0402_1%
Trace length limit (Don't care)
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_HT
JCPU1A
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
H_CTLIP1
H_CTLIN1
H_CTLIP0
H_CTLIN0
JCPU1A
AJ4
VLDT_06
AJ3
VLDT_05
AJ2
VLDT_02
AJ1
VLDT_01
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
HT LINK
HT LINK
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
VLDT_08
VLDT_07
VLDT_04
VLDT_03
H6
H5
H2
H1
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
1 2
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0
H_CTLON0
C455
C455
4.7U_0805_10V4Z
4.7U_0805_10V4Z
SOC127MM48X51-948! 6090022000; JCPU1
TEMP SYMBOL
H_CADOP15 12
H_CADON15 12
H_CADOP14 12
H_CADON14 12
H_CADOP13 12
H_CADON13 12
H_CADOP12 12
H_CADON12 12
H_CADOP11 12
H_CADON11 12
H_CADOP10 12
H_CADON10 12
H_CADOP9 12
H_CADON9 12
H_CADOP8 12
H_CADON8 12
H_CADOP7 12
H_CADON7 12
H_CADOP6 12
H_CADON6 12
H_CADOP5 12
H_CADON5 12
H_CADOP4 12
H_CADON4 12
H_CADOP3 12
H_CADON3 12
H_CADOP2 12
H_CADON2 12
H_CADOP1 12
H_CADON1 12
H_CADOP0 12
H_CADON0 12
H_CLKOP1 12
H_CLKON1 12
H_CLKOP0 12
H_CLKON0 12
H_CTLOP0 12
H_CTLON0 12
FAN Conn
+5VS
+VCC_FAN1
EN_DFAN128
1 2
R733 0_0402_5%R733 0_0402_5%
EN_DFAN1_R
1
2
C760
C760
0.01U_0402_16V7K@
0.01U_0402_16V7K@
C47 10U_0805_10V4ZC47 10U_0805_10V4Z
1 2
U1
U1
1
VEN
2
VIN
3
VO
4
VSET
APL5605_SOP8L
APL5605_SOP8L
FAN_SPEED128
GND
GND
GND
GND
8
7
6
5
PVT
+3VS
12
R34
R34
10K_0402_5%
10K_0402_5%
+5VS
12
D3
D3
CH355PT_SOD323
CH355PT_SOD323
12
D4
D4
BAS16_SOT23-3
BAS16_SOT23-3
FAN1
PVT
1
C92
C92
1000P_0402_50V7K
1000P_0402_50V7K
2
W=40mils
+VCC_FAN1
1 2
C83 10U_0805_10V4ZC83 10U_0805_10V4Z
1 2
C90 1000P_0402_50V7KC90 1000P_0402_50V7K
JP20
JP20
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
ACES_85205-03001
CONN@
CONN@
+1.2V_HT
1
C164
C164
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
LAYOUT: Place bypass cap on topside of board
A A
5
1
C156
C156
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
C158
C158
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
2
1
C163
C163
2
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C145
C145
180P_0402_50V8J
180P_0402_50V8J
1
2
1
2
4
C152
C152
180P_0402_50V8J
180P_0402_50V8J
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/11 2006/10/11
2005/10/11 2006/10/11
2005/10/11 2006/10/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
AMD CPU HT I/F
AMD CPU HT I/F
AMD CPU HT I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
Date: Sheet
1
of
of
of
650Friday, August 08, 2008
650Friday, August 08, 2008
650Friday, August 08, 2008
2.0
2.0
2.0
A
B
C
D
E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
4 4
+0.9V
+1.8V
12
R13
R13
39.2_0402_1%~D
39.2_0402_1%~D
R22
R22
12
39.2_0402_1%~D
39.2_0402_1%~D
PLACE THEM CLOSE TO
CPU WITHIN 1"
3 3
2 2
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
+1.8V
12
R33
R33
1K_0402_1%
1K_0402_1%
1 1
R23
R23
1K_0402_1%
1K_0402_1%
12
1000P_0402_50V7K
1000P_0402_50V7K
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
1
2
DDR_CS3_DIMMA#10
DDR_CS2_DIMMA#10
DDR_CS1_DIMMA#10
DDR_CS0_DIMMA#10
DDR_CS3_DIMMB#11
DDR_CS2_DIMMB#11
DDR_CS1_DIMMB#11
DDR_CS0_DIMMB#11
DDR_CKE1_DIMMB11
DDR_CKE0_DIMMB11
DDR_CKE1_DIMMA10
DDR_CKE0_DIMMA10
DDR_A_MA[15..0]10
C32
C32
10:8:10:8:10
DDR_A_BS#210
DDR_A_BS#110
DDR_A_BS#010
DDR_A_RAS#10
DDR_A_CAS#10
DDR_A_WE#10
1
C66
C66
1.5P_0402_50V8C
1.5P_0402_50V8C
2
1
C132
C132
1.5P_0402_50V8C
1.5P_0402_50V8C
2
1
C33
C33
1000P_0402_50V7K
1000P_0402_50V7K
2
+0.9VREF_CPU
TP3PAD TP3PAD
M_ZN
M_ZP
CPU_VREF_REF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VTT_SENSE
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
C34
C34
D12
C12
B12
A12
AK12
AJ12
AH12
AG12
AL12
F12
E12
AH11
AJ11
AD27
AA25
AC25
AA24
AE29
AB31
AE30
AC31
M31
M29
L27
M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
N25
Y27
AA27
AA26
AB25
AB27
1
1
2
2
1000P_0402_50V7K
1000P_0402_50V7K
JCPU1B
JCPU1B
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
MEMVREF
VTT_SENSE
MEMZN
MEMZP
MA1_CS_L1
MA1_CS_L0
MA0_CS_L1
MA0_CS_L0
MB1_CS_L1
MB1_CS_L0
MB0_CS_L1
MB0_CS_L0
MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_RAS_L
MA_CAS_L
MA_WE_L
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
+0.9VREF_CPU
1
C28
C28
C29
C29
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
DDR II: CMD/CTRL/CLK
DDR II: CMD/CTRL/CLK
MA1_CLK_H2
MA1_CLK_L2
MA1_CLK_H1
MA1_CLK_L1
MA1_CLK_H0
MA1_CLK_L0
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MA0_CLK_H0
MA0_CLK_L0
MB1_CLK_H2
MB1_CLK_L2
MB1_CLK_H1
MB1_CLK_L1
MB1_CLK_H0
MB1_CLK_L0
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_CLK_H0
MB0_CLK_L0
MB1_ODT0
MB0_ODT0
MA1_ODT0
MA0_ODT0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_RAS_L
MB_CAS_L
MB_WE_L
AE20
AE19
G20
G21
V27
W27
DDR_A_CLK2
AG21
DDR_A_CLK#2
AG20
DDR_A_CLK1
G19
DDR_A_CLK#1
H19
U27
U26
AL19
AL18
C19
D19
W29
W28
DDR_B_CLK2
AJ19
DDR_B_CLK#2
AK19
DDR_B_CLK1
A18
DDR_B_CLK#1
A19
U31
U30
DDR_B_ODT1
AD31
DDR_B_ODT0
AD29
DDR_A_ODT1
AC27
DDR_A_ODT0
AC28
DDR_B_MA15
N28
DDR_B_MA14
N29
DDR_B_MA13
AE31
DDR_B_MA12
N30
DDR_B_MA11
P29
DDR_B_MA10
AA29
DDR_B_MA9
P31
DDR_B_MA8
R29
DDR_B_MA7
R28
DDR_B_MA6
R31
DDR_B_MA5
R30
DDR_B_MA4
T31
DDR_B_MA3
T29
DDR_B_MA2
U29
DDR_B_MA1
U28
DDR_B_MA0
AA30
DDR_B_BS#2
N31
DDR_B_BS#1
AA31
DDR_B_BS#0
AA28
DDR_B_RAS#
AB29
DDR_B_CAS#
AC29
DDR_B_WE#
AC30
1
C35
C35
1.5P_0402_50V8C
1.5P_0402_50V8C
2
1
C173
C173
1.5P_0402_50V8C
1.5P_0402_50V8C
2
DDR_A_CLK2 10
DDR_A_CLK#2 10
DDR_A_CLK1 10
DDR_A_CLK#1 10
DDR_B_CLK2 11
DDR_B_CLK#2 11
DDR_B_CLK1 11
DDR_B_CLK#1 11
DDR_B_ODT1 11
DDR_B_ODT0 11
DDR_A_ODT1 10
DDR_A_ODT0 10
DDR_B_MA[15..0] 11
DDR_B_BS#2 11
DDR_B_BS#1 11
DDR_B_BS#0 11
DDR_B_RAS# 11
DDR_B_CAS# 11
DDR_B_WE# 11
DDR_B_D[63..0]11
To reverse SODIMM socket
DDR_B_DQS711
DDR_B_DQS#711
DDR_B_DQS611
DDR_B_DQS#611
DDR_B_DQS511
DDR_B_DQS#511
DDR_B_DQS411
DDR_B_DQS#411
DDR_B_DQS311
DDR_B_DQS#311
DDR_B_DQS211
DDR_B_DQS#211
DDR_B_DQS111
DDR_B_DQS#111
DDR_B_DQS011
DDR_B_DQS#011
Processor DDR2 Memory Interface
JCPU1C
DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
JCPU1C
AH13
MB_DATA63
AL13
MB_DATA62
AL15
MB_DATA61
AJ15
MB_DATA60
AF13
MB_DATA59
AG13
MB_DATA58
AL14
MB_DATA57
AK15
MB_DATA56
AL16
MB_DATA55
AL17
MB_DATA54
AK21
MB_DATA53
AL21
MB_DATA52
AH15
MB_DATA51
AJ16
MB_DATA50
AH19
MB_DATA49
AL20
MB_DATA48
AJ22
MB_DATA47
AL22
MB_DATA46
AL24
MB_DATA45
AK25
MB_DATA44
AJ21
MB_DATA43
AH21
MB_DATA42
AH23
MB_DATA41
AJ24
MB_DATA40
AL27
MB_DATA39
AK27
MB_DATA38
AH31
MB_DATA37
AG30
MB_DATA36
AL25
MB_DATA35
AL26
MB_DATA34
AJ30
MB_DATA33
AJ31
MB_DATA32
E31
MB_DATA31
E30
MB_DATA30
B27
MB_DATA29
A27
MB_DATA28
F29
MB_DATA27
F31
MB_DATA26
A29
MB_DATA25
A28
MB_DATA24
A25
MB_DATA23
A24
MB_DATA22
C22
MB_DATA21
D21
MB_DATA20
A26
MB_DATA19
B25
MB_DATA18
B23
MB_DATA17
A22
MB_DATA16
B21
MB_DATA15
A20
MB_DATA14
C16
MB_DATA13
D15
MB_DATA12
C21
MB_DATA11
A21
MB_DATA10
A17
MB_DATA9
A16
MB_DATA8
B15
MB_DATA7
A14
MB_DATA6
E13
MB_DATA5
F13
MB_DATA4
C15
MB_DATA3
A15
MB_DATA2
A13
MB_DATA1
D13
MB_DATA0
K29
MB_CHECK7
K31
MB_CHECK6
G30
MB_CHECK5
G29
MB_CHECK4
L29
MB_CHECK3
L28
MB_CHECK2
H31
MB_CHECK1
G31
MB_CHECK0
J29
MB_DM8
AJ14
MB_DM7
AH17
MB_DM6
AJ23
MB_DM5
AK29
MB_DM4
C30
MB_DM3
A23
MB_DM2
B17
MB_DM1
B13
MB_DM0
J31
MB_DQS_H8
J30
MB_DQS_L8
AK13
MB_DQS_H7
AJ13
MB_DQS_L7
AK17
MB_DQS_H6
AJ17
MB_DQS_L6
AK23
MB_DQS_H5
AL23
MB_DQS_L5
AL28
MB_DQS_H4
AL29
MB_DQS_L4
D31
MB_DQS_H3
C31
MB_DQS_L3
C24
MB_DQS_H2
C23
MB_DQS_L2
D17
MB_DQS_H1
C17
MB_DQS_L1
C14
MB_DQS_H0
C13
MB_DQS_L0
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
DDRII: DATA
DDRII: DATA
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MA_DQS_H8
MA_DQS_H7
MA_DQS_H6
MA_DQS_H5
MA_DQS_H4
MA_DQS_H3
MA_DQS_H2
MA_DQS_H1
MA_DQS_H0
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_L8
MA_DQS_L7
MA_DQS_L6
MA_DQS_L5
MA_DQS_L4
MA_DQS_L3
MA_DQS_L2
MA_DQS_L1
MA_DQS_L0
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
K25
J26
G28
G27
L24
K27
H29
H27
J25
AF15
AF19
AJ25
AH29
B29
E24
E18
H15
J28
J27
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
F19
F15
G15
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D[63..0] 10
DDR_A_DM[7..0] 10DDR_B_DM[7..0]11
DDR_A_DQS7 10
DDR_A_DQS#7 10
DDR_A_DQS6 10
DDR_A_DQS#6 10
DDR_A_DQS5 10
DDR_A_DQS#5 10
DDR_A_DQS4 10
DDR_A_DQS#4 10
DDR_A_DQS3 10
DDR_A_DQS#3 10
DDR_A_DQS2 10
DDR_A_DQS#2 10
DDR_A_DQS1 10
DDR_A_DQS#1 10
DDR_A_DQS0 10
DDR_A_DQS#0 10
To normal SODIMM socket
AF1
A1
Athlon 64 S1g1
uPGA638
Top View
A26
VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/10/11 2006/10/11
2005/10/11 2006/10/11
2005/10/11 2006/10/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Title
Title
Title
AMD CPU DDRII MEMORY I/F
AMD CPU DDRII MEMORY I/F
AMD CPU DDRII MEMORY I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
Date: Sheet
E
of
of
of
750Friday, August 08, 2008
750Friday, August 08, 2008
750Friday, August 08, 2008
2.0
2.0
2.0
5
+2.5VS
FCM2012C-800_0.25ohm/600mA_0805
FCM2012C-800_0.25ohm/600mA_0805
1
+
+
150U_D2_6.3VM
150U_D2_6.3VM
2
@
D D
CPU_PWRGD18
680_0402_5%
680_0402_5%
LDT_STOP#14,18
C C
680_0402_5%
680_0402_5%
SB_PWROK18,28,37
LDT_RST#18
680_0402_5%
680_0402_5%
@
Un-stuff
R63
R63
300_0402_5% @
300_0402_5% @
12
R688
R688
R88
R88
300_0402_5% @
300_0402_5% @
12
R689
R689
R71
R71
300_0402_5% @
300_0402_5% @
@
@
1 2
R82 0_0402_5%
R82 0_0402_5%
12
R690
R690
1 2
C506
C506
+1.8VS
12
+1.8VS
12
+1.8VS
12
SB_PWROK_R
LDT_RST#
+1.8V
L4
L4
1
C189
C189
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.8V+3VS
12
R64
R64
4.7K_0402_5%@
4.7K_0402_5%@
R543 0_0402_5%R543 0_0402_5%
R544 0_0402_5%R544 0_0402_5%
R545 0_0402_5%R545 0_0402_5%
2
B
1
A
1 2
2
B
1
A
1 2
2
B
1
A
1 2
+1.8V
+1.8V
5
U5
P
Y
G
NC7SZ08P5X_NL_SC70-5@U5NC7SZ08P5X_NL_SC70-5@
3
5
U8
P
Y
G
NC7SZ08P5X_NL_SC70-5@U8NC7SZ08P5X_NL_SC70-5@
3
5
U6
P
Y
G
NC7SZ08P5X_NL_SC70-5@U6NC7SZ08P5X_NL_SC70-5@
3
C147 0.1U_0402_16V4Z
C147 0.1U_0402_16V4Z
1 2
@
@
R70
R70
4
C155 0.1U_0402_16V4Z
C155 0.1U_0402_16V4Z
1 2
@
@
R79
R79
4
C282 0.1U_0402_16V4Z
C282 0.1U_0402_16V4Z
1 2
@
@
R65
R65
4
1
C187
C187
2
0.22U_0603_16V7K
0.22U_0603_16V7K
@
@
1 2
@
@
1 2
@
@
1 2
HDT Connector
12
12
12
12
B B
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
2200P_0402_50V7K
A A
2200P_0402_50V7K
EC_SMB_CK228
EC_SMB_DA228
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
C451
C451
5
HDT@
HDT@
R361 220_0402_5%
R361 220_0402_5%
1
2
EC_SMB_CK2
EC_SMB_DA2
12
+1.8V
HDT@
HDT@
HDT@
HDT@
HDT@
HDT@
HDT@
HDT@
R364 220_0402_5%
R364 220_0402_5%
R362 220_0402_5%
R362 220_0402_5%
R363 220_0402_5%
R363 220_0402_5%
R365 220_0402_5%
R365 220_0402_5%
U38
CPU_THERMDA
CPU_THERMDC
U38
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARMZ-2REEL_MSOP8
ADM1032ARMZ-2REEL_MSOP8
U4524 CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE
CLOSE TO PROCESSOR WITHIN 1" INCH
JP4
JP4
1
3
5
7
9
11
13
15
17
19
21
SAMTEC_ASP-68200-07
SAMTEC_ASP-68200-07
CONN@
CONN@
+3VS
1
C454
C454
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
VDD1
ALERT#
THERM#
GND
2
4
6
8
10
12
14
16
18
20
22
2423
26
1
6
4
5
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
4
1
C136
C136
3300P_0402_50V7K
3300P_0402_50V7K
2
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
12
R374
R374
10K_0402_5%@
10K_0402_5%@
4
W=50mils
3V_LDT_RST#
R572
R572
220_0402_5%
220_0402_5%
HDT@
HDT@
R372 300_0402_5%R372 300_0402_5%
+1.8VS
CPU_SIC18
CPU_SID18
+1.2V_HT
place them to CPU within 1"
+3VALW+3VS
12
2
G
G
1 3
D
D
Q33
Q33
2N7002_SOT23HDT@
2N7002_SOT23HDT@
1 2
R582 300_0402_5%@R582 300_0402_5%@
1 2
R583 300_0402_5%
R583 300_0402_5%
1 2
@
R584 0_0402_5%@R584 0_0402_5%@
R585 0_0402_5%
R585 0_0402_5%
S
S
@
1 2
1 2
@
@
R36 44.2_0603_1%R36 44.2_0603_1%
1 2
R35 44.2_0603_1%R35 44.2_0603_1%
1 2
CPUCLK17
CPUCLK#17
CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST21_SCANEN
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST24_SCANCLK1
CPU_TEST20_SCANCLK2
R683 0_0402_5%
R683 0_0402_5%
1 2
3
LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
12/22 Modify
CPU_SIC_R
CPU_SID_R
CPU_HTREF1
CPU_HTREF0
5:10
CPU_VCC_SENSE48
CPU_VSS_SENSE48
C501
C501
1 2
3900P_0402_50V7K
3900P_0402_50V7K
C502
C502
1 2
3900P_0402_50V7K
3900P_0402_50V7K
169_0402_1%
169_0402_1%
R389
R389
12
SCAN Connector
+1.8V
JP38
JP38
1
3
5
7
9
11
13
15
17
19
21
23
25
ASP-68200-03
ASP-68200-03
CONN@
CONN@
CPU_HT_RESET#CPU_HT_RESET#_R
@
@
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST12_SCANSHIFTENB
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
3
R366 300_0402_5%R366 300_0402_5%
R369 1K_0402_5%R369 1K_0402_5%
R47 510_0402_5%R47 510_0402_5%
R684 300_0402_5% @R684 300_0402_5% @
R685 300_0402_5% @R685 300_0402_5% @
R686 300_0402_5% @R686 300_0402_5% @
R687 300_0402_5% @R687 300_0402_5% @
R368 300_0402_5%R368 300_0402_5%
R54 510_0402_5%R54 510_0402_5%
R92 300_0402_5%R92 300_0402_5%
R91 300_0402_5%R91 300_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
TP2PAD TP2PAD
TP1PAD TP1PAD
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST12_SCANSHIFTENB
CPU_THERMDC
CPU_THERMDA
10:10
2
4
6
8
10
12
14
16
18
20
22
24
KEY
KEY
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
ATHLON Control and Debug
JCPU1D
VDDA=300mA
CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_VCC_SENSE
CPU_VSS_SENSE
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
TP5PAD TP5PAD
TP6PAD TP6PAD
TP8PAD TP8PAD
TP9PAD TP9PAD
+1.8V
Compal Secret Data
Compal Secret Data
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
JCPU1D
C10
VDDA2
D10
C7
C9
D8
AL6
AK6
V8
V7
G2
G1
AK11
AL11
A8
B8
B6
AL9
AH10
AJ10
AL10
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AG9
AG8
AH7
AJ6
L25
L26
L31
L30
W26
W25
AE27
U24
V24
AE28
AD25
AE24
AE25
AJ18
AJ20
C18
C20
G24
G25
H25
V29
W30
Deciphered Date
Deciphered Date
Deciphered Date
THERMTRIP_L
VDDA1
PROCHOT_L
RESET_L
PWROK
LDTSTOP_L
SIC
SID
HT_REF1
HT_REF0
VDD_FB_H
VDD_FB_L
VDDIO_FB_H
VDDIO_FB_L
CLKIN_H
CLKIN_L
DBRDY
TMS
TCK
TRST_L
TDI
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
AMD AM2 Processor Socket
2
VID5
VID4
VID3
VID2
VID1
VID0
CPU_PRESENT_L
PSI_L
NC#1
NC#2
NC#3
NC#4
DBREQ_L
TDO
TEST29_H
TEST29_L
NC#5
NC#6
NC#7
NC#8
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
MISC
MISC
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
+1.8V
12
R5
R5
300_0402_5%
300_0402_5%
H_THERMTRIP_S# H_THERMTRIP#
CPU_PROCHOT#_1.8
AK7
AL7
D2
D1
C1
E3
E2
E1
AL3
F1
H3
H4
H20
H21
A5
AK10
C11
D11
AE7
AD19
AE8
AD18
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
E20
B19
AL4
AK4
AK3
F2
F3
G4
G3
G5
Y31
Y30
AG31
V31
W31
AF31
Q3
Q3
MMBT3904_SOT23
MMBT3904_SOT23
R7
R7
300_0402_5%
H_THERMTRIP_S#
CPU_PROCHOT#_1.8
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
TP7 PADTP7 PAD
3 1
300_0402_5%
VID5
VID4
VID3
VID2
VID1
VID0
CPU_PRESENT#
PSI#
CPU_DBREQ#
CPU_TDO
5:4:5
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST26_BURNIN#
+1.8V
12
R4
R4
1K_0402_5%
1K_0402_5%
2
+1.8V
12
R8
R8
10K_0402_5%
10K_0402_5%
CPU_PH_G
B
B
2
Q4
Q4
E
E
3 1
C
C
MMBT3904_SOT23
MMBT3904_SOT23
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
+1.8V
12
12
R78
R78
300_0402_5%
300_0402_5%
PSI# 48
R68
R68
1 2
80.6_0402_1%
80.6_0402_1%
+3VALW
12
R3
R3
10K_0402_5%
10K_0402_5%
AMD CPU CTRL & DEBUG
AMD CPU CTRL & DEBUG
AMD CPU CTRL & DEBUG
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
+3VALW
12
R2
1K_0402_5%@R21K_0402_5%@
2
Q2
3 1
H_THERMTRIP# 18
+3VS
12
R6
R6
4.7K_0402_5%
4.7K_0402_5%
@
@
EC_THERM# 19,28
1
VID5 48
VID4 48
VID3 48
VID2 48
VID1 48
VID0 48
MMBT3904_SOT23@Q2MMBT3904_SOT23@
1
MAINPWON 42,43,45
of
of
of
850Friday, August 08, 2008
850Friday, August 08, 2008
850Friday, August 08, 2008
2.0
2.0
2.0
5
+CPU_CORE
D D
C C
B B
A A
JCPU1E
JCPU1E
A4
VDD1
A6
VDD2
AA8
VDD3
AA10
VDD4
AA12
VDD5
AA14
VDD6
AA16
VDD7
AA18
VDD8
AB7
VDD9
AB9
VDD10
AB11
VDD11
AC4
VDD12
AC5
VDD13
AC8
VDD14
AC10
VDD15
AD2
VDD16
AD3
VDD17
AD7
VDD18
AD9
VDD19
AE10
VDD20
AF7
VDD21
AF9
VDD22
AG4
VDD23
AG5
VDD24
AG7
VDD25
AH2
VDD26
AH3
VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41
E10
VDD42
F5
VDD43
F7
VDD44
F9
VDD45
F11
VDD46
G6
VDD47
G8
VDD48
G10
VDD49
G12
VDD50
H7
VDD51
H11
VDD52
H23
VDD53
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
JCPU1G
JCPU1G
A3
VSS1
A7
VSS2
A9
VSS3
A11
VSS4
AA4
VSS5
AA5
VSS6
AA7
VSS7
AA9
VSS8
AA11
VSS9
AA13
VSS10
AA15
VSS11
AA17
VSS12
AA19
VSS13
AA21
VSS14
AA23
VSS15
AB2
VSS16
AB3
VSS17
AB8
VSS18
AB10
VSS19
AB12
VSS20
AB14
VSS21
AB16
VSS22
AB18
VSS23
AB20
VSS24
AB22
VSS25
AC7
VSS26
AC9
VSS27
AC11
VSS28
AC13
VSS29
AC15
VSS30
AC17
VSS31
AC19
VSS32
AC21
VSS33
AC23
VSS34
AD8
VSS35
AD10
VSS36
AD12
VSS37
AD14
VSS38
AD16
VSS39
AD20
VSS40
AD22
VSS41
AD24
VSS42
AE4
VSS43
AE5
VSS44
AE9
VSS45
AE11
VSS46
AF2
VSS47
AF3
VSS48
AF8
VSS49
AF10
VSS50
AF12
VSS51
AF14
VSS52
AF16
VSS53
AF18
VSS54
AF20
VSS55
AF22
VSS56
AF24
VSS57
AF26
VSS58
AF28
VSS59
AG10
VSS61
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
5
GND1
GND1
POWER1
POWER1
VDD106
VDD105
VDD104
VDD103
VDD102
VDD101
VDD100
VDD99
VDD98
VDD97
VDD96
VDD95
VDD94
VDD93
VDD92
VDD91
VDD90
VDD89
VDD88
VDD87
VDD86
VDD85
VDD84
VDD83
VDD82
VDD81
VDD80
VDD79
VDD78
VDD77
VDD76
VDD75
VDD74
VDD73
VDD72
VDD71
VDD70
VDD69
VDD68
VDD67
VDD66
VDD65
VDD64
VDD63
VDD62
VDD61
VDD60
VDD59
VDD58
VDD57
VDD56
VDD55
VDD54
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
R10
R8
R5
R4
P19
P17
P15
P13
P11
P9
P7
N18
N16
N14
N12
N10
N8
M19
M17
M15
M13
M11
M9
M7
M3
M2
L18
L16
L14
Y19
Y17
L12
L10
L8
L5
L4
K23
K21
K19
K17
K15
K13
K11
K9
K7
J24
J22
J20
J18
J16
J14
J12
J8
H10
H8
G11
G9
F30
F28
F26
F24
F22
F20
F18
F16
F14
F4
E11
D30
D28
D26
D24
D22
D20
D18
D16
D14
C3
B30
B28
B26
B24
B22
B20
B18
B16
B14
B11
B9
B4
AL5
AK30
AK28
AK26
AK24
AK22
AK20
Y16
Y14
AK18
AK16
AK14
AK2
AH30
AH28
AH26
AH24
AH22
AH20
AH18
AH16
AH14
AG11
AM2 Processor
Socket
AM2 Processor Socket
4
+CPU_CORE
4
JCPU1F
JCPU1F
R12
VDD107
R14
VDD108
R16
VDD109
R18
VDD110
R20
VDD111
T2
VDD112
T3
VDD113
T7
VDD114
T9
VDD115
T11
VDD116
T13
VDD117
T15
VDD118
T17
VDD119
T19
VDD120
T21
VDD121
U8
VDD122
U10
VDD123
U12
VDD124
U14
VDD125
U16
VDD126
U18
VDD127
U20
VDD128
V9
VDD129
V11
VDD130
V13
VDD131
V15
VDD132
V17
VDD133
V19
VDD134
V21
VDD135
W4
VDD136
W5
VDD137
W8
VDD138
W10
VDD139
W12
VDD140
W14
VDD141
W16
VDD142
W18
VDD143
W20
VDD144
Y2
VDD145
Y3
VDD146
Y7
VDD147
Y9
VDD148
Y11
VDD149
Y13
VDD150
Y15
VDD151
Y21
VDD152
AA20
VDD153
AA22
VDD154
AB13
VDD155
AB15
VDD156
AB17
VDD157
AB19
VDD158
AB21
VDD159
AB23
VDD160
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
JCPU1H
JCPU1H
T22
VSS183
T20
VSS182
T18
VSS181
T16
VSS180
T14
VSS179
T12
VSS178
T10
VSS177
T8
VSS176
R23
VSS175
R21
VSS174
R19
VSS173
R17
VSS172
R15
VSS171
R13
VSS170
R11
VSS169
R9
VSS168
R7
VSS167
P22
VSS166
P20
VSS165
P18
VSS164
P16
VSS163
P14
VSS162
P12
VSS161
P10
VSS160
P8
VSS159
P3
VSS158
P2
VSS157
N23
VSS156
N21
VSS155
N19
VSS154
N17
VSS153
Y18
VSS152
K22
VSS151
K20
VSS150
K18
VSS149
K16
VSS148
K14
VSS147
K12
VSS146
K10
VSS145
K8
VSS144
K3
VSS143
K2
VSS142
J23
VSS141
J21
VSS140
J19
VSS139
J17
VSS138
J15
VSS137
J13
VSS136
J11
VSS135
J9
VSS134
J7
VSS133
J5
VSS132
J4
VSS131
H30
VSS130
H28
VSS129
H26
VSS128
H24
VSS127
H22
VSS126
H18
VSS125
H16
VSS124
H14
VSS123
H12
VSS122
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P
CONN@
CONN@
GND2
GND2
3
+1.8V+CPU_CORE
Y29
VDDIO28
Y28
VDDIO27
Y26
VDDIO26
Y24
VDDIO25
V30
VDDIO24
V28
VDDIO23
V26
VDDIO22
V25
VDDIO21
T30
VDDIO20
T28
VDDIO19
T26
VDDIO18
T24
VDDIO17
P30
VDDIO16
P28
VDDIO15
P26
VDDIO14
P24
VDDIO13
M30
VDDIO12
M28
VDDIO11
M26
VDDIO10
M24
VDDIO9
AF30
VDDIO
AD30
VDDIO8
AD28
VDDIO7
AD26
VDDIO6
AC24
POWER2
POWER2
VDDIO5
AB30
VDDIO4
AB28
VDDIO3
AB26
VDDIO2
VDDIO1
VDD184
VDD183
VDD182
VDD181
VDD180
VDD179
VDD178
VDD177
VDD176
VDD175
VDD174
VDD173
VDD172
VDD171
VDD170
VDD169
VDD168
VDD167
VDD166
VDD165
VDD164
VDD163
VDD162
VDD161
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
AB24
Y23
W22
V23
U22
T23
R22
P23
P21
N22
N20
M23
M21
L22
L20
AF11
AE12
AD23
AD11
AC22
AC20
AC18
AC16
AC14
AC12
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
+CPU_CORE
+CPU_CORE
1
C70
C70
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
+1.8V
KAW60
1
C82
C82
22U_0805_6.3V6M
22U_0805_6.3V6M
2
A1
PVT
1
C120
C120
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
1
C102
C102
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Athlon 64 S1g1
uPGA638
Top View
AF1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+CPU_CORE
1
+
+
C505
C505
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
+CPU_CORE
10U_0805_10V6M
10U_0805_10V6M
1
C17
C17
@
@
2
10U_0805_10V6M
10U_0805_10V6M
1
2
1
C195
C195
2
10U_0805_10V6M
10U_0805_10V6M
@
@
CPU SOCKET AM2 DECOUPLING
+CPU_CORE
1
C73
C73
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C100
C100
180P_0402_50V8J
180P_0402_50V8J
2
1
C72
C72
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
+1.8V
+0.9V
1
2
1
2
1
C472
C472
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C127
C127
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
1
C188
C188
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C39
C39
1000P_0402_50V7K
1000P_0402_50V7K
2
1
C76
C76
22U_0805_6.3V6M
22U_0805_6.3V6M
2
C91
C91
0.01U_0402_16V7K
0.01U_0402_16V7K
C116
C116
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
C471
C471
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C128
C128
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
C30
C30
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C41
C41
1000P_0402_50V7K
1000P_0402_50V7K
2
A26
PROCESSOR POWER AND GROUND
Compal Secret Data
Compal Secret Data
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
1
+
+
C504
C504
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
10U_0805_10V6M
10U_0805_10V6M
1
C194
C194
C193
C193
@
@
2
1
C86
10U_0805_10V6M
10U_0805_10V6M
2
1
C738
C738
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Deciphered Date
Deciphered Date
Deciphered Date
2
1
C192
C192
@
@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
@C86
@
1
C479
C479
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C85
C85
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
C36
C36
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C178
C178
1000P_0402_50V7K
1000P_0402_50V7K
2
2
CPU_CORE 820u 330u 22u 10u .22u .01u 180p
HCW51
Moray
KAW60 3 15 3 1 1
1
+
+
C453
C453
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
1
+
2
560u
2 2412211
2
C452
@+C452
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1
15 4 1
KAW60
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C97
C97
2
10U_0805_10V6M
10U_0805_10V6M
1
C118
C118
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C16
C16
2
+CPU_CORE
1
+
@
@
1
C109
C109
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+
C450
C450
560U_25V_M_R10
560U_25V_M_R10
2
SMD POLY CAP
SF000001K00 S_A-P_CAP 560U 2.5V M 6.3X5.7 LESR10M H5.7
SF000001J00 S_A-P_CAP 560U 2.5V M 6.3X5.7 LESR13M H5.7
1
C96
@C96
@
10U_0805_10V6M
10U_0805_10V6M
2
1
+
+
C449
C449
560U_25V_M_R10
560U_25V_M_R10
2
1
C89
C89
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C113
C113
22U_0805_6.3V6M
22U_0805_6.3V6M
2
KAW60
1
C739
C739
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C740
C740
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C741
C741
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C742
C742
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C743
C743
22U_0805_6.3V6M
22U_0805_6.3V6M
2
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
1
C480
C480
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
2
1
C181
C181
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C22
C22
1000P_0402_50V7K
1000P_0402_50V7K
2
22u310u
+1.8V .01u 180p
HCW51
Moray
KAW60 2 6423
1
2
C68
C68
180P_0402_50V8J
180P_0402_50V8J
1
2
2
C104
C104
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C184
C184
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
C84
C84
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
1
C105
C105
180P_0402_50V8J
180P_0402_50V8J
2
1
2
1
2
1
C185
C185
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
1
C179
C179
180P_0402_50V8J
180P_0402_50V8J
2
+0.9V 1000p 180p
HCW51
Moray 4
KAW60 4 4 4 4
Title
Title
Title
AMD CPU PWR & GND
AMD CPU PWR & GND
AMD CPU PWR & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
Date: Sheet
.22u
4.7u
6
C129
C129
0.22U_0402_10V4Z
0.22U_0402_10V4Z
C27
C27
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
C175
C175
180P_0402_50V8J
180P_0402_50V8J
2
.22u
.0047u
4
1
2 2
1
2
42
2 5 1
1
2
C745
C745
180P_0402_50V8J
180P_0402_50V8J
1
2
C26
C26
180P_0402_50V8J
180P_0402_50V8J
4.7u
4
2 4 4
1
C124
C124
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C744
C744
0.22U_0402_10V4Z
0.22U_0402_10V4Z
2
.0047u
C23
C23
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
C182
C182
180P_0402_50V8J
180P_0402_50V8J
2
4 4
4
of
of
of
950Tuesday, July 29, 2008
950Tuesday, July 29, 2008
950Tuesday, July 29, 2008
2
2.0
2.0
2.0
5
4
3
2
1
+1.8V+DIMM_VREF+1.8V+1.8V
0.1U_0402_16V4Z
JDIMM2
JDIMM2
1
VREF
3
DDR_A_D0
D D
C C
DDR_CKE0_DIMMA7
DDR_CS2_DIMMA#7
DDR_A_BS#27
DDR_A_BS#07
DDR_A_WE#7
DDR_A_CAS#7
DDR_CS1_DIMMA#7
DDR_A_ODT17
B B
A A
SB_CK_SDAT11,17,19,31
SB_CK_SCLK11,17,19,31
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18 DDR_A_D22
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43 DDR_A_D47
DDR_A_D48
DDR_A_D49 DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51 DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C448
C448
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692C-A0G16
P-TWO_A5692C-A0G16
CONN@
CONN@
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D52
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_DM6
DDR_A_D54
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R12 10K_0402_5%R12 10K_0402_5%
1 2
R10 10K_0402_5%R10 10K_0402_5%
1 2
DDR_A_CLK1 7
DDR_A_CLK#1 7
DDR_CKE1_DIMMA 7
DDR_A_BS#1 7
DDR_A_RAS# 7
DDR_CS0_DIMMA# 7
DDR_A_ODT0 7
DDR_CS3_DIMMA# 7
DDR_A_CLK2 7
DDR_A_CLK#2 7
0.1U_0402_16V4Z
C507
C507
4.7U_0805_10V4Z
4.7U_0805_10V4Z
DDR_A_D[0..63]7
DDR_A_DM[0..7]7
DDR_A_DQS[0..7]7
DDR_A_MA[0..15]7
DDR_A_DQS#[0..7]7
1
1
2
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C503
C503
3
12
R398
R398
1K_0402_1%
1K_0402_1%
12
R397
R397
1K_0402_1%
1K_0402_1%
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
2005/10/11 2006/10/11
2005/10/11 2006/10/11
2005/10/11 2006/10/11
+1.8V
1
2
C639
C639
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C63
C63
C67
C67
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_CS3_DIMMA#
+0.9V
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C644
1
2
C643
C643
0.01U_0402_16V7K
0.01U_0402_16V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C114
C114
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C618
C618
C644
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C98
C98
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C107
C107
C95
C95
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C619
C619
C646
C646
10P_0402_25V8K
10P_0402_25V8K
1
1
2
2
C645
C645
10P_0402_25V8K
10P_0402_25V8K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C475
C475
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C69
C69
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C55
C55
C56
C56
C642
C640
C640
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
2
C470
C470
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C642
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
1
2
2
C641
C641
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
C62
C62
C77
C77
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C80
C80
C71
C71
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
RP28 47_0404_4P2R_5%RP28 47_0404_4P2R_5%
RP25 47_0404_4P2R_5%RP25 47_0404_4P2R_5%
RP21 47_0404_4P2R_5%RP21 47_0404_4P2R_5%
RP18 47_0404_4P2R_5%RP18 47_0404_4P2R_5%
RP13 47_0404_4P2R_5%RP13 47_0404_4P2R_5%
RP9 47_0404_4P2R_5%RP9 47_0404_4P2R_5%
RP5 47_0404_4P2R_5%RP5 47_0404_4P2R_5%
R32 47_0402_1%R32 47_0402_1%
1 2
R28 47_0402_1%R28 47_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C616
C616
C617
C617
Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V
2
C648
C648
0.22U_0603_16V7K
0.22U_0603_16V7K
1
1
2
2
C647
C647
0.22U_0603_16V7K
0.22U_0603_16V7K
+1.8V
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
1
C473
C473
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C74
C74
1 4
2 3
RP22 47_0404_4P2R_5%RP22 47_0404_4P2R_5%
1 4
2 3
RP17 47_0404_4P2R_5%RP17 47_0404_4P2R_5%
1 4
2 3
RP14 47_0404_4P2R_5%RP14 47_0404_4P2R_5%
1 4
2 3
RP10 47_0404_4P2R_5%RP10 47_0404_4P2R_5%
1 4
2 3
RP6 47_0404_4P2R_5%RP6 47_0404_4P2R_5%
1 4
2 3
RP2 47_0404_4P2R_5%RP2 47_0404_4P2R_5%
1 4
2 3
RP1 47_0404_4P2R_5%RP1 47_0404_4P2R_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C620
C620
Title
Title
Title
DDR2 SO-DIMM I
DDR2 SO-DIMM I
DDR2 SO-DIMM I
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
1
2
C649
C649
0.22U_0603_16V7K
0.22U_0603_16V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C57
C57
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C88
C88
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C621
C621
C650
C650
0.22U_0603_16V7K
0.22U_0603_16V7K
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C463
C463
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C45
C45
C65
C65
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C622
C622
1
1
2
2
C651
C651
0.22U_0603_16V7K
0.22U_0603_16V7K
1
1
+
+
C477
C477
220U_D2_4VM_R15
220U_D2_4VM_R15
C58
C58
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C101
C101
DDR_A_MA15
DDR_A_MA7
DDR_A_MA14
DDR_A_MA6
DDR_A_MA11
DDR_A_MA2
DDR_A_MA4
DDR_A_BS#1
DDR_A_MA0
DDR_A_RAS#
DDR_A_MA13DDR_A_ODT1
DDR_A_ODT0
1
2
C623
C623
1
C652
C652
0.22U_0603_16V7K
0.22U_0603_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C636
C636
1
+
+
150U_D2_6.3VM
150U_D2_6.3VM
2
2
C51
C51
+1.8V
of
of
of
10 50Friday, August 08, 2008
10 50Friday, August 08, 2008
10 50Friday, August 08, 2008
2.0
2.0
2.0
5
4
3
2
1
1
C52
C52
2
0.1U_0402_16V4ZC70.1U_0402_16V4Z
1
2
C7
DDR_B_D[0..63]7
DDR_B_DM[0..7]7
DDR_B_DQS[0..7]7
DDR_B_MA[0..15]7
DDR_B_DQS#[0..7]7
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C99
C99
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C10
C10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Deciphered Date
Deciphered Date
Deciphered Date
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C103
C103
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C18
C18
C13
C13
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
1 4
2 3
RP27 47_0404_4P2R_5%RP27 47_0404_4P2R_5%
1 4
2 3
RP24 47_0404_4P2R_5%RP24 47_0404_4P2R_5%
1 4
2 3
RP19 47_0404_4P2R_5%RP19 47_0404_4P2R_5%
1 4
2 3
RP15 47_0404_4P2R_5%RP15 47_0404_4P2R_5%
1 4
2 3
RP11 47_0404_4P2R_5%RP11 47_0404_4P2R_5%
1 4
2 3
RP8 47_0404_4P2R_5%RP8 47_0404_4P2R_5%
1 4
2 3
RP7 47_0404_4P2R_5%RP7 47_0404_4P2R_5%
R29 47_0402_1%R29 47_0402_1%
1 2
R30 47_0402_1%R30 47_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C624
C624
C625
C625
Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V
2
+DIMM_VREF+1.8V+1.8V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C202
4.7U_0805_10V4Z
C202
JDIMM1
JDIMM1
1
VREF
3
DDR_B_D0
D D
C C
DDR_CKE0_DIMMB7
DDR_CS2_DIMMB#7
DDR_B_BS#27
DDR_B_BS#07
DDR_B_WE#7
DDR_B_CAS#7
DDR_CS1_DIMMB#7
DDR_B_ODT17
B B
A A
SB_CK_SDAT10,17,19,31
SB_CK_SCLK10,17,19,31
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51 DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C21
C21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
P-TWO_A5652C-A0G16
CONN@
CONN@
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D52
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_DM6
DDR_B_D54
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R11 10K_0402_5%R11 10K_0402_5%
1 2
R9 10K_0402_5%R9 10K_0402_5%
1 2
4.7U_0805_10V4Z
1
2
DDR_B_CLK1 7
DDR_B_CLK#1 7
DDR_CKE1_DIMMB 7
DDR_B_BS#1 7
DDR_B_RAS# 7
DDR_CS0_DIMMB# 7
DDR_B_ODT0 7
DDR_CS3_DIMMB# 7
DDR_B_CLK2 7
DDR_B_CLK#2 7
+3VS
C198
C198
1
2
<BOM Structure>
<BOM Structure>
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+0.9V
0.1U_0402_16V4ZC40.1U_0402_16V4Z
1
2
C4
DDR_CS2_DIMMB#
DDR_CKE0_DIMMB
DDR_B_MA12
DDR_B_BS#2
DDR_B_MA8
DDR_B_MA9
DDR_B_MA3
DDR_B_MA5
DDR_B_MA10
DDR_B_MA1
DDR_B_WE#
DDR_B_BS#0
DDR_CS0_DIMMB#
DDR_B_RAS#
DDR_B_ODT1
DDR_CS3_DIMMB#
+0.9V
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/11 2006/10/11
2005/10/11 2006/10/11
2005/10/11 2006/10/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
2
1
2
C626
C626
C59
C59
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C64
C64
2
0.1U_0402_16V4ZC80.1U_0402_16V4Z
1
2
C627
C627
+1.8V
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C53
C53
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C11
C11
C8
+0.9V
0.1U_0402_16V4ZC50.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C12
C12
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
C81
C81
C78
C78
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C19
C19
C14
C14
1 4
2 3
RP26 47_0404_4P2R_5%RP26 47_0404_4P2R_5%
1 4
2 3
RP23 47_0404_4P2R_5%RP23 47_0404_4P2R_5%
1 4
2 3
RP20 47_0404_4P2R_5%RP20 47_0404_4P2R_5%
1 4
2 3
RP16 47_0404_4P2R_5%RP16 47_0404_4P2R_5%
1 4
2 3
RP12 47_0404_4P2R_5%RP12 47_0404_4P2R_5%
1 4
2 3
RP3 47_0404_4P2R_5%RP3 47_0404_4P2R_5%
1 4
2 3
RP4 47_0404_4P2R_5%RP4 47_0404_4P2R_5%
0.1U_0402_16V4ZC60.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
C5
1
2
2
C6
C628
C628
Title
Title
Title
DDR2 SO-DIMM II
DDR2 SO-DIMM II
DDR2 SO-DIMM II
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
Date: Sheet
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
1
2
C629
C629
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C61
C61
0.1U_0402_16V4ZC90.1U_0402_16V4Z
1
2
C9
DDR_CKE1_DIMMB
DDR_CS1_DIMMB#
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C630
C630
1
1
+
+
C125
C125
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_CAS#
DDR_B_ODT0
DDR_B_MA13
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C631
C631
C633
C633
220U_D2_4VM_R15
220U_D2_4VM_R15
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C20
C20
C15
C15
+1.8V
1
2.0
2.0
2.0
of
of
of
11 50Friday, August 08, 2008
11 50Friday, August 08, 2008
11 50Friday, August 08, 2008
5
D D
C C
VDDHT_PKG
H_CADOP156
H_CADON156
H_CADOP146
H_CADON146
H_CADOP136
H_CADON136
H_CADOP126
H_CADON126
H_CADOP116
H_CADON116
H_CADOP106
H_CADON106
H_CADOP96
H_CADON96
H_CADOP86
H_CADON86
H_CADOP76
H_CADON76
H_CADOP66
H_CADON66
H_CADOP56
H_CADON56
H_CADOP46
H_CADON46
H_CADOP36
H_CADON36
H_CADOP26
H_CADON26
H_CADOP16
H_CADON16
H_CADOP06
H_CADON06
H_CLKOP16
H_CLKON16
H_CLKOP06
H_CLKON06
H_CTLOP06
H_CTLON06
R382 49.9_0402_1%R382 49.9_0402_1%
R380 49.9_0402_1%R380 49.9_0402_1%
1 2
1 2
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0
H_CTLON0
HT_RXCALP
HT_RXCALN
W19
W20
AC21
AB22
AB20
AA20
AA19
AA25
AA24
AB23
AA23
AB24
AB25
AC24
AC25
W21
W22
W25
4
U39A
U39A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N
HT_RXCLK1P
HT_RXCLK1N
Y24
HT_RXCLK0P
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALP
C24
HT_RXCALN
216MQA6AVA11FG_FCBGA465_RS690M
216MQA6AVA11FG_FCBGA465_RS690M
PART 1 OF 5
PART 1 OF 5
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
HYPER TRANSPORT I/F
HYPER TRANSPORT I/F
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
H_CTLIP0
H_CTLIN0
HT_TXCALP
HT_TXCALN
3
R379
R379
1 2
100_0402_1%
100_0402_1%
H_CADIP15 6
H_CADIN15 6
H_CADIP14 6
H_CADIN14 6
H_CADIP13 6
H_CADIN13 6
H_CADIP12 6
H_CADIN12 6
H_CADIP11 6
H_CADIN11 6
H_CADIP10 6
H_CADIN10 6
H_CADIP9 6
H_CADIN9 6
H_CADIP8 6
H_CADIN8 6
H_CADIP7 6
H_CADIN7 6
H_CADIP6 6
H_CADIN6 6
H_CADIP5 6
H_CADIN5 6
H_CADIP4 6
H_CADIN4 6
H_CADIP3 6
H_CADIN3 6
H_CADIP2 6
H_CADIN2 6
H_CADIP1 6
H_CADIN1 6
H_CADIP0 6
H_CADIN0 6
H_CLKIP1 6
H_CLKIN1 6
H_CLKIP0 6
H_CLKIN0 6
H_CTLIP0 6
H_CTLIN0 6
2
1
RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
RS690MC-HT LINK0 I/F
RS690MC-HT LINK0 I/F
RS690MC-HT LINK0 I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
2
Date: Sheet
12 50Friday, August 08, 2008
12 50Friday, August 08, 2008
12 50Friday, August 08, 2008
1
2.0
2.0
2.0
of
of
of
5
D D
WLAN
LAN
C C
PCIE_MRX_PTX_P031
PCIE_MRX_PTX_N031
PCIE_MRX_C_PTX_P126
PCIE_MRX_C_PTX_N126
A_MRX_STX_P218
A_MRX_STX_N218
A_MRX_STX_P318
A_MRX_STX_N318
A_MRX_STX_P018
A_MRX_STX_N018
A_MRX_STX_P118
A_MRX_STX_N118
4
PCIE_MRX_PTX_P0
PCIE_MRX_PTX_N0
PCIE_MRX_C_PTX_P1
PCIE_MRX_C_PTX_N1
A_MRX_STX_P2
A_MRX_STX_N2
A_MRX_STX_P3
A_MRX_STX_N3
A_MRX_STX_P0
A_MRX_STX_N0
A_MRX_STX_P1
A_MRX_STX_N1
U39B
U39B
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
P4
GFX_RX8P
P5
GFX_RX8N
R4
GFX_RX9P
R5
GFX_RX9N
R7
GFX_RX10P
R8
GFX_RX10N
U4
GFX_RX11P
U5
GFX_RX11N
W4
GFX_RX12P
W5
GFX_RX12N
Y4
GFX_RX13P
Y5
GFX_RX13N
V9
GFX_RX14P
W9
GFX_RX14N
AB7
GFX_RX15P
AB6
GFX_RX15N
Y7
GPP_RX2P
AA7
GPP_RX2N
AB9
GPP_RX3P
AA9
GPP_RX3N
W11
GPP_RX0P(SB_RX2P)
W12
GPP_RX0N(SB_RX2N)
AA11
GPP_RX1P(SB_RX3P)
AB11
GPP_RX1N(SB_RX3N)
W14
SB_RX0P
W15
SB_RX0N
AB12
SB_RX1P
AA12
SB_RX1N
AA14
PCE_ISET(NC)
AB14
PCE_TXISET(NC)
216MQA6AVA11FG_FCBGA465_RS690M
216MQA6AVA11FG_FCBGA465_RS690M
PART 2 OF 5
PART 2 OF 5
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
3
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
PCIE GFX I/F
PCIE GFX I/F
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX0P(SB_TX2P)
GPP_TX0N(SB_TX2N)
GPP_TX1P(SB_TX3P)
GPP_TX1N(SB_TX3N)
SB_TX0P
SB_TX0N
SB_TX1P
PCE_PCAL(PCE_CALRP)
PCE_NCAL(PCE_CALRN)
SB_TX1N
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
PCIE_MTX_PRX_P0
AD4
PCIE_MTX_PRX_N0
AE5
PCIE_MTX_PRX_P1
AD5
PCIE_MTX_PRX_N1
AD6
AD8
A_MTX_SRX_N2
AE8
AD7
A_MTX_SRX_N3
AE7
AE9
A_MTX_SRX_N0
AD10
AC8
A_MTX_SRX_N1
AD9
R375 562_0402_1%R375 562_0402_1%
AD11
AE11
1 2
R376 2K_0402_1%R376 2K_0402_1%
1 2
R375:
R376:
C457 0.1U_0402_10V6KC457 0.1U_0402_10V6K
1 2
C458 0.1U_0402_10V6KC458 0.1U_0402_10V6K
1 2
C466 0.1U_0402_10V6KC466 0.1U_0402_10V6K
1 2
C467 0.1U_0402_10V6KC467 0.1U_0402_10V6K
1 2
C659 0.1U_0402_10V6KC659 0.1U_0402_10V6K
1 2
C660 0.1U_0402_10V6KC660 0.1U_0402_10V6K
1 2
C661 0.1U_0402_10V6KC661 0.1U_0402_10V6K
1 2
C662 0.1U_0402_10V6KC662 0.1U_0402_10V6K
1 2
C465 0.1U_0402_10V6KC465 0.1U_0402_10V6K
1 2
C464 0.1U_0402_10V6KC464 0.1U_0402_10V6K
1 2
C468 0.1U_0402_10V6KC468 0.1U_0402_10V6K
1 2
C469 0.1U_0402_10V6KC469 0.1U_0402_10V6K
1 2
150 Ohm FOR RS485
562 Ohm FOR RS690
82.5 Ohm FOR RS485
2KOhm FOR RS690
2
PCIE_MTX_C_PRX_P0
PCIE_MTX_C_PRX_N0
PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1
A_MTX_C_SRX_P2A_MTX_SRX_P2
A_MTX_C_SRX_N2
A_MTX_C_SRX_P3A_MTX_SRX_P3
A_MTX_C_SRX_N3
A_MTX_C_SRX_P0A_MTX_SRX_P0
A_MTX_C_SRX_N0
A_MTX_C_SRX_P1A_MTX_SRX_P1
A_MTX_C_SRX_N1
VDDA12_PKG2
PCIE_MTX_C_PRX_P0 31
PCIE_MTX_C_PRX_N0 31
PCIE_MTX_C_PRX_P1 26
PCIE_MTX_C_PRX_N1 26
A_MTX_C_SRX_P2 18
A_MTX_C_SRX_N2 18
A_MTX_C_SRX_P3 18
A_MTX_C_SRX_N3 18
A_MTX_C_SRX_P0 18
A_MTX_C_SRX_N0 18
A_MTX_C_SRX_P1 18
A_MTX_C_SRX_N1 18
1
WLAN
LAN
RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
RS690MC-PCIE LINK I/F
RS690MC-PCIE LINK I/F
RS690MC-PCIE LINK I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
2
Date: Sheet
13 50Friday, August 08, 2008
13 50Friday, August 08, 2008
13 50Friday, August 08, 2008
1
2.0
2.0
2.0
of
of
of
5
R540 0_0805_5%R540 0_0805_5%
D D
MBK2012121YZF_0.2ohm/800mA_0805
MBK2012121YZF_0.2ohm/800mA_0805
MBK2012121YZF_0.2ohm/800mA_0805
MBK2012121YZF_0.2ohm/800mA_0805
150U_D2_6.3VM
150U_D2_6.3VM
C C
MBK2012121YZF_0.2ohm/800mA_0805
MBK2012121YZF_0.2ohm/800mA_0805
B B
A A
+1.8VS
1
+
+
C183
C183
2
+1.8VS
4.7K_0402_5%
4.7K_0402_5%
NOTE: ACCESS TO STRAP_DATA and I2C_CLK PINS
IS MANDATORY.
AVDDQ
L52
L52
1 2
L53
L53
1 2
L56
L56
1 2
+1.2V_HT +PLLVDD12
MBC1608121YZF_0.4ohm/300mA_0603
MBC1608121YZF_0.4ohm/300mA_0603
R50
R50
@
@
1 2
1
C495
C495
10U_0805_10V4Z
10U_0805_10V4Z
@
@
2
PLLVDD
1
C499
C499
10U_0805_10V4Z
10U_0805_10V4Z
@
@
2
HTPVDD
10U_0805_10V4Z
10U_0805_10V4Z
1
C493
@ C493
@
2
1 2
+3VS
4.7K_0402_5%
4.7K_0402_5%
R51
R51
1 2
U2
U2
1
A0
2
A1
3
A2
4
VSS
AT24C04N-10SI-2.7_SO8
AT24C04N-10SI-2.7_SO8
@
@
5
2.2U_0805_10V6K
2.2U_0805_10V6K
1
C489
C489
2
AVSSQ_GND
1
1
C485
C485
2
2
1U_0603_10V4Z
1U_0603_10V4Z
1
C498
C498
2
1U_0603_10V4Z
1U_0603_10V4Z
L70
L70
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
4.7K_0402_5%
4.7K_0402_5%
R49
R49
1 2
VCC
WP
SCL
SDA
1
C484
C484
1U_0603_10V4Z
1U_0603_10V4Z
2
C492
C492
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C488
C488
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
LDT_STOP#8,18
PLLVDD12=70mA
1
1
C691
C690
C690
EDID_LCD_CLK
EDID_LCD_DAT
8
7
6
5
C691
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
DDC_DATA
+3VS +3VS
12
1
C117
C117
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
@
@
R230-R232 CLOSE TO NB
CRT_R24
CRT_G24
CRT_B24
+1.8VS
R568 10K_0402_5%R568 10K_0402_5%
R40
R40
10K_0402_5%
10K_0402_5%
@
@
EDID_LCD_CLK
150_0402_1%
150_0402_1%
1 2
150U_D2_6.3VM
150U_D2_6.3VM
CRT_R
CRT_G
CRT_B
150_0402_1%
150_0402_1%
12
R75
R75
12
B
B
2
E
E
3 1
C
C
MMBT3904_SOT23
MMBT3904_SOT23
NBSRC_CLKP17
NBSRC_CLKN17
12
R41
R41
10K_0402_5%
10K_0402_5%
STRP_DATA
12
R39
R39
10K_0402_5%
10K_0402_5%
@
@
C186
C186
Q27
Q27
4
12
4
3
+3VS AVDD
L43
L43
1 2
MBK2012121YZF_0.2ohm/800mA_0805
MBK2012121YZF_0.2ohm/800mA_0805
AVSSQ_GND
+1.8VS
1 2
1
+
+
1U_0603_10V4Z
1U_0603_10V4Z
2
150_0402_1%
150_0402_1%
12
R76
R76
R74
R74
+3VS
12
R46
R46
1K_0402_5%
1K_0402_5%
ALLOW_LDTSTOP18
HTREFCLK17
RS690 A11: This clock is needed even if External Graphic slot is not supported
SBLINK_CLKP17
SBLINK_CLKN17
LOAD_ROM#16
1U_0603_10V4Z
1U_0603_10V4Z
L44 MBK2012121YZF_0.2ohm/800mA_0805L44 MBK2012121YZF_0.2ohm/800mA_0805
1
C490
C490
2
AVDDQ
AVSSQ_GND
8mils TRACE
VGA_DDC_CLK24
VGA_DDC_DATA24
NB_RST#19,26,28,31
NB_PWROK28,37
NB_OSC17
BMREQ#18
1
C496
C496
2.2U_0805_10V6K
2.2U_0805_10V6K
2
VGA_CRT_VSYNC24
VGA_CRT_HSYNC24
1
C483
C483
2
R73 2.7K_0402_5%@R73 2.7K_0402_5%@
1 2
R60 2.7K_0402_5%@R60 2.7K_0402_5%@
1 2
R57 2.7K_0402_5%@R57 2.7K_0402_5%@
1 2
R58 2.7K_0402_5%@R58 2.7K_0402_5%@
1 2
R59 2.7K_0402_5%@R59 2.7K_0402_5%@
1 2
R634 0_0402_5%@ R634 0_0402_5%@
1 2
12
R377
R377
4.7K_0402_5%
4.7K_0402_5%
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AVDD=100mA
1
C487
C487
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
AVDD=250mA
AVDDQ=200mA
1 2
R386 715_0402_1%R386 715_0402_1%
R55 0_0402_5%R55 0_0402_5%
1 2
R56 0_0402_5%R56 0_0402_5%
1 2
PLLVDD
HTPVDD
R62 0_0402_5%R62 0_0402_5%
1 2
R383 10K_0402_5%R383 10K_0402_5%
+PLLVDD12
EDID_LCD_CLK25
EDID_LCD_DAT25
Issued Date
Issued Date
Issued Date
3
2
+3VS
R575
R575
4.7K_0402_5%
4.7K_0402_5%
12
12
R576
R576
4.7K_0402_5%
4.7K_0402_5%
U39C
U39C
VGA_CRT_VSYNC
VGA_CRT_HSYNC
PLLVDD18=625mA
HTPVDD=200mA
LDT_STOP#_NB
12
PLLVDD12=70mA
DFT_GPIO0
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
EDID_LCD_CLK
EDID_LCD_DAT
DDC_DATA
STRP_DATA
C22
G17
H17
C21
C20
D19
G19
C10
C11
C23
AA15
AB15
C14
B22
A20
B20
A21
A22
E19
F19
C6
A5
B21
B6
A6
A10
B10
B24
B25
C5
B5
B23
C2
B11
A11
F2
E1
G1
G2
D6
D7
C8
C7
B8
A8
B2
A2
B4
B3
C3
A3
PART 3 OF 5
PART 3 OF 5
AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI
AVDDQ
AVSSQ
C
Y
COMP
RED
GREEN
BLUE
DACVSYNC
DACHSYNC
RSET
DACSCL
DACSDA
PLLVDD(PLLVDD18)
PLLVSS
HTPVDD
HTPVSS
SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
HTTSTCLK
HTREFCLK
TVCLKIN
OSCIN
OSCOUT(PLLVDD12)
GFX_CLKP
GFX_CLKN
SB_CLKP
SB_CLKN
DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N
TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA
216MQA6AVA11FG_FCBGA465_RS690M
216MQA6AVA11FG_FCBGA465_RS690M
CRT/TVOUT
CRT/TVOUT
LVTM
LVTM
LVDDR18A_1(LVDDR33_1)
LVDDR18A_2(LVDDR33_2)
PLL PWR
PLL PWR
PMCLOCKs
PMCLOCKs
DVO_D0(GPP_TX0P)
DVO_D1(GPP_TX0N)
DVO_D2(DEBUG6)
DVO_D3(GPP_RX0P)
DVO_D4(GPP_RX0N)
DVO_D5(DEBUG9)
DVO_D6(DEBUG10)
DVO_D7(GPP_TX1N)
DVO_D8(GPP_TX1P)
DVO_D9(GPP_RX1N)
DVO_D10(GPP_RX1P)
DVO
DVO
MIS.
MIS.
DVO_D11(DEBUG15)
DVO_VSYNC(DEBUG0)
DVO_DE(DEBUG2)
DVO_HSYNC(DEBUG1)
DVO_IDCKP(DEBUG14)
DVO_IDCKN(DEBUG13)
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
LVDDR18D_1
LVDDR18D_2
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LPVDD
LPVSS
LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVSSR12
LVSSR13
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
E14
A12
B12
C12
C13
A16
A14
D12
C19
C15
C16
F14
F15
E12
G12
F12
AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21
AD13
AC13
AE13
AE17
AD17
RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA
R541 0_0805_5%R541 0_0805_5%
1 2
LPVSS_GND
R542 0_0805_5%R542 0_0805_5%
1 2
LVSSR_GND
Compal Secret Data
Compal Secret Data
2005/03/08 2006/03/08
2005/03/08 2006/03/08
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
1
LVDS_TXLP0
LVDS_TXLN0
LVDS_TXLP1
LVDS_TXLN1
LVDS_TXLP2
LVDS_TXLN2
LVDS_TXUP0
LVDS_TXUN0
LVDS_TXUP1
LVDS_TXUN1
LVDS_TXUP2
LVDS_TXUN2
LVDS_TXLCKP
LVDS_TXLCKN
LVDS_TXUCKP
LVDS_TXUCKN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LVDDR33=180mA
LVDS_ENVDD
LVDS_ENBKL
TP4 PADTP4 PAD
LVDS_ENVDD ENVDD
LVDS_ENVDD
1 2
R746 2K_0402_5%R746 2K_0402_5%
NB_PWROK
LVDS_ENBKL
1 2
R747 2K_0402_5%R747 2K_0402_5%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
LVDS_TXLP0 25
LVDS_TXLN0 25
LVDS_TXLP1 25
LVDS_TXLN1 25
LVDS_TXLP2 25
LVDS_TXLN2 25
LVDS_TXUP0 25
LVDS_TXUN0 25
LVDS_TXUP1 25
LVDS_TXUN1 25
LVDS_TXUP2 25
LVDS_TXUN2 25
LVDS_TXLCKP 25
LVDS_TXLCKN 25
LVDS_TXUCKP 25
LVDS_TXUCKN 25
1
1
C172
C172
C154
C154
2
2
1U_0603_10V4Z
1U_0603_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C171
C171
1
1
C176
1U_0603_10V4Z
1U_0603_10V4Z
RS690M-SYSTEM I/F & CLKGEN
RS690M-SYSTEM I/F & CLKGEN
RS690M-SYSTEM I/F & CLKGEN
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
C176
2
2
R744 0_0402_5%
R744 0_0402_5%
1 2
R745 0_0402_5%
R745 0_0402_5%
1 2
@
@
@
@
1 2
1
MBK2012121YZF_0805
MBK2012121YZF_0805
C177
C177
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C481
C481
2
ENBKLLVDS_ENBKL
+3VS
5
2
P
B
1
A
G
3
5
2
P
B
1
A
G
3
1
L54
L54
LPVSS_GND
1 2
MBK2012121YZF_0805
MBK2012121YZF_0805
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C763
C763
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
Y
U48
U48
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
4
Y
U49
U49
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
L57
L57
C131
C131
RS485: LVDDR18A=1.8V
+1.8VS
+1.8VS
C491
C491
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1
1
2
2
LVSSR_GND
PVT
ENVDD 25
ENBKL 28
ENVDD
ENBKL
of
of
of
14 50Friday, August 08, 2008
14 50Friday, August 08, 2008
14 50Friday, August 08, 2008
+3VS
C497
C497
12
L55MBK2012121YZF_0805 L55MBK2012121YZF_0805
2.0
2.0
2.0
5
4
3
2
1
NB RS485 POWER STATES
Power Signal
VDDHT
VDDR
VDD18
D D
VDDC
VDDA18
VDDA12
AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
L63
L63
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
L64
L64
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
10U_0805_10V4Z
10U_0805_10V4Z
C C
1
C37
C37
2
2006/4/14 FOR EMI
+1.8VS VDD18
L2
L2
1 2
MBC1608121YZF_0.4ohm/300mA_0603
MBC1608121YZF_0.4ohm/300mA_0603
820P_0402_50V7K
820P_0402_50V7K
+1.2V_HT
L58
L58
1 2
1
+
+
C25
C25
150U_D2_6.3VM
150U_D2_6.3VM
2
+3VS VDDR3
MBC1608121YZF_0.4ohm/300mA_0603
MBC1608121YZF_0.4ohm/300mA_0603
B B
+1.8VS
MBK2012121YZF_0.2ohm/800mA_0805
MBK2012121YZF_0.2ohm/800mA_0805
VDDA12
MBC1608121YZF_0.4ohm/300mA_0603
MBC1608121YZF_0.4ohm/300mA_0603
RS485: 0 Ohm RESISTOR
RS690: 220 Ohm 500mA FERRITE BEAD
L3
L3
1 2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
L1
L1
1 2
1 2
L76
L76
+1.2V_HT
12
12
VDD_HT
1
1
C46
C46
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C330
C330
2
2.2U_0805_10V6K
2.2U_0805_10V6K
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
10U_0805_10V4Z
10U_0805_10V4Z
1
1
C44
C44
2
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C161
C161
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C38
C38
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C54
C54
C50
C50
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C141
C141
C142
C142
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C459
C459
C40
C40
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C160
C160
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
VDDR
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C460
C460
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C42
C42
C43
C43
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDPLL VDDA12_PKG1
1
C140
C140
C168
C168
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C49
C49
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C462
C462
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C48
C48
2
1
C123
C123
2
VDDA12
1
C456
C456
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
LVDDR18D
LVDDR18A OFFON ON OFF OFF
+1.2VS_SB_VDD=500mA
VDD_HT=800mA
VDD18=2mA
VDD12=2.5A
1
C461
C461
2
VDDR3=70mA
VDDR=100mA
VDD12=50mA
VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2
1
C134
C134
10U_0805_10V4Z
10U_0805_10V4Z
2
AA17
AB17
AB19
AC18
AC19
AC20
AD21
AD22
AD23
AD24
AE23
AE24
AE25
W17
AC3
AD2
AC12
AD12
AE12
AC11
Y17
AB3
AB4
AE1
AE2
D11
E11
D22
S3
S0
S1
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFFAVDD
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
U39D
U39D
PART 4 OF 5
PART 4 OF 5
VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
J14
VDD18_1
J15
VDD18_2
VDDA18_1(VDDA12_13)
VDDA18_2(VDDA12_14)
VDDA18_3(VDDA12_15)
VDDA18_4(VDDA12_16)
VDDA18_5(VDDA12_17)
VDDA18_6(VDDA12_18)
U7
VDDA18_7(VDDA12_19)
VDDA18_8(VDDA12_20)W7VDDC_14
VDDR3_1
VDDR3_2
VDD_DVO1(VDDR_1)
VDD_DVO2(VDDR_2)
VDD_DVO3(VDDR_3)
E7
VDDA12(VDDPLL_1)
F7
VDDA12(VDDPLL_2)
F9
VSSA12(VSSPLL_1)
G9
VSSA12(VSSPLL_2)
VDDHT_PKG
M1
VDDA12_PKG1
VDDA12_PKG2
216MQA6AVA11FG_FCBGA465_RS690M
216MQA6AVA11FG_FCBGA465_RS690M
S4/S5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
POWER
POWER
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8
VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
B1
C1
D1
D2
D3
E2
E3
F4
E6
G7
L9
M9
A4
A7
A9
A19
B9
B19
C9
D9
D20
G20
H11
J11
J19
L11
L13
L15
L17
M12
M14
N11
N13
N15
P12
P14
P17
R11
R13
R15
U11
U12
U14
U15
VDDA12
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C110
C110
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C24
C24
+
+
150U_D2_6.3VM
150U_D2_6.3VM
2
VDDA12=2.5A
1
C130
C130
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDC=5A
1
C115
C115
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C31
C31
10U_0805_10V4Z
10U_0805_10V4Z
2
1
C112
C112
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C126
C126
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA
1
C93
C93
10U_0805_10V4Z
10U_0805_10V4Z
2
1
C87
C87
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C108
C108
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
1
2
1
C94
C94
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C138
C138
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2
C106
C106
10U_0805_10V4Z
10U_0805_10V4Z
+1.2V_HT
1
1
C60
C60
2
2
1
C135
C135
2
L60
L60
1
C75
C75
+
+
150U_D2_6.3VM
150U_D2_6.3VM
2
C79
C79
1U_0402_6.3V4Z
1U_0402_6.3V4Z
L59
L59
1 2
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
+1.2V_HT
G11
AE18
M15
G23
M11
M20
M23
M25
W23
AD25
W24
AC23
G24
AC14
AC22
AE22
AE14
M17
AC15
M13
AC16
U39E
U39E
A25
VSS1
F11
D23
E9
Y23
P11
R24
J22
J12
L12
L14
L20
L23
N12
N14
L24
P13
P20
P15
R12
R14
R20
Y25
U20
H25
Y22
D25
R23
C4
T23
T25
R17
H23
A23
F17
D4
H12
B7
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS59
VSS60
VSS61
VSS62
PAR 5 OF 5
PAR 5 OF 5
GROUND
GROUND
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
VSSA9
VSSA10
VSSA11
VSSA13
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA30
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51
V12
V11
V14
F3
V15
A1
H1
G3
J2
H3
J6
F1
L6
M2
M6
J3
P6
T1
N3
R6
U2
T3
U3
U6
Y1
W6
AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
Y15
AC4
P9
AE6
AE10
M3
216MQA6AVA11FG_FCBGA465_RS690M
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/10 2006/10/10
2005/10/10 2006/10/10
2005/10/10 2006/10/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
216MQA6AVA11FG_FCBGA465_RS690M
Title
Title
Title
RS690MC-POWER
RS690MC-POWER
RS690MC-POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KAW60 LA-4661P
KAW60 LA-4661P
KAW60 LA-4661P
Date: Sheet
Date: Sheet
Date: Sheet
1
of
of
of
15 50Thursday, August 07, 2008
15 50Thursday, August 07, 2008
15 50Thursday, August 07, 2008
2.0
2.0
2.0
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