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ASPIRE 5252
Schematics
45 pgs8.76 Mb0
User Manual
260 pgs13.59 Mb0

Acer Aspire 5252 Schematics

A
B
C
D
E
1 1
Compal Confidential
2 2
PEW76/86/96 M/B Schematics Document
AMD Danube Only UMA
AMD Champlain Processor with RS880M/SB820M
3 3
2010-07-20
LA6552P REV: 1.0
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
145Thursday, July 22, 2010
145Thursday, July 22, 2010
145Thursday, July 22, 2010
B
B
B
A
B
C
D
E
Danube
Compal Confidential
LVDS
page 15
CRT
page 17
PCB
ZZZ
ZZZ
LA-6552P RE1 M/B
LA-6552P RE1 M/B
LA-6552P MB Rev0: DA60000IM00 LA-6552P MB Rev1: DA60000IM10 LA-6552P MB Rev1: DAZ0FQ00200
Model Name : PEW96 File Name : LA-6552P P/N : DA60000IM10
1 1
AMD S1G4 Processor
uPGA-638 Package Champlain
page 6,7,8,9
Hyper Transport Link 16 x 16
ATI RS880M
uFCBGA-528
page 12,13,14
Memory BUS(DDR3)
Dual Channel
1.5V DDRIII 1066~1333MHz
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
Thermal Sensor
ADM1032
page 27 page 15 page 27 page 26
page 8
page 10,11
page 26
HDMI Conn.
page 16
2 2
MINI Card 1
WLAN
page 26
LAN(GbE)
Broadcom BCM57780
page 24
A link Express2
Gen1
ATI SB820M
uFCBGA-605
page 18,19,20,21,22
USB conn X 3
USB port 0,1,2
3.3V 48MHz
3.3V 24.576MHz/48Mhz
S-ATA
Gen2
CMOS Camera
USB port 5 USB port 7 USB port 8
Bluetooth Conn
<Option>
USB
HD Audio
GPP0GPP1
RJ45
page 25
LED
3 3
page 29
RTC CKT.
page 18
LID SW / MEDIA/B
page 28
Fan Control
page 32
Extend Card/B
1. USB X2
2. ODD X1
Touch Pad
EC I/O Buffer
ENE KB926
page 29
page 29
LPC BUS
page 28
Int.KBD
BIOS
SATA HDD Conn.
port 0
page 29
page 29
page 23
SATA ODD FFC Conn.
page 23
port 1
Mini card (WL)X1
HDA Codec ALC272X
page 30
Audio AMP
page 31
Phone Jack x2
page 31
Card Reader RTS5137
USB port 6
Power On/Off CKT.
page 32
DC/DC Interface CKT.
4 4
Power Circuit
page 34,35,36,37,38 39,40,41,42
page 33
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
B
B
245Thursday, July 22, 2010
245Thursday, July 22, 2010
245Thursday, July 22, 2010
B
5
4
3
2
1
D D
32.768K Hz 25MHz
MEM_MA_CLK1_P/N
C C
A_SODIMM
B_SODIMM
B B
CardReader RTS5137
MEM_MA_CLK7_P/N
MEM_MB_CLK1_P/N MEM_MB_CLK7_P/N
CLK_48M_SD
48MHz
1066MHz
1066MHz
AMD
S1G4 CPU SOCKET
CLK_PCIE_WWAN
WWAN Mini PCI Socket
100MHz
CPU_CLKP/N 200MHz
CLK_PCIE_MINI1
100MHz
WLAN Mini PCI Socket
RTC SATA
AMD
ATI SB SB820M
Internal CLK GEN.
CLK_PCIE_LAN
100MHz
GbE LAN BCM 57780
CLK_SBLINK_BCLK
100MHz
CLK_NBHT
100MHz
AMD
ATI NB RS880M
A A
Security Classification
Security Classification
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
CLOCK DISTRIBUTION
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
Date: Sheet
Date: Sheet
2
Date: Sheet
345Thursday, July 22, 2010
345Thursday, July 22, 2010
345Thursday, July 22, 2010
1
B
B
B
of
of
of
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+ +CPU_CORE +CPU_CORE_NB OFFOFFONVoltage for On-die Northbridge of CPU(0.8-1.1V) +CPU_VDDR 1.05V switched power rail ON OFF OFF +0.75V 0.75V switched power rail for DDR terminator +1.1VS +1.5V 1.5V power rail for CPU VDDIO and DDR ON OFFON
+2.5VS 2.5V for CPU_VDDA OFFOFFON +3VALW 3.3V always on power rail ON ON*ON +3VS 3.3V switched power rail OFFON OFF +3V_LAN 3.3V power rail for LAN ON ON ON +5VALW +5VS +VSB +RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU (1.375-1.5V)
1.1V switched power rail for NB VDDC & VGA
1.8V switched power rail+1.8VS OFFON OFF
5V always on power rail 5V switched power rail VSB always on power rail ON
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON
ON ON OFF OFF
OFF OFF+1.5VS 1.5V power rail for MINI Card ON
ON
ON ON* OFFON OFF
ON
ON ON
ON
N/AN/AN/A OFF
OFF
ON*
C
SIGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW LOW
SLP_S4# SLP_S5# +VALW +V +VS Clock
LOW
HIGH
LOWLOWLOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6 7NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
BOARD ID Table
Board ID
0 1 2 3 4
PCB Revision
EVT / PVT stage (w/ pach code)
D
ON
ON
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
OFF
ON
OFF
ON
V
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
BTO Option Table
E
ON ON
LOW
ON
OFF
OFF
OFF
OFF
OFF
OFF
max
0.538 V
0.875 V
2.341 V
3.300 V
BTO Item BOM Structure
Bluetooth BT@ Vari-Bright VB@
No Vari-Bright UNVB@
HDMI HDMI@
5 6 7
3 3
EC SM Bus1 address
Device
Smart Battery
Address Address
HEX
EC SM Bus2 address
Device
ADI ADM1032 (CPU) SB-Temp Sensor
1001 100X b0001 011X b
HEX 98H16H 98H
Project ID Table
Board ID
0 1 2
PCB Revision
PEW76/86/96
3 4
SB820 SM Bus 0 address
Device
Clock Generator (SILEGO SLG8SP626)
DDR DIMM1 DDR DIMM2 Mini card
4 4
Address
1101 001Xb
1001 000Xb 1001 010Xb
HEX
D2 90
94
A
SB820 SM Bus 1 address
Device Address
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 6 7
Compal Secret Data
Compal Secret Data
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Notes List
Notes List
Notes List
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
B
B
445Thursday, July 22, 2010
445Thursday, July 22, 2010
445Thursday, July 22, 2010
B
5
BATTERY
12.6V
BATT+
PU5 CHARGER ISL6261AHAZ-T
PU15 ISL6265IRZ-T
AC ADAPTOR 19V 90W
D D
VIN
B+
PU7 RT8209BGQW
4
+CPU_CORE +CPU_CORE_NB
+1.5V
3
PU16 APL5508-25DC
+2.5VS
PU12 APL5915
+1.05VS
2
+1.5V
+CPU_CORE
+CPU_CORE_NB
+1.05VS
+1.1VS
AMD CPU S1G4
0.7~1.3V
0.8~1.2V
2.5V
1.5V
1.05V
1.1V
VDD CORE 36A VDDNB 4A VDDA 250mA VDDIO 3A VDDR 1.5A VLDT 1.5A
RAM DDRIII SODIMMX2
1.5V
0.75V
VDD_MEM 4A VTT_MEM 0.5A
1
+0.75VS
PU10 APL5913
NorthBridge AMD RS880M
PU8 RT8209BGQW
+NB_CORE
+1.1VS
1.0~1.1V
1.1V_S0
1.8V_S0
+1.5VS
+1.1VALW
U36 SI4800BDY
+1.1VS
3.3V_S0
No Use
PU6 RT8209BGQW
C C
+1.1VALW
PU19 TSP51117RGYR
+1.5V
U35 SI4800BDY
VDDC 1.0V-1.1V 7.6A
VDDHTRX+HT 0.68A VDDPCIE 1.1A VDDHTTX 0.68A PLLs 0.23A
VDDA18 0.64A VDDG18 0.005A VDDLT18 0.22A PLLs 0.1A
VDDG33 0.06A AVDD 0.125A VDDLT33 0A
VDD18_MEM 1.8V 0.005A VDD_MEM 1.8V 0.23A
VGA ATI Madison / Park
PU17 APW7138NITRL
+INVPWR_B+
B B
LCD panel
15.6"
B+ 300mA +3.3 350mA
FAN Control APL5607
PU4 SN0806081 RHBR
+5VS 500mA
U25/U40 TPS2061DRG4
A A
USB X3
+5V Dual+1
2.5A
+USB_VCCA +USB_VCCB
5
Audio AMP TPA6017A2
+5V 25mA
SATA
+5V 3A +3.3V
Audio Codec ALC272X
+5V 45mA +3.3VS 25mA
+GPU_CORE +VDDCI
+1.8VS
+3VALW
PU14 APL5913
+1.8VSP2
PU11 MP2121DQ
+5VALW
U34 SI4800BDY
Realtek RTS5137
4
EC ENE KB926
+3.3VALW 30mA +3.3VS 3mA
+1.8VSP1
+5VS
PU10 APL5913
LAN BCM57780
+3.3VALW 750mA
+1VSG
U37 SI1800BDY
3
+1.5VS
+3VS
Delay
+1.1VALW
+3VALW
ICS9LPRS488B
+3.3V 400mA +1.1V
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
Mini Card
+1.5VS 500mA +3.3VS 1A+3.3VS 300mA +3.3VALW 330mA
RTC Bettary
Compal Secret Data
Compal Secret Data
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+3VS_DELAY
0.85~1.1V
1.0V
1.5V
1.8V
3.3V
VDDC 29 A VDDCI 4 A
PCIE_VDDC 2 A DP[F:A]_VDD10 230 mA DPLL_VDDC 125 mA SPV10 100 mA
VDDR1 TBD A
PCIE_PVDD 40 mA PCIE_VDDR 400 mA TSVDD 5 mA VDDR4 TBD mA VDD_CT 17 mA DP[F:A]_PVDD 20 mA DP[F:A]_VDD18 330 mA AVDD 70 mA VDD1DI 45 mA A2VDDQ 1.5 mA VDD2DI 50 mA DPLL_PVDD 75 mA MPV18 150 mA SPV18 50 mA
VDDR3 60 mA A2VDD 130 mA
SouthBridge AMD SB820M
VDDCR_11 1.1V 0.5A VDDAN_11_PCIE 1A
1.1V_S0
1.1V_S5
3.3V_S0
3.3V_S5
No Use
BAT
VDDAN_11_SATA 0.8A VDDAN_11_CLK 0.4A
VDDCR_11_S 113mA VDDAN_11_USB_S 200mA VDDCR_11_USB_S 197mA VDDPL_11_SYS_S
VDDIO_33_PCIGP 0.020A VDDPL_33_PCIE 0.030A VDDPL_33_SATA 0.020A VDDPL_33_SYS
VDDIO_33_S VDDPL_33_USB_S VDDAN_33_USB_S 0.2A VDDAN_33_S VDDXL_33_S VDDIO_AZ_S
VDDCR_11_GBE_S VDDRF_GBE_S VDDIO_33_GBE_S VDDIO_GBE_S VDDIO_18_FC
VDDBT_RTC_G2.5~3.6V
Title
Title
Title
POWER DELIVERY CHART
POWER DELIVERY CHART
POWER DELIVERY CHART
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
Date: Sheet
Date: Sheet
Date: Sheet
VRAM 1GB 64Mx16 (K4B1G1646E) * 8
1.5V 2.4 A
1
B
B
B
of
545Thursday, July 22, 2010
of
545Thursday, July 22, 2010
of
545Thursday, July 22, 2010
A
B
C
D
E
1 1
+1.1VS
250 mil
2
C1
H_CADIP[0..15]<12>
H_CADIP[0..15] H_CADIN[0..15]
H_CADOP[0..15] H_CADON[0..15]
H_CADOP[0..15] <12> H_CADON[0..15] <12>H_CADIN[0..15]<12>
C1 10U_0805_10V4Z
10U_0805_10V4Z
1
2
C2
C2 10U_0805_10V4Z
10U_0805_10V4Z
1
VLDT CAP.
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
2
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C5
C5 180P_0402_50V8J
180P_0402_50V8J
2
1
C6
C6 180P_0402_50V8J
180P_0402_50V8J
2
Near CPU Socket
+1.1VS
2 2
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12
3 3
H_CLKIP0<12> H_CLKIN0<12> H_CLKIP1<12> H_CLKIN1<12>
H_CTLIP0<12> H_CTLIP1<12> H_CTLOP1 <12>
H_CTLIN1<12>
H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
JCPU1A
JCPU1A
TBD
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
HT LINK
HT LINK
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1 L0_CTLOUT_H0
L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1
+1.1VS
AE2 AE3 AE4 AE5
H_CADOP0
AD1
H_CADON0
AC1
H_CADOP1
AC2
H_CADON1
AC3
H_CADOP2
AB1
H_CADON2
AA1
H_CADOP3
AA2
H_CADON3
AA3
H_CADOP4
W2
H_CADON4
W3
H_CADOP5
V1
H_CADON5
U1
H_CADOP6
U2
H_CADON6
U3
H_CADOP7
T1
H_CADON7
R1
H_CADOP8
AD4
H_CADON8
AD3
H_CADOP9
AD5
H_CADON9
AC5
H_CADOP10
AB4
H_CADON10
AB3
H_CADOP11
AB5
H_CADON11
AA5
H_CADOP12
Y5
H_CADON12
W5
H_CADOP13
V4
H_CADON13
V3
H_CADOP14
V5
H_CADON14
U5
H_CADOP15
T4
H_CADON15
T3 Y1
W1 Y4 Y3
R2 R3 T5 R5
C7
C7
12
10U_0805_10V4Z
10U_0805_10V4Z
H_CLKOP0 <12> H_CLKON0 <12> H_CLKOP1 <12> H_CLKON1 <12>
H_CTLOP0 <12> H_CTLON0 <12>H_CTLIN0<12>
H_CTLON1 <12>
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G4 HT I/F
AMD CPU S1G4 HT I/F
AMD CPU S1G4 HT I/F
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
of
645Thursday, July 22, 2010
645Thursday, July 22, 2010
645Thursday, July 22, 2010
B
B
B
A
B
C
D
E
DDRB_SDQ[63..0]<11>
1 1
AMD suggest
2 2
+1.5V
R410 0_0603_5%R410 0_0603_5%
10U_0805_10V4Z
10U_0805_10V4Z
3 3
+1.5V
R1
R1
1K_0402_1%
1K_0402_1%
1 2
R2
R2
1K_0402_1%
1K_0402_1%
1 2
12
1
C95
C95
@
@
2
DDRA_SMA[15..0]<10> DDRB_SMA[15..0] <11>
MEM_VREF
1
1
C9
DDRA_SBS0#<10> DDRA_SBS1#<10> DDRA_SBS2#<10>
DDRA_SRAS#<10> DDRA_SCAS#<10> DDRA_SWE#<10>
C8
2
0.01U_0402_25V7KC90.01U_0402_25V7K
Place them close to CPU within 1"
R4 39.2_0402_1%R4 39.2_0402_1%
1 2 1 2
R5 39.2_0402_1%R5 39.2_0402_1%
1000P_0402_50V7KC81000P_0402_50V7K
JCPU1B
JCPU1B
1.5A
D10
VDDR1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
C10
VDDR2
B10
VDDR3
AD10
MEMZP
MEMZN MEM_MA_RST# DDRA_ODT0
DDRA_ODT1
DDRA_SCS0# DDRA_SCS1# DDRB_SCS0#
DDRA_CKE0 DDRA_CKE1
DDRA_CLK0 DDRA_CLK0#
DDRA_CLK1 DDRA_CLK1#
DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15
DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#
DDRA_SRAS# DDRA_SCAS# DDRA_SWE#
VDDR4
AF10
MEMZP
AE10
MEMZN
H16
MA_RESET_L
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H5
N20
MA_CLK_L5
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H7
AA16
MA_CLK_L7
P19
MA_CLK_H4
P20
MA_CLK_L4
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
VDDR_SENSE
MB_RESET_L
VDDR5 VDDR6 VDDR7 VDDR8 VDDR9
MEMVREF
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
W10 AC10 AB10 AA10 A10
Y10 W17 B18 W26
W23 Y26
V26 W25 U22
J25 H26
P22 R22 A17 A18 AF18 AF17 R26 R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
+CPU_VDDR+CPU_VDDR
VDDR: DDR3 under 1033MHz set to 0.9V to save power
VTT_SENSE MEM_VREF MEM_MB_RST# DDRB_ODT0
DDRB_ODT1
DDRB_SCS1#
DDRB_CKE0 DDRB_CKE1
DDRB_CLK0 DDRB_CLK0#
DDRB_CLK1 DDRB_CLK1#
DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15
DDRB_SBS0# DDRB_SBS1# DDRB_SBS2#
DDRB_SRAS# DDRB_SCAS# DDRB_SWE#
2
MEM_MA_RST#<10>
DDRA_ODT0<10> DDRA_ODT1<10>
DDRA_SCS0#<10> DDRA_SCS1#<10> DDRB_SCS0# <11>
DDRA_CKE0<10> DDRA_CKE1<10>
DDRA_CLK0<10>
DDRA_CLK0#<10>
DDRA_CLK1<10>
DDRA_CLK1#<10>
T1PAD T1PAD
MEM_MB_RST# <11> DDRB_ODT0 <11>
DDRB_ODT1 <11>
DDRB_SCS1# <11>
DDRB_CKE0 <11> DDRB_CKE1 <11>
DDRB_CLK0 <11> DDRB_CLK0# <11>
DDRB_CLK1 <11> DDRB_CLK1# <11>
DDRB_SBS0# <11> DDRB_SBS1# <11> DDRB_SBS2# <11>
DDRB_SRAS# <11> DDRB_SCAS# <11> DDRB_SWE# <11>
DDRB_SDM[7..0]<11> DDRA_SDM[7..0] <10>
DDRB_SDQS0<11> DDRB_SDQS0#<11> DDRB_SDQS1<11> DDRB_SDQS1#<11> DDRB_SDQS2<11> DDRB_SDQS2#<11> DDRB_SDQS3<11> DDRB_SDQS3#<11> DDRB_SDQS4<11> DDRB_SDQS4#<11> DDRB_SDQS5<11> DDRB_SDQS5#<11> DDRB_SDQS6<11> DDRB_SDQS6#<11> DDRB_SDQS7<11> DDRB_SDQS7#<11>
Processor DDR3 Memory Interface
JCPU1C
JCPU1C
MEM:DATA DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63
DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7
DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7#
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23
G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11 AE14 AF14 AF11 AD11
A12
B16
A22
E25 AB26 AE22 AC16 AD12
C12
B12
D16
C16
A24
A23
F26
E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
MEM:DATA
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63
DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7
DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#
DDRA_SDQ[63..0] <10>
DDRA_SDQS0 <10> DDRA_SDQS0# <10> DDRA_SDQS1 <10> DDRA_SDQS1# <10> DDRA_SDQS2 <10> DDRA_SDQS2# <10> DDRA_SDQS3 <10> DDRA_SDQS3# <10> DDRA_SDQS4 <10> DDRA_SDQS4# <10> DDRA_SDQS5 <10> DDRA_SDQS5# <10> DDRA_SDQS6 <10> DDRA_SDQS6# <10> DDRA_SDQS7 <10> DDRA_SDQS7# <10>
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G4 DDRIII I/F
AMD CPU S1G4 DDRIII I/F
AMD CPU S1G4 DDRIII I/F
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
745Thursday, July 22, 2010
745Thursday, July 22, 2010
745Thursday, July 22, 2010
E
B
B
B
A
L1
+2.5VS
1 1
LDT_RST#<18>
2 2
H_PWRGD<18>
3 3
CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>
+1.5VS
R17
R17 300_0402_5%
300_0402_5%
1 2
LDT_RST#
1
C17
C17
0.01U_0402_25V4Z
0.01U_0402_25V4Z @
@
2
+1.5VS
R21
R21 300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C19
C19
0.01U_0402_25V4Z
0.01U_0402_25V4Z @
@
2
+3VS
1
@
@ C20
C20
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
C21 100P_0402_50V8J
C21 100P_0402_50V8J
@
@
LDT_STOP#<13,18>
THERMDA_CPU THERMDC_CPU
+
+
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
12
C11
C11
220U_6.3V_M
220U_6.3V_M
1 2
C16
C16
1 2
C15 3900P_0402_50V7KC15 3900P_0402_50V7K
+1.5VS
1 2
LDT_STOP#
1
C18
C18
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
@
@
U1
U1
1
VDD
2
D+
3
D­THERM#4GND
ADM1032ARMZ_MSOP8
ADM1032ARMZ_MSOP8
Address
1 2
3900P_0402_50V7K
3900P_0402_50V7K
12
R10
R10 169_0402_1%
169_0402_1%
R18
R18 300_0402_5%
300_0402_5%
@
@
SCLK
SDATA
ALERT#
1001 100X b
L1
CPU internal thermal sensor
1 2
C22 0.1U_0402_16V4ZC22 0.1U_0402_16V4Z
R42
R41
R41
+3VS
31.6K_0402_1%
31.6K_0402_1%
4 4
CPU_SID
CPU_SIC
R42
30K_0402_5%
30K_0402_5%
2
13
D
D
2
13
D
D
12
12
G
G
S
S
Q2 FDV301N_NL_SOT23-3
Q2 FDV301N_NL_SOT23-3
G
G
S
S
Q3 FDV301N_NL_SOT23-3
Q3 FDV301N_NL_SOT23-3
A
EC_SMB_DA2
EC_SMB_CK2
FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V
For PVT
1.607V for Gate
+1.5V +1.5V
+1.1VS
EC_SMB_CK2
8
EC_SMB_DA2
7 6 5
BSH111, the Vgs is: min = 0.4V Typ = 1.0V Max = 1.3V
B
+2.5VDDA
3300P_0402_50V7K
3300P_0402_50V7K
1
1
C124.7U_0805_10V4Z C124.7U_0805_10V4Z
C13
C13
2
2
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
1 2
R12 1K_0402_5%R12 1K_0402_5%
1 2
R14 1K_0402_5%R14 1K_0402_5%
R15 44.2_0402_1%R15 44.2_0402_1%
1 2
R16 44.2_0402_1%R16 44.2_0402_1%
1 2
CPU_VDD0_FB_H<42> CPU_VDD0_FB_L<42>
CPU_VDD1_FB_H<42> CPU_VDD1_FB_L<42>
EC_SMB_CK2 <28>
EC_SMB_DA2 <28>
B
VDDA=0.25A
1
C14
C14
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
LDT_RST# H_PWRGD LDT_STOP#
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
1 2
R24 0_0402_5%R24 0_0402_5%
C
Champlain: C1E C1E: LDT_REQ# no connect CLMC: LDT_REQ# connect to NB
LDT_RES# / MEMHOT# no support in S1g4
JCPU1D
JCPU1D
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
T2 PADT2 PAD
CPU_SIC CPU_SID
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_FB_H CPU_VDD0_FB_L
CPU_VDD1_FB_H CPU_VDD1_FB_L
CPU_TEST23 CPU_TEST18
CPU_TEST19 CPU_TEST25H
CPU_TEST25L
CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
C
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H VDDNB_FB_L
M11
VSS
W18
RSVD11
MEMHOT_L
THERMDC THERMDA
DBREQ_L
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST10
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
CPU_SVC
A6
SVC
CPU_SVD
A4
SVD
AF6 AC7 AA8
THERMDC_CPU
W7
THERMDA_CPU
W8
W9 Y9
CPU_VDDNB_FB_H
H6
CPU_VDDNB_FB_L
G6
CPU_DBREQ#
E10
CPU_TDO
AE9
TDO
J7 H8
CPU_TEST17
D7
CPU_TEST16
E7
CPU_TEST15
F7
CPU_TEST14
C7 C3
TEST7
K8 C4
TEST8
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
H18 H19 AA7 D5 C5
+1.5V
R38220_0402_5%
R38220_0402_5%
R37220_0402_5%
R37220_0402_5%
R39300_0402_5%
R39300_0402_5%
R36220_0402_5%
R36220_0402_5%
12
12
12
12
@
@
@
@
@
@
@
@
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
CPU_SVC <42> CPU_SVD <42>
CPU_THERMTRIP#_R H_PROCHOT#
T3PAD T3PAD
T4PAD T4PAD T11PAD T11PAD
R40300_0402_5% R40300_0402_5%
1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
CPU_VDDNB_FB_H <42> CPU_VDDNB_FB_L <42>
T5PAD T5PAD T6PAD T6PAD T7PAD T7PAD T8PAD T8PAD
R25 80.6_0402_1%R25 80.6_0402_1%
JP2
JP2
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
CONN@ SAMTEC_ASP-68200-07
CONN@
Deciphered Date
Deciphered Date
Deciphered Date
D
12
HDT_RST#
D
R7
R7
1K_0402_5%
1K_0402_5%
CPU_THERMTRIP#_R
1 2
+1.5V
R11 300_0402_5%R11 300_0402_5%
H_PROCHOT#
PROCHOT: Input: For HTC Function Output: Over Temperature Condition
U2
4
1 2
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
CPU_SVC CPU_SVD
CPU_TEST25H
CPU_TEST25L
CPU_TEST27
For SCAN connect use
CPU_TEST12 CPU_TEST18 CPU_TEST19 CPU_TEST20 CPU_TEST21 CPU_TEST22 CPU_TEST24 CPU_TEST23
R43
R43
1 2
0_0402_5%@
0_0402_5%@
+3VS
5
2
P
B
Y
1
A
G
NC7SZ08P5X_NL_SC70-5@U2NC7SZ08P5X_NL_SC70-5@
3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
+1.5V
12
R6
R6 10K_0402_5%
10K_0402_5% <BOM Structure>
<BOM Structure>
B
B
2
Q1
Q1
E
E
3 1
1 2
R19 1K_0402_5%R19 1K_0402_5%
1 2
R20 1K_0402_5%R20 1K_0402_5%
1 2
R22 510_0402_5%R22 510_0402_5%
1 2
R23 510_0402_5%@R23 510_0402_5%@
1 2
R26 510_0402_5%@R26 510_0402_5%@
1 2
R27 510_0402_5%R27 510_0402_5%
1 2
R28 1K_0402_5%R28 1K_0402_5%
1 2
R29 1K_0402_5%R29 1K_0402_5%
1 2
R30 1K_0402_5%R30 1K_0402_5%
1 2
R31 1K_0402_5%R31 1K_0402_5%
1 2
R32 1K_0402_5%R32 1K_0402_5%
1 2
R33 1K_0402_5%R33 1K_0402_5%
1 2
R34 1K_0402_5%R34 1K_0402_5%
1 2
R35 1K_0402_5%R35 1K_0402_5%
1 2
R265 1K_0402_5%R265 1K_0402_5%
1 2
C
C
R8 0_0402_5%R8 0_0402_5%
1 2
R9 0_0402_5%@R9 0_0402_5%@
1 2
R13 0_0402_5%R13 0_0402_5%
LDT_RST#
SB_PWRGD <13,19,28>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AMD CPU S1G4 CTRL
AMD CPU S1G4 CTRL
AMD CPU S1G4 CTRL
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
+1.5V
+1.5V
+1.5V
+1.5V
E
H_THERMTRIP# <19>
MAINPWON <35,36>
H_PROCHOT_R# <18>
of
845Thursday, July 22, 2010
845Thursday, July 22, 2010
845Thursday, July 22, 2010
B
B
B
A
VDD(+CPU_CORE) decoupling.
1 1
+CPU_CORE
+CPU_CORE
2 2
+CPU_CORE
1
+
+
C23
C23
330U_D2_2V_Y
330U_D2_2V_Y 2
Change as SGA19331D10 (ESR9 ohm) for PVT
1
C28
C28 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C36
C36
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C29
C29 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C37
C37
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
+
+
330U_D2_2V_Y
330U_D2_2V_Y 2
1
C30
C30 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C38
C38 180P_0402_50V8J
180P_0402_50V8J
2
C24
C24
Near CPU Socket
1
C35
C35 22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
VDDIO decoupling.
+1.5V
1
C44
C44 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C45
C45 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C46
C46
0.22U_0603_16V4Z
0.22U_0603_16V4Z 2
Under CPU Socket
3 3
4 4
+1.5V
1
C51
C51
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+1.5V +1.5V
1
C64
C64
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
+1.5V
1
2
Between CPU Socket and DIMM
C71
C71
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C52
C52
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C65
C65
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
C72
C72
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C53
C53
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2
1
1
2
1
C47
C47
0.22U_0603_16V4Z
0.22U_0603_16V4Z 2
1
C54
C54
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
C66
C66
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
Change as SGA19331D10 (ESR9 ohm) for PVT
C73
C73
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
1
+
+
C25
C25
330U_D2_2V_Y
330U_D2_2V_Y 2
1
180P_0402_50V8J
180P_0402_50V8J 2
C67
C67
0.1U_0402_16V7K
0.1U_0402_16V7K
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
B
+CPU_CORE
1
C31
C31 22U_0805_6.3V6M
22U_0805_6.3V6M
2
C48
C48
1
C354
C354
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C68
C68 180P_0402_50V8J
180P_0402_50V8J
2
1
+
+
C75
C75
330U_D2_2V_Y
330U_D2_2V_Y
2
1
+
+
C26
C26
330U_D2_2V_Y
330U_D2_2V_Y 2
+CPU_CORE
1
C50
C50 180P_0402_50V8J
180P_0402_50V8J
2
1
C32
C32 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C39
C39
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C355
C355
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C69
C69 180P_0402_50V8J
180P_0402_50V8J
2
C
1
+
+
C27
C27 @
@
330U_D2_2V_Y
330U_D2_2V_Y 2
1
2
1
2
C33
C33 22U_0805_6.3V6M
22U_0805_6.3V6M
C40
C40
0.01U_0402_25V4Z
0.01U_0402_25V4Z
1
C34
C34 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C41
C41 180P_0402_50V8J
180P_0402_50V8J
2
+CPU_CORE
+CPU_CORE_NB
+1.5V
4A
G4
H2
J9 J11 J13
J15
K6 K10 K12 K14
L4
L7
L9 L11 L13 L15
M2 M6 M8
M10
N7
N9 N11
K16
M16
P16 T16 V16
H25 J17 K18 K21 K23 K25 L17
M18 M21 M23 M25
N17
Athlon 64 S1 Processor Socket
+CPU_CORE_NB decoupling.
+CPU_CORE_NB
1
C42
C42 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C43
C43 22U_0805_6.3V6M
22U_0805_6.3V6M
2
VDDR decoupling.
+CPU_VDDR
1
C57
C57
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+CPU_VDDR
1
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C58
C58
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side.
1
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
2
1
C59
C59
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C78
C78
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C49
C49 22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_VDDR
Near Power Supply
12
+
+
C56 220U_6.3V_M
C56 220U_6.3V_M
1
C60
C60
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C79
C79
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
D
JCPU1E
JCPU1E
VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23
VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
1
C55
C55 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C61
C61 1000P_0402_50V7K
1000P_0402_50V7K
2
1
C80
C80 1000P_0402_50V7K
1000P_0402_50V7K
2
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8
VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
1
C62
C62 1000P_0402_50V7K
1000P_0402_50V7K
2
1
C81
C81 1000P_0402_50V7K
1000P_0402_50V7K
2
36A
TBD
+CPU_CORE
+1.5V
1
C63
C63 180P_0402_50V8J
180P_0402_50V8J
2
1
C82
C82 180P_0402_50V8J
180P_0402_50V8J
2
JCPU1F
JCPU1F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ63823-284S-41F_Champlian
FOX_PZ63823-284S-41F_Champlian
Athlon 64 S1 Processor Socket
+1.5V
1
C70
C70 180P_0402_50V8J
180P_0402_50V8J
2
1
C83
C83 180P_0402_50V8J
180P_0402_50V8J
2
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
@
2
1
E
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
C98 0.1U_0402_16V7K@C98 0.1U_0402_16V7K
C97 0.1U_0402_16V7K@C97 0.1U_0402_16V7K
2
2
@
@
1
1
Reserve for EMI
C101 0.1U_0402_16V7K@C101 0.1U_0402_16V7K
C100 0.1U_0402_16V7K@C100 0.1U_0402_16V7K
C99 0.1U_0402_16V7K@C99 0.1U_0402_16V7K
2
@
1
C96 0.1U_0402_16V7K@C96 0.1U_0402_16V7K
2
2
@
@
1
1
Near CPU Socket Left side.
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G4 PWR & GND
AMD CPU S1G4 PWR & GND
AMD CPU S1G4 PWR & GND
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
945Thursday, July 22, 2010
945Thursday, July 22, 2010
945Thursday, July 22, 2010
E
B
B
B
A
B
C
D
E
+VREF_DQ
DDRA_SDQ0
1 1
DDRA_SDQS1#<7> DDRA_SDQS1<7>
DDRA_SDQS2#<7> DDRA_SDQS2<7>
DDRA_CKE0<7>
2 2
3 3
4 4
2.2U_0805_10V6K
2.2U_0805_10V6K
DDRA_SBS2#<7>
DDRA_CLK0<7> DDRA_CLK0#<7>
DDRA_SBS0#<7>
DDRA_SWE#<7>
DDRA_SCAS#<7> DDRA_ODT0 <7>
DDRA_SCS1#<7>
DDRA_SDQS4#<7> DDRA_SDQS4<7>
DDRA_SDQS6#<7> DDRA_SDQS6<7>
+3VS
1
C90
C90
C91
C91
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
A
DDRA_SDQ1 DDRA_SDM0 DDRA_SDQ2
DDRA_SDQ3 DDRA_SDQ8
DDRA_SDQ9 DDRA_SDQS1#
DDRA_SDQS1 DDRA_SDQ10
DDRA_SDQ11 DDRA_SDQ16
DDRA_SDQ17 DDRA_SDQS2#
DDRA_SDQS2 DDRA_SDQ18
DDRA_SDQ19 DDRA_SDQ24
DDRA_SDQ25 DDRA_SDM3 DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
DDRA_SBS2# DDRA_SMA12
DDRA_SMA9 DDRA_SMA8
DDRA_SMA5 DDRA_SMA3
DDRA_SMA1 DDRA_CLK0
DDRA_CLK0# DDRA_SMA10
DDRA_SBS0# DDRA_SWE#
DDRA_SCAS# DDRA_ODT0 DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32 DDRA_SDQ33
DDRA_SDQS4# DDRA_SDQS4
DDRA_SDQ34 DDRA_SDQ35
DDRA_SDQ40 DDRA_SDQ41
DDRA_SDM5 DDRA_SDQ42
DDRA_SDQ43 DDRA_SDQ48
DDRA_SDQ49 DDRA_SDQS6#
DDRA_SDQS6 DDRA_SDQ50
DDRA_SDQ51 DDRA_SDQ56
DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58
DDRA_SDQ59
R50 10K_0402_5%R50 10K_0402_5%
+3VS
1
2
1 2
+1.5V +1.5V
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
12
R51
R51 10K_0402_5%
10K_0402_5%
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
DQS#0
VSS10
VSS17
VSS19
VSS21
VDD10
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30 VSS31
VSS33
VSS35
DQS#5
VSS38
VSS40
VSS42 VSS43
VSS45
VSS47
DQS#7
VSS50
VSS52
EVENT#
FOX_AS0A626-U8SN-7F
FOX_AS0A626-U8SN-7F CONN@
CONN@
DIMM_A STD H:8mm
<Address: 00>
DQ4 DQ5
VSS3
DQS0
VSS6
DQ6 DQ7
VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2
DQ22 DQ23
DQ28 DQ29
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1#
RAS#
ODT0 ODT1
NC2
DQ36 DQ37
DM4
DQ38 DQ39
DQ44 DQ45
DQS5 DQ46
DQ47 DQ52
DQ53
DM6
DQ54 DQ55
DQ60 DQ61
DQS7 DQ62
DQ63
SDA
VTT2
2
DDRA_SDQ4
4
DDRA_SDQ5
6 8
DDRA_SDQS0#
10
DDRA_SDQS0
12 14
DDRA_SDQ6
16
DDRA_SDQ7
18 20
DDRA_SDQ12
22
DDRA_SDQ13
24 26
DDRA_SDM1
28
MEM_MA_RST#
30 32
DDRA_SDQ14
34
DDRA_SDQ15
36 38
DDRA_SDQ20
40
DDRA_SDQ21
42 44
DDRA_SDM2
46 48
DDRA_SDQ22
50
DDRA_SDQ23
52 54
DDRA_SDQ28
56
DDRA_SDQ29
58 60
DDRA_SDQS3#
62
DDRA_SDQS3
64 66
DDRA_SDQ30
68
DDRA_SDQ31
70 72
DDRA_CKE1
74 76
DDRA_SMA15
78
A15 A14
A11
A7 A6
A4 A2
A0
CK1
BA1
S0#
SCL
G2
DDRA_SMA14
80 82
DDRA_SMA11
84
DDRA_SMA7
86 88
DDRA_SMA6
90
DDRA_SMA4
92 94
DDRA_SMA2
96
DDRA_SMA0
98 100
DDRA_CLK1
102
DDRA_CLK1#
104 106
DDRA_SBS1#
108
DDRA_SRAS#
110 112
DDRA_SCS0#
114 116 118
DDRA_ODT1
120 122 124 126 128
DDRA_SDQ36
130
DDRA_SDQ37
132 134
DDRA_SDM4
136 138
DDRA_SDQ38
140
DDRA_SDQ39
142 144
DDRA_SDQ44
146
DDRA_SDQ45
148 150
DDRA_SDQS5#
152
DDRA_SDQS5
154 156
DDRA_SDQ46
158
DDRA_SDQ47
160 162
DDRA_SDQ52
164
DDRA_SDQ53
166 168
DDRA_SDM6
170 172
DDRA_SDQ54
174
DDRA_SDQ55
176 178
DDRA_SDQ60
180
DDRA_SDQ61
182 184
DDRA_SDQS7#
186
DDRA_SDQS7
188 190
DDRA_SDQ62
192
DDRA_SDQ63
194 196 198 200 202 204
206
B
T9PAD T9PAD
+0.75VS
DDRA_SDQS0# <7> DDRA_SDQS0 <7>
MEM_MA_RST# <7>
DDRA_SDQS3# <7> DDRA_SDQS3 <7>
DDRA_CKE1 <7>
DDRA_CLK1 <7> DDRA_CLK1# <7>
DDRA_SBS1# <7> DDRA_SRAS# <7>
DDRA_SCS0# <7>
DDRA_ODT1 <7>
+VREF_CA
1
C89
C89
2
1000P_0402_50V7K
1000P_0402_50V7K
DDRA_SDQS5# <7> DDRA_SDQS5 <7>
DDRA_SDQS7# <7> DDRA_SDQS7 <7>
SB_SMDAT0 <11,19,26> SB_SMCLK0 <11,19,26>
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DDRA_SDQ[0..63] <7>
DDRA_SDM[0..7] <7>
DDRA_SMA[0..15] <7>
1
C10
C10
2
1000P_0402_50V7K
1000P_0402_50V7K
2
C88
C88
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C664
C664
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.5V
R48
R48 1K_0402_1%
1K_0402_1%
1 2
R49
R49 1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C644
C644
1
C961
C961
C691
C691
0.01U_0402_16V7K
0.01U_0402_16V7K
2
C640
C640
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C692
C692
1
D
+VREF_DQ
+VREF_DQ
2
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V +0.75VS
@
@
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
C84
C84 @
@
1
0.01U_0402_25V7K
0.01U_0402_25V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C87
C87
1
+0.75VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C665
C665
1
C690
C690
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
C85
C85
2
C643
C643
1
2
1
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
2
1
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C645
C645
1
C693
C693
+1.5V+VREF_CA
R310
R310 1K_0402_1%
1K_0402_1%
C680
C680
2
C642
C642
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
R315
R315 1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C647
C647
1
+VREF_CA
0.01U_0402_25V7K
0.01U_0402_25V7K
2
C235
C235 @
@
1
2
C641
C641
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C351
C351
2
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C646
C646
1
Place near DIMM1
2
1
0.01U_0402_16V7K
0.01U_0402_16V7K
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII SO-DIMM 1
DDRIII SO-DIMM 1
DDRIII SO-DIMM 1
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
B
B
10 45Thursday, July 22, 2010
10 45Thursday, July 22, 2010
10 45Thursday, July 22, 2010
B
A
B
C
D
E
DQ4 DQ5
VSS3 DQS0
VSS6
DQ6
DQ7 VSS8 DQ12 DQ13
DM1
DQ14 DQ15
DQ20 DQ21
DM2 DQ22
DQ23 DQ28
DQ29
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
CK1 CK1#
BA1 RAS#
ODT0 ODT1
NC2
DQ36 DQ37
DM4 DQ38
DQ39 DQ44
DQ45
DQS5 DQ46
DQ47 DQ52
DQ53
DM6 DQ54
DQ55 DQ60
DQ61
DQS7 DQ62
DQ63
SDA
SCL VTT2
+1.5V+1.5V
2
DDRB_SDQ4
4
DDRB_SDQ5
6 8
DDRB_SDQS0#
10
DDRB_SDQS0
12 14
DDRB_SDQ6
16
DDRB_SDQ7
18 20
DDRB_SDQ12
22
DDRB_SDQ13
24 26
DDRB_SDM1
28
MEM_MB_RST#
30 32
DDRB_SDQ14
34
DDRB_SDQ15
36 38
DDRB_SDQ20
40
DDRB_SDQ21
42 44
DDRB_SDM2
46 48
DDRB_SDQ22
50
DDRB_SDQ23
52 54
DDRB_SDQ28
56
DDRB_SDQ29
58 60
DDRB_SDQS3#
62
DDRB_SDQS3
64 66
DDRB_SDQ30
68
DDRB_SDQ31
70 72
DDRB_CKE1
74 76
DDRB_SMA15
78
A15 A14
A11
A7 A6
A4 A2
A0
S0#
G2
B
DDRB_SMA14
80 82
DDRB_SMA11
84
DDRB_SMA7
86 88
DDRB_SMA6
90
DDRB_SMA4
92 94
DDRB_SMA2
96
DDRB_SMA0
98 100
DDRB_CLK1
102
DDRB_CLK1#
104 106
DDRB_SBS1#
108
DDRB_SRAS#
110 112
DDRB_SCS0#
114
DDRB_ODT0DDRB_SCAS#
116 118
DDRB_ODT1
120 122 124 126 128
DDRB_SDQ36
130
DDRB_SDQ37
132 134
DDRB_SDM4
136 138
DDRB_SDQ38
140
DDRB_SDQ39
142 144
DDRB_SDQ44
146
DDRB_SDQ45
148 150
DDRB_SDQS5#
152
DDRB_SDQS5
154 156
DDRB_SDQ46
158
DDRB_SDQ47
160 162
DDRB_SDQ52
164
DDRB_SDQ53
166 168
DDRB_SDM6
170 172
DDRB_SDQ54
174
DDRB_SDQ55
176 178
DDRB_SDQ60
180
DDRB_SDQ61
182 184
DDRB_SDQS7#
186
DDRB_SDQS7
188 190
DDRB_SDQ62
192
DDRB_SDQ63
194 196 198 200 202 204
206
T10PAD T10PAD
+0.75VS
DDRB_SDQS0# <7> DDRB_SDQS0 <7>
MEM_MB_RST# <7>
DDRB_SDQS3# <7> DDRB_SDQS3 <7>
DDRB_CKE1 <7>
DDRB_CLK1 <7> DDRB_CLK1# <7>
DDRB_SBS1# <7> DDRB_SRAS# <7>
DDRB_SCS0# <7> DDRB_ODT0 <7>
DDRB_ODT1 <7>
+VREF_CA
1
C94
C94
2
1000P_0402_50V7K
1000P_0402_50V7K
DDRB_SDQS5# <7> DDRB_SDQS5 <7>
DDRB_SDQS7# <7> DDRB_SDQS7 <7>
SB_SMDAT0 <10,19,26> SB_SMCLK0 <10,19,26>
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
+VREF_DQ
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.5V
2
C677
C677
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.75VS
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
+VREF_DQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
C92
C92
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C670
C670
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C676
C676
1
Deciphered Date
Deciphered Date
Deciphered Date
DDRB_SDQ[0..63] <7>
DDRB_SDM[0..7] <7>
DDRB_SMA[0..15] <7>
1
C682
C682
C93
C93
2
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C666
C666
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C675
C675
C925
C925
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D
2
1
+VREF_CA
C671
C671
1
C352
C352
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
1
+
+
2
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
1
C353
C353
C683
C683
2
2
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C667
C667
C86
C86
330U_X_2VM_R6M@
330U_X_2VM_R6M@
2
C672
C672
1
2
C668
C668
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C673
C673
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Place near DIMM2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII SO-DIMM 2
DDRIII SO-DIMM 2
DDRIII SO-DIMM 2
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
2
C669
C669
1
E
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C674
C674
1
B
B
11 45Thursday, July 22, 2010
11 45Thursday, July 22, 2010
11 45Thursday, July 22, 2010
B
+VREF_DQ
DDRB_SDQ0
+3VS
DDRB_SDQ1 DDRB_SDM0 DDRB_SDQ2
DDRB_SDQ3 DDRB_SDQ8
DDRB_SDQ9 DDRB_SDQS1#
DDRB_SDQS1 DDRB_SDQ10
DDRB_SDQ11 DDRB_SDQ16
DDRB_SDQ17 DDRB_SDQS2#
DDRB_SDQS2 DDRB_SDQ18
DDRB_SDQ19 DDRB_SDQ24
DDRB_SDQ25 DDRB_SDM3 DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2# DDRB_SMA12
DDRB_SMA9 DDRB_SMA8
DDRB_SMA5 DDRB_SMA3
DDRB_SMA1 DDRB_CLK0
DDRB_CLK0# DDRB_SMA10
DDRB_SBS0# DDRB_SWE#
DDRB_SMA13 DDRB_SCS1#
DDRB_SDQ32 DDRB_SDQ33
DDRB_SDQS4# DDRB_SDQS4
DDRB_SDQ34 DDRB_SDQ35
DDRB_SDQ40 DDRB_SDQ41
DDRB_SDM5 DDRB_SDQ42
DDRB_SDQ43 DDRB_SDQ48
DDRB_SDQ49 DDRB_SDQS6#
DDRB_SDQS6 DDRB_SDQ50
DDRB_SDQ51 DDRB_SDQ56
DDRB_SDQ57 DDRB_SDM7 DDRB_SDQ58
DDRB_SDQ59
R52 10K_0402_5%R52 10K_0402_5%
1 2
12
R53
R53 10K_0402_5%
10K_0402_5%
1 1
DDRB_SDQS1#<7> DDRB_SDQS1<7>
DDRB_SDQS2#<7> DDRB_SDQS2<7>
DDRB_CKE0<7>
2 2
3 3
4 4
DDRB_SBS2#<7>
DDRB_CLK0<7> DDRB_CLK0#<7>
DDRB_SBS0#<7>
DDRB_SWE#<7>
DDRB_SCAS#<7>
DDRB_SCS1#<7>
DDRB_SDQS4#<7> DDRB_SDQS4<7>
DDRB_SDQS6#<7> DDRB_SDQS6<7>
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-U4SN-7F
FOX_AS0A626-U4SN-7F CONN@
CONN@
DQS#0
VSS10
VSS17
VSS19
VSS21
VDD10
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30 VSS31
VSS33
VSS35 DQS#5
VSS38
VSS40
VSS42 VSS43
VSS45
VSS47 DQS#7
VSS50
VSS52
EVENT#
DIMM_B STD H:4mm
<Address: 01>
A
A
B
C
D
E
1 1
PCIE_PTX_C_IRX_P0<24> PCIE_PTX_C_IRX_N0<24> PCIE_PTX_C_IRX_P1<26>
2 2
PCIE_PTX_C_IRX_N1<26>
SB_RX0P<18> SB_RX0N<18> SB_RX1P<18> SB_RX1N<18> SB_RX2P<18> SB_RX2N<18> SB_RX3P<18> SB_RX3N<18>
3 3
4 4
U3B
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780M_FCBGA528
RS780M_FCBGA528
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
RS880 A11(SA000032710)
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
PCIE_ITX_PRX_P0
AC1
PCIE_ITX_PRX_N0
AC2
PCIE_ITX_PRX_P1
AB4
PCIE_ITX_PRX_N1
AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5 AC8
AB8
GMCH_HDMI_TXD2+ <16> GMCH_HDMI_TXD2- <16> GMCH_HDMI_TXD1+ <16> GMCH_HDMI_TXD1- <16> GMCH_HDMI_TXD0+ <16> GMCH_HDMI_TXD0- <16> GMCH_HDMI_TXC+ <16> GMCH_HDMI_TXC- <16>
C127 0.1U_0402_16V7KC127 0.1U_0402_16V7K
1 2
C128 0.1U_0402_16V7KC128 0.1U_0402_16V7K
1 2
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
1 2
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2 1 2
1 2
R59 1.27K_0402_1%R59 1.27K_0402_1% R58 2K_0402_1%R58 2K_0402_1%
+1.1VS
PCIE_ITX_C_PRX_P0 <24> PCIE_ITX_C_PRX_N0 <24> PCIE_ITX_C_PRX_P1 <26> PCIE_ITX_C_PRX_N1 <26>
SB_TX0P <18> SB_TX0N <18> SB_TX1P <18> SB_TX1N <18> SB_TX2P <18> SB_TX2N <18> SB_TX3P <18> SB_TX3N <18>
GLAN WLAN
H_CADOP[0..15]<6> H_CADON[0..15]<6> H_CADIN[0..15] <6>
H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CLKOP0<6>
H_CLKON0<6>
H_CLKOP1<6>
H_CLKON1<6>
H_CTLOP0<6> H_CTLON0<6>
H_CTLON1<6>
301_0402_1%~D
301_0402_1%~D
0718 Place within 1" layout 1:2
R60
R60
1 2
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
HT_RXCALP HT_RXCALN
H_CADON[0..15]
U3A
U3A
Y25
HT_RXCAD0P
Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
AC24 AC25 AB25 AB24 AA24 AA25
Y22
Y23 W21 W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23 AA22
M22 M23
R21
R20
C23
A24
RS780M_FCBGA528
RS780M_FCBGA528
HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
PART 1 OF 6
PART 1 OF 6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
RS880 A11(SA000032710)
H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP HT_TXCALN
H_CADIP[0..15] <6>
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18 H24
H25 L21 L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
HT_TXCALP
B24
HT_TXCALN
B25
0718 Place within 1" layout 1:2
H_CLKIP0 <6> H_CLKIN0 <6> H_CLKIP1 <6> H_CLKIN1 <6>
H_CTLIP0 <6>
H_CTLIN0 <6>
H_CTLIP1 <6>H_CTLOP1<6>
H_CTLIN1 <6>
R61
R61
1 2
301_0402_1%~D
301_0402_1%~D
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
RS880-HT/PCIE
RS880-HT/PCIE
RS880-HT/PCIE
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
E
of
12 45Thursday, July 22, 2010
12 45Thursday, July 22, 2010
12 45Thursday, July 22, 2010
B
B
B
A
B
C
D
E
+1.8VS+1.8VS +1.8VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R417
+1.1VS
L2
L2
1 2
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
2.2U_0603_6.3V4Z
1 1
2.2U_0603_6.3V4Z
L5
L5
1 2
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.8VS
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
2 2
3 3
+1.8VS
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
+3VS
L7
L7
1 2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
L9
L9
1 2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
R77 4.7K_0402_5%R77 4.7K_0402_5%
1 2
R78 4.7K_0402_5%R78 4.7K_0402_5%
1 2
R79 4.7K_0402_5%
R79 4.7K_0402_5%
1 2
@
@
R80 4.7K_0402_5%
R80 4.7K_0402_5%
1 2
@
@
C141
C141
C146
C146
C150
C150
C154
C154
+NB_PLLVDD
1
1
C142
C142 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
+NB_HTPVDD+1.8VS
1
1
C147
C147 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
+VDDA18HTPLL
1
1
C151
C151 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
+VDDA18PCIEPLL
1
1
C155
C155 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA
+3VS
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
+1.8VS
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
+1.8VS
L6
L6
1 2
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
NB_PWRGD<19>
+1.8VS
12
R68 300_0402_5%R68 300_0402_5%
POWER_SEL<39>
RS880
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
L3
L3
1 2
L4
L4
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+AVDDQ
1
C148
C148
2
GMCH_CRT_R<17> GMCH_CRT_G<17> GMCH_CRT_B<17>
GMCH_CRT_HSYNC<14,17> GMCH_CRT_VSYNC<14,17>
GMCH_CRT_CLK<17>
GMCH_CRT_DATA<17>
1 2
R67 0_0402_5%R67 0_0402_5%
CLK_NBHT<18> CLK_NBHT#<18>
NB_DISP_CLKP<18> NB_DISP_CLKN<18>
CLK_SBLINK_BCLK<18> CLK_SBLINK_BCLK#<18>
GMCH_LCD_CLK<15> GMCH_LCD_DATA<15> GMCH_HDMI_DATA<16>
GMCH_HDMI_CLK<16>
POWER_SEL
C696
C696
1
@
@
2
1
C145
C145
2
1
C149
C149 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
R65 715_0402_1%R65 715_0402_1% +NB_PLLVDD
+NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
A_RST#<14,18,28>
R106
R106
1 2
R83
R83
1 2
R82 2K_0402_5%R82 2K_0402_5%
C679
C679
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+AVDDDI
4mA
GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B
GMCH_CRT_HSYNC GMCH_CRT_VSYNC
1 2
NB_ALLOW_LDTSTOP
4.7K_0402_5%
4.7K_0402_5% CLK_NBGFX CLK_NBGFX#
4.7K_0402_5%
4.7K_0402_5%
GMCH_LCD_CLK GMCH_LCD_DATA GMCH_HDMI_DATA GMCH_HDMI_CLK
1 2
POWER_SEL
1 2
R85 150_0402_1%R85 150_0402_1%
C144
C144
C143
C143
1
1
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
20mA
GMCH_CRT_CLK GMCH_CRT_DATA
DAC_RSET
+NB_PLLVDD +NB_HTPVDD
20mA 120mA
NB_PWRGD_R
NB_LDTSTOP#
close NB
+AVDD1
125mA
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
65mA
A12
PLLVDD(NC)
D14
20mA
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M_FCBGA528
RS780M_FCBGA528
RS880 A11(SA000032710)
LDT_STOP#<8,18>
R417
300_0402_5%
300_0402_5%
PART 3 OF 6
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
1 2
C684
@
@
LVDS_DIGON(PCE_TCALRP)
LVDS_ENA_BL(PWM_GPIO2)
C684
2
1 2
TXOUT_L2N(DBG_GPIO0) TXOUT_L3N(DBG_GPIO2)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
LVDS_BLON(PCE_RCALRP)
SUS_STAT#(PWM_GPIO5)
B
1
A
1 2
R64 0_0402_5%@R64 0_0402_5%@
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L3P(NC)
TXOUT_U0P(NC) TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
5
P
Y
G
U8
U8
3
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
A13 B13
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
D9 D10
D12 AE8
AD8 D13
4
15mA 300mA
R73
R73
R63
R63
2.2K_0402_5%
2.2K_0402_5%
1 2
+VDDLTP18
+VDDLT18
VARY_ENBKL
12
12
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5% R74
R74
@
@
1 2
R81 0_0402_5%
R81 0_0402_5%
1 2
R84
R84
1.8K_0402_5%
1.8K_0402_5%
NB_LDTSTOP#
AMD suggest
12
4.7K_0402_5%
4.7K_0402_5%
R75
R75
SB_PWRGD<8,19,28>
TXOUT0+ <15> TXOUT0- <15> TXOUT1+ <15> TXOUT1- <15> TXOUT2+ <15> TXOUT2- <15>
1U_0402_6.3V4Z
TXCLK+ <15> TXCLK- <15>
R71 0_0402_5%UNVB@R71 0_0402_5%UNVB@
1 2
R72 0_0402_5%VB@R72 0_0402_5%VB@
1 2
R76 0_0402_5%VB@R76 0_0402_5%VB@
1 2
If support VB, pop VB@ and reserve R71
GMCH_HDMI_DET <16>
SUS_STAT# <19> SUS_STAT_R# <14>
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
To SB Strap pin
NB_PWRGD
+VDDLTP18
C152
C152
+VDDLT18
C156
C156
2 1
1
1
C153
C153
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
2
1
1
C157
C157
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2
GMCH_ENVDD <15> ENBKL <28> GMCH_INVT_PWM <15>
+1.8VS
U4
U4
5
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
P
B
NB_PWRGD_R
4
Y
A
G
@
@
3
L8
L8
1 2
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
L10
L10
1 2
BLM18AG601SN1D_2P
BLM18AG601SN1D_2P
+1.8VS
+1.8VS
HIGH 0.95V
1.1VLOW
4 4
ALLOW_LDTSTOP<18>
R90
R90
1K_0402_5%
1K_0402_5%
A
+1.8VS
12
R91 0_0402_5%R91 0_0402_5%
1 2
NB_ALLOW_LDTSTOP
B
1 2
R87 140_0402_1%R87 140_0402_1%
1 2
R88 150_0402_1%R88 150_0402_1%
1 2
R89 150_0402_1%R89 150_0402_1%
GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
RS880 VEDIO/CLK GEN
RS880 VEDIO/CLK GEN
RS880 VEDIO/CLK GEN
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
13 45Thursday, July 22, 2010
13 45Thursday, July 22, 2010
13 45Thursday, July 22, 2010
E
B
B
B
A
0.1U_0402_16V4Z
12
C165
C165
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
1
C164
C164
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C174
C174
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
C179
C179
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
1
C166
C166
2
1
C169
C169
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C175
C175
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C192
C192
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
L11
L13
L13
12
10U_0805_10V4Z
10U_0805_10V4Z
L15
L15
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
L11
C261
C261
@
@
12
C181
C181
1.3A
+1.1VS
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1 1
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
L14
+1.1VS
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
2 2
L14
+1.8VS
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1
1
C159
C159
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C170
C170
C161
C161
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C176
C176
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C185
C185
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS
C197
C197
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C167
C167
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C201
C201
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C177
C177
C178
C178
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C190
C190
C186
C186
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C200
C200
+VDDHTRX
+VDDHT
1
2
1
2
+VDDHTTX
1
C202
C202
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDA18PCIE
1
2
B
600mA
U3E
U3E
J17
VDDHT_1
K16 L16
M16
P16
R16
T16
700mA
H18 G19
F20 E21
D22
B23 A23
680mA
AE25 AD24 AC23
1
AB22 AA21
700mA
10mA
5mA
AE11 AD11
W19 U17 R17 M17
M10
R10 AA9
AB9 AD9 AE9 U10
Y20 V18 T17 P17
J10 P10 K10
L10 W9
H9
T10
Y9
F9
G9
2
PART 5/6
PART 5/6
VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
RS780M_FCBGA528
RS780M_FCBGA528
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12
POWER
POWER
VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
RS880 A11(SA000032710)
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11 H12
C
2.5A
23mA
60mA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDA11PCIE
10A
1
C1910.1U_0402_16V4Z C1910.1U_0402_16V4Z
2
C198
C198
L12
L12
1 2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C160 10U_0805_10V4ZC160 10U_0805_10V4Z
1 2
C162 10U_0805_10V4ZC162 10U_0805_10V4Z
1 2
C163 4.7U_0805_10V4ZC163 4.7U_0805_10V4Z
1 2
C168 1U_0402_6.3V4ZC168 1U_0402_6.3V4Z
1 2
C171 1U_0402_6.3V4ZC171 1U_0402_6.3V4Z
1 2 1 2
C172 0.1U_0402_16V4ZC172 0.1U_0402_16V4Z
1 2
C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z
1
1
C1940.1U_0402_16V4Z C1940.1U_0402_16V4Z
C1930.1U_0402_16V4Z C1930.1U_0402_16V4Z
2
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
1
C1880.1U_0402_16V4Z C1880.1U_0402_16V4Z
C1800.1U_0402_16V4Z C1800.1U_0402_16V4Z
2
2
1
1
C1820.1U_0402_16V4Z C1820.1U_0402_16V4Z
C1870.1U_0402_16V4Z C1870.1U_0402_16V4Z
2
2
1
C199
C199
2
D
U3F
U3F
A25
VSSAHT1
D23
W22 W24 W25
AD25
W11
W15 AC12 AA14
AB11 AB15 AB17 AB19 AE20 AB21
E22 G22 G24 G25 H19
J22
L17
L22
L24
L25 M20 N22
P20 R19 R22 R24 R25 H20 U22
V19
Y21
L12 M14 N13
P12
P15 R11 R14
T12 U14 U11 U15
V12
Y18
K11
+1.1VS
+NB_CORE
C189 220U_C6_6.3V_M_R15+C189 220U_C6_6.3V_M_R15
1
1
1
1
1
C19610U_0805_10V4Z C19610U_0805_10V4Z
C18410U_0805_10V4Z C18410U_0805_10V4Z
C1830.1U_0402_16V4Z C1830.1U_0402_16V4Z
C1950.1U_0402_16V4Z C1950.1U_0402_16V4Z
2
2
+3VS
+
2
2
2
PART 6/6
PART 6/6
VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
RS780M_FCBGA528
RS780M_FCBGA528
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
E
RS880 A11(SA000032710)
U3D
3 3
Side port and Strap setting
Debug Mode
GMCH_CRT_VSYNC<13,17>
Load EEPROM Strap
SUS_STAT_R#<13>
4 4
Enable Side Port Memory
GMCH_CRT_HSYNC<13,17>
D1
@D1
@
CH751H-40_SC76
CH751H-40_SC76
2 1
R264 3K_0402_5%@R264 3K_0402_5%@
12
R94 3K_0402_5%R94 3K_0402_5% R95 3K_0402_5%
R95 3K_0402_5%
12
R92 3K_0402_5%R92 3K_0402_5%
12
R93 3K_0402_5%@R93 3K_0402_5%@
A_RST# <13,18,28>
12
@
@
12
+3VS
+3VS
A
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO. (VSYNC) 1 : Disable 0 : Enable
DFT_GPIO1: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
Enable Side Port Memory
RS880: HSYNC# 0: Enable 1 : Disable
B
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/04/12 2010/10/12
2010/04/12 2010/10/12
2010/04/12 2010/10/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
U3D
PAR 4 OF 6
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
AB12 AE16
V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
Y14 AD16
AE17 AD17
W12
Y12 AD18 AB13 AB18
V14
V15
W14
AE12 AD12
RS780M_FCBGA528
RS780M_FCBGA528
RS880 A11(SA000032710)
AA18 AA20 AA19
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)
MEM_DQ12(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RS880 PWR/GND
RS880 PWR/GND
RS880 PWR/GND
Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23 AE24
AD23 AE18
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
PEW/76/86/96 LA-6552P
15mA 26mA
E
+1.8VS
+1.1VS
14 45Thursday, July 22, 2010
14 45Thursday, July 22, 2010
14 45Thursday, July 22, 2010
B
B
B
of
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