Page 1
A
B
C
D
E
http://hobi-elektronika.net
1 1
2 2
Compal Confidential
HCW50 Schematics Document
AMD/Sempron/ATI RX485/SB460 W/s M52/54/56P
2006 / 02 / 28
3 3
4 4
Rev:0.3 (For PVT)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/05/09 2006/03/08
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M /B LA-3151P
401412
星期四
09, 2006
三月
E
B
of
155,
Page 2
5
4
3
2
1
Compal confidential
http://hobi-elektronika.net
Project Code: HCW50
File Name : LA-3151P
D D
DVI-D Conn.
page 30
Thermal Sensor
ADM1032ARM
page 7 page 15
LCD CONN
page 29
CRT & TV-OUT
Clock Generator
ICS951462
page 28
AMD Turion/Sempron CPU
Socket S1 638P
H_A#(3..31)
page 5,6,7,8
ATI-RX485M
DDRII DDRII-SO-DIMM X2
page 9,10
Dual Channel DDR-II
H_D#(0..63)
HT 16x16 800MHZ
465 BGA
page 11,12,13,14
A-Link Express
PCI-Express
ATI M52PG/M54P/M56P
with 64/128/256MB VRAM
C C
page 16,17,18,19,20,21
ATI-SB460
PCI BUS
Mini PCI Socket
Mini card / CAM RTL8110SCL
B B
page 36
Realtek
RTL8100CL
page 31
RJ45 CONN
page 32
ENE Controller
CB714
page 37
Slot 0
page 38
6in1 CardReader
Slot
1394 Controller
page 38
VT6311S
page 40
1394
Conn.
page 40
LPC BUS
549 BGA
page 22,23,24,25,26
2 x PCIE
PATA
USB 2.0
USB 2.0
AC-LINK
SATA
One Channel
USB conn x 2 / New card
BT Conn
Audio CKT
ALC883
MDC Conn.
page 39
page 34
AMP & Audio Jack
page 44
page 34
SATA HDD Conn.
page 27
HDD Conn.
CDROM Conn.
page 27
page 45
Power On/Off C KT / LID switch / Power OK CKT
page 42
DC/DC Interface CKT.
page 46
CIR/LED
page 43
RTC CKT.
page 22
SMsC LPC47N207
page 41
ENE KB910
page 33
Power Circuit DC/DC
page 46~
A A
5
4
FIR module
page 41
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Touch Pad
CONN.
2005/03/08 2006/03/08
page 34
Compal Secret Data
Deciphered Date
Int. KBD
page 34
BIOS
page 35
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
月
255,
1
of
B
Page 3
5
4
3
2
1
http://hobi-elektronika.net
Voltage Rails
Power Plane Description
D D
C C
VIN
B+
+CPU_CORE
+0.9V 0.9V switched power rail for DDRII terminator
+1.2V_HT
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON*
+RT CVCC RTC power
+1.2VS 1.2V switched power rail for PCIE ON O FF OFF
+0.9VS 0.9V switched power rail for VRAM terminator O N OFF OFF
+1.8VALW 1.8V switched power rail O N ON ON*
+V DD_COR E 1.0~1.2V switched power rail for VGA ON OFF OFF
Note : ON* means that this power plane is ON only with AC power avail able, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail
1.5V switched power rail
1.8V power rail for DDRII
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
CardBus(SD)
1394
LAN(10/100)
Mini-PCI(WLAN/TV-Tuner)
AD20
AD16 0
AD17
AD18
2
3
1
S0 S3 S5
N/A N/A N/A
ON OFF
ON ON
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON
ON
ON
ON
PIRQE/PIRQH
PIRQE
PIRQF
PIRQG/PORQH
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON ON*
OFF
OFF
ON*
ON
OFF
OFFON
ON*ON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
B B
EC SM Bus1 address
Device
Smart Battery
EEPROM(24C16/02)
GMT G781-1
Address Address
1010 000X b
1001 101X b
EC SM Bus2 address
Device
Fintek F75383M
1001 100X b0001 011X b
SKU ID Table
SKU ID
0
1
2
3
4
5
SB460 SM Bus address
Device
Clock Generator
A A
(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0
DDR DIMM2
Address
1101 001Xb
1001 000Xb
1001 010Xb
6
7
SIGNAL
SLP_S1# SLP_S3#
HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW LOW
SLP_S4# SLP_S5# +VA LW +V +VS Clock
HIGH
LOW
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
PCB Revision
0.1
SKU
PM
GM
LOWLOWLOW
ON
HIGH
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
V
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
BTO Option Table
BTO Item BOM Structure
VGA
UMA
UMA's DVI
LAN(10/100)
LAN(GIGA)
MINI CARD1
MINI CARD2
SATA-to-IDE
PATA
GRAPEVINE
G72MV Only
G73 Only
VRAM
VRAM 64M
VRAM 128M
VRAM 256M
MEDIA/B
CIR
FIR
GENEVA
LCM
Sub-woofer
ON ON
ON
OFF
OFF
OFF
max
0.538 V
0.875 V
2.341 V
3.300 V
LOW
OFF
OFF
OFF
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
2
月
355,
1
B
of
Page 4
5
+3.3VALW_NTB
+3.3VSUS_NTB
+VDC
BATTERY
BATTERY
D D
CPU
CHARGER
PWR
12V
12V
5VSB
5V
+/-5%
+/-5%
+/-5%
+/-5%
SWITCH
ATX POWER SUPPLY
C C
3.3V
+/-5%
MAIN PWR SW
REGULATOR
+3.3VALW LDO
REGULATOR
SW
+5VSUS
+5VALW_NTB
+5VSUS_NTB
+VIN_MEM
SW
SW
4
+5VALW_ATX
+5VDUAL_ATX
+5V_ATX
+3.3VALW_ATX
+3.3VDUAL_ATX
+3.3V_ATX
+3.3V_NTB
+5V_NTB
SWITCH
3
http://hobi-elektronika.net
+3.3VALW
+3.3VSUS
+3.3V
POWER SWITCH
+5VALW
+5V
+VIN
+5V
+VIN
+5V
+VIN
+5V
+VIN
+5V
+5V
+3.3V
1.5V SW
REGULATOR
SW REGULATOR
VLDT 1.2V SW
REGULATOR
NB CORE SW
REGULATOR
PCIE&SB SW
REGULATOR
1.8V SW
REGULATOR
+5VSUS
+5V
+VIN
+5VSUS
1.8V VDD&VTT
SW REGULATOR
2
CPU_VDDA_RUN (S0, S1)
CPU_VDD_RUN (S0, S1)
VLDT_RUN (S0, S1)
VCC_NB (S0, S1)
VDDA_1V2(S0, S1)
+1.8V(S0, S1)
AVDD (S0, S1)
CPU_VDDIO_SUS (S0, S1, S3)
CPU_VTT_SUS (S0, S1,S3)
AMD CPU
VCCA 2.5V
VDDCORE
0.375-1.500V 30A
VLDT 1.2V 3A
DDRII SODIMMX2
VDD MEM 4A
VTT_MEM 0.5A
1
NB RS485
HT VLDT 1.2V 1A
NB CORE 10A
PCI-E CORE
&PCI-E IO 3.5A
HTPLL (1.8V) 200mA
PLL & DAC-Q(1.8V)
200mA
TRANSFORMER
400mA
DAC 300mA
SB SB600
VCC_SB (S0, S1)
X4 PCI-E 0.8A
ATA I/O 0.2A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
1.2V S5 PW 0.22A
3.3V I/O 0.45A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
-12V
+/-5%
CONTROL SIGNAL:
MOBILE: BATTERY
DESKTOP: ATX
+3.3VALW
+3.3V
+3.3VALW
1.2V LDO
REGULATOR
+1.2VALW
+5V
+3.3V
B B
+5V
+3.3VALW
MINI PCI SLOT
3.3V(S0, S1)1.5A
5V (S0, S1) 0.1A
3.3V(S3, S5) 0.2A
+VIN
+3.3V
+5V
PCI Slot (per slot)
5V
3.3V
12V
3.3Vaux
-12V
A A
5
5.0A
7.6A
0.5A
0.375A
0.1A
3.3V
12V
3.3Vaux
0.5A
0.1A
4
X16 PCIEX1 PCIE per
3.3V
12V
3.0A3.0A
5.5A
CNR CONNECTOR
5V
3.3V
12V
3.3Vaux
-12V
5VDual
1.0A
1.0A
0.5A
1.0A
0.1A
0.5A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+5VALW
USB X7 FR
VDD
5VDual
3.5A
2005/03/08 2006/03/08
3
VDD
5VDual
1.0A
Compal Secret Data
Deciphered Date
2XPS/2USB X2 RL
5VDual
1.0A
2
GBIT ENTHENET
3.3V 0.5A
(S0, S1, S3, S4, S5)
PCI-E CARD
1.5V (S0, S1) 0.7A
3.3V (S3, S5) 0.3A
3.3V (S0, S1) 1.3A
SUPER I/O
+3.3VDUAL (S3) 0.01A
+3.3V (S0, S1) 0.01A
+5V (S0, S1) 0.1A
HD CODEC
3.3V CORE 0.3A
5V ANALOG 0.1A
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
月
455,
1
of
B
Page 5
5
HTT Interface
4
3
2
1
H_CADIP[0..15]<11>
H_CADIP[0..15]
H_CADIN[0..15]
http://hobi-elektronika.net
H_CADOP[0..15]
H_CADON[0..15]
H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>
PROCESSOR HYPERTRANSPORT INTERFACE
D D
C C
H_CLKIP1<11>
H_CLKIN1<11>
1 2
1 2
H_CLKIP0<11>
H_CLKIN0<11>
H_CTLIP0<11>
H_CTLIN0<11>
+1.2V_HT
R2 51_0402_1%
R3 51_0402_1%
B B
VLDT_A x AND VLDT_Bx ARE C ONN EC T E D TO THE LDT _RUN POWER
SUPPLY THRO UGH T HE PA CKA GE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOA RD T O DEC OUPLING NEA R THE CPU PACKA GE
H_CADIP15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
H_CTLIP1
H_CTLIN1
H_CTLIP0
H_CTLIN0
+1.2V_HT
D4
D3
D2
D1
N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2
J5
K5
J3
J2
P3
P4
N1
P1
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
JP72A
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Athlon 64 S1
Processor Socket
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
AE5
AE4
AE3
AE2
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
Y4
Y3
Y1
W1
T5
R5
R2
R3
1 2
H_CADOP15
H_CADON15H_CADIN15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0
H_CTLON0
C1
4.7U_0805_10V4Z
H_CLKOP1 <11>
H_CLKON1 <11>
H_CLKOP0 <11>
H_CLKON0 <11>
H_CTLOP0 <11>
H_CTLON0 <11>
FAN1 Conn
+5VS
+VCC_FAN1
EN_DFAN1<33>
EN_DFAN1
C2 10U_0805_10V4Z
U2
1
VEN
2
VIN
3
VO
4
VSET
G993P1UF_SOP8
FAN_SPEED1<33>
1 2
GND
GND
GND
GND
8
7
6
5
+3VS
12
R1
10K_0402_5%
1
C5
1000P_0402_50V7K
2
40mil
+VCC_FAN1
+5VS
12
D1
1SS355_SOD323
1N4148_SOT23
1 2
10U_0805_10V4Z
1000P_0402_50V7K
D2
C3
1 2
C4
1 2
ACES_85205-03001
JP73
1
2
3
+1.2V_HT
1
C6
10U_0805_10V4Z
2
A A
5
1
C8
2
0.22U_0603_10V7K
LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
1
C9
2
180P_0402_50V8J
0.22U_0603_10V7K
C10
1
2
1
C11
180P_0402_50V8J
2
4
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/11 2006/10/11
Compal Secret Data
Deciphered Date
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
月
555,
1
of
B
Page 6
A
DDRII Data
DDRII Cmd/Ctrl//Clk
B
C
D
E
http://hobi-elektronika.net
DDR_B_D[0..63]<10>
DDR_B_MA[0..15] <10>
Processor DDR2 Memory Interface
DDR_B_D63
AD11
DDR_B_D62
AF11
DDR_B_D61
AF14
DDR_B_D60
AE14
To reverse SODIMM socket
DDR_B_DM[0..7]<10>
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
AD12
AC16
AE22
AB26
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
Y11
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
E25
A22
B16
A12
F26
E26
A24
A23
D16
C16
C12
B12
JP72C
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
DDR: DATA
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D[0..63] <9>
DDR_A_DM[0..7] <9>
To normal SODIMM socket
DDR_A_DQS[0..7]<9>
DDR_A_DQS#[0..7]<9>
+0.9V
1
C13
1.5P_0402_50V8C
2
1
C15
1.5P_0402_50V8C
2
DDR_A_MA[0..15]
DDR_B_DQS#[0..7]
DDR_A_CLK2 <9>
DDR_A_CLK#2 <9>
DDR_A_CLK1 <9>
DDR_A_CLK#1 <9>
DDR_B_CLK2 <10>
DDR_B_CLK#2 <10>
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>
DDR_B_ODT1 <10>
DDR_B_ODT0 <10>
DDR_A_ODT1 <9>
DDR_A_ODT0 <9>
DDR_B_BS#2 <10>
DDR_B_BS#1 <10>
DDR_B_BS#0 <10>
DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>
DDR_A_MA[0..15]<9>
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE P A CKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
4 4
3 3
2 2
+1.8V
12
R4
39.2_0402_1%~D
R5
12
39.2_0402_1%~D
PLACE THEM CLOSE TO
CPU WITHIN 1"
DDR_CS3_DIMMA#<9>
DDR_CS2_DIMMA#<9>
DDR_CS1_DIMMA#<9>
DDR_CS0_DIMMA#<9>
DDR_CS3_DIMMB#<10>
DDR_CS2_DIMMB#<10>
DDR_CS1_DIMMB#<10>
DDR_CS0_DIMMB#<10>
DDR_CKE1_DIMMB<10>
DDR_CKE0_DIMMB<10>
DDR_CKE1_DIMMA<9>
DDR_CKE0_DIMMA<9>
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
PLACE CLOSE TO P RO CESSOR
WITHIN 1.5 INCH
+0.9VREF_CPU
M_ZN
M_ZP
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
1
C12
1.5P_0402_50V8C
2
1
C14
1.5P_0402_50V8C
2
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_BS#2<9>
DDR_A_BS#1<9>
DDR_A_BS#0<9>
DDR_A_RAS#<9>
DDR_A_CAS#<9>
DDR_A_WE#<9>
AE10
AF10
W17
Y10
V19
J22
V22
T19
Y26
J24
W24
U23
H26
J23
J20
J21
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
K22
R20
T22
T20
U20
U21
JP72B
M_VREF
VTT_SENSE
M_ZN
M_ZP
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_RAS_L
MA_CAS_L
MA_WE_L
Athlon 64 S1
Processor
Socket
DDR_B_DQS[0..7]<10>
DDR_B_DQS#[0..7]<10>
D10
VTT1
C10
VTT2
B10
VTT3
AD10
VTT4
W10
VTT5
AC10
VTT6
AB10
VTT7
AA10
VTT8
A10
VTT9
Y16
MA0_CLK_H2
AA16
MA0_CLK_L2
E16
MA0_CLK_H1
F16
MA0_CLK_L1
AF18
MB0_CLK_H2
AF17
MB0_CLK_L2
A17
MB0_CLK_H1
A18
MB0_CLK_L1
W23
MB0_ODT1
W26
MB0_ODT0
V20
MA0_ODT1
U19
MA0_ODT0
J25
MB_ADD15
J26
MB_ADD14
W25
MB_ADD13
L23
MB_ADD12
L25
MB_ADD11
U25
MB_ADD10
L24
MB_ADD9
M26
MB_ADD8
L26
MB_ADD7
N23
MB_ADD6
N24
MB_ADD5
N25
MB_ADD4
N26
MB_ADD3
P24
MB_ADD2
P26
MB_ADD1
T24
MB_ADD0
K26
MB_BANK2
T26
MB_BANK1
U26
MB_BANK0
U24
MB_RAS_L
V26
MB_CAS_L
U22
MB_WE_L
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
PLACE CLOSE TO P RO CESSOR
WITHIN 1.5 INCH
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0
DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]DDR_B_DQS[0..7]
ATI check ,Use +0.9V PWR , can delete or not
A1
+1.8V
12
R6
1K_0402_1%
1
12
1 1
R7
1K_0402_1%
C16
2
1000P_0402_50V7K
+0.9VREF_CPU
0.1U_0402_16V4Z
C18
VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU
A
1
1
2
2
1000P_0402_50V7K
+0.9VREF_CPU
1
C20
C19
1U_0402_6.3V4Z
2
Security Classification
Issued Date
THIS SHEET OF ENG INE ERIN G D RAW ING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE INFORMATI ON IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT O F COMPAL ELECTRONICS , INC.
C
2005/10/11 2006/10/11
Compal Secret Data
Deciphered Date
D
Title
SCHEMATIC, M/B LA-3151P
Size Document Number Rev
Custom
401412
星期四 三月
Date: Sheet
Athlon 64 S1g1
uPGA638
Top View
AF1
Compal Electronics, inc.
006
E
A26
B
of
655, 09, 2
Page 7
5
MISC
+2.5VS
L1
12
FBM-L11-321611-260-LMT_1206
D D
1
2
4.7U_0805_10V4Z
+VDDA_25V
C22
50mil width(600mA)
1
C23
2
0.22U_0603_10V7K
SB460 ONLY
+3VS
4.7K_0402_5%
@
+1.8V
12
R15
U49
2
B
1
A
R806 0_0402_5%@
+1.8V
U50
2
B
1
A
R807 0_0402_5%@
+1.8V
U51
2
B
1
A
R808 0_0402_5%@
C26
1 2
5
0.1U_0402_16V4Z
P
4
Y
G
NC7SZ08P5X_NL_SC70-5
3
1 2
C28
1 2
5
0.1U_0402_16V4Z
P
4
Y
G
NC7SZ08P5X_NL_SC70-5
3
1 2
C29
1 2
5
0.1U_0402_16V4Z
P
4
Y
G
NC7SZ08P5X_NL_SC70-5
3
1 2
+1.8VS
12
R14
300_0402_5%
CPU_PWRGD<23>
+1.8VS
12
R18
300_0402_5%
C C
SB_PWRGD<23,42>
LDT_STOP#<13,23>
R804 0_0402_5%
1 2
LDT_RST#<22>
300_0402_5%
SB_PWROK_R
+1.8V
+1.8VS
12
R19
HDT Connector
12
12
12
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
+3VS
12
R24 220_0402_5%@
R26 220_0402_5%@
R28 220_0402_5%@
R27 220_0402_5%@12R25 220_0402_5%@
C30
0.1U_0402_16V4Z
1 2
+1.8V
JP74
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
@
B B
NOTE: HDT TERMINA TION IS REQUIRED
FOR REV. Ax SILICON ONLY.
4
1
C24
3300P_0402_50V7K
2
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
3V_LDT_RST#
+1.2V_HT
place them to CPU within 1"
LDT_RST# 3V_LDT_RST#
3
http://hobi-elektronika.net
LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIE L D) AND 500 mils LONG.
R10 300_0402_5%
1 2
R12 44.2_0603_1%
1 2
R13 44.2_0603_1%
1 2
CPUCLK<15>
CPUCLK#<15>
Modify 11/22
+1.8VS
12
R844
10K_0402_5%@
B
2
Q47
E
3 1
C
MMBT3904_SOT23@
+1.8V
12
R22
300_0402_5%
H_THERMTRIP_S# H_THERMTRIP#
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_SIC_R
CPU_HTREF1
CPU_HTREF0 VID0
CPU_VCC_SENSE<54>
CPU_VSS_SENSE<54>
C25
1 2
3900P_0402_50V7K
C27
1 2
3900P_0402_50V7K
+1.8V
Q1
3 1
MMBT3904_SOT23
169_0402_1%
+3VS
12
R845
4.7K_0402_5%@
12
R20
1K_0402_5%
2
12
R16
+3VALW
12
R23
10K_0402_5%
R32 300_0402_5%
R33 1K_0402_5%
R34 510_0402_5%
1 2
1 2
1 2
ATHLON Control and Debug
CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_VCC_SENSE
CPU_VSS_SENSE
VDDIOFB_H
T1PAD
VDDIOFB_L
T2PAD
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_THERMDC
CPU_THERMDA
+3VALW
12
R21
1K_0402_5%@
2
Q2
MMBT3904_SOT23@
3 1
H_THERMTRIP# <23>
+1.8V
T13PAD
T15PAD
T17PAD
T19PAD
T20PAD
T23PAD
T25PAD
T28PAD
T30PAD
MAINPWON <47,48,50>
2
JP72D
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HTREF1
R6
HTREF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
TEST25_HE9TEST29_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
AMD NPT S1 SOCKET
Processor Socket
THERMTRIP_L
PROCHOT_L
CPU_PRESENT_L
PSI_L
DBREQ_L
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
CPU_PROCHOT#_1.8
H_THERMTRIP_S#
AF6
CPU_PROCHOT#_1.8
AC7
A5
VID5
C6
VID4
A6
VID3
A4
VID2
C5
VID1
B5
VID0
AC6
A3
E10
AE9
TDO
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
VID5
VID4
VID3
VID2
VID1
CPU_PRESENT#
PSI#
CPU_DBREQ#
CPU_TDO
T14 PAD
T16 PAD
T18 PAD
CPU_TEST21_SCANEN
T21 PAD
T24 PAD
T26 PAD
T27 PAD
CPU_TEST26_BURNIN#
T29 PAD
T31 PAD
R29
10K_0402_5%
300_0402_5%
+1.8V
12
CPU_PH_G
B
2
Q3
E
3 1
C
MMBT3904_SOT23
+1.8V
12
R8
PSI# <54>
1 2
80.6_0402_1%
1
12
R9
300_0402_5%
VID5 <54>
VID4 <54>
VID3 <54>
VID2 <54>
VID1 <54>
VID0 <54>
Place within 0.5" from CPU
25mil/6mil/6mil/6mil/25mil
R17
ROUTE AS 80 Oh m D IFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
+3VS
12
R30
4.7K_0402_5%
EC_THERM# <23,33>
1
C31
A A
2200P_0402_50V7K
2
CPU_THERMDA
CPU_THERMDC
U4
1
VDD
SCLK
2
D+
SDATA
3
ALERT#
DTHERM#4GND
ADM1032ARMZ-2REEL_MSOP8
F75383M_MSOP8
8
7
6
5
EC_SMB_CK2 <33>
EC_SMB_DA2 <33>
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST21_SCANEN
SMBus Address: 1001110X (b)
5
4
3
R42 510_0402_5%
1 2
R43 300_0402_5%
1 2
R44 300_0402_5%
1 2
R35 300_0402_5%
1 2
Security Classification
Issued Date
THIS SHEET OF ENG INE ERIN G D RAW ING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT O F COMPAL ELECTRONICS , INC.
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number Rev
C
401412
星期四 三月
Date: Sheet
006
1
of
755, 09, 2
B
Page 8
5
Power
Ground
4
3
2
1
http://hobi-elektronika.net
D D
BOTTOMSIDE DECOUPLING
+CPU_CORE
1
2
1
C60
180P_0402_50V8J
2
+0.9V
1
2
1
2
1
C38
22U_0805_6.3V6M
2
C46
22U_0805_6.3V6M
1
C54
0.22U_0603_10V7K
2
1
+
C795
220U_D2_4VM
2
C63
4.7U_0805_10V4Z
C71
1000P_0402_50V7K
1
C39
22U_0805_6.3V6M
2
1
C47
0.22U_0603_10V7K
2
1
C55
0.22U_0603_10V7K
2
1
C65
0.22U_0603_10V7K
2
1
C76
180P_0402_50V8J
2
1
C40
22U_0805_6.3V6M
2
1
C48
0.22U_0603_10V7K
2
1
JP72F
AA4
VSS1
AA11
JP72E
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
C C
B B
M6
M8
M10
N7
N9
N11
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
V6
V8
V10
+CPU_CORE
1
45@
2
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
Athlon 64 S1
Processor Socket
+
C796
820U_E9_2.5V_M_R7
45@
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
1
+
C797
820U_E9_2.5V_M_R7
2
+CPU_CORE+CPU_CORE
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
+1.8V
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
1
+
C798
330U_D2E_2.5VM_R9
2
1
+
C799
330U_D2E_2.5VM_R9
2
AA13
AA15
AA17
AA19
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
VSS2
VSS3
VSS4
VSS5
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
AD6
VSS18
AD8
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
Athlon 64 S1
Processor Socket
J6
VSS66
J8
VSS67
J10
VSS68
J12
VSS69
J14
VSS70
J16
VSS71
J18
VSS72
K2
VSS73
K7
VSS74
K9
VSS75
K11
VSS76
K13
VSS77
K15
VSS78
K17
VSS79
L6
VSS80
L8
VSS81
L10
VSS82
L12
VSS83
L14
VSS84
L16
VSS85
L18
VSS86
M7
VSS87
M9
VSS88
M11
VSS89
M17
VSS90
N4
VSS91
N8
VSS92
N10
VSS93
N16
VSS94
N18
VSS95
P2
VSS96
P7
VSS97
P9
VSS98
P11
VSS99
P17
VSS100
R8
VSS101
R10
VSS102
R16
VSS103
R18
VSS104
T7
VSS105
T9
VSS106
T11
VSS107
T13
VSS108
T15
VSS109
T17
VSS110
U4
VSS111
U6
VSS112
U8
VSS113
U10
VSS114
U12
VSS115
U14
VSS116
U16
VSS117
U18
VSS118
V2
VSS119
V7
VSS120
V9
VSS121
V11
VSS122
V13
VSS123
V15
VSS124
V17
VSS125
W6
VSS126
Y21
VSS127
Y23
VSS128
N6
VSS129
C32
10U_0805_10V4Z
2
+CPU_CORE
1
C41
0.22U_0603_10V7K
2
1
C923
0.01U_0402_16V7K
2
1
C33
10U_0805_10V4Z
2
1
2
1
C924
180P_0402_50V8J
2
+1.8V
1
C49
4.7U_0805_10V4Z
2
1
C56
0.22U_0603_10V7K
2
CPU left-hand side CPU right-hand side
C42
0.22U_0603_10V7K
1
C34
10U_0805_10V4Z
2
1
C43
0.22U_0603_10V7K
2
1
C35
10U_0805_10V4Z
2
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+0.9V
1
C61
4.7U_0805_10V4Z
2
1
C69
1000P_0402_50V7K
2
1
C50
4.7U_0805_10V4Z
2
1
2
C57
0.01U_0402_16V7K
1
C68
0.22U_0603_10V7K
2
1
C74
180P_0402_50V8J
2
1
C51
4.7U_0805_10V4Z
2
1
C44
0.22U_0603_10V7K
2
1
C58
0.01U_0402_16V7K
2
1
C36
10U_0805_10V4Z
2
1
C52
4.7U_0805_10V4Z
2
1
C59
180P_0402_50V8J
2
+1.8V
1
C45
22U_0805_6.3V6M
2
1
C37
22U_0805_6.3V6M
2
1
C53
0.22U_0603_10V7K
2
A1
A26
PROCESSOR POWER AND GROUND
Athlon 64 S1g1
uPGA638
Top View
A A
AF1
Security Classification
Issued Date
THIS SHEET OF ENG INE ERIN G D RAW ING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRE T INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE INFORMATI ON IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT O F COMPAL ELECTRONICS , INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number Rev
C
401412
星期四 三月
Date: Sheet
006
1
of
855, 09, 2
B
Page 9
5
4
3
2
1
http://hobi-elektronika.net
JP1
1
VREF
3
DDR_A_D0
D D
C C
DDR_CKE0_DIMMA<6>
DDR_CS2_DIMMA#<6>
DDR_A_BS#2<6>
DDR_A_BS#0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6>
DDR_CS1_DIMMA#<6>
DDR_A_ODT1<6>
B B
A A
SB_CK_SDAT<10,15,23>
SB_CK_SCLK<10,15,23>
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18 DDR_A_D22
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43 DDR_A_D47
DDR_A_D48
DDR_A_D49 DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51 DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C104
0.1U_0402_16V4Z
2
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692C-A0G16
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_CS3_DIMMA#
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D52
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_DM6
DDR_A_D54
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R77 10K_0402_5%
1 2
R78 10K_0402_5%
1 2
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_CKE1_DIMMA <6>
DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>
DDR_CS3_DIMMA# <6>
DDR_A_CLK2 <6>
DDR_A_CLK#2 <6>
0.1U_0402_16V4Z
C77
1
2
4.7U_0805_10V4Z
Security Classification
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C78
2
Issued Date
3
+1.8V+DIMM_VREF+1.8V+1.8V
12
R45
1K_0402_1%
12
R46
1K_0402_1%
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_CAS#
DDR_A_WE#
DDR_A_RAS#
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_A_ODT1
DDR_A_ODT0
DDR_A_D[0..63]<6>
DDR_A_DM[0..7]<6>
DDR_A_DQS[0..7]<6>
DDR_A_MA[0..15]<6>
DDR_A_DQS#[0..7]<6>
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C79
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C89
R47 47_0402_5%
1 2
R48 47_0402_5%
1 2
R49 47_0402_5%
1 2
R50 47_0402_5%
1 2
R51 47_0402_5%
1 2
R52 47_0402_5%
1 2
R53 47_0402_5%
1 2
R54 47_0402_5%
1 2
R55 47_0402_5%
1 2
R56 47_0402_5%
1 2
R57 47_0402_5%
1 2
R58 47_0402_5%
1 2
R59 47_0402_5%
1 2
R60 47_0402_5%
1 2
R61 47_0402_5%
1 2
R62 47_0402_5%
1 2
R63 47_0402_5%
1 2
R64 47_0402_5%
1 2
R65 47_0402_5%
1 2
R66 47_0402_5%
1 2
R67 47_0402_5%
1 2
R68 47_0402_5%
1 2
R69 47_0402_5%
1 2
R70 47_0402_5%
1 2
R71 47_0402_5%
1 2
R72 47_0402_5%
1 2
R73 47_0402_5%
1 2
R74 47_0402_5%
1 2
R75 47_0402_5%
1 2
R76 47_0402_5%
1 2
2005/10/11 2006/10/11
4.7U_0805_10V4Z
1
1
C80
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C91
C90
+0.9V
Compal Secret Data
Deciphered Date
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C82
C81
2
0.1U_0402_16V4Z
1
1
2
2
C92
C93
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
4.7U_0805_10V4Z
1
1
C83
C84
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C94
C95
0.1U_0402_16V4Z
+0.9V
2
+1.8V
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C96
11/3 Modify
1
2
C926
1
1
C86
C85
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C97
C98
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C927
C928
Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C87
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C100
C99
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C929
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number Rev
Custom
401412
星期四 三月
Date: Sheet
1
2
C930
1
1
+
C802
C88
220U_D2_4VM
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C931
1
2
2
C102
C103
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C932
C933
1
1
2
C101
1
2
11/01 modify
1
+
C925
150U_D2_6.3VM
2
+1.8V
B
of
955, 09, 2006
Page 10
5
4
3
2
1
http://hobi-elektronika.net
JP2
1
VREF
3
DDR_B_D0
D D
C C
DDR_CKE0_DIMMB<6>
DDR_CS2_DIMMB#<6>
DDR_B_BS#2<6>
DDR_B_BS#0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_CS1_DIMMB#<6>
DDR_B_ODT1<6>
B B
A A
SB_CK_SDAT<9,15,23>
SB_CK_SCLK<9,15,23>
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51 DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C132
0.1U_0402_16V4Z
2
5
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5652C-A0G16
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
4
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D52
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_DM6
DDR_B_D54
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R109 10K_0402_5%
1 2
R110 10K_0402_5%
1 2
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_CKE1_DIMMB <6>
DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>
DDR_CS3_DIMMB# <6>
DDR_B_CLK2 <6>
DDR_B_CLK#2 <6>
4.7U_0805_10V4Z
+3VS
+DIMM_VREF+1.8V+1.8V
0.1U_0402_16V4Z
C105
1
2
C106
1
2
4.7U_0805_10V4Z
1
C107
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C117
DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#
DDR_B_ODT1
DDR_B_ODT0
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/11 2006/10/11
DDR_B_D[0..63]<6>
DDR_B_DM[0..7]<6>
DDR_B_DQS[0..7]<6>
DDR_B_MA[0..15]<6>
DDR_B_DQS#[0..7]<6>
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
C108
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C119
C118
Compal Secret Data
Deciphered Date
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
C110
C109
0.1U_0402_16V4Z
1
2
C120
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V
R79 47_0402_5%
1 2
R80 47_0402_5%
1 2
R81 47_0402_5%
1 2
R82 47_0402_5%
1 2
R83 47_0402_5%
1 2
R84 47_0402_5%
1 2
R85 47_0402_5%
1 2
R86 47_0402_5%
1 2
R87 47_0402_5%
1 2
R88 47_0402_5%
1 2
R89 47_0402_5%
1 2
R90 47_0402_5%
1 2
R91 47_0402_5%
1 2
R92 47_0402_5%
1 2
R93 47_0402_5%
1 2
R94 47_0402_5%
1 2
R95 47_0402_5%
1 2
R96 47_0402_5%
1 2
R97 47_0402_5%
1 2
R98 47_0402_5%
1 2
R99 47_0402_5%
1 2
R100 47_0402_5%
1 2
R101 47_0402_5%
1 2
R102 47_0402_5%
1 2
R103 47_0402_5%
1 2
R104 47_0402_5%
1 2
R105 47_0402_5%
1 2
R106 47_0402_5%
1 2
R107 47_0402_5%
1 2
R108 47_0402_5%
1 2
C111
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C121
C122
2
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
+1.8V
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C112
2
0.1U_0402_16V4Z
1
1
2
2
C123
C124
+0.9V
1
2
0.1U_0402_16V4Z
+0.9V
4.7U_0805_10V4Z
1
C113
C114
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C125
C126
11/3 Modify
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C934
Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V
Size Document Number Rev
Custom
Date: Sheet
1
1
C116
C115
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C127
C128
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C935
C936
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
0.1U_0402_16V4Z
1
1
2
C129
1
2
C937
1
2
2
C130
C131
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C938
C939
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.8V
0.1U_0402_16V4Z
1
1
2
2
C940
C941
B
of
10 55, 09, 2006
Page 11
5
4
3
2
1
http://hobi-elektronika.net
D D
H_CADOP[0..15]
H_CADON[0..15] H_CADIN[0..15]
C C
H_CLKOP1<5>
H_CLKON1<5>
H_CLKOP0<5>
H_CLKON0<5>
B B
H_CTLOP0<5>
H_CTLON0<5>
R111 49.9_0402_1%
R113 49.9_0402_1%
+1.2V_HT
1 2
1 2
H_CADOP[0..15] <5> H_CADIP[0..15]<5>
H_CADON[0..15] <5>
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKON0
H_CTLON0
HT_RXCALP
HT_RXCALN
U58A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
W19
HT_RXCAD11P
W20
HT_RXCAD11N
AC21
HT_RXCAD10P
AB22
HT_RXCAD10N
AB20
HT_RXCAD9P
AA20
HT_RXCAD9N
AA19
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
AA25
HT_RXCAD3P
AA24
HT_RXCAD3N
AB23
HT_RXCAD2P
AA23
HT_RXCAD2N
AB24
HT_RXCAD1P
AB25
HT_RXCAD1N
AC24
HT_RXCAD0P
AC25
HT_RXCAD0N
W21
HT_RXCLK1P
W22
HT_RXCLK1N
Y24
HT_RXCLK0P
W25
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALP
C24
HT_RXCALN
215NSA4ALA11FG RS485M_BGA465
PART 1 OF 5
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU
I/F
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
H_CADIN[0..15]<5>
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13H_CADON13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0H_CLKOP0
H_CLKIN0
H_CTLIP0H_CTLOP0
H_CTLIN0
HT_TXCALP
HT_TXCALN
1 2
R112
100_0402_1%
H_CADIP[0..15]
H_CLKIP1 <5>
H_CLKIN1 <5>
H_CLKIP0 <5>
H_CLKIN0 <5>
H_CTLIP0 <5>
H_CTLIN0 <5>
A A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
2
月
11 55,
1
B
of
Page 12
5
4
3
2
1
http://hobi-elektronika.net
PCIE_GTX_C_MRX_P[0..15]<16>
D D
C C
PCIE_MRX_PTX_P0<39>
PCIE_MRX_PTX_N0<39>
PCIE_MRX_PTX_P1<36>
PCIE_MRX_PTX_N1<36>
B B
PCIE_GTX_C_MRX_N[0..15]<16>
10KOhm FOR RS485
R214:
1.47KOhm FOR RS690
8.25KOhm FOR RS485
R213:
DNI FOR RS690
R114 0_0402_5%
1 2
R115 0_0402_5%
1 2
R116 0_0402_5%
1 2
R117 0_0402_5%
1 2
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
A_MRX_STX_P0<22>
A_MRX_STX_N0<22>
A_MRX_STX_P1<22>
A_MRX_STX_N1<22>
R118 10K_0402_1%
1 2
R120 8.25K_0402_1%
1 2
U58B
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
P4
GFX_RX8P
P5
GFX_RX8N
R4
GFX_RX9P
R5
GFX_RX9N
R7
GFX_RX10P
R8
GFX_RX10N
U4
GFX_RX11P
U5
GFX_RX11N
W4
GFX_RX12P
W5
GFX_RX12N
Y4
GFX_RX13P
Y5
GFX_RX13N
V9
GFX_RX14P
W9
GFX_RX14N
AB7
GFX_RX15P
AB6
PCIE_MRX_PTX_P0_R
PCIE_MRX_PTX_N0_R
PCIE_MRX_PTX_P1_R
PCIE_MRX_PTX_N1_R
A_MRX_STX_P0
A_MRX_STX_N0 A_MTX_SRX_N0
A_MRX_STX_P1
A_MRX_STX_N1
GFX_RX15N
W11
GPP_RX0P
W12
GPP_RX0N
AA11
GPP_RX1P
AB11
GPP_RX1N
Y7
GPP_RX2P
AA7
GPP_RX2N
AB9
GPP_RX3P
AA9
GPP_RX3N
W14
SB_RX0P
W15
SB_RX0N
AB12
SB_RX1P
AA12
SB_RX1N
AA14
PCEH_ISET
AB14
PCEH_TXISET
215NSA4ALA11FG RS485M_BGA465
PART 2 OF 5
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCEH_PCAL
PCEH_NCAL
PCIE_MTX_GRX_P0
J1
PCIE_MTX_GRX_N0
H2
PCIE_MTX_GRX_P1
K2
PCIE_MTX_GRX_N1
K1
PCIE_MTX_GRX_P2
K3
PCIE_MTX_GRX_N2
L3
PCIE_MTX_GRX_P3
L1
PCIE_MTX_GRX_N3
L2
PCIE_MTX_GRX_P4
N2
PCIE_MTX_GRX_N4
N1
PCIE_MTX_GRX_P5
P2
PCIE_MTX_GRX_N5
P1
PCIE_MTX_GRX_P6
P3
PCIE_MTX_GRX_N6
R3
PCIE_MTX_GRX_P7
R1
PCIE_MTX_GRX_N7
R2
PCIE_MTX_GRX_P8
T2
PCIE_MTX_GRX_N8
U1
PCIE_MTX_GRX_P9
V2
PCIE_MTX_GRX_N9
V1
PCIE_MTX_GRX_P10
V3
PCIE_MTX_GRX_N10
W3
PCIE_MTX_GRX_P11
W1
PCIE_MTX_GRX_N11
W2
PCIE_MTX_GRX_P12
Y2
PCIE_MTX_GRX_N12
AA1
PCIE_MTX_GRX_P13
AA2
PCIE_MTX_GRX_N13
AB2
PCIE_MTX_GRX_P14
AB1
PCIE_MTX_GRX_N14
AC1
PCIE_MTX_GRX_P15
AE3
PCIE_MTX_GRX_N15
AE4
PCIE_MTX_PRX_P0
AD8
PCIE_MTX_PRX_N0
AE8
PCIE_MTX_PRX_P1
AD7
PCIE_MTX_PRX_N1
AE7
AD4
AE5
AD5
AD6
AE9
AD10
AC8
A_MTX_SRX_N1
AD9
R119 150_0402_1%
AD11
R121 100_0402_1%
AE11
R119:
R121:
1 2
1 2
150 Ohm FOR RS485
562 Ohm FOR RS690
100 Ohm FOR RS485
2KOhm FOR RS690
C134 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7K
1 2
C140 0.1U_0402_16V7K
1 2
C142 0.1U_0402_16V7K
1 2
C144 0.1U_0402_16V7K
1 2
C146 0.1U_0402_16V7K
1 2
C148 0.1U_0402_16V7K
1 2
C150 0.1U_0402_16V7K
1 2
C152 0.1U_0402_16V7K
1 2
C154 0.1U_0402_16V7K
1 2
C156 0.1U_0402_16V7K
1 2
C158 0.1U_0402_16V7K
1 2
C160 0.1U_0402_16V7K
1 2
C162 0.1U_0402_16V7K
1 2
C164 0.1U_0402_16V7K
1 2
C165 0.1U_0402_16V7K
1 2
C167 0.1U_0402_16V7K
1 2
C169 0.1U_0402_16V7K
1 2
C171 0.1U_0402_16V7K
1 2
ATI side check , use +1.2V or not
PCIE_MTX_C_GRX_P[0..15]<16>
PCIE_MTX_C_GRX_N[0..15]<16>
C133 0.1U_0402_16V7K
1 2
C135 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7K
1 2
C139 0.1U_0402_16V7K
1 2
C141 0.1U_0402_16V7K
1 2
C143 0.1U_0402_16V7K
1 2
C145 0.1U_0402_16V7K
1 2
C147 0.1U_0402_16V7K
1 2
C149 0.1U_0402_16V7K
1 2
C151 0.1U_0402_16V7K
1 2
C153 0.1U_0402_16V7K
1 2
C155 0.1U_0402_16V7K
1 2
C157 0.1U_0402_16V7K
1 2
C159 0.1U_0402_16V7K
1 2
C161 0.1U_0402_16V7K
1 2
C163 0.1U_0402_16V7K
1 2
C166 0.1U_0402_16V7K
1 2
C168 0.1U_0402_16V7K
1 2
C170 0.1U_0402_16V7K
1 2
C172 0.1U_0402_16V7K
1 2
+1.2V_HT
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_PRX_P0
PCIE_MTX_C_PRX_N0
PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1
A_MTX_C_SRX_P0A_MTX_SRX_P0
A_MTX_C_SRX_N0
A_MTX_C_SRX_P1A_MTX_SRX_P1
A_MTX_C_SRX_N1
PCIE_MTX_C_PRX_P0 <39>
PCIE_MTX_C_PRX_N0 <39>
PCIE_MTX_C_PRX_P1 <36>
PCIE_MTX_C_PRX_N1 <36>
A_MTX_C_SRX_P0 <22>
A_MTX_C_SRX_N0 <22>
A_MTX_C_SRX_P1 <22>
A_MTX_C_SRX_N1 <22>
A A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
2
月
12 55,
1
B
of
Page 13
5
4
3
2
1
http://hobi-elektronika.net
ATI check , CRT / TV/ LVDS can delete or not when I use RX485
D D
Modify 11/29
+1.8VS
+1.8VS
MBK1608800YZF_0805
+1.8VS
C C
1 2
MBK1608800YZF_0805
Modify : 11/07
L63
1 2
L67
PLLVDD
1
C173
2
HTPVDD
1
C175
2
1
2
10U_0805_10V4Z
1
2
10U_0805_10V4Z
C174
4.7U_0805_10V4Z
C176
4.7U_0805_10V4Z
Modify : 11/07
+1.8VS
R810
10K_0402_5%
B
E
LDT_STOP#<7,23>
3 1
MMBT3904_SOT23
+1.8VS
+3VS
12
12
R125
2
1K_0402_5%
Q4
C
LOAD_ROM#: LOAD ROM ST RAP ENABLE
High, LOAD R O M S TRAP DISABLE
B B
Low, LOAD ROM STRAP ENABLE
1 2
NB_PWRGD<42>
ALLOW_LDTSTOP<22>
NBSRC_CLKP<15>
NBSRC_CLKN<15>
SBLINK_CLKP<15>
SBLINK_CLKN<15>
R847
0_0603_5%
NB_RST#<16,22,27,33,36,41>
HTREFCLK<15>
NB_OSC<15>
R129
1 2
1
C948
2
R846
0_0603_5%
1 2
3K_0402_5%@
1
2
1U_0402_6.3V4Z@
R126 0_0402_5%
1 2
R128 2.7K_0402_5%@
R130 2.7K_0402_5%@
R131 2.7K_0402_5%@
R132 2.7K_0402_5%@
R133 2.7K_0402_5%@
BMREQ#<22>
12
R134
4.7K_0402_5%
+3VS
C947
1U_0402_6.3V4Z@
PLLVDD
HTPVDD
LDT_STOP#_NB
R127 10K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
R809 0_0603_5%
1 2
R123 715_0402_1%@
12
DFT_GPIO0
LOAD_ROM#
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
T11PAD
T7PAD
DFT_GPIO5
T8PAD
T9PAD
T10PAD
D33 1N4148_SOT23
12
U58C
B22
AVDD1
C22
AVDD2
G17
AVSSN1
H17
AVSSN2
A20
AVDDDI
B20
AVSSDI
A21
AVDDQ
A22
AVSSQ
C21
C_R
C20
Y_G
D19
COMP_B
E19
RED
F19
GREEN
G19
BLUE
C6
DACVSYNC
A5
DACHSYNC
B21
RSET
B6
DACSCL
A6
DACSDA
A10
PLLVDD
B10
PLLVSS
B24
HTPVDD
B25
HTPVSS
C10
SYSRESET#
C11
POWERGOOD
C5
LDTSTOP#
B5
ALLOW_LDTSTOP
C23
HTTSTCLK
B23
HTREFCLK
C2
TVCLKIN
B11
OSCIN
A11
OSCOUT
F2
GFX_CLKP
E1
GFX_CLKN
G1
SB_CLKP
G2
SB_CLKN
D6
DFT_GPIO0
D7
DFT_GPIO1
C8
DFT_GPIO2
C7
DFT_GPIO3
B8
DFT_GPIO4
A8
DFT_GPIO5
B2
BMREQb
A2
I2C_CLK
B4
I2C_DATA
AA15
THERMALDIODE_P
AB15
THERMALDIODE_N
C14
TMDS_HPD
B3
DDC_DATA
C3
TESTMODE
A3
STRP_DATA
215NSA4ALA11FG RS485M_BGA465
PART 3 OF 5
CRT/TVOUT
PLL PWR
PM
CLOCKs
MIS.
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LPVDD
LPVSS
LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2
LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVSSR12
LVSSR13
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
DVO_VSYNC
DVO_DE
DVO_HSYNC
DVO_IDCKP
DVO_IDCKN
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
E14
A12
B12
C12
C13
A16
A14
D12
C19
C15
C16
F14
F15
E12
G12
F12
AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21
AD13
AC13
AE13
AE17
AD17
T4 PAD
T5 PAD
T6 PAD
C950
1U_0402_6.3V4Z@
1
2
Modify 11/29
R848
1 2
0_0603_5%
1
C949
1U_0402_6.3V4Z@
2
R849
1 2
0_0603_5%
R850
1 2
0_0603_5%
1
C951
1U_0402_6.3V4Z@
2
+1.8VS
+1.8VS
A A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
2
月
13 55,
1
B
of
Page 14
5
4
3
2
1
NB RS485 POWER STATES
Power Signal
VDDHT
VDDR
VDD18
D D
VDDC
VDDA18
VDDA12
S0
ON
ON
ON
ON
ON
ON
ON
AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
LVDDR18D
ON
ON
ON
ON
ON
ON
http://hobi-elektronika.net
S3
S1
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFFAVDD
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
S4/S5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LVDDR18A OFFON ON OFF OFF
U58E
A25
VSS1
F11
AE18
M15
M11
M20
M23
M25
W23
AD25
W24
AC23
AC14
AC22
AE22
AE14
M17
AC15
AC16
M13
D23
G11
Y23
P11
R24
G23
N12
N14
P13
P20
P15
R12
R14
R20
Y25
U20
H25
Y22
D25
G24
H12
R23
T23
T25
R17
H23
A23
F17
E9
J22
J12
L12
L14
L20
L23
B7
L24
C4
D4
CURRENT MEASUREMENT
+1.2V_HT
C C
KC FBM-L11- 2 01 209-221LMAT_0805
+1.8VS
1 2
MBK1608800YZF_0805
RS690: VDDA18=1.2V
RS485: VDDA18=1.8V
+1.8VS
L64
1 2
KC FBM-L11- 2 0 1209-221LMAT_0805
+3VS
B B
+1.8VS
Modify 11/07 for EMI
+VDD_HT
L70
1 2
L2
1
2
3A bead
10U_0805_10V4Z
L3
1 2
MBK1608800YZF_0805
L4
1 2
MBK1608800YZF_0805
+VDDA_12
10U_0805_10V4Z
1
C183
C184
2
10U_0805_10V4Z
1
C190
2.2U_0603_6.3V6K
2
1
1
C198
2
2
10U_0805_10V4Z
VDDR3
1
C208
4.7U_0805_10V4Z
2
1U_0402_6.3V4Z
1
C209
@
2
1U_0402_6.3V4Z@
4.7U_0805_10V4Z
1
2
1
C185
2
1U_0402_6.3V4Z
VDD18
1
C200
C199
2
1U_0402_6.3V4Z
VDDR
1
C210
2
1U_0402_6.3V4Z@
1
C213
C214
1U_0402_6.3V4Z
2
1
C186
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C191
2.2U_0603_6.3V6K
2
1
C201
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C211
2
1
C187
2
1U_0402_6.3V4Z
1
C202
2
1U_0402_6.3V4Z
1
C188
2
VDDA18
1
C203
2
1U_0402_6.3V4Z
+1.2V_HT
1
2
1
C189
1U_0402_6.3V4Z
2
1
C204
2
+1.2V_HT
+1.2V_HT
+1.2V_HT
C212
10U_0805_10V4Z
Close to U58.M1
U58D
AE24
AD24
AD22
AB17
AE23
W17
AC18
AD21
AC19
AC20
AB19
AD23
AA17
AE25
AC3
AD2
AC12
AD12
AE12
AC11
Y17
AE2
AB3
AB4
AE1
E11
D11
D22
J14
J15
U7
W7
E7
F7
F9
G9
M1
PART 4 OF 5
VDD_HT1
VDD_HT2
VDD_HT5
VDD_HT6
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD18_1
VDD18_2
VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8
VDDR3_2
VDDR3_1
VDDR_1
VDDR_2
VDDR_3
VDDA12/VDDPLL_1
VDDA12/VDDPLL_2
VSSA12/VSSPLL_1
VSSA12/VSSPLL_2
VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2
215NSA4ALA11FG RS485M_BGA465
VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
POWER
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6
L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15
1U_0402_6.3V4Z
1
C178
2
1U_0402_6.3V4Z
10U_0805_10V4Z
1
+
C803
220U_D2_4VM
2
1
C179
2
1
C192
2
10U_0805_10V4Z
1
C180
2
1U_0402_6.3V4Z
10U_0805_10V4Z
1
C193
2
+VDDA_12
1
C181
2
10U_0805_10V4Z
1
C194
2
1U_0402_6.3V4Z
1
C205
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2
1
KC FBM-L11- 2 01 209-221LMAT_0805
C182
2
1U_0402_6.3V4Z
1
1
C196
C195
2
2
1U_0402_6.3V4Z
1
1
C206
C207
2
2
1U_0402_6.3V4Z
L69
+1.2V_HT
1
C197
1U_0402_6.3V4Z
2
+1.2V_HT
PAR 5 OF 5
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
215NSA4ALA11FG RS485M_BGA465
GROUND
VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
M3
V12
V11
V14
F3
V15
A1
H1
G3
J2
H3
AE10
J6
AE6
F1
L6
M2
M6
J3
P6
T1
N3
P9
R6
U2
T3
U3
U6
AC4
Y1
Y15
W6
AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
RS485: 0 Ohm RESISTOR
RS690: 220 Ohm 500mA FERRITE BEAD
A A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date: Sheet
星期四 三
09, 2006
2
月
14 55,
1
B
of
Page 15
5
4
3
2
1
+3VS
L5
1 2
MBK2012121YZF_0805
D D
1- PLACE ALL SERIAL TERMINATION
RESISTORS CLOSE TO U800
2- PUT DECOUPLING CAPS CLOSE TO U800
POWER PIN
C C
CLK_VDD
12
R153
10K_0402_5%
1
C230
0.1U_0402_16V4Z
2
@
CLK_VDD
10U_0805_10V4Z
1
1
C215
2
0.1U_0402_16V4Z
+3VS
+3VS
1
C216
2
2
0.1U_0402_16V4Z
L7
1 2
MBK2012121YZF_0805
2.2U_0603_6.3V6K
L8
1 2
MBK2012121YZF_0805
2.2U_0603_6.3V6K
Parallel Resonance Crystal
C228
1 2
33P_0402_50V8J
Y1
33P_0402_50V8J
1 2
C229
SB_CK_SCLK<9,10,23>
SB_CK_SDAT<9,10,23>
1
1
C218
C217
0.1U_0402_16V4Z
1
C226
2
1
C227
2
12
14.31818MHz_20P_1BX14318BE1A
Ioh = 5 * Iref
(2.32mA)
C219
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R148
@
1M_0402_5%
1 2
R154 0_0402_5%
SB_CK_SCLK
SB_CK_SDAT
Voh = 0.71V @ 60 ohm
ICH_SMBDATA<36,39>
B B
ICH_SMBCLK<36,39>
ICH_SMBDATA
ICH_SMBCLK
R192 0_0402_5%
1 2
R193 0_0402_5%
1 2
SB_CK_SDAT
SB_CK_SCLK
http://hobi-elektronika.net
1
C220
2
CLK_VDD
12
1 2
1
C221
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
54
14
23
28
44
39
60
53
15
22
29
45
38
58
11
61
10
48
R173
475_0402_1%
1
1
C223
C222
2
2
0.1U_0402_16V4Z
U8
VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDSRC
5
VDD48
VDDATIG
2
VDDREF
VDDHTT
GNDCPU
GNDSRC
GNDSRC
GNDSRC
GNDSRC
8
GND48
GNDATIG
1
GNDREF
GNDHTT
3
X1
4
X2
RESET_IN#
NC
9
SMBCLK
SMBDAT
IREF
ICS951462AGLFT_TSSOP64
VDDA
GNDA
CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1
SRCCLKT6
SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
CLKREQC#
48MHz_1
48MHz_0
FS1/REF1
FS0/REF0
FS2/REF2
HTTCLK0
CLK_VDDA
50
49
CPUCLK_EXT_R
56
CPUCLK#_EXT_R
55
52
51
SBLINK_CLKP_R
16
SBLINK_CLKN_R
17
NBSRC_CLKP_R
41
NBSRC_CLKN_R
40
GFX_CLKP_R
37
GFX_CLKN_R
36
35
34
30
31
SBSRC_CLKP_R
18
SBSRC_CLKN_R
19
GPP_CLK4P_R
20
GPP_CLK4N_R
21
GPP_CLK0P_R
24
GPP_CLK0N_R
25
26
27
47
46
43
42
12
13
57
R158 0_0402_5%
32
1 2
R171 0_0402_5%
33
1 2
CLK_48M_SIO_R
7
CLK_48M_USB_R
6
63
64
62
59
2
C224
0.1U_0402_16V4Z
1
R140 47_0402_1%
1 2
R141 47_0402_1%
1 2
R142 33_0402_1%
R143 33_0402_1%
R144 33_0402_1%
R145 33_0402_1%
R146 33_0402_1%
R147 33_0402_1%
R149 33_0402_1%
R150 33_0402_1%
R151 33_0402_1%
R152 33_0402_1%
R155 33_0402_1%
R156 33_0402_1%
R175 33_0402_1%
1 2
R176 33_0402_1%
1 2
SB_OSCIN_R
FS0
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
EXP_CLKREQ# <39>
MINI1_CLKREQ# <36>
R186 33_0402_1%
R187 33_0402_1%
L6
1 2
MBK2012121YZF_0805
C225
10U_0805_10V4Z
R139
261_0402_1%
1 2
R160 49.9_0402_1%
R159 49.9_0402_1%
R161 49.9_0402_1%
1 2
1 2
1 2
CLK_SD_48M <37>
CLK_USB_48M <23>
R180 8.2K_0402_5%
1 2
R182 8.2K_0402_5%
1 2
R184 8.2K_0402_5%
1 2
1 2
1 2
+3VS
R162 49.9_0402_1%
1 2
R164 49.9_0402_1%
R163 49.9_0402_1%
1 2
1 2
CLK_VDD
2.2K_0402_5%
CPUCLK <7>
CPUCLK# <7>
2.2K_0402_5%
12
R177
R178
SB_OSCIN <23>
CLK_14M_SIO <41>
R166 49.9_0402_1%
R165 49.9_0402_1%
1 2
1 2
12
R169 49.9_0402_1%
R167 49.9_0402_1%
R170 49.9_0402_1%
R168 49.9_0402_1%
1 2
1 2
1 2
1 2
12
R179
2.2K_0402_5%
R181 0_0402_5%@
R183 0_0402_5%@
R185 0_0402_5%@
SBLINK_CLKP <13>
SBLINK_CLKN <13>
NBSRC_CLKP <13>
NBSRC_CLKN <13>
CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>
SBSRC_CLKP <22>
SBSRC_CLKN <22>
CLK_PCIE_CARD <39>
CLK_PCIE_CARD# <39>
CLK_PCIE_MINI1 <36>
CLK_PCIE_MINI1# <36>
12
12
12
NB_OSCIN_R
HTREFCLK_R
R188 33_0402_1%
1 2
R190 33_0402_1%
1 2
12
R191
51.1_0402_1%
NB_OSC <13>
HTREFCLK <13>
EXT CLK FREQUENCY SELECT TABLE(MHZ)
FS2
0 0 0
A A
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
CPUFS1
Hi-Z
X
180.00
220.00
100.00
133.33
200.00
5
HTTFS0 PCI
SRCCLK
[2:1]
Hi-Z Hi-Z100.00 Reserve d
100.00
100.00
36.56 73.12
100.00
66.66 33.33
100.00
66.66 33.33
100.00
66.66 33.33 Normal ATHLON64 operation
100.00
USB
COMMENT
48.00
48.00
48.00
48.00
48.00
48.00
48.00
Reserved
Reserved
Reserved
Reserved
Reserved
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size D ocu ment Number Rev
Custom
401412
Date : Sheet
星期四 三
09, 2006
2
月
15 55,
1
B
of
X/6X/3
30.0060.00
Page 16
5
PCIE Lane Reversal
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
D D
C C
R210
2.2K_0402_5%
THM@
D+
D-
C264
1 2
B B
2200P_0402_50V7KTHM@
+3VS
12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P[0..15]<12>
PCIE_GTX_C_MRX_N[0..15]<12>
PCIE_MTX_C_GRX_P[0..15]<12>
PCIE_MTX_C_GRX_N[0..15]<12>
+3VS
Thermal sensor
12
U10
1
VDD
2
D+
3
D-
4
OVERT#
MAX6649MUA_8UMAXTHM@
SCLK
SDATA
ALERT#
GND
C232 0.1U_0402_16V7K
1 2
C234 0.1U_0402_16V7K
1 2
C236 0.1U_0402_16V7K
1 2
C238 0.1U_0402_16V7K
1 2
C240 0.1U_0402_16V7K
1 2
C242 0.1U_0402_16V7K
1 2
C244 0.1U_0402_16V7K
1 2
C246 0.1U_0402_16V7K
1 2
C248 0.1U_0402_16V7K
1 2
C251 0.1U_0402_16V7K
1 2
C253 0.1U_0402_16V7K
1 2
C255 0.1U_0402_16V7K
1 2
C257 0.1U_0402_16V7K
1 2
C259 0.1U_0402_16V7K
1 2
C261 0.1U_0402_16V7K
1 2
C263 0.1U_0402_16V7K
1 2
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
THERM_SCL
8
THERM_SDA
7
6
1 2
R212 0_0402_5%
5
THM@
C231 0.1U_0402_16V7K
1 2
C233 0.1U_0402_16V7K
1 2
C235 0.1U_0402_16V7K
1 2
C237 0.1U_0402_16V7K
1 2
C239 0.1U_0402_16V7K
1 2
C241 0.1U_0402_16V7K
1 2
C243 0.1U_0402_16V7K
1 2
C245 0.1U_0402_16V7K
1 2
C247 0.1U_0402_16V7K
1 2
C249 0.1U_0402_16V7K
1 2
C252 0.1U_0402_16V7K
1 2
C254 0.1U_0402_16V7K
1 2
C256 0.1U_0402_16V7K
1 2
C258 0.1U_0402_16V7K
1 2
C260 0.1U_0402_16V7K
1 2
C262 0.1U_0402_16V7K
1 2
+3VS
R211
2.2K_0402_5%
THM@
1 2
THER_ALERT#
NB_RST#<13,22,27,33,36,41>
Spread spectrum
R222
0_0603_5%
SSC@
1
C265
2
SSC@
A A
+3VS
0.1U_0402_16V4Z
12
R230
1K_0402_5%
U11
7
VDD
1
XIN
8
XOUT
2
VSS
ASM3P1819N-SR_SO8
SSC@
1 2
C266
0.1U_0402_16V4Z
X1
4
VDD
1
OE
27MHZ_15P
5
5
REF
4
MODOUT
PD#
OUT
GND
NC
3
2
1 2
R226 22_0402_5%
3
6
Minimize distance from X1 pin3 to U3 pin1
OSC_IN
Keep away from other signal at last 25mils
Memory Interface SS
OSC_SPREAD
SSC@
4
AL28
AK28
AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28
V28
V27
U27
U25
R28
R27
P27
AJ31
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32
Y32
Y31
W31
W30
V30
V32
U32
U31
R30
R32
P32
P31
N31
AE24
AD24
AB24
AG24
AA24
AF24
AG12
AH12
AE12
AF12
AL26
AM26
T25
T28
T31
T30
U9A
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
PERST#
PCIE_TEST
PERST#_MASK
DPLUS
DMINUS
DDC3DATA
DDC3CLK
XTALIN
XTALOUT
M56P
M56@
XTAL
CLK_PCIE_VGA<15>
CLK_PCIE_VGA#<15>
+1.2VS
+3VS
R224
R225
OSC_IN
CLK_PCIE_VGA
CLK_PCIE_VGA#
PCIE_GTX_MRX_N15
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P0
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
R215 2K_0402_1%
1 2
R217 562_0603_1%
1 2
R218 1.47K_0603_1%
1 2
R220 0_0402_5%
1 2
R221 10K_0402_5%
1 2
4.7K_0402_5%
1 2
1 2
4.7K_0402_5%
1 2
R227 121_0402_1%
71.5_0402_1%
http://hobi-elektronika.net
D+
D-
THERM_SDA
THERM _SCL
12
R229
3
AD4
GPIO_0
AD2
GPIO
PCI EXPRESS
THERMAL
GPIO_1
AD1
GPIO_2
AD3
GPIO_3
AC1
GPIO_4
AC2
GPIO_5
AC3
GPIO_6
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
VREFG
DVPCLK
HSYNC
VSYNC
DDC1CLK
RSET
H2SYNC
V2SYNC
COMP
R2SET
ROMCS#
PLLTEST
TESTEN
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AB6
NC
AC8
AK4
AL4
AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
AK24
R
AM24
G
AL24
B
AJ23
AJ22
AH22
AH23
AK22
AF23
AL22
AK15
R2
AM15
G2
AL15
B2
AF15
AG15
AJ15
Y
AJ13
C
AH15
AK14
AC7
AG14
AG22
GPIO_7_BLON
NC_DVOVMODE_0
NC_DVOVMODE_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
VIP HOST/ EXTERNAL TMDS
DVPDATA_23
CRT
DDC1DATA
GENERICA
GENERICB
TV
R194 10K_0402_5%
R195 10K_0402_5%
R196 10K_0402_5%
R197 10K_0402_5%
R198 10K_0402_5%
R199 10K_0402_5%
R200 10K_0402_5%
R201 10K_0402_5%
R202 10K_0402_5%
POWER_SEL
OSC_SPREAD
THER_ALERT#
R203 499_0402_1%
R204 499_0402_1%
MEMID0
MEMID1
MEMID2
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
CRT_HSYNC
CRT_VSYNC
R213 4.7K_0402_5%
R214 4.7K_0402_5%
R216 1K_0402_5%
R219 499_0402_1%
VGA_TV_Y
VGA_TV_C
VGA_TV_COMP
R223 715_0402_1%
R228 1K_0402_5%
2
+3VS
1 2
1 2
@
1 2
1 2
@
1 2
@
1 2
TP1
@
1 2
X76@
1 2
X76@
1 2
12
1 2
C250
1 2
0.1U_0402_16V4Z
R205 4.7K_0402_5%
TP2
TP3
TP4
1 2
R206 4.7K_0402_5%
1 2
R207 10K_0402_5% X76@
1 2
R208 10K_0402_5% X76@
1 2
R209 10K_0402_5% X76@
1 2
VGA_CRT_R <28>
VGA_CRT_G <28>
VGA_CRT_B <28>
CRT_HSYNC <28>
12
12
12
12
CRT_VSYNC <28>
VGA_TV_Y <28>
VGA_TV_C <28>
VGA_TV_COMP <28>
1 2
1 2
GENERICA NC,GENERICB Grounded -->Internal SS
Low -> VDDC=1.2V
High -> VDDC=1.0V
POWER_SEL <53>
+3VS
+3VS
I2C_DAT
I2C_CLK
+3VS
VGA_CRT_DAT
VGA_CRT_CLK
LVDS Bus
+3VS
Need Level Shift
Straps: (Internal pull down)
Transmitter power
saving enable
Transmitter
de-emphasis enable
Debug Access GPIO[4]
ROM ID Config GPIO[9,
I2C_DAT <29>
I2C_CLK <29>
Need Level Shift
VGA_CRT_DAT <28>
VGA_CRT_CLK <28>
GPIO[0]
GPIO[1] 0: TX de-emphasis disable
GPIO[6,5]PLL_IBIAS_RD Default : 0 1
13:11]
Vedio Memory Config. (VGA Internal PD)
MEMID[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Size Vender Chips
Size
16M16 Hynix 2
64MB
64MB
16M16 Samsung 2
128MB
16M16 Hynix 4
128MB
16M16 Samsung 4
256MB
32M16 Hynix 4
256MB
32M16 Samsung 4
Resreved
Resreved
1
0: 50% TX output swing
1: Full TX output swing
1: TX de-emphasis enable
0: OFF Pad must be available
1: ON
000X: No ROM,
AP_SIZE=00
001X: No ROM,
AP_SIZE=01
010X: No ROM,
AP_SIZE=10
011X: No ROM,
AP_SIZE=11
128M share
Memory
256M share
Memory
64M share
Memory
Reserved
FrequenceVGA
A-test
A-test
TBD
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRI ETARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/10
3
Compal Secret Data
Deciphered Date
2006/09/10
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期
|, 09, 2006
三月
1
of
16 55
B
Page 17
5
U9B
AE13
GPIO_18
AF13
GPIO_19
AF9
GPIO_20
AG7
GPIO_21
AE10
GPIO_22
AE9
GPIO_23
AF7
GPIO_24
D D
+VDD_CORE
C C
B B
+VDD25
0.1U_0402_16V4Z
C267
1
2
AF8
AH6
AF10
AG10
AH9
AJ8
AH8
AG9
AH7
AG8
AE23
Y23
K15
R10
AC17
100mA
AC14
M23
V10
K18
L10
K22
100mA
AA10
1
C268
2
0.1U_0402_16V4Z
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GENERICC
BBN
BBN
BBN
BBN
BBP
BBP
BBP
BBP
VDD25
VDD25
VDD25
M56P
M56@
EXPAND GPIO
FOREARD
COMPATIBILITY
TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LN
TXCLK_LP
TXOUT_L0P
LVDS
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
VARY_BL
DIGON
GENERICD
INTERGRATED TMDS
DDC2DATA
DDC2CLK
TXCM
TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TX3M
TX3P
TX4M
TX4P
TX5M
TX5P
HPD1
4
http://hobi-elektronika.net
AJ21
AK21
AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21
AL18
AM18
AL19
AK19
AM20
AL20
AM21
AL21
AJ18
AK18
AD12
AE11
AD23
AL9
AM9
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AH13
AG13
AF11
VGA_LVDSBC+
VGA_LVDSBCVGA_LVDSB0+
VGA_LVDSB0VGA_LVDSB1+
VGA_LVDSB1VGA_LVDSB2+
VGA_LVDSB2-
VGA_LVDSACVGA_LVDSAC+
VGA_LVDSA0+
VGA_LVDSA0VGA_LVDSA1+
VGA_LVDSA1VGA_LVDSA2+
VGA_LVDSA2-
R231 10K_0402_5%
1 2
ENVDD
DVI_TXC-_L
R629 0_0402_5% DVI@
DVI_TXC+_L
R630 0_0402_5% DVI@
DVI_TX0-_L
R631 0_0402_5% DVI@
DVI_TX0+_L
R632 0_0402_5% DVI@
DVI_TX1-_L
R633 0_0402_5% DVI@
DVI_TX1+_L
R634 0_0402_5% DVI@
DVI_TX2-_L
R635 0_0402_5% DVI@
DVI_TX2+_L
R636 0_0402_5% DVI@
11/07/05"
R236 6.8K_0402_5%
1 2
R237 6.8K_0402_5%
1 2
VGA_DVI_DAT
VGA_DVI_CLK
VGA_DVI_DET
DVI_TXC-
DVI_TXC+
DVI_TX0-
DVI_TX0+
DVI_TX1-
DVI_TX1+
DVI_TX2-
DVI_TX2+
VGA_LVDSBC+ <29>
VGA_LVDSBC- <29>
VGA_LVDSB0+ <29>
VGA_LVDSB0- <29>
VGA_LVDSB1+ <29>
VGA_LVDSB1- <29>
VGA_LVDSB2+ <29>
VGA_LVDSB2- <29>
VGA_LVDSAC- <29>
VGA_LVDSAC+ <29>
VGA_LVDSA0+ <29>
VGA_LVDSA0- <29>
VGA_LVDSA1+ <29>
VGA_LVDSA1- <29>
VGA_LVDSA2+ <29>
VGA_LVDSA2- <29>
ENBKL <33>
ENVDD <29>
10/20/05"
12
12
12
12
12
12
12
12
+3VS
R232 180_0402_5%DVI@
1 2
R233 180_0402_5%DVI@
1 2
R234 180_0402_5%DVI@
1 2
R235 180_0402_5%DVI@
1 2
10/20/05"
Close to connector
3
To EC
DVI_TXC-
DVI_TXC+
DVI_TX0-
DVI_TX0+
DVI_TX1-
DVI_TX1+
DVI_TX2-
DVI_TX2+
Need Level
Shift
VGA_DVI_DAT <30>
VGA_DVI_CLK <30>
VGA_DVI_DET <30>
AH27
AC23
AL27
R23
P25
R25
T26
U26
Y26
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
Y28
U28
P28
AH29
AF28
V29
AC29
W27
AB27
V26
AJ26
AJ32
AK29
P26
P29
R29
T29
U29
W29
Y29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
N30
R31
AF30
AC30
V31
P30
AA31
U30
AD31
AK32
AJ28
Y30
AJ30
AK31
DVI_TXC- <30>
DVI_TXC+ <30>
DVI_TX0- <30>
DVI_TX0+ <30>
DVI_TX1- <30>
DVI_TX1+ <30>
DVI_TX2- <30>
DVI_TX2+ <30>
U9G
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
M56P
M56@
PCIE GND
TXVSSR
TXVSSR
TXVSSR
TXVSSR
TXVSSR
TPVSS
TMDS GNDCRT GNDTV GNDPLL GNDLVD S PLL&I/O GND
AVSSQ
AVSSN
AVSSN
VSS1DI
A2VSSQ
A2VSSN
A2VSSN
VSS2DI
MPVSS
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
PCIE_PVSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PVSS
LPVSS
2
AJ7
AK7
AL7
AM7
AK8
AL8
AK23
AK25
AJ24
AL23
AK13
AM17
AL17
AJ17
AH14
A5
AE18
AK17
AJ19
AF18
AH17
AG17
AG19
AH19
AF22
AF17
AF21
W23
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
AG31
W26
N24
AA23
Use 15mils trace
connect to GND
AD7
AE8
AL1
AM2
AD10
K10
E12
AC9
AF14
AD8
AA4
AG11
AG16
AD16
AA6
AD17
AH11
C10
AM13
AC10
AL13
A11
U10
AD6
AD14
AD13
D11
K12
A13
E13
K16
W18
1
U9F
B1
VSS
H1
VSS
L1
VSS
P1
VSS
U1
VSS
Y1
VSS
VSS
VSS
VSS
A2
VSS
VSS
VSS
E8
VSS
H5
VSS
VSS
M8
VSS
T10
VSS
VSS
VSS
VSS
VSS
C5
VSS
F10
VSS
J3
VSS
L6
VSS
M6
VSS
P6
VSS
VSS
VSS
V3
VSS
VSS
CORE
R3
VSS
C6
VSS
C9
VSS
F6
VSS
H7
VSS
GND
J6
VSS
VSS
VSS
P7
VSS
P5
VSS
M3
VSS
M9
VSS
L7
VSS
M7
VSS
VSS
VSS
A8
VSS
U7
VSS
VSS
E9
VSS
F3
VSS
J9
VSS
N7
VSS
N3
VSS
Y5
VSS
VSS
VSS
Y6
VSS
U6
VSS
E5
VSS
VSS
VSS
U8
VSS
U9
VSS
VSS
R6
VSS
VSS
V6
VSS
VSS
VSS
VSS
J12
VSS
VSS
VSS
F13
VSS
VSS
F15
VSS
VSS
VSS
M56P
M56@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16
K23
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRI ETARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/10
3
Compal Secret Data
Deciphered Date
2006/09/10
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期
|, 09, 2006
三月
1
of
17 55
B
Page 18
5
U9C
M31
DQA_0
M30
DQA_1
L31
DQA_2
L30
DQA_3
H30
DQA_4
G31
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
MVREFD_0
MVREFS_0
M56P
M56@
MEMORY A
G30
F31
M27
M29
H29
G29
G27
M26
M25
G28
H27
H26
G26
H25
H24
H23
H22
E23
D22
D23
E22
E20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
E15
E14
D13
H18
H17
G18
G17
G15
G14
H14
C31
C30
L28
L27
J27
L26
L25
J25
F26
J23
J22
F20
F17
F14
J14
D D
C C
T32PAD
B B
T33PAD
Modify 11/22
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMA#_0
DQMA#_1
DQMA#_2
DQMA#_3
DQMA#_4
DQMA#_5
DQMA#_6
DQMA#_7
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0#
QSA_1#
QSA_2#
QSA_3#
QSA_4#
QSA_5#
QSA_6#
QSA_7#
ODTA0
ODTA1
CLKA0
CLKA0#
CKEA0
RASA0#
CASA0#
WEA0#
CSA0#_0
CSA0#_1
CLKA1
CLKA1#
CKEA1
RASA1#
CASA1#
WEA1#
CSA1#_0
CSA1#_1
D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
B25
C25
E27
E29
H31
J29
J26
G23
E21
B15
D14
J17
J31
K29
K25
F23
D20
B16
D16
H15
K31
K28
K26
G24
D21
C16
D15
J15
F29
D24
D31
E31
B30
B28
C29
B31
B29
C28
B20
C19
C22
B24
B22
B21
B23
C23
4
http://hobi-elektronika.net
FBCD[0..63]<20,21>
FBCA[0..12]<20,21>
FBCDQS[0..7]<20,21>
FBCDQS#[0..7]<20,21>
FBCDQM#[0..7]<20,21>
FBC_BA0<20,21>
FBC_BA1<20,21>
FBCCLK0
FBCCLK0#
FBCCLK1
FBCCLK1#
12
R238
100_0402_1%
1
C270
2
0.1U_0402_16V4Z
R637 56_0402_5%
R638 56_0402_5%
R639 56_0402_5%
R640 56_0402_5%
10/20/05"
Close to Memory Side
+MVREFD_1
(15mils)
12
R242
100_0402_1%
12
12
64BIT@
12
64BIT@
12
3
FBCD[0..63]
FBCA[0..12]
FBCDQS[0..7]
FBCDQS#[0..7]
FBCDQM#[0..7]
FBC_BA0
FBC_BA1
1 2
470P_0402_50V7K
1 2
470P_0402_50V7K
+1.8VS+1.8VS
C269
C804
C805
64BIT@
12
R239
100_0402_1%
1
2
0.1U_0402_16V4Z
(15mils)
12
R240
100_0402_1%
R241
1 2
4.7K_0402_5%
R243
1 2
4.7K_0402_5%
R244
1 2
4.7K_0402_5%
R245
1 2
243_0603_1%
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
+MVREFD_1
+MVREFS_1
MEM_RST
MEMTEST
(15mil)
2
B12
C12
B11
C11
F12
D12
E11
F11
G12
G11
H12
H11
AA3
AA5
AA2
AA7
C8
B7
C7
B6
F9
D8
D7
F7
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
B3
C3
U9D
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MVREFD_1
MVREFS_1
DRAM_RST
TEST_MCLK
TEST_YCLK
MEMTEST
M56P
M56@
MEMORY B
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
DQMB#_0
DQMB#_1
DQMB#_2
DQMB#_3
DQMB#_4
DQMB#_5
DQMB#_6
DQMB#_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
QSB_0#
QSB_1#
QSB_2#
QSB_3#
QSB_4#
QSB_5#
QSB_6#
QSB_7#
ODTB0
ODTB1
CLKB0
CLKB0#
CKEB0
RASB0#
CASB0#
WEB0#
CSB0#_0
CSB0#_1
CLKB1
CLKB1#
CKEB1
RASB1#
CASB1#
WEB1#
CSB1#_0
CSB1#_1
G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
H2
H3
F5
D5
B8
D9
G9
K7
M5
V2
W4
T9
B9
D10
H10
K6
N4
U2
U4
V8
B10
E10
G10
J7
M4
U3
V4
V9
D6
J4
B4
B5
C2
E2
D3
B2
D2
E3
N2
P3
L3
J2
L2
M2
K2
K3
FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBC_BA0
FBC_BA1
FBCA12
FBCDQM#0
FBCDQM#1
FBCDQM#2
FBCDQM#3
FBCDQM#4
FBCDQM#5
FBCDQM#6
FBCDQM#7
FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7
FBCDQS#0
FBCDQS#1
FBCDQS#2
FBCDQS#3
FBCDQS#4
FBCDQS#5
FBCDQS#6
FBCDQS#7
FBCODT0
FBCODT1
FBCCLK0
FBCCLK0#
FBC_CKE0
FBCRAS0#
FBCCAS0#
FBCWE0#
FBCCS0#
FBCCLK1
FBCCLK1#
FBC_CKE1
FBCRAS1#
FBCCAS1#
FBCWE1#
FBCCS1#
1
FBCODT0 <20>
FBCODT1 <21>
FBCCLK0 <20>
FBCCLK0# <20>
FBC_CKE0 <20>
FBCRAS0# <20>
FBCCAS0# <20>
FBCWE0# <20>
FBCCS0# <20>
FBCCLK1 <21>
FBCCLK1# <21>
FBC_CKE1 <21>
FBCRAS1# <21>
FBCCAS1# <21>
FBCWE1# <21>
FBCCS1# <21>
A A
GDDR2
5
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRI ETARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/10
3
Compal Secret Data
Deciphered Date
2006/09/10
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期
|, 09, 2006
三月
1
of
18 55
B
Page 19
5
C272
0.1U_0402_16V4Z
C281
+1.8VS
2
C357
1
0.1U_0402_16V4Z
+2.5VS
+VDDRH1
2
1
0.1U_0402_16V4Z
C284
0.1U_0402_16V4Z
C294
0.1U_0402_16V4Z
C297
0.1U_0402_16V4Z
C304
0.1U_0402_16V4Z
C311
0.1U_0402_16V4Z
C318
0.1U_0402_16V4Z
C324
0.1U_0402_16V4Z
C330
0.1U_0402_16V4Z
2
1
1 2
BLM15AG121SN1D_0402
2
C356
0.1U_0402_16V4Z
1
D D
C C
B B
L13
1 2
+2.5VS
BLM15AG121SN1D_0402
A A
+1.8VS
1 2
BLM18PG121SN1D_0603
22U_0805_6.3V6M
5
22U_0805_6.3V6M
L60
C922
+1.8VS
C271220U_D2_4VM@
12
+
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
L12
1 2
BLM18PG121SN1D_0603
22U_0805_6.3V6M
C358
22U_0805_6.3V6M
L17
4
C273
1 2
0.1U_0402_16V4Z
C282
1 2
0.1U_0402_16V4Z
C285
1 2
0.1U_0402_16V4Z
C295
1 2
0.1U_0402_16V4Z
C298
1 2
0.1U_0402_16V4Z
C305
1 2
0.1U_0402_16V4Z
C312
1 2
0.1U_0402_16V4Z
C319
1 2
0.1U_0402_16V4Z
C325
1 2
0.1U_0402_16V4Z
C331
1 2
0.1U_0402_16V4Z
C336
1 2
0.1U_0402_16V4Z
C339
1 2
0.1U_0402_16V4Z
C345
1 2
0.1U_0402_16V4Z
+VDDRH0
2
1
+AVDD
BLM15AG121SN1D_0402
+2.5VS
C360 0.1U_0402_16V4Z
2
C364
1
0.1U_0402_16V4Z
4
1000mA for GDDR1
2400mA for GDDR3
C274
1 2
22U_0805_6.3V6M
C283
1 2
22U_0805_6.3V6M
C286
1 2
0.1U_0402_16V4Z
C296
1 2
0.1U_0402_16V4Z
C299
1 2
0.1U_0402_16V4Z
C306
1 2
0.1U_0402_16V4Z
C313
1 2
0.1U_0402_16V4Z
C320
1 2
0.1U_0402_16V4Z
C326
1 2
0.1U_0402_16V4Z
C332
1 2
22U_0805_6.3V6M
C337
1 2
0.1U_0402_16V4Z
C340
1 2
0.1U_0402_16V4Z
C346
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C354
1
L15
1 2
12
+A2VDD
2
C365
1
0.1U_0402_16V4Z
C355
3
http://hobi-elektronika.net
+1.8VS
+3VS+3VS
400mA
50mA
100mA
?mA
+VDDRH1
100mA
50mA
+VDD1DI
120mA
50mA
+VDD1DI
C370
U9E
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR5
VDDR5
VDDR5
VDDR5
VDDRH0
VDDRH1
VSSRH0
VSSRH1
AVDD
AVDD
VDD1DI
A2VDD
A2VDD
NC_A2VDDQ
VDD2DI
M56P
M56@
POWER
PCI EXPRESSCOREI/O INTERNALLVDS PLL, I/O
MEMORY I/OI/O
CLOCK
MEM I/O
CRT
TMDS
TV
PLL
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDD25
VDD25
VDD25
VDDPLL
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
LPVDD/VDDL0
LVDDR/VDDL0
LVDDR/VDDL0
LVDDR/VDDL0
LVDDR/VDDL1
LVDDR/VDDL1
LVDDR/VDDL1
LVDDR/VDDL2
LVDDR/VDDL2
LVDDR/VDDL2
TPVDD
TXVDDR
TXVDDR
TXVDDR
TXVDDR
PVDD
MPVDD
C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9
Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32
F32
L32
AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20
AJ5
AM5
AL5
AK5
AE2
AE3
AE4
AE5
A27
F1
A28
E1
AL25
AM25
AM23
AM16
AL16
AL14
AJ16
2
1
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRI ETARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/10
3
100mA
V23
N23
P23
U23
1500mA
N29
N28
N27
N26
N25
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
100mA
AC13
AC16
AC18
60mA
AC15
500mA
W10
T14
W17
P16
T23
K14
U19
20mA
AE19
300mA
AF20
AE20
AF19
AC21
AC22
AD22
AE21
AD21
AE22
60mA
AM8
150mA
AJ6
AK6
AL6
AM6
160mA
AJ14
240mA
A6
22U_0805_6.3V6M
Compal Secret Data
2
+1.2VS
1U_0402_6.3V4Z
2
C275
1
22U_0805_6.3V6M
2
1
+VDD_CORE +VDD_CORE +VDD_CORE
C300
1 2
22U_0805_6.3V6M
C307
1 2
22U_0805_6.3V6M
C314
1 2
22U_0805_6.3V6M
C321
1 2
22U_0805_6.3V6M
C327
1 2
0.1U_0402_16V4Z
+VDDPLL
2
@
C808
1
22U_0805_6.3V6M
+LPVDD
0.1U_0402_16V4Z
2
1
22U_0805_6.3V6M
+LPVDD
22U_0805_6.3V6M
+MPVDD
2
C368
1
Deciphered Date
1U_0402_6.3V4Z
2
C276
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C288
C287
1
22U_0805_6.3V6M
VDDC+VDDCI=18A
C301
0.1U_0402_16V4Z
C308
0.1U_0402_16V4Z
C315
0.1U_0402_16V4Z
C322
0.1U_0402_16V4Z
C328
0.1U_0402_16V4Z
L10
1 2
BLM15AG121SN1D_0402
2
C338
0.1U_0402_16V4Z
1
+VDDCI
C347
12
0.1U_0402_16V4Z
2
C349
C348
1
0.1U_0402_16V4Z
2
2
1
2
1
C362
C361
1
0.1U_0402_16V4Z
L18
1 2
BLM15AG121SN1D_0402
C369
0.1U_0402_16V4Z
2
C277
1
2
C289
1
1U_0402_6.3V4Z
1 2
1 2
1 2
1 2
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C350
1
2
C363
0.1U_0402_16V4Z
1
+VDD_CORE
1U_0402_6.3V4Z
2
C278
1
1U_0402_6.3V4Z
0.1U_0402_16V4Z
2
C290
1
+1.2VS
2
1
2
C351
1
0.1U_0402_16V4Z
+2.5VS
2006/09/10
2
+PCIE_PVDD
2
C279
1
2
C291
1
0.1U_0402_16V4Z
C302
1 2
0.1U_0402_16V4Z
C309
1 2
0.1U_0402_16V4Z
C316
1 2
0.1U_0402_16V4Z
C323
1 2
0.1U_0402_16V4Z
C329
1 2
0.1U_0402_16V4Z
22U_0805_6.3V6M
2
1
0.1U_0402_16V4Z
2
C342
C341
1
0.1U_0402_16V4Z
+LVDDR
2
C352
1
2
1
22U_0805_6.3V6M
2
1
22U_0805_6.3V6M
0.1U_0402_16V4Z
2
C292
1
2
C333
1
0.1U_0402_16V4Z
2
1
2
C353
0.1U_0402_16V4Z
1
BLM15AG121SN1D_0402
1
C359
0.1U_0402_16V4Z
2
+PVDD
2
C366
1
L47
1 2
BLM18PG121SN1D_0603
C280
+PCIE_VDDR
2
1
C303
1 2
0.1U_0402_16V4Z
C310
1 2
0.1U_0402_16V4Z
C317
@
C334
C343
0.1U_0402_16V4Z
1 2
BLM18PG121SN1D_0603
L14
1 2
1 2
BLM15AG121SN1D_0402
C367
0.1U_0402_16V4Z
Title
Size Document Number Rev
Custom
Date: Sheet
2
C293
220U_D2_4VM
+VDD25
2
1
C806
1
0.1U_0402_16V4Z
12
+
L9
1 2
MBK1608301YZF_0603
2
C335
0.1U_0402_16V4Z
1
L11
1 2
BLM18PG121SN1D_0603
C344
Modify 11/18
L71
L16
+2.5VS
+2.5VS
+2.5VS
Compal Electronics, Inc.
401412
星期
|, 09, 2006
三月
1
10/20/05"
For PCIE_PVDD_12 only
L need close to chip
+1.2VS
0.1U_0402_16V4Z
2
1
1 2
C807
10/20/05"
+2.5VS
+VDD_CORE
R641
0_0805_5%
SCHEMATIC, M/B LA-3151P
of
19 55
1
B
Page 20
5
4
3
2
1
http://hobi-elektronika.net
11/03/05' SWAP NET
11/04/05' SWAP NET
11/08/05' SWAP NET
U12
L2
BA0
L3
D D
C C
+1.8VS
12
12
R247
1K_0402_1%
1
C375
0.047U_0402_16V4Z
2
+VRAM_VREFC
R248
1K_0402_1%
FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0
FBCCLK0#
FBCCLK0
FBC_CKE0
FBCCS0#
FBCWE0#
FBCRAS0#
FBCCAS0#
FBCDQM#1
FBCDQM#3
FBCODT0
FBCDQS1
FBCDQS#1
FBCDQS3
FBCDQS#3
Close to U12
B B
0.01U_0402_16V7K
1
C377
2
1000P_0402_50V7K
A A
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621AFP-25X76@
DDR2 BGA MEMORY DDR2 BGA MEMORY
1
1
C379
C378
2
2
0.01U_0402_16V7K
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
0.1U_0402_16V4Z
1
C380
2
1U_0402_6.3V4Z
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSS1
VSS2
VSS3
VSS4
VSS5
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
0.1U_0402_16V4Z
1
C381
2
FBCD26
FBCD30
FBCD24
FBCD29
FBCD28
FBCD27
FBCD31
FBCD25
FBCD11
FBCD14
FBCD9
FBCD15
FBCD13
FBCD10
FBCD12
FBCD8
1
2
1
C382
2
0.1U_0402_16V4Z
+1.8VS
C371
0.1U_0402_16V4Z
1
1
C383
2
2
1
C372
1U_0402_6.3V4Z
2
C384
0.01U_0402_16V7K
+VRAM_VREFC
1
C376
0.047U_0402_16V4Z
2
Close to U13
1000P_0402_50V7K
(SSTL-1.8) VREF = .5*VDDQ(SSTL-1.8) VREF = .5*VDDQ
+1.8VS+1.8VS
1
C385
2
FBC_BA0FBC_BA0
FBC_BA1FBC_BA1
FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0
FBCCLK0#
FBCCLK0
FBC_CKE0
FBCCS0#
FBCWE0#
FBCRAS0#
FBCCAS0#
FBCDQM#0
FBCDQM#2
FBCODT0
FBCDQS0
FBCDQS#0
FBCDQS2
FBCDQS#2
0.01U_0402_16V7K
1
C386
2
0.01U_0402_16V7K
L2
L3
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
K8
J8
K2
L8
K3
K7
L7
F3
B3
K9
F7
E8
B7
A8
J2
A2
E2
L1
R3
R7
R8
0.1U_0402_16V4Z
1
C387
2
U13
BA0
BA1
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
ODT
LDQS
LDQS
UDQS
UDQS
VREF
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
HY5PS561621AFP-25X76@
1
C388
2
VDDQ10
VSSQ10
1
C389
2
1U_0402_6.3V4Z
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
A9
VDDQ1
C1
VDDQ2
C3
VDDQ3
C7
VDDQ4
C9
VDDQ5
E9
VDDQ6
G1
VDDQ7
G3
VDDQ8
G7
VDDQ9
G9
A1
VDD1
E1
VDD2
J9
VDD3
M9
VDD4
R1
VDD5
J1
VDDL
J7
VSSDL
A7
VSSQ1
B2
VSSQ2
B8
VSSQ3
D2
VSSQ4
D8
VSSQ5
E7
VSSQ6
F2
VSSQ7
F8
VSSQ8
H2
VSSQ9
H8
A3
VSS1
E3
VSS2
J3
VSS3
N1
VSS4
P9
VSS5
0.1U_0402_16V4Z
1
C390
2
11/03/05' SWAP NET
FBCD20
FBCD17
FBCD18
FBCD23
FBCD22
FBCD19
FBCD21
FBCD16
FBCD7
FBCD0
FBCD6
FBCD3
FBCD2
FBCD5
FBCD1
FBCD4
1
C373
0.1U_0402_16V4Z
2
1
1
C391
C392
0.01U_0402_16V7K
2
0.1U_0402_16V4Z
2
+1.8VS
1
C374
1U_0402_6.3V4Z
2
FBCD[0..63]<18,21>
FBCA[0..12]<18,21>
FBCDQS[0..7]<18,21>
FBCDQS#[0..7]<18,21>
FBCDQM#[0..7]<18,21>
FBCODT0
FBC_CKE0
FBCRAS0#
FBCCAS0#
FBCWE0#
FBCCS0#
FBC_BA0
FBC_BA1
FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0
FBCODT0<18>
FBC_CKE0<18>
FBCRAS0#<18>
FBCCAS0#<18>
FBCWE0#<18>
FBCCS0#<18>
FBCCLK0<18>
FBCCLK0#<18>
FBC_BA0<18,21>
FBC_BA1<18,21>
R249 56_0402_5%M56@
R250 56_0402_5%M56@
R251 56_0402_5%M56@
R252 56_0402_5%M56@
R253 56_0402_5%M56@
R254 56_0402_5%M56@
R255 56_0402_5%M56@
R256 56_0402_5%M56@
R257 56_0402_5%M56@
R258 56_0402_5%M56@
R259 56_0402_5%M56@
R260 56_0402_5%M56@
R261 56_0402_5%M56@
R262 56_0402_5%M56@
R263 56_0402_5%M56@
R264 56_0402_5%M56@
R265 56_0402_5%M56@
R266 56_0402_5%M56@
R267 56_0402_5%M56@
R268 56_0402_5%M56@
R269 56_0402_5%M56@
M56 Only
FBCD[0..63]
FBCA[0..12]
FBCDQS[0..7]
FBCDQS#[0..7]
FBCDQM#[0..7]
FBC_BA0
FBC_BA1
FBCODT0
FBC_CKE0
FBCRAS0#
FBCCAS0#
FBCWE0#
FBCCS0#
FBCCLK0
FBCCLK0#
+0.9VS
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
401412
星期四 三月
1
B
of
20 55, 09, 2006
Page 21
5
4
3
2
1
http://hobi-elektronika.net
11/03/05' SWAP NET 11/03/05' SWAP NET
U14
L2
BA0
L3
D D
C C
+1.8VS
12
12
R270
1K_0402_1%
64BIT@
1
C397
0.047U_0402_16V4Z
64BIT@
2
Close to U14 Close to U15
+VRAM_VREFD
R271
1K_0402_1%
64BIT@
FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0
FBCCLK1#
FBCCLK1
FBC_CKE1
FBCCS1#
FBCWE1#
FBCRAS1#
FBCCAS1#
FBCDQM#6
FBCDQM#4
FBCODT1
FBCDQS6
FBCDQS#6
FBCDQS4
FBCDQS#4
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621AFP-25X76@
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
FBCD32
B9
FBCD39
B1
FBCD34
D9
FBCD37
D1
FBCD38
D3
FBCD33
D7
FBCD36
C2
FBCD35
C8
FBCD49
F9
FBCD55
F1
FBCD50
H9
FBCD53
H1
FBCD54
H3
FBCD48
H7
FBCD52
G2
FBCD51
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
1
C393
0.1U_0402_16V4Z
64BIT@
2
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
1
C394
1U_0402_6.3V4Z
64BIT@
2
+VRAM_VREFD
1
C398
0.047U_0402_16V4Z
64BIT@
2
FBC_BA0FBC_BA0
FBC_BA1FBC_BA1
FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0
FBCCLK1#
FBCCLK1
FBC_CKE1
FBCCS1#
FBCWE1#
FBCRAS1#
FBCCAS1#
FBCDQM#5
FBCDQM#7
FBCODT1
FBCDQS5
FBCDQS#5
FBCDQS7
FBCDQS#7
(SSTL-1.8) VREF = .5*VDDQ(SSTL-1.8) VREF = .5*VDDQ
U15
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
HY5PS561621AFP-25X76@
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
FBCD62
B9
FBCD58
B1
FBCD63
D9
FBCD56
D1
FBCD57
D3
FBCD61
D7
FBCD59
C2
FBCD60
C8
FBCD45
F9
FBCD41
F1
FBCD47
H9
FBCD42
H1
FBCD43
H3
FBCD46
H7
FBCD40
G2
FBCD44
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
1
C395
0.1U_0402_16V4Z
64BIT@
2
+1.8VS+1.8VS
1
C396
1U_0402_6.3V4Z
64BIT@
2
FBCD[0..63]<18,20>
FBCA[0..12]<18,20>
FBCDQS[0..7]<18,20>
FBCDQS#[0..7]<18,20>
FBCDQM#[0..7]<18,20>
FBC_BA0<18,20>
FBC_BA1<18,20>
FBCODT1<18>
FBC_CKE1<18>
FBCRAS1#<18>
FBCCAS1#<18>
FBCWE1#<18>
FBCCS1#<18>
FBCCLK1<18>
FBCCLK1#<18>
FBCD[0..63]
FBCA[0..12]
FBCDQS[0..7]
FBCDQS#[0..7]
FBCDQM#[0..7]
FBC_BA0
FBC_BA1
FBCODT1
FBC_CKE1
FBCRAS1#
FBCCAS1#
FBCWE1#
FBCCS1#
FBCCLK1
FBCCLK1#
B B
+1.8VS
1
C399
2
1000P_0402_50V7K
DDR2 BGA MEMORY DDR2 BGA MEMORY
0.01U_0402_16V7K
1
C400
2
0.01U_0402_16V7K
0.1U_0402_16V4Z
1
C401
2
1
C402
2
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
C403
2
1
C404
2
0.1U_0402_16V4Z
1
2
C405
1
C406
0.01U_0402_16V7K
2
+1.8VS
0.01U_0402_16V7K
1
C407
2
1000P_0402_50V7K
1
C408
2
0.01U_0402_16V7K
0.1U_0402_16V4Z
1
C409
2
1
C410
2
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
C411
2
1
C412
2
0.1U_0402_16V4Z
1
2
C413
1
C414
0.01U_0402_16V7K
2
FBCRAS1#
FBC_CKE1
FBCODT1
FBCCAS1#
FBCWE1#
FBCCS1#
+0.9VS
R273 56_0402_5%M56@
12
R274 56_0402_5%M56@
12
R275 56_0402_5%M56@
12
R276 56_0402_5%M56@
12
R277 56_0402_5%M56@
12
R278 56_0402_5%M56@
12
M56 Only
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
401412
星期四 三月
1
B
of
21 55, 09, 2006
Page 22
PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO U600
D D
FOR SB600 VCC_SB= 1.2V
FOR SB460 VCC_SB= 1.8V
R294 CALRP: SB600=562R 1%, SB460=150R 1%
R295 CALRN: SB600=2.05K 1%, SB460=150R 1%
R296 CALRN: SB600=0R 1%, SB460=4.12K 1%
+1.8VS
KC FBM-L11-201209-221LMAT_0805
C C
B B
A A
+1.8VS
KC FBM-L11-201209-221LMAT_0805
RP1
1 8
+3VS
2 7
3 6
4 5
8.2K_1206_8P4R_5%
LPC_DRQ#0
LPC_DRQ#1
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
SERIRQ
5
SBSRC_CLKP<15>
SBSRC_CLKN<15>
A_MRX_STX_P0<12>
A_MRX_STX_N0<12>
A_MRX_STX_P1<12>
A_MRX_STX_N1<12>
L19
1 2
L20
1 2
FOR SB600, CONNECT TO CPU_PG/LDT_PG
FOR SB460, CONNECT TO SSMUXSEL/GPIO0
PCI_SERR#
PCI_TRDY#
PCI_FRAME#
PCI_STOP#
SB460 ONLY
R299 10K_0402_5%
1 2
R300 10K_0402_5%
1 2
R301 100K_0402_5%
1 2
R302 100K_0402_5%
1 2
R304 100K_0402_5%
1 2
R305 100K_0402_5%
1 2
R306 10K_0402_5%
1 2
1
2
22U_0805_6.3V6M
R303
20M_0603_5%
C429
10P_0402_50V8K
1 2
1 2
C430
10P_0402_50V8K
C423
1U_0402_6.3V4Z
12
ALLOW_LDTSTOP<13>
+1.2V_HT
A_MRX_STX_P0
A_MRX_STX_N0
A_MRX_STX_P1
A_MRX_STX_N1
A_MTX_C_SRX_P0<12>
A_MTX_C_SRX_N0<12>
A_MTX_C_SRX_P1<12>
A_MTX_C_SRX_N1<12>
C608 AND C609 CLOSE
TO U600.U29
1
C424
2
20M_0603_5%
R298
1 2
+3VS
C415 0.01U_0402_16V7K
1 2
C416 0.01U_0402_16V7K
1 2
C417 0.01U_0402_16V7K
1 2
C418 0.01U_0402_16V7K
1 2
PCIE_VDDR
1
C421
10U_0805_10V4Z
1
C425
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Y2
4
OUT
1
IN
32.768KHZ_12.5PF_6H03200468
PLACE THES E CO MP ONENTS CLO SE TO U600 , AND
USE GROUND GUARD FOR 32K_X1 AND 32K_X2
R777 10K_0402_5%@
1 2
2
1
C426
2
NC
NC
1U_0402_6.3V4Z
1
C427
2
1U_0402_6.3V4Z
3
2
R289 49.9_0402_1%@
R290 49.9_0402_1%@
R291 49.9_0402_1%@
R293 49.9_0402_1%@
R294 150_0402_1%
R295 150_0402_1%
R296 4.12K_0402_1%
PCIE_VDDR
LPC PULL UPS
5
4
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
C422
2
1
C428
1U_0402_6.3V4Z
2
32K_X1
32K_X2
LDT_RST#<7>
FOR SB460, THIS BALL
IS LDT_RST# ONLY
4
A_RST#
A_MRX_C_STX_P0
A_MRX_C_STX_N0
A_MRX_C_STX_P1
A_MRX_C_STX_N1
A_MTX_C_SRX_P0
A_MTX_C_SRX_N0
A_MTX_C_SRX_P1
A_MTX_C_SRX_N1
PCIE_VDDR
3
U16A
http://hobi-elektronika.net
AG10
A_RST#
J24
PCIE_RCLKP
J25
PCIE_RCLKN
P29
PCIE_TX0P
P28
PCIE_TX0N
M29
PCIE_TX1P
M28
PCIE_TX1N
K29
PCIE_TX2P
K28
PCIE_TX2N
H29
PCIE_TX3P
H28
PCIE_TX3N
T25
PCIE_RX0P
T26
PCIE_RX0N
T22
PCIE_RX1P
T23
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
32K_X1
32K_X2
PCIE_RX1N
M25
PCIE_RX2P
M26
PCIE_RX2N
M22
PCIE_RX3P
M23
PCIE_RX3N
E29
PCIE_CALRP
E28
PCIE_CALRN
E27
PCIE_CALI
U29
PCIE_PVDD
U28
NC
F27
PCIE_VDDR_1
F28
PCIE_VDDR_2
F29
PCIE_VDDR_3
G26
PCIE_VDDR_4
G27
PCIE_VDDR_5
G28
PCIE_VDDR_6
G29
PCIE_VDDR_7
J27
PCIE_VDDR_8
J29
PCIE_VDDR_9
L25
PCIE_VDDR_10
L26
PCIE_VDDR_11
L29
PCIE_VDDR_12
N29
PCIE_VDDR_13
D2
X1
C1
X2
AC26
CPU_PG
W26
INTR/LINT0
W24
NMI/LINT1
W25
INIT#
AA24
SMI#
AA23
NC
AA22
IGNNE#
AA26
A20M#
Y27
FERR#
AA25
STPCLK#/ALLOW_LDTSTP
AH9
CPU_STP#/DPSLP_3V#
B24
NC
W23
DPRSLPVR
AC25
LDT_RST#/DPRSTP#/PROCHOT#
218S4RASA11GS SB460_BGA549
SB460
Part 1 of 4
PCI EXPRESS INTERFACE
REQ4#/PLL_BP33/PDMA_REQ1#
GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#
XTAL
CPU
RTC_IRQ#/ACPWR_STRAP
PCI CLKS
SPDIF_OUT/GPIO41
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
DEVSEL#/ROMA0
PCI INTERFACE
TRDY#/ROMOE#
PAR/ROMA19
REQ3#/PDMA_REQ0#
CLKRUN#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
LFRAME#
LPC
RTC_GND
RTC
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCIRST#
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE3#
FRAME#
IRDY#
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
GNT0#
GNT1#
GNT2#
LOCK#
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#
BMREQ#
SERIRQ
RTCCLK
VBAT
U2
T2
U1
V2
W3
U3
V1
T1
AJ9
W7
Y1
W8
W5
AA5
Y3
AA6
AC5
AA7
AC3
AC7
AJ7
AD4
AB11
AE6
AC9
AA3
AJ4
AB1
AH4
AB2
AJ3
AB3
AH3
AC1
AH2
AC2
AH1
AD2
AG2
AD1
AG1
AB9
AF9
AJ5
AG3
AA2
AH6
AG5
AA1
AF7
Y2
AG8
AC11
AJ8
AE2
AG9
AH8
AH5
AD11
AF2
AH7
AB12
AG4
AG7
AF6
AD3
AF1
AF4
AF3
AG24
AG25
AH24
AH25
AF24
AJ24
AH26
W22
AF23
D3
F5
E1
D1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
CLK_PCI_LAN_R
CLK_PCI_LPC_R
CLK_PCI_MINI_R
CLK_PCI_PCM_R
CLK_PCI_1394_R
CLK_PCI_SIO_R
PCI_CLK6_R
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_I RDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PM_CLKRUN#
PCI_PLOCK#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
BMREQ#
R280 22_0402_5%
1 2
R281 22_0402_5%@
1 2
R282 22_0402_5%@
1 2
R283 22_0402_5%@
1 2
R284 22_0402_5%@
1 2
R285 22_0402_5%@
1 2
R286 22_0402_5%
1 2
R287 0_0402_5%
1 2
PCI_AD[31..0]
+3VS +3VS
12
L68
FBM-L11-160808-800LMT_0603
R839
C944
1
1U_0402_6.3V4Z
2
PCI_CBE#[3..0]
PCI_FRAME# <31,36,37,40>
PCI_DEVSEL# <31,36,37,40>
PCI_IRDY# <31,36, 37, 40>
PCI_TRDY# <31,36,37,40>
PCI_PAR <31,36,37, 40>
PCI_STOP# <31,36,37,40>
PCI_PER R # <31, 36, 37, 40>
PCI_SER R# <31,36,37>
PCI_REQ#0 <40>
PCI_REQ#1 <36>
PCI_REQ#2 <37>
PCI_REQ#3 <31>
PCI_GNT#0 <40>
PCI_GNT#1 <36>
PCI_GNT#2 <37>
PCI_GNT#3 <31>
PM_CLKRUN# <31,36,41>
PCI_PIRQE# <37,40>
PCI_PIRQF# <31>
PCI_PIRQG# <36>
PCI_P IRQH# <36,37>
LPC_AD0 <33,41>
LPC_AD1 <33,41>
LPC_AD2 <33,41>
LPC_AD3 <33,41>
LPC_FRAME# <26,33,41>
LPC_DRQ#0 <41>
BMREQ# <13>
SERIRQ <33,37,41>
RTC_CLK <26>
VBAT_IN
1
C431
2
1U_0402_6.3V4Z
2005/03/08 2006/03/08
RTC_IRQ# <26>
1
C432
0.1U_0402_16V4Z
2
JOPEN1
2
112
JUMP_43X39 @
Please Closed RAM
Door
Compal Secret Data
PCIRST#
PCI_AD[31..0] <26,31,36,37,40>
CLK_PCI_LAN_R
1 2
10K_0402_5%
PCI_CBE# [3..0] <31,36,37,40>
R307
1K_0603_5%
R308
0_0603_5%
1 2
Deciphered Date
12
12
2
CLK_PCI_LAN <31>
CLK_PCI_LPC <33>
CLK_PCI_MINI <36>
CLK_PCI_PCM <37>
CLK_PCI_1394 <40>
CLK_PCI_SIO <41>
PCI_CLK6 <26>
SB_SPDIFO <26>
EMI 11/2 Modify
R834
10K_0402_5%
U59
@
8
DLY CNTRL
1
CLKIN
3
VDD
13
VDD
9
SSON
4
SS%
5
GND
12
GND
R842
ASM3P623S00EF-16-TR_TSSOP16
10K_0402_5%
A_RST#
PCIRST#
R297
8.2K_0402_5%
+3VS
RTC Battery
45@
BATT1
RTCBATT
+RTCVCC
12
2
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
CLKOUT7
CLKOUT8
12
R292
8.2K_0402_5%
12
R646 0_0402_5%@
RP2
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
+
+RTCBATT
12
1
CLK_PCI_LAN_R
CLK_PCI_LPC_R
CLK_PCI_MINI_R
CLK_PCI_PCM_R
CLK_PCI_1394_R
CLK_PCI_SIO_R
CLKOUT1
2
6
7
10
11
14
15
16
R645 0_0402_5%@
1 2
PCI_PLOCK#
PCI_I RDY#
PCI_PERR#
PCI_DEVSEL#
R835 22_0402_5%@
CLKOUT2
R836 22_0402_5%
CLKOUT3
R837 22_0402_5%
CLKOUT4
R838 22_0402_5%
CLKOUT5
R840 22_0402_5%
CLKOUT6
R841 22_0402_5%
+3VALW
1 2
5
1
U17
P
OE#
I2O
G
74LVC1G125GW_SOT3535
3
1 2
+3VALW
1 2
5
1
U18
P
OE#
I2O
G
74LVC1G125GW_SOT3535
3
+RTCBATT
1
2
3
1
C434
0.1U_0402_16V4Z
2
4
4
D3
BAS40-04_SOT23
CLK_PCI_LAN_R <26>
CLK_PCI_LPC_R <26>
CLK_PCI_MINI_R <26>
CLK_PCI_PCM_R <26>
CLK_PCI_1394_R <26>
CLK_PCI_SIO_R <26>
1 2
1 2
1 2
1 2
1 2
1 2
12/26:Modify
C419
0.1U_0402_16V4Z
NB_RST#
1 2
R279 33_0402_5%
12/26:Modify
C420
0.1U_0402_16V4Z
PCI_RST#
1 2
R288 33_0402_5%
+3VS
+3VS
+3VS
+CHGRTC
CLK_PCI_LAN
CLK_PCI_LPC
CLK_PCI_MINI
CLK_PCI_PCM
CLK_PCI_1394
CLK_PCI_SIO
RP3
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
RP4
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
RP5
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
R812
1 2
10K_0402_5%
Modify 11/07
Compal Electronics, inc.
Title
SCHEMATIC, M /B LA -3151P
Size Document Number Rev
Custom
401412
Date: Sheet
期四 三月
1
NB_RST# <13,16,27,33,36,41>
PCI_RST# <31,36,37,39,40>
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQH#
PCI_PIRQG#
PCI_REQ#3
PCI_REQ#0
PCI_REQ#2
PCI_REQ#1
PCI_REQ#4
PM_CLKRUN#
PCI_PAR
BMREQ#
1
C942
15P_0402_50V8J
2
of
22 55¬P , 09, 2006
B
Page 23
5
SB460 ONLY
+3VS
R309 10K_0402_5%
R310 10K_0402_5%
R644 10K_0402_5%
+3VALW
R313 10K_0402_5%
R314 10K_0402_5%
D D
C C
ICH_BITCLK_MDC<34>
ICH_BITCLK_AUDIO<44>
ICH_SYNC_AUDIO<44>
B B
A A
ICH_RST_AUDIO#<44>
ICH_SDOUT_AUDIO<44>
R315 10K_0402_5% @
R316 10K_0402_5%
R318 10K_0402_5%
R320 10K_0402_5%
R322 4.7K_0402_5%
R323 4.7K_0402_5%
R324 4.7K_0402_5%
R325 10K_0402_5%
R326 10K_0402_5%
R328 10K_0402_5%
R329 10K_0402_5%
R330 10K_0402_5%
R331 10K_0402_5%
R332 10K_0402_5%
R333 10K_0402_5%
+3VS
R337 2.2K_0402_5%
R338 2.2K_0402_5%
R647 10K_0402_5%
R831 10K_0402_5%
ICH_SYNC_MDC<34>
ICH_RST_MDC#<34>
ICH_SDOUT_MDC<34>
R351 10K_0402_5%@
R352 10K_0402_5%@
R354 10K_0402_5%@
R355 10K_0402_5%
R356 10K_0402_5%@
R357 10K_0402_5%@
R358 10K_0402_5%@
R648 10K_0402_5%
EC_FLASH#<35>
R341
R342
R343
R346
R347
R348
R349
R350
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
LPC_SMI#
EC_FLASH#_R
SB_INT_FLASH_SEL#
SYS_RESET#
LPC_PME#
EC_KBRST#
PBTN_OUT#
EC_SWI#
SB_PCIE_WAKE#
PM_SLP_S5#
PM_SLP_S3#
S3_STATE_R
EC_SCI#
BLINK/GPM6#
EC_SMI#
USB_OC#0
USB_OC#1
USB_OC#3
CP_PE#
USB_OC#6
SB_CK_SCLK
SB_CK_SDAT
GPIO13
IDE_HRESET#
EC_FLASH# USB_OC#3
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
ICH_AC_SDIN2
ICH_AC_SDIN1
ICH_AC_SDIN0
AZ_RST#
AZ_SYNC
AZ_SDATA_OUT
AZ_BIT_CLK
AC_RST#
C945
10P_0402_50V8K@
Modify : 11/07
S3_STATE<33>
R830 0_0402_5%
R832 0_0402_5%@
AZ_BIT_CLK
AZ_SYNC
AZ_RST#
AZ_SDATA_OUT
12
12
R814 10K_0402_5%
ICH_BITCLK_AUDIOICH_BITCLK_MDC
1
C946
10P_0402_50V8K@
2
4
http://hobi-elektronika.net
EC_SWI#<33>
EC_SCI#<33>
PM_SLP_S3#<33>
PM_SLP_S5#<33>
PBTN_OUT#<33>
SB_PWRGD<7,42>
SUS_STAT#<35>
EC_GA20<33>
EC_KBRST#<33>
R813 0_0402_5%@
SB_PCIE_WAKE#<36,39>
H_THERMTRIP#<7>
EC_RSMRST#<33>
SB_OSCIN<15>
+3VS
SB_INT_FLASH_SEL#<35>
SB_SPKR<44>
SB_CK_SCLK<9,10,15>
SB_CK_SDAT<9,10,15>
CPU_PWRGD<7>
BALLS(C6 AND C5) ARE FOR SB600 ONLY (NC FOR SB460)
EC_SMI#<33>
CP_PE#<39>
EC_LID_OUT#<33>
USB_OC#0<39>
AZ_BIT_CLK
AZ_SDATA_OUT
AZ_SYNC
AC_SDATA_OUT<26>
ICH_AC_SDIN0<44>
ICH_AC_SDIN1<34>
12
IDE_HRESET#<27>
EC_THERM#<7,33>
LDT_STOP#<7,13>
EC_SWI#
EC_SCI#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
R319 10K_0402_5%
R321 10K_0402_5%
12
R334 10K_0402_5%
R335 10K_0402_5%
R336 10K_0402_5%
R339 10K_0402_5%
R340 10K_0402_5%
AC_SDATA_OUT
ICH_AC_SDIN0
ICH_AC_SDIN1
ICH_AC_SDIN2
AC_RST#
SB460 ONLY
IDE_HRESET#
GPIO13
EC_THERM#
12
12
EC_GA20
EC_KBRST#
LPC_PME#
LPC_SMI#
S3_STATE_R
SYS_RESET#
SB_PCIE_WAKE#
BLINK/GPM6#
H_THERMTRIP#
EC_RSMRST#
SB_OSC_INT
12
12
12
EC_FLASH#_R
SB_INT_FLASH_SEL#
SB_CK_SCLK
SB_CK_SDAT
12
12
CPU_PWRGD
EC_SMI#
USB_OC#6
AZ_RST#
CP_PE#
EC_LID_OUT#
USB_OC#1
USB_OC#0
R353 0_0402_5%
T12PAD
12
TEST POINT TP602 FOR
SB460_FANOUT0
3
U16D
A3
PCI_PME#/GEVENT4#
B2
RI#/EXTEVNT0#
F7
SLP_S3#
A5
SLP_S5#
E3
PWR_BTN#
B5
PWR_GOOD
B3
SUS_STAT#
F9
NC
E9
TEST1
G9
TEST0
AF26
GA20IN
AG26
KBRST#
D7
LPC_PME#/GEVENT3#
C25
LPC_SMI#/EXTEVNT1#
D9
S3_STATE/GEVENT5#
F4
SYS_RESET#/GPM7#
E7
WAKE#/GEVENT8#
C2
BLINK/GPM6#
G7
SMBALERT#/THRMTRIP#/GEVENT2#
E2
RSMRST#
B23
14M_OSC
C28
NC
A26
ROM_CS#/GPIO1
B29
GHI#/GPIO6
A23
VGATE/GPIO7
B27
GPIO4
D23
GPIO5
B26
SPKR/GPIO2
C27
SCL0/GPOC0#
B28
SDA0/GPOC1#
C3
NC
F3
NC
D26
DDC1_SCL/GPIO9
C26
DDC1_SDA/GPIO8
A27
LDT_PG/SSMUXSEL/GPIO0
A4
NC
C6
NC
C5
NC
C4
USB_OC7#/GEVENT7#
B4
USB_OC6#/GEVENT6#
B6
USB_OC5#/AZ_RST#/GPM5#
A6
USB_OC4#/GPM4#
C8
USB_OC3#/GPM3#
C7
USB_OC2#/FANOUT1/LLB#/GPM2#
B8
USB_OC1#/GPM1#
A8
USB_OC0#/GPM0#
N2
AZ_BITCLK
M2
AZ_SDOUT
K2
NC
L3
AZ_SYNC
K3
NC
L1
AC_BITCLK/GPIO38
L2
AC_SDOUT/GPIO39
L4
ACZ_SDIN0/GPIO42
J2
ACZ_SDIN1/GPIO43
J4
ACZ_SDIN2/GPIO44
M3
AC_SYNC/GPIO40
L5
AC_RST#/GPIO45
E23
FANOUT0/GPIO3
AC21
GPIO31
AD7
GPIO13
AE7
DPSLP_OD#/GPIO37
AA4
GPIO14
T4
TALERT#/GPIO10
D4
SLP#/LDT_STP#
AB19
NC
218S4RASA11GS SB460_BGA549
OSC / RST
AC97 AZALIA
SB460
GPIO
USB OC
ACPI / WAKE UP EVENTS
Part 4 of 4
USB INTERFACE
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
USB PWR
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31
AVSS_USB_32
AVSS_USB_33
USBCLK
USB_RCOMP
USB_ATEST1
USB_ATEST0
USB_HSDP7+
USB_HSDM7-
USB_HSDP6+
USB_HSDM6-
USB_HSDP5+
USB_HSDM5-
USB_HSDP4+
USB_HSDM4-
USB_HSDP3+
USB_HSDM3-
USB_HSDP2+
USB_HSDM2-
USB_HSDP1+
USB_HSDM1-
USB_HSDP0+
USB_HSDM0-
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDC
AVSSC
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
CLK_USB_48M
A17
R312 11.3K_0402_1%
A14
A11
A10
H12
NC
G12
NC
E12
NC
D12
NC
E14
D14
USB20_P6
G14
USB20_N6
H14
USB20_P5
D16
USB20_N5
E16
USB20_P4
D18
USB20_N4
E18
USB20_P3
G16
USB20_N3
H16
USB20_P2
G18
USB20_N2
H18
USB20_P1
D19
USB20_N1
E19
USB20_P0
G19
USB20_N0
H19
B9
B11
B13
B16
B18
A9
B10
B12
B14
B17
A12
A13
A16
C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F19
F21
G11
G21
H11
H21
J11
J12
J14
J16
J18
J19
2
12
01/03/05" modify
SB600 ONLY
(NC for SB460)
1
C435
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C443
2
0.1U_0402_16V4Z
PLACE C443,C444 AND
C445 CLOSE TO U16
USB20_P6 <43>
USB20_N6 <43>
USB20_P5 <34>
USB20_N5 <34>
USB20_P4 <36>
USB20_N4 <36>
USB20_P3 <43>
USB20_N3 <43>
USB20_P2 <39>
USB20_N2 <39>
USB20_P1 <39>
USB20_N1 <39>
USB20_P0 <39>
USB20_N0 <39>
1
1
C436
C437
2
2
1U_0402_6.3V4Z
1
C444
2
2.2U_0603_6.3V6K
CLK_USB_48M <15>
1
C438
2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
+3.3V_AVDDC
1
C445
1U_0402_6.3V4Z
2
AVDD_USB
1
C439
2
0.1U_0402_16V4Z
1
1
C441
C440
2
2
0.1U_0402_16V4Z
L22
1 2
KC FBM-L11- 2 0 1209-221LMAT_0805
1
L21
1 2
1
KC FBM-L11- 2 01 209-221LMAT_0805
C442
0.1U_0402_16V4Z
2
+3VALW
+3VALW
Modify 11/27
5
4
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
月
23 55,
1
of
B
Page 24
5
4
3
2
1
http://hobi-elektronika.net
PLACE SATA AC COUPLING
D D
SATA_STX_C_DRX_P0<27>
SATA_STX_C_DRX_N0<27>
SATA_DTX_C_SRX_N0<27>
SATA_DTX_C_SRX_P0<27>
+1.8VS
1 2
MBK2012121YZF_0805
C C
B B
C650 CLOSE TO THE
BALL OF U600
+1.8VS
L61
1 2
MBK2012121YZF_0805
SATA@
+1.8VS
KC FBM-L11- 2 0 1209-221LMAT_0805
1 2
PLLVDD_ATA
L23
1U_0402_6.3V4Z
1
SATA@
L62
SATA@
22U_0805_6.3V6M
SATA@
2
1
C454
2
SATA_X1
R363
10M_0603_5%
SATA@
SATA_X2
VCC_SB=1.2V WHEN SB600
VCC_SB 1.8V WHEN SB460
1U_0402_6.3V4Z
1
C450
2
SATA@
C649 CLOSE TO THE
BALL OF U600
12
0.1U_0402_16V4ZSATA@
1
C455
2
0.1U_0402_16V4Z
SATA@
12
12
25MHZ_20PF_6X25000017
SATA@
12
C451
SATA@
R779
0_0402_5%
PATA@
1
2
Y3
R778
0_0402_5%
PATA@
XTLVDD_ATA
AVDD_SATA
1
C456
C457
2
0.1U_0402_16V4Z
SATA@
R781
1 2
0_0402_5%PATA@
C459 27P_0402_50V8J
1 2
C460
1 2
27P_0402_50V8J
SATA@
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0
1
C453
1U_0402_6.3V4Z
2
SATA@
1
C458
1U_0402_6.3V4Z
2
SATA@
SATA@
SATA_LED#<33>
12
R780
0_0402_5%
PATA@
CAPS CLOSE TO U16
SATA_STX_DRX_P0
C4460.01U_0402_16V7KSATA@
1 2
0.01U_0402_16V7KSATA@
0.01U_0402_16V7KSATA@
+3VS PLLVDD_ATA
1 2
1 2
1 2
PLACE SATA_CAL
RES & CAP VERY
CLOSE TO BALL
OF U16
R360 1K_0402_1%
1 2
2.2U_0603_6.3V6K
@
SATA_LED#
1 2
R362 4.7K_0402_5%
NOTE:
R360 IS 1K 1% FOR 25MHz
XTAL, 4.99K 1% FOR 100MHz
INTERNAL CLOCK
SATA_STX_DRX_N0
C447
SATA_DTX_SRX_N0
C4480.01U_0402_16V7KSATA@
SATA_DTX_SRX_P0
C449
SATA@
12
C452
R361 0_0402_5%
XTLVDD_ATA
AVDD_SATA
SATA_CAL
SATA_X1
SATA_X2
12
SATA@
U16B
AH21
SATA_TX0+
AJ21
SATA_TX0-
AH20
SATA_RX0-
AJ20
SATA_RX0+
AH18
SATA_TX1+
AJ18
SATA_TX1-
AH17
SATA_RX1-
AJ17
SATA_RX1+
AH13
SATA_TX2+
AH14
SATA_TX2-
AH16
SATA_RX2-
AJ16
SATA_RX2+
AJ11
SATA_TX3+
AH11
SATA_TX3-
AH12
SATA_RX3-
AJ13
SATA_RX3+
AF12
SATA_CAL
AD16
SATA_X1
AD18
SATA_X2
AC12
SATA_ACT#
AD14
PLLVDD_SATA_1
AJ10
PLLVDD_SATA_2
AC16
XTLVDD_SATA
AE14
AVDD_SATA_1
AE16
AVDD_SATA_2
AE18
AVDD_SATA_3
AE19
AVDD_SATA_4
AF19
AVDD_SATA_5
AF21
AVDD_SATA_6
AG22
AVDD_SATA_7
AG23
AVDD_SATA_8
AH22
AVDD_SATA_9
AH23
AVDD_SATA_10
AJ12
AVDD_SATA_11
AJ14
AVDD_SATA_12
AJ19
AVDD_SATA_13
AJ22
AVDD_SATA_14
AJ23
AVDD_SATA_15
AB14
AVSS_SATA_1
AB16
AVSS_SATA_2
AB18
AVSS_SATA_3
AC14
AVSS_SATA_4
AC18
AVSS_SATA_5
AC19
AVSS_SATA_6
AD12
AVSS_SATA_7
AD19
AVSS_SATA_8
AD21
AVSS_SATA_9
AE12
AVSS_SATA_10
AE21
AVSS_SATA_11
AF11
AVSS_SATA_12
AF14
AVSS_SATA_13
AF16
AVSS_SATA_14
AF18
AVSS_SATA_15
AG11
AVSS_SATA_16
AG12
AVSS_SATA_17
AG13
AVSS_SATA_18
AG14
AVSS_SATA_19
AG16
AVSS_SATA_20
AG17
AVSS_SATA_21
AG18
AVSS_SATA_22
AG19
AVSS_SATA_23
AG20
AVSS_SATA_24
AG21
AVSS_SATA_25
AH10
AVSS_SATA_26
AH19
AVSS_SATA_27
218S4RASA11GS SB460_BGA549
SB460
Part 2 of 4
SERIAL ATA
SERIAL ATA POWER
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15
AB29
IDE_IRQ
AA28
IDE_A0
AA29
IDE_A1
AB27
IDE_A2
Y28
IDE_DACK#
AB28
IDE_DREQ
AC27
IDE_IOR#
AC29
IDE_IOW#
AC28
IDE_CS1#
W28
IDE_CS3#
W27
IDE_D0
AD28
IDE_D1
AD26
IDE_D2
AE29
IDE_D3
AF27
IDE_D4
AG29
IDE_D5
AH28
IDE_D6
AJ28
IDE_D7
AJ27
IDE_D8
AH27
IDE_D9
AG27
IDE_D10
AG28
IDE_D11
AF28
IDE_D12
AF29
IDE_D13
AE28
IDE_D14
AD25
IDE_D15
AD29
J3
NC
J6
NC
G3
NC
G2
NC
G6
NC
C23
NC
G5
NC
M4
NC
T3
NC
V4
NC
N3
NC
P2
NC
W4
NC
P5
NC
P7
NC
P8
NC
T8
NC
T7
NC
V5
NC
L7
NC
M8
NC
V6
NC
M6
NC
P4
NC
M7
NC
V7
NC
N1
NC
M1
NC
PIDE_IORDY
PIDE_DACK#
ATA 66/100
SPI ROMHW MONITOR
IDE_IORDY
IDE_D[0..15]<27>
IDE_A[0..2]<27>
IDE_IORDY <27>
IDE_IRQ <27>
IDE_DACK# <26,27>
IDE_DREQ <27>
IDE_IOR# <27>
IDE_IOW# <27>
IDE_CS1# <27>
IDE_CS3# <27>
IDE_D[0..15]
IDE_A[0..2]
A A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Title
Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
月
2
24 55,
1
B
of
Page 25
5
4
3
2
1
http://hobi-elektronika.net
+3VS
D D
0.1U_0402_16V4Z
C C
+1.8VALW
1
+
C461
220U_D2_4VM
2
1U_0402_6.3V4Z
1
C468
+1.8VS
1 2
R815 0_0805_5%
1
C469
2
2
0.1U_0402_16V4Z
22U_0805_6.3V6M
0.1U_0402_16V4Z
+3VALW
1
2
C470
C462
1U_0402_6.3V4Z
1
2
1
C463
2
1U_0402_6.3V4Z
1
C471
0.1U_0402_16V4Z
2
1
C464
2
1
C465
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C466
2
VCC_SB=1.8V WHEN SB460
1
C472
22U_0805_6.3V6M
2
1U_0402_6.3V4Z
22U_0805_6.3V6M
+USB_PHY_18
1
C481
C480
2
0.1U_0402_16V4Z
1
C473
2
1U_0402_6.3V4Z
C477
1
C482
2
0.1U_0402_16V4Z
1
1
C474
2
2
1U_0402_6.3V4Z
1
1
C478
2
2
0.1U_0402_16V4Z
1
1
C483
2
2
0.1U_0402_16V4Z
C475
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C467
2
1U_0402_6.3V4Z
1
C476
1U_0402_6.3V4Z
2
1
C479
2
1
C484
2
CPU_PWR=1.2V WHEN SB460
B B
+5VS
+3VS
R364
1K_0402_5%
1 2
D4
CH751H-40_SC76
2 1
+1.8VS
MBK1608800YZF_0805
V5_VREF
L24
1 2
+1.2V_HT
0.1U_0402_16V4Z
1
C487
2.2U_0603_6.3V6K
2
C485
2
C486
1
1U_0402_6.3V4Z
2
1
U16C
A25
VDDQ_1
A28
VDDQ_2
C29
VDDQ_3
D24
VDDQ_4
L9
VDDQ_5
L21
VDDQ_6
M5
VDDQ_7
P3
VDDQ_8
P9
VDDQ_9
T5
VDDQ_10
V9
VDDQ_11
W2
VDDQ_12
W6
VDDQ_13
W21
VDDQ_14
W29
VDDQ_15
AA12
VDDQ_16
AA16
VDDQ_17
AA19
VDDQ_18
AC4
VDDQ_19
AC23
VDDQ_20
AD27
VDDQ_21
AE1
VDDQ_22
AE9
VDDQ_23
AE23
VDDQ_24
AH29
VDDQ_25
AJ2
VDDQ_26
AJ6
VDDQ_27
AJ26
VDDQ_28
M13
VDD_1
M17
VDD_2
N12
VDD_3
N15
VDD_4
N18
VDD_5
R13
VDD_6
R17
VDD_7
U12
VDD_8
U15
VDD_9
U18
VDD_10
V13
VDD_11
V17
VDD_12
A2
S5_3.3V_1
A7
S5_3.3V_2
F1
S5_3.3V_3
J5
S5_3.3V_4
J7
S5_3.3V_5
K1
S5_3.3V_6
G4
S5_1.8V_1
H1
S5_1.8V_2
H2
S5_1.8V_3
H3
S5_1.8V_4
A18
USB_PHY_1.8V_1
A19
USB_PHY_1.8V_2
B19
USB_PHY_1.8V_3
B20
USB_PHY_1.8V_4
B21
USB_PHY_1.8V_5
AA27
CPU_PWR
AE11
V5_VREF
A24
AVDDCK
A22
NC
B22
AVSSCK
V29
PCIE_VSS_42
V28
PCIE_VSS_41
V27
PCIE_VSS_40
V26
PCIE_VSS_39
V25
PCIE_VSS_38
V24
PCIE_VSS_37
V23
PCIE_VSS_36
V22
PCIE_VSS_35
U27
PCIE_VSS_34
T29
PCIE_VSS_33
T28
PCIE_VSS_32
T27
PCIE_VSS_31
T24
PCIE_VSS_30
T21
PCIE_VSS_29
P27
PCIE_VSS_28
218S4RASA11GS SB460_BGA549
SB460
Part 3 of 4
POWER
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
A1
A20
A21
A29
B1
B7
B25
C21
C22
C24
D6
E24
F2
F23
G1
J1
J8
L6
L8
M9
M12
M15
M18
N13
N17
P1
P6
P21
R12
R15
R18
T6
T9
U13
U17
V3
V8
V12
V15
V18
V21
W1
W9
Y29
AA11
AA14
AA18
AC6
AC24
AD9
AD23
AE3
AE27
AG6
AJ1
AJ25
AJ29
D27
D28
D29
F26
G23
G24
G25
H27
J23
J26
J28
K27
L22
L23
L24
L27
L28
M21
M24
M27
N27
N28
P22
P23
P24
P25
P26
A A
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Title
Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date: Sheet
星期四 三
09, 2006
月
2
25 55,
1
B
of
Page 26
5
4
3
2
1
REQUIRED STRAPS
SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT,
15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE
REQUIRED
D D
AC_SDATA_OUT<23>
RTC_CLK<22>
CLK_PCI_1394_R<22>
PCI_CLK6<22>
CLK_PCI_LAN_R<22>
CLK_PCI_LPC_R<22>
C C
PULL
HIGH
PULL
LOW
+3VS
12
R649
12
R650
10K_0402_5%
AC_SDATA_OUT
USE DEBUG
STRAPS
IGNORE DEBUG
STRAPS
DEFAULT
10K_0402_5% @
12
RTC_CLK
INTERNAL
RTC
DEFAULT
EXTERNAL
RTC
DEBUG STRAPS
+3VS +3VS +3VS +3VS +3VS +3VS +3VS
12
R384
B B
IDE_DACK#<24,27>
PCI_AD28<22,31,36,37,40>
PCI_AD27<22,31,36,37,40>
PCI_AD26<22,31,36,37,40>
PCI_AD25<22,31,36,37,40>
PCI_AD24<22,31,36,37,40>
PCI_AD23<22,31,36,37,40>
10K_0402_5%
12
R393
10K_0402_5%
@
+3VS +3VS +3VS +3VS+3VALW
R370
10K_0402_5%
12
R371
10K_0402_5%
@
12
R381
10K_0402_5%
12
R372
10K_0402_5%
12
R373
10K_0402_5%
@
12
R382
10K_0402_5%
12
12
SB600 SB460
PCI_CLK4
CLK_PCI_1394
USE INT.
PLL48
USE EXT.
48MHZ
DEFAULT
PCI_CLK6
CPU IF=K8
DEFAULT
CPU IF=P4
ROM TYPE:
H, H = PCI ROM
H, L = SPI ROM
L, H = LPC ROM
L, L = FWH ROM
PCI_CLK1PCI_CLK0
CLK_PCI_LPCCLK_PCI_LAN CLK_PCI_LPCCLK_PCI_LAN
DEFAULT
SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
12
R385
10K_0402_5%
@
12
R394
10K_0402_5%
@
12
R386
10K_0402_5%
12
R395
10K_0402_5%
@
12
R387
10K_0402_5%
12
R396
10K_0402_5%
@
12
R388
10K_0402_5%
12
R397
10K_0402_5%
@
http://hobi-elektronika.net
NOTE: R365 PU RESISTOR FOR
RTC_IRQ# IS REQUIRED FOR SB460
TO KEEP THE INPUT FROM FLOATING.
R374
10K_0402_5%
R383
10K_0402_5%
@
PCI_CLK1PCI_CLK0
ROM TYPE:
H, H = PCI ROM
H, L = LPC I ROM
L, H = LPC II ROM
L, L = FWH ROM
NOTE: FOR SB460, PCICLK[8:7] ARE
CONNECTED TO SUBSTRATE
BALLS PCICLK[1:0 ]
12
R389
10K_0402_5%
12
R398
10K_0402_5%
@
12
R390
10K_0402_5%
@
12
R399
10K_0402_5%
@
DEFAULT
2.2K IF USED FOR SB600.
10K IF USED FO R SB460.
SB460 ONLY
+3VALW +3VS +3VS +3VS +3VS
12
R368
10K_0402_5%
12
R379
10K_0402_5%
@
R377
10K_0402_5%
12
R367
10K_0402_5%
12
R378
10K_0402_5%
@
12
R365
10K_0402_5%
RTC_IRQ#<22>
SB_SPDIFO<22>
CLK_PCI_MINI_R<22>
CLK_PCI_PCM_R<22>
CLK_PCI_SIO_R<22>
LPC_FRAME#<22,33,41>
12
R375
10K_0402_5%
@
12
R366
10K_0402_5%@
12
R376
10K_0402_5%
12
ACPWRON PCI_CLK2 PCI_CLK3 PCI_CLK5 LFRAME #SPDIF_OUT
PULL
HIGH
PULL
LOW
RTC_IRQ#
MANUAL
PWR ON
DEFAULT
AUTO
PWR
ON
SB_SPDIFO
SIO 24MHz
SIO 48MHz
DEFAULT
CLK_PCI_MINI
XTAL MODE
NOT
SUPPORTED
48MHZ OSC
MODE
DEFAULT
CLK_PCI_PCM
USB PHY
POWERDOWN
DISABLE
DEFAULT
USB PHY
POWERDOWN
ENABLE
CLK_PCI_SIO
PCIE_CM_SET
LOW
DEFAULT
PCIE_CM_SET
HIGH
OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.
LPC_FRAME#
ENABLE
THERMTRIP#
DEFAULT
DISABLE
THERMTRIP#
12
R369
10K_0402_5%
12
R380
10K_0402_5%
@
IDE_DACK#
USE
PULL
LONG
HIGH
RESET
DEFAULT
USE
A A
PULL
LOW
SHORT
RESET
PCI_AD28
USE
LONG
RESET
DEFAULT
USE
SHORT
RESET
PCI_AD27 PCI_AD26
USE PCI
PLL
DEFAULT
BYPASS
PCI PLL
USE ACPI
BCLK
DEFAULT
BYPASS
ACPI
BCLK
PCI_AD25
USE IDE
PLL
DEFAULT
BYPASS IDE
PLL
PCI_AD24
USE DEFAULT
PCIE STRAPS
DEFAULT
USE EEPROM
PCIE STRAPS
SB600 ONLYSB460 ONLY
5
4
PCI_AD23
BOOTFAILTIMER
DISABLED
DEFAULT
BOOTFAILTIMER
ENABLED
SB600 ONLY
NOTE: FOR
SB460,
PCI_AD23 IS
RESERVED
Security Classification
Issued Date
THIS SHEET O F EN GINEE RIN G DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DI SCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
2
Compal Electronics, inc.
Title
SCHEMATIC, M/B LA-3151P
Size Document Number R ev
Custom
401412
Date : Sheet
星期四 三
09, 2006
月
26 55,
1
of
B
Page 27
5
4
3
2
1
http://hobi-elektronika.net
HDD CONN
JP5
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
10U_0805_10V4Z
4
IDE_D[0..15]
IDE_A[0..2]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
C498
+3VS
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_CSEL
R403 470_0402_5%
PDIAG#
IDE_A2
IDE_CS3#
80mils80mils
1
C499
2
0.1U_0402_16V4Z
IDE_HRESET#<23>
NB_RST#<13,16,22,33,36,41>
1 2
1
2
PATA@
IDE_CS3# <24>
+5VS
10U_0805_10V4Z
0.1U_0402_16V4Z
1
C500
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C501
2
1000P_0402_50V7K
3
+5VS
+5VS
R783 470_0402_5%@
R405 470_0402_5%SATA@
IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or High for Slaver (Normal)
IDE_HRESET#
NB_RST#
+5VS
1
C490
2
1U_0603_10V4Z
IDE_RESET#
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
IDE_IOW#
IDE_IORDY
IDE_IRQ
IDE_A1
IDE_A0 IDE_A2
IDE_CS1#
IDE_LED#
12
SD_CSEL
12
2
+3VS
C943
1 2
5
U60
1
P
IN1
4
O
2
IN2
G
SN74AHC1G08DCKR_SC70
3
@
R833
1 2
33_0402_5%
0.1U_0402_16V4Z
1
C491
2
1
C492
2
1000P_0402_50V7K
CDROM CONN
JP6
1
2
1
2
3
4
3
4
5
6
5
6
7
8
7
8
9
10
9
10
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
OCTEK_CDR-50JL1G
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
23
24
26
25
26
28
27
28
30
29
30
32
31
32
34
33
34
36
35
36
38
37
38
40
39
40
42
41
42
44
43
44
46
45
46
48
47
48
50
49
50
Title
Size Document Number R ev
Date: Sheet of
0.1U_0402_16V4Z@
IDE_RESET#
1
C493
2
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_DREQ
IDE_IOR#
IDE_DACK#
PDIAG#
IDE_CS3#
1 2
R782
100K_0402_5%@
80mils
1 2
R406
100K_0402_5%@
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四
09, 2006
三月
+5VS
+5VS
+5VS
B
27 55,
1
IDE_D[0..15]<24>
IDE_A[0..2]<24>
D D
+5VS
IDE_DREQ<24>
IDE_IOW#<24>
12
R402
100K_0402_5%
C494
IDE_LED#
+5VS
1
2
1
C495
2
0.1U_0402_16V4Z
IDE_LED#<33>
C C
10U_0805_10V4Z
B B
IDE_IOR#<24>
IDE_IORDY<24>
IDE_DACK#<24,26>
IDE_IRQ<24>
IDE_CS1#<24>
150U_D2_6.3VM
@
0.1U_0402_16V4Z
1
C496
2
IDE_RESET#
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
IDE_DREQ
IDE_IOW#
IDE_IOR#
IDE_IORDY
IDE_DACK#
IDE_IRQ
IDE_A1
IDE_A0
IDE_CS1#
+5VS
C489
1
C497
2
1000P_0402_50V7K
1
+
2
OCTEK_HDD-22SG1G_NR
PATA@
SATA HDD Conn.
JP7
1
SATA_STX_C_DRX_P0<24>
SATA_STX_C_DRX_N0<24>
SATA_DTX_C_SRX_N0<24>
SATA_DTX_C_SRX_P0<24>
+3VS
+5VS
A A
1 2
R816 0_0805_5%
1 2
R817 0_0805_5%
Modify 11/07 for EMI
5
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0
GND
2
HTX+
3
HTX-
4
GND
5
HRX-
6
HRX+
7
GND
8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
14
VCC5
15
VCC5
16
VCC5
17
GND
18
RESERVED
19
GND
20
VCC12
21
VCC12
22
VCC12
OCTEK_SAT-22SG1G_NRSATA@
(NEW)
Page 28
A
B
C
D
E
http://hobi-elektronika.net
D7
2 1
RB411D_SOT23
C510
100P_0402_50V8J
W=40mils
F1
1.1A_6VDC_FUSE
0.1U_0402_16V4Z
DDC_MD2
1
2
1
2
C512
68P_0402_50V8K
Place clos e d to chipset
+CRT_VCC
21
C503
W=40mils
1
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
SUYIN_070549FR015S208CR
DSUB_12
DSUB_15
1
C515
68P_0402_50V8K
2
+CRT_VCC+R_CRT_VCC
JP8
D8
@
DAN217_SC59
1 1
VGA_CRT_R<16>
VGA_CRT_G<16>
VGA_CRT_B<16>
Close to Connector
Route 8mil width (for 37.5ohm)
2 2
CRT Connector
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
CRT_HSYNC<16>
CRT_HSYNC
12
R407
75_0402_1%
R408
75_0402_1%
1 2
C511 0.1U_0402_16V4Z
Place closed to chipset
CRT_VSYNC<16>
CRT_VSYNC CRT_VSYNC_B
VGA:8P_0402_50V8K
UMA:10P_0402_50V8J
12
75_0402_1%
12
R409
8P_0402_50V8K
+CRT_VCC
5
P
A2Y
G
SN74AHCT1G125DCKR_SC70-5
3
1 2
C516 0.1U_0402_16V4Z
+3VS
L25
L26
L27
12
CRT_R_L
CRT_G_L
CRT_B_L
C507
8P_0402_50V8K
1
2
1 2
FCM2012C-800_0805
1 2
FCM2012C-800_0805
1 2
1
C504
2
1
U20
OE#
4
1
C505
2
8P_0402_50V8K
+CRT_VCC
FCM2012C-800_0805
1
C506
8P_0402_50V8K
2
R410 10K_0402_5%
CRT_HSYNC_B
1
5
U21
P
4
OE#
A2Y
G
SN74AHCT1G125DCKR_SC70-5
3
D9
@
DAN217_SC59
2
3
1
C508
8P_0402_50V8K
2
1
3
10P_0402_50V8K
1
2
1 2
L28 MBK1608301YZF_0603
1 2
L29 MBK1608301YZF_0603
D10
@
DAN217_SC59
1
2
3
1
C509
8P_0402_50V8K
2
CRT_HSYNC_L
CRT_VSYNC_L
1
C513
2
+5VS
1
C514
10P_0402_50V8K
2
+3VS
12
12
R411
4.7K_0402_5%
1
3
C525
Issued Date
D13
@
DAN217_SC59
1
2
3
TV_CRMA_L
TV_COMPS_L
TV_LUMA_L
1
150P_0402_50V8J
2
TVOUT@
C
DSUB_12
DSUB_15
JP9
3
6
7
5
2
4
1
8
9
SUYIN_030107FR007SX08FU
TVOUT@
(ECQ60)
1 2
R818 0_0805_5%TVOUT@
Modify 11/07 for EMI
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
D
D12
@
DAN217_SC59
1
C524
2
1
150P_0402_50V8J
2
TVOUT@
3
+3VS
TVOUT@
TVOUT@
TVOUT@
C523
D11
@
DAN217_SC59
2
TVOUT@
TVOUT@
TVOUT@
1
150P_0402_50V8J
2
TVOUT@
3 3
TV-OUT Conn.
C517 22P_0402_50V8J
VGA_TV_Y<16>
VGA_TV_C<16>
VGA_TV_COMP<16>
4 4
VGA_TV_Y
VGA_TV_C
VGA_TV_COMP
12
R415
75_0402_1%
TVOUT@
12
C520
75_0402_1%
TVOUT@
150P_0402_50V8J
TVOUT@
12
R414
R413
75_0402_1%
TVOUT@
Close to Connector
Route 8mil width (for 37.5ohm)
1
1
2
C522
C521
2
150P_0402_50V8J
TVOUT@
VGA:82P_0402_50V8J
UMA:6P_0402_50V8J
1 2
1 2
L30 MBK1608301YZF_0603
C518 22P_0402_50V8J
1 2
1 2
L31 MBK1608301YZF_0603
C519 22P_0402_50V8J
1 2
1 2
L56 MBK1608301YZF_0603
2005/09/22
1
150P_0402_50V8J
2
TVOUT@
Security Classification
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R412
4.7K_0402_5%
Q7
2N7002_SOT23
2
G
1 3
D
S
2
G
1 3
D
S
Q8
2N7002_SOT23
Title
Size Document Number Rev
B
Date: Sheet
星期四 三月
401412
VGA_CRT_DAT <16>
VGA_CRT_CLK <16>
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
28 55, 09, 2006
E
B
of
Page 29
5
LCD POWER CIRCUIT
4
3
2
1
http://hobi-elektronika.net
D D
ENVDD<17>
C C
1
C529
0.1U_0402_16V4Z
2
12
D15
1N4148_SOT23@
B B
Q9
2N7002_SOT23
ENVDD
10K_0402_5%
INVT_PWM
1
C530
1U_0402_6.3V4Z@
2
07/07/'05
+LCDVDD +5VALW
12
R416
360_0402_5%
13
D
S
R419
1 2
2
G
13
D
2
G
12
S
R417
100K_0402_5%
Q11
BSS138_SOT23
Modify 11/22
R418
12
1K_0402_5%
BKOFF#<33>
+3VS
W=60mils
S
G
Q10
2
1
C526
0.047U_0402_16V4Z
2
4.7U_0805_10V4Z
BKOFF# DISPOFF#
D14
RB751V_SOD323
21
D
1 3
1
C893
2
SI2301BDS_SOT23
7.3
W=60mils
+LCDVDD
+3VS+3VS
12
R420
4.7K_0402_5%
+LCDVDD
1
C894
0.1U_0402_16V4Z
2
Modify 11/07 for EMI
+INVPWR_B+
L45
KC FBM-L11-201209-221LMAT_0805
L46
KC FBM-L11-201209-221LMAT_0805
1
C790
68P_0402_50V8K
2
12
12
B+
LCD/PANEL BD. Conn.
JP10
20
40
19
39
18
38
17
37
16
36
15
35
14
34
13
33
12
32
11
31
10
30
9
29
8
28
7
27
6
26
5
25
4
24
3
23
2
22
1
21
ACES_88107-4000G
VGA_LVDSB0-<17>
VGA_LVDSB0+<17>
VGA_LVDSB1+<17>
VGA_LVDSB1-<17>
VGA_LVDSB2+<17>
VGA_LVDSB2-<17>
VGA_LVDSBC-<17>
VGA_LVDSBC+<17>
+INVPWR_B+
12
I2C_CLK<16>
I2C_DAT<16>
I2C_CLK
I2C_DAT
TZOUT0-
TZOUT1+
TZOUT1-
TZOUT2+
TZOUT2-
TZCLKTZCLK+
KC FBM-L11-201209-221LMAT_0805
L72
+3VS +LCDVDD
(SAME AS ACES_87216-4016)
DAC_BRIG
INVT_PWM
DISPOFF#
L73
KC FBM-L11-201209-221LMAT_0805
(60 MIL)
VGA_LVDSA0VGA_LVDSA0+TZOUT0+
VGA_LVDSA1VGA_LVDSA1+
VGA_LVDSA2+
VGA_LVDSA2-
VGA_LVDSACVGA_LVDSAC+
DAC_BRIG <33>
INVT_PWM <33>
12
VGA_LVDSA0- <17>
VGA_LVDSA0+ <17>
VGA_LVDSA1- <17>
VGA_LVDSA1+ <17>
VGA_LVDSA2+ <17>
VGA_LVDSA2- <17>
VGA_LVDSAC- <17>
VGA_LVDSAC+ <17>
Modify 11/07 for EMI
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/08 2006/03/08
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M /B LA-3151P
401412
星期四
09, 2006
三月
1
B
of
29 55,
Page 30
5
4
3
2
1
http://hobi-elektronika.net
D D
H5
H_C177D144
@
1
H1
H_S394D138
@
1
H23
H_S394D138
@
1
C C
B B
H8
H_C236D165
@
1
H29
H_C236D161
@
1
H18
H_O134X118D55X39
@
1
H25
H_S354D138
@
1
H30
H_C177D144
1
H2
H_S394D138
1
H14
H_S394D138
1
H9
H_C236D165
1
H31
H_S315D118
1
H16
H_C276D118
1
H32
H_S315D138
1
@
@
@
@
@
@
@
H20
H_C163D163N
@
1
H4
H_S394D138
@
1
H15
H_S394D138
@
1
H10
H_C236D165
@
1
H11
H_O134X118D55X39
@
1
H19
H_C276D118
@
1
H33
H_C315D236
@
1
H21
H_S394D138
@
1
H28
H_S394D138
@
1
H3
H_C236D161
@
1
H12
H_O134X118D55X39
@
1
H13
H_S354D138
@
1
H34
H_O217X157D217X157N
@
1
H22
H_S394D138
@
1
H7
H_C236D165
@
1
H6
H_C236D161
@
1
H17
H_O134X118D55X39
@
1
H24
H_S354D138
@
1
DVI-D Connector
JP11
VGA_DVI_DET<17>
17
TMDS_DATA0-
18
TMDS_DATA0+
9
TMDS_DATA1-
10
TMDS_DATA1+
1
TMDS_DATA2-
2
TMDS_DATA2+
12
TMDS_DATA3-
13
TMDS_DATA3+
4
TMDS_DATA4-
5
TMDS_DATA4+
20
TMDS_DATA5-
21
TMDS_DATA5+
23
TMDS_Clock+
24
TMDS_Clock-
8
Analog VSYNC
SUYIN_070939FR024S531PL DVI@
TMDS_DATA2/4 shield
TMDS_DATA1/3 shield
TMDS_DATA0/5 shield
TMDS_Clock shield
VGA_DVI_DET
D17
SKS10-04AT_TSMA@
DDC_CLOCK
Hot Plug Detect
DVI_TX0-<17>
DVI_TX0+<17>
DVI_TX1-<17>
DVI_TX1+<17>
DVI_TX2-<17>
DVI_TX2+<17>
DVI_TXC+<17>
DVI_TXC-<17>
DDC_DATA
GND
2 1
+5V
14
W=40mils
6
7
16
3
11
19
22
15
R423
1 2
12
R424
DVI@
100K_0402_5%
DVI_SCLK
DVI_SDATA
20K_0402_5% DVI@
+DVI_VCC
1
2
C531
D32
RB411D_SOT23DVI@
21
+5VS
0.1U_0402_16V4ZDVI@
(HDQ70)
+DVI_VCC
+3VS
12
12
4.7K_0402_5%
2
DVI@
R422
1 3
Q12
2N7002_SOT23
DVI@
2
G
D
1 3
Q13
2N7002_SOT23
DVI@
S
2
G
D
S
Title
Size Document Number Rev
B
Date: Sheet
VGA_DVI_DAT <17>
VGA_DVI_CLK <17>
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
401412
星期四 三月
1
B
of
30 55, 09, 2006
FD1
FD2
1
CF20
1
A A
5
CF17
1
CF8
1
FD3
@
@
1
1
CF14
CF18
@
@
1
1
CF16
CF19
@
@
1
1
CF22
CF23
@
@
1
1
FD4
FD5
@
1
CF21
@
1
CF13
@
1
CF24
@
1
FD6
@
@
@
@
@
CF7
CF9
@
1
1
CF12
CF10
@
@
CF1
1
1
CF2
@
1
1
1
@
1
CF6
CF4
@
1
CF3
@
1
4
CF15
@
@
@
CF5
@
1
1
CF11
@
@
1
1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/20 2006/06/20
DVI_SDATA
DVI_SCLK
Compal Secret Data
Deciphered Date
R421
4.7K_0402_5%
DVI@
Page 31
5
4
3
2
1
http://hobi-elektronika.net
PCI_AD[0..31]<22,26,36,37,40>
D D
C C
B B
CLK_PCI_LAN
A A
5
PCI_CBE#0<22,36,37,40>
PCI_CBE#1<22,36,37,40>
PCI_CBE#2<22,36,37,40>
PCI_CBE#3<22,36,37,40>
PCI_AD17 LAN_IDSEL
PCI_FRAME#<22,36,37,40>
PCI_DEVSEL#<22,36,37,40>
PCI_PIRQF#<22>
CLK_PCI_LAN<22>
PM_CLKRUN#<22,36,41>
12
R786
1
C911
2
PCI_AD[0..31]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
1 2
R434 100_0402_5%
PCI_PAR<22,36,37,40>
PCI_IRDY#<22,36,37,40>
PCI_TRDY#<22,36,37,40>
PCI_STOP#<22,36,37,40>
PCI_PERR#<22,36,37,40>
PCI_SERR#<22,36,37>
PCI_REQ#3<22>
PCI_GNT#3<22>
LAN_PME#<33>
PCI_RST#<22,36,37,39,40>
10_0402_5%@
18P_0402_50V8J@
CLK_PCI_LAN
PM_CLKRUN#
RTL8110SBL change to Ver.D
104
103
102
98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33
92
77
60
44
46
76
61
63
67
68
69
70
75
30
29
25
31
27
28
65
4
17
128
21
38
51
66
81
91
101
119
35
52
80
100
U22
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
IDSEL
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
REQ#
GNT#
INTA#
PME#
RST#
CLK
CLKRUN#
GND/VSS
GND/VSS
GND/VSS
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND
GND
GND
GND
RTL8110SBL_LQFP1288110S@
EEDO
AUX/EEDI
EESK
EECS
LED0
LED1
LED2
NC/LED3
TXD+/MDI0+
TXD-/MDI0-
RXIN+/MDI1+
RXIN-/MDI1-
NC/MDI2+
NC/MDI2-
NC/MDI3+
NC/MDI3-
X1
X2
LWAKE
ISOLATE#
RTSET
NC/SMBCLK
NC/SMBDATA
NC/M66EN
NC/AVDDH
AVDDH
PCI I/F
NC/HSDAC+
NC/HG
NC/LG2
NC/VSS
NC/VSS
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
LAN I/F
NC/GND
CTRL25
CTRL12
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
AVDDL
AVDDL
AVDDL
AVDDL
VDD12
VDD12
VDD12
VDD12
VDD12
NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12
NC/VDD12
Power
NC
4
R425 3.6K_0402_5%
LAN_EEDO
108
LAN_EEDI
109
LAN_EECLK
111
LAN_EECS
106
ACTIVITY#
117
LINK_100#
115
114
LINK_1000#
113
LAN_MDI0+
1
LAN_MDI0-
2
LAN_MDI1+
5
LAN_MDI1-
6
LAN_MDI2+
14
LAN_MDI2-
15
LAN_MDI3+
18
LAN_MDI3-
19
121
122
105
23
127
72
74
88
10
120
11
123
124
9
13
22
48
62
73
112
118
8
125
26
41
56
71
84
94
107
3
7
20
16
126
32
54
78
99
24
45
64
110
116
12
20mils
LAN_X1
LAN_X2
R428 1K_0402_5%
1 2
R429 15K_0402_5%
1 2
1 2
1 2
+LAN_AVDDH
12
R785
CTRL25
CTRL12
1
C541
0.1U_0402_16V4Z
2
+LAN_AVDDL25
20mils
1
C909
0.1U_0402_16V4Z
2
2
C555
1
0.1U_0402_16V4Z8110S@
V_12P
1
2
R441
R787
C560
0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
U23
4
DO
3
DI
2
SK
1
CS
AT93C46-10SU-2.7_SO8
1 2
R426 0_0402_5%
12
R427 0_0402_5%@
LAN_MIDI0+ <32>
LAN_MIDI0- <32>
LAN_MIDI1+ <32>
LAN_MIDI1- <32>
LAN_MIDI2+ <32>
LAN_MIDI2- <32>
LAN_MIDI3+ <32>
LAN_MIDI3- <32>
5.6K_0603_1%8100C@
R784
2.49K_0603_1%8110S@
R431
20mils
1 2
R437
1 2
1 2
0_0402_5%8110S@
1
C534
0.1U_0402_16V4Z8110S@
2
1
2
1
C901
0.1U_0402_16V4Z
2
0_0402_5%8110S@
1
C551
0.1U_0402_16V4Z
2
2
C912
0.1U_0402_16V4Z8110S@
1
0_0402_5%8100C@
C900
27P_0402_50V8J
0_0402_5%8110S@
+3VALW
5
GND
6
NC
7
NC
8
VCC
+3VS
1
C896
0.1U_0402_16V4Z8110S@
2
Y4
1 2
25MHZ_20P
1
2
+2.5V_LAN
0.1U_0402_16V4Z8110S@
+2.5V_LAN
+LAN_AVDDH
2005/07/29 2006/07/29
3
LAN_ACTIVITY# <32>
LAN_LINK# <32>
R432
1 2
LAN_X2LAN_X1
27P_0402_50V8J
1
C902
0.1U_0402_16V4Z
2
C905
0.1U_0402_16V4Z
1
C552
0.1U_0402_16V4Z
2
2
C913
1
1
C895 0.1U_0402_16V4Z
2
0_0805_5%8110S@
+3VALW
RSET 5.6K for 8100CL
2.49K for 8110S(B)
+3VALW
1
C540
2
1
C903
0.1U_0402_16V4Z
2
1
C906
0.1U_0402_16V4Z
2
1
C910
0.1U_0402_16V4Z
2
2
C914
1
0.1U_0402_16V4Z8110S@
Compal Secret Data
Deciphered Date
1
2
+LAN_DVDD
40mils
2
1
C897
1U_0402_6.3V4Z
CTRL25
+3VALW
1
C904
0.1U_0402_16V4Z
2
C907
0.1U_0402_16V4Z
R439
R440
+1.2V_LAN
C915
0.1U_0402_16V4Z8110S@
8100CL(10/100 LAN) 8110SBL(10/100/1000 LAN)
PIN
RSET 5.6K 2.49K
8100CL(10/100 LAN) 8110SBL(10/10 0/1000 LAN)BOM structure
8100C@
Stuff No_Stuff
8110S@ StuffNo_Stuff
@
+3VALW
12
2
B
1
2
1 2
1 2
2
31
E
C
22U_0805_6.3V6M
C908
0.1U_0402_16V4Z
0_0805_5%8110S@
0_0805_5%8100C@
No_Stuff No_Stuff
+2.5V_LAN
Q15
2SB1197K_SOT23
40mils
1
C536
2
+LAN_AVDDL
40mils
R435
R436
Title
Size Document Number Rev
B
Date: Sheet
1 2
1 2
+1.2V_LAN
+2.5V_LAN
星期四
+3VALW
8110S@
2SB1197K_SOT23
CTRL12
0_0805_5%8100C@
0_0805_5%8110S@
31
E
Q14
2
B
C
22U_0805_6.3V6M
8110S@
C898
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
09, 2006
三月
+1.2V_LAN
1
2
+3VALW
+2.5V_LAN
1
40mils
1
C899
2
0.1U_0402_16V4Z
8110S@
of
31 55,
B
Page 32
5
4
3
2
1
http://hobi-elektronika.net
LAN RTL8110SBL/RTL8100CL
D D
unpop when use RTL8100CL(10/100)
1
C916
0.01U_0402_16V7K8110S@
2
12
12
R446
C C
B B
R789
49.9_0402_1%8110S@
LAN_MIDI3-<31>
LAN_MIDI3+<31>
LAN_MIDI2-<31>
LAN_MIDI2+<31>
LAN_MIDI1-<31>
LAN_MIDI1+<31>
LAN_MIDI0-<31>
LAN_MIDI0+<31>
49.9_0402_1%
49.9_0402_1%8110S@
12
12
R791
R790
49.9_0402_1%
C570
1
0.01U_0402_16V7K
2
49.9_0402_1%
1
C917
2
12
R447
49.9_0402_1%8110S@
12
R453
C571
1
0.01U_0402_16V7K
2
0.01U_0402_16V7K8110S@
12
R448
49.9_0402_1%8110S@
LAN_MDI3LAN_MDI3+
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
LAN_MDI0LAN_MDI0+
12
R454
49.9_0402_1%
1
C564
2
0.01U_0402_16V7K8110S@
24HST1041A-3(SP050002110) for RTL8110SBL(GbE)
+2.5V_LAN
24ST0023-3(SP050005000) for RTL8100CL(10/100)
24ST0023-3: Half port(TD[3:4], MX[3:4])
12
R444
0_0603_5%8110S@
1 2
R449 0_0402_5%8110S@
0.01U_0402_16V7K8110S@
1
1
C919
C565
2
2
0.01U_0402_16V7K
RJ45_MDI3+
RJ45_MDI3-
RJ45_MDI2+
RJ45_MDI2-
1
C567
0.01U_0402_16V7K
2
8110S@
R794 0_0402_5%8100C@
R795 0_0402_5%8100C@
R459 0_0402_5%8100C@
R460 0_0402_5%8100C@
reseved for RTL8100CL(10/100)
T3
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
TD2-6MX2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
0.5u_GST5009
8110S@
1 2
1 2
1 2
1 2
MCT1
MX1+
MX1-
MCT2
MX2+
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
24
23
22
21
20
19
18
17
16
15
14
13
R792
75_0402_1%
12
R461
75_0402_1%
12
R793
75_0402_1%
12
RJ45_MDI3RJ45_MDI3+
RJ45_MDI2RJ45_MDI2+
RJ45_MDI1RJ45_MDI1+
RJ45_MDI0RJ45_MDI0+
12
R796
75_0402_1%
RJ45_GND
LAN_ACTIVITY#<31>
+3VALW
LAN_LINK#<31>
+3VALW
LAN_ACTIVITY#
R788 300_0603_5%
LAN_LINK#
R450 300_0603_5%
RJ45_GND LANGND
12
RJ45_MDI3RJ45_MDI3+
RJ45_MDI1RJ45_MDI2RJ45_MDI2+
RJ45_MDI1+
RJ45_MDI0RJ45_MDI0+
12
C918
1000P_1206_2KV7K
JP75
12
Amber LED-
11
Amber LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
SUYIN_100073FR012S100ZL
HBL-50
1 2
SHLD4
SHLD3
SHLD2
SHLD1
1
C920
2
0.1U_0402_16V4Z
16
15
14
13
1
C921
4.7U_0805_10V4Z
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/07/29 2006/07/29
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
2
Date: Sheet of
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四
09, 2006
三月
1
B
32 55,
Page 33
5
KBA[0..19]
ADB[0..7]
L58
1 2
FBM-L11-160808-800LMT_0603
D D
MINI_PME#<36>
LAN_PME#<31>
C C
RCIRRX<43>
+5VS
RP6
1 8
2 7
3 6
4 5
4.7K_1206_8P4R_5%
+3VALW
RP7
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%
+3VALW
RP8
B B
A A
1 8
2 7
3 6
4 5
100K_1206_8P4R_5%
+3VS
1 2
R476 10K_0402_5%
+5VALW
RP9
1 8
2 7
3 6
4 5
4.7K_1206_8P4R_5%
+5VS
+3VALW
KBA[0..19] <35>
ADB[0..7] <35>
ECAGND
20mil
C581
22P_0402_50V8J@
R799 0_0402_5%
1 2
R470 0_0402_5%
1 2
KB_CLK
KB_DATA
PS_CLK
PS_DATA
FRD#
SELIO#
FSEL#
IE_BTN#
EMPWR_BTN#
E-MAIL_BTN#
USER_BTN#
5IN1_LED#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
R4794.7K_0402_5%
R4804.7K_0402_5%
R4821K_0402_5%
R4831K_0402_5%
R4851K_0402_5%
12
R471
10K_0402_5%
D18
RB751V_SOD323
TP_CLK
12
TP_DATA
12
KBA1
12
KBA4
12
KBA5
12
5
R463 33_0402_5%@
CLK_PCI_LPC<22>
+3VALW
1 2
21
+3VALW
12
+3VALW
R798
10K_0402_5%
1 2
EC_PME#
EC_RCIRRX
BTSW_EN#
1 2
R474 100K_0402_5%
R475 100K_0402_5%
+3VALW
WLSW_EN#
1 2
C587 0.1U_0402_16V4Z
12
R478 47K_0402_5%
1 2
R484 1K_0402_5%
1 2
R486 1K_0402_5%
1
C572
2
0.1U_0402_16V4Z
+3VALW
12
DPLL_TP
TEST_TP
4
+3VALW
0.1U_0402_16V4Z
1
2
LPC_FRAME#<22,26,41>
R473 100K_0402_5%
TP_DATA<34>
EC_SMB_CK1<35,50>
EC_SMB_DA1<35,50>
EC_SMB_CK2<7>
EC_SMB_DA2<7>
EMPWR_BTN#<43>
E-MAIL_BTN#<43>
IE_BTN#<43>
IDE_LED#<27>
USER_BTN#<43>
EC_SWI#<23>
5IN1_LED#<37>
BTSW_EN#<43>
PBTN_OUT#<23> EC_THERM# <7,23>
CAPS_LED#<43>
NUM_LED#<43> EAPD <44>
SATA_LED#<24>
EC_GA20<23>
EC_KBRST#<23>
C573
0.1U_0402_16V4Z
LPC_AD0<22,41>
LPC_AD1<22,41>
LPC_AD2<22,41>
LPC_AD3<22,41>
NB_RST#<13,16,22,27,36,41>
SERIRQ<22,37,41>
FRD#<35>
FWR#<35>
FSEL#<35>
TP_CLK<34>
EC_SCI#<23>
ENBKL<17>
BKOFF#<29>
FSTCHG<49>
EC_SMI#<23>
VGATE<54>
LID_SW#<42>
BT_ON#<34>
SYSON<39,46>
SUSP#<35,39,46,51,53>
VR_ON<54>
0.1U_0402_16V4Z
1
1
C574
2
12
C575
2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FRD#
FWR#
FSEL#
SELIO#
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19 TV_THERM#
KB_CLK
KB_DATA
PS_CLK
PS_DATA
TP_CLK
TP_DATA
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EMPWR_BTN#
EC_SCI#
E-MAIL_BTN#
IE_BTN#
ENBKL
BKOFF#
FSTCHG
EC_SMI#
IDE_LED#
USER_BTN#
VGATE
LID_SW#
BT_ON#
SYSON
SUSP#
VR_ON
BTSW_EN#
PBTN_OUT#
CAPS_LED#
NUM_LED#
SATA_LED#
http://hobi-elektronika.net
1 2
FBM-L11-160808-800LMT_0603
C576
U24
15
LAD0
14
LAD1
13
LAD2
10
LAD3
9
LFRAME#
LRST#/GPIO2C
18
LCLK
7
SERIRQ
25
CLKRUN#/GPIO0C
24
LPCPD#/GPIO0B
RD#
WR#
MEMCS#
IOCS#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1/XIOP_TP
A2
A3
A4/DMRP_TP
A5/EMWB_TP
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20/GPIO23
E51CS#/GPIO20/ISPEN
PSCLK1
PSDAT1
PSCLK2
PS2 Interface
PSDAT2
PSCLK3
PSDAT3
SCL1
SDA1
SCL2
SDA2
8
GPIO04
20
GPIO07
21
GPIO08
22
GPIO09
27
GPIO0D
28
GPIO0E
48
GPIO10
62
GPIO13
63
GPIO14
69
GPIO15
70
GPIO16
75
GPIO17
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO2A
GPIO2B
GPIO2D
55
FnLock#/GPIO12
54
CapLock#/GPIO011
23
NumLock#/GPIO0A
41
ScrollLock#/GPIO0F
19
ECRST#
5
GA20/GPIO02
6
KBRST#/GPIO03
31
ECSCI#
2
C577
1000P_0402_50V7K
1
VCC16VCC34VCC45VCC
LPC Interface
*
*
X-BUS Interface
SMBus
GPIO
*
*
*
*
MISC
2
1000P_0402_50V7K
1
165
150
151
173
152
138
139
140
141
144
145
146
147
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
108
105
110
111
114
115
116
117
163
164
169
170
109
118
119
148
149
155
156
162
168
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
L57
+EC_VCCA
20mil
1
2
ECAGND
123
96
136
157
166
95
161
VCC
VCC
VCC
VCCA
AGND
Pulse Width
Wake Up Pin
ENE-KB910-B4
Analog To Digital
Digital To Analog
Expanded I/O
FAN
TEST_TP/GPIO05/FAN3PWM
Timer Pin
GND17GND35GND46GND
GND
GND
122
137
167
20mil
C578
0.1U_0402_16V4Z
159
GPOK0/KSO0
GPOK1/KSO1
VCCBAT
BATGND
GPOK2/KSO2
GPOK3/KSO3
GPOK4/KSO4
GPOK5/KSO5
GPOK6/KSO6
GPOK7/KSO7
GPOK8/KSO8
GPOK9/KSO9
GPOK10/KSO10
GPOK11/KSO11
GPOK12/KSO12
GPOK13/KSO13
GPOK14/KSO14
GPOK15/KSO15
GPOK16/KSO16
GPOK17/KSO17
GPIK0/KSI0
GPIK1/KSI1
GPIK2/KSI2
GPIK3/KSI3
GPIK4/KSI4
Internal Keyboard
GPIK5/KSI5
GPIK6/KSI6
GPIK7/KSI7
GPOW0/PWM0
GPOW1/PWM1
FAN2PWM/GPOW2/PWM2
GPOW3/PWM3
GPOW4/PWM4
GPOW5/PWM5
GPOW6/PWM6
FAN1PWM/GPOW7/PWM7
TIN1/GPWU6
TIN2/FANFB2/GPWU7
GPIAD0/AD0
GPIAD1/AD1
GPIAD2/AD2
GPIAD3/AD3
GPIAD4/AD4
GPIAD5/AD5
GPIAD6/AD6
GPIAD7/AD7
GPODA0/DA0
GPODA1/DA1
GPODA2/DA2
GPODA3/DA3
GPODA4/DA4
GPODA5/DA5
GPODA6/DA6
GPODA7/DA7
GPIO18/XIO8CS#
*
GPIO19/XIO9CS#
*
GPIO1A/XIOACS#
*
*
GPIO1B/XIOBCS#
GPIO1C/XIOCCS#
*
GPIO1D/XIODCS#
*
GPIO1E/XIOECS#
*
GPIO1F/XIOFCS#
*
GPIO2E/TOUT1/FANFB1
DPLL_TP/GPIO06/FANFB3
TOUT2/GPIO2F
E51IT0/GPIO00
E51IT1/GPIO01
E51RXD/GPIO21/ISPCLK
E51TXD/GPIO22/ISPDAT
KB910Q B4_LQFP176
KB910 C1 VERSION
0.1U_0402_16V4Z
GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
XCLKI
XCLKO
2005/06/20 2006/06/20
3
+3VALW
1
1
C579
2
2
KSO0
49
KSO1
50
KSO2
51
KSO3
52
KSO4
53
KSO5
56
KSO6
57
KSO7
58
KSO8
59
KSO9
60
KSO10
61
KSO11
64
KSO12
65
KSO13
66
KSO14
67
KSO15
68
KSO16
153
KSO17
154
KSI0
71
KSI1
72
KSI2
73
KSI3
74
KSI4
77
KSI5
78
KSI6
79
KSI7
80
INVT_PWM
32
BEEP#
33
VLDT_EN
36
ACOFF
37
38
EC_ON
39
EC_LID_OUT#
40
EC_MUTE
43
ON/OFF
2
26
29
PM_SLP_S3#
30
PM_SLP_S5#
44
EC_RCIRRX
76
EC_PME#
172
S3_STATE
176
BATT_TEMP
81
SKU_ID
82
BATT_OVP
83
84
87
TV_THERM#
88
AD_BID0
89
POUT
90
DAC_BRIG
99
100
IREF
101
EN_DFAN1
102
1
42
47
174
PWR_LED
85
PWR_SUSP_LED#
86
BATT_GRN_LED#
91
BATT_AMB_LED#
92
WL_LED#
93
BT_LED#
94
E-MAIL_LED#
97
MEDIA_LED#
98
FAN_SPEED1
171
DPLL_TP
12
TEST_TP
11
EC_THERM#
175
3
WLSW_EN#
4
E51_RXD
106
E51_TXD
107
CRY2
158
CRY1
160
Compal Secret Data
Deciphered Date
C580
1U_0402_6.3V4Z
KSO16 <34>
KSO17 <34>
INVT_PWM <29>
BEEP# <44>
VLDT_EN <42,46>
ACOFF <47,49>
USB_EN# <39,43>
EC_ON <42>
EC_LID_OUT# <23>
EC_MUTE <45>
ON/OFF <42>
ACIN <50>
PM_SLP_S3# <23>
PM_SLP_S5# <23>
S3_STATE <23>
BATT_OVP <49>
TV_THERM# <36>
POUT <54>
DAC_BRIG <29>
IREF <49>
EN_DFAN1 <5>
WL_OFF# <36>
MINI1_OFF# <36>
PWR_LED <43>
PWR_SUSP_LED# <43>
BATT_GRN_LED# <43>
BATT_AMB_LED# <43>
WL_LED# <43>
BT_LED# <43>
E-MAIL_LED# <43>
MEDIA_LED# <43>
FAN_SPEED1 <5>
EC_RSMRST# <23>
WLSW_EN# <43>
1 2
R477 0_0402_5%
2
KSI[0..7]
KSO[0..15]
2
KSI[0..7] <34>
KSO[0..15] <34>
+3VALW +3VALW
Ra
1 2
Rb
1 2
Board ID
VGA
UMA
ECAGND
12
C584 0.01U_0402_16V7K
EAPD
1
For EC Tools
+3VALW
JP76
1
1
E51_RXD
2
2
E51_TXD
3
3
4
4
ACES_85205-0400@
R797
100K_0402_5%
AD_BID0
1
R800
0_0402_5%
@
C582
2
0.1U_0402_16V4Z
Ra Rb Rc Rd
VX
VX
R472
100K_0402_5%
BATT_TEMP <50>
CRY1 CRY2
1
C585
10P_0402_50V8K
2
X2
32.768KHZ_12.5P_1TJS125DJ2A073
R481
100K_0402_5%@
EAPD
Title
Size Document Number Rev
B
星期四 三月
Date: Sheet
R465
1 2
SKU_ID
R801
0_0402_5%
PATA@
1 2
100K_0402_5%SATA@
1
2
C583
0.1U_0402_16V4Z
PATA@
Rc
Rd
SATA Status
W/S SATA
VVXX
W/O SATA
+3VS
12
1
4
OUT
NC3NC
+3VS
C586
10P_0402_50V8K
2
1
IN
2
12
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
1
33 55, 09, 2006
B
of
Page 34
http://hobi-elektronika.net
+3VALW
1
C588
1U_0402_6.3V4Z
MDC Conn.
JP14
1
ICH_SDOUT_MDC<23>
ICH_SYNC_MDC<23>
ICH_AC_SDIN1<23>
ICH_RST_MDC#<23>
ICH_SDOUT_MDC
R487 33_0402_5%
ICH_SYNC_MDC
1 2
ICH_RST_MDC#
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
IAC_BITCLK
GND13GND14GND15GND16GND17GND
RES0
RES1
3.3V
GND3
GND4
ACES_88018-124G
18
2
4
6
8
10
12
2
20mil
ICH_BITCLK_MDC
1
C589
22P_0402_50V8J
2
+3VALW
ICH_BITCLK_MDC <23>
Connector for MDC Rev1.5
BTN_L
2005/09/04
KSI[0..7]
KSO[0..15]
KSI[0..7] <33>
KSO[0..15] <33>
JP15
1
2
3
KSO17<33>
KSO16<33>
KSO17
KSI2
KSI5
KSO16
KSI3
KSI4
4
5
6
7
8
9
10
ACES_85201-10051Media@
+5VS
C590
0.1U_0402_16V4Z
INT_KBD Conn.
KSO15
C599 100P_0402_50V8J
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
KSO8
1 2
C601 100P_0402_50V8J
1 2
C603 100P_0402_50V8J
1 2
C605 100P_0402_50V8J
1 2
C607 100P_0402_50V8J
1 2
C609 100P_0402_50V8J
1 2
C611 100P_0402_50V8J
1 2
C614 100P_0402_50V8J
1 2
C616 100P_0402_50V8J
1 2
C618 100P_0402_50V8J
1 2
C620 100P_0402_50V8J
1 2
C622 100P_0402_50V8J
1 2
KSO7
C600 100P_0402_50V8J
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
KSI5
KSI7
1 2
C602 100P_0402_50V8J
1 2
C604 100P_0402_50V8J
1 2
C606 100P_0402_50V8J
1 2
C608 100P_0402_50V8J
1 2
C610 100P_0402_50V8J
1 2
C612 100P_0402_50V8J
1 2
C615 100P_0402_50V8J
1 2
C617 100P_0402_50V8J
1 2
C619 100P_0402_50V8J
1 2
C621 100P_0402_50V8J
1 2
C623 100P_0402_50V8J
1 2
(Right)
(Left)
KSO15
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
KSO8KSI4
KSO7
KSO6
KSO5
KSO4
KSO3
KSI4
KSO2
KSO1
KSO0
KSI5
KSI6KSI6
KSI7
JP17
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_85201-24051
BT_ON#<33>
SW2
EVQPLHA15_4P
3
4
1
2
5
6
Left Righ t
SW5
EVQPLHA15_4P
2
1
3
4
TP_DATA<33>
TP_CLK<33>
TP_DATA
TP_CLK
3
D34
@
PSOT24C_SOT23
1
2
5
6
+5VS
Modify 11/07 for EMI
12
R805
100K_0402_5%
11/01 modify
Scroll Up
SW1
SCRL_U
EVQPLHA15_4P
3
4
5
1
2
6
Scroll Down
SW4
SCRL_D
EVQPLHA15_4P
3
4
5
1
2
6
To TP/B Conn.
JP16
1
TP_DATA
TP_CLK
BTN_R
SCRL_R
SCRL_U
SCRL_L
SCRL_D
BTN_L
2
3
4
5
6
7
8
9
10
11
12
ACES_87151-1207
Bluetooth Conn.
+3VALW
1
C613
G
2
S
D
1 3
1
C624
4.7U_0805_10V4Z
2
1U_0402_6.3V4Z
2
Q16
SI2301BDS_SOT23
W=40mils
C625
0.1U_0402_16V4Z
+BT_VCC
SCRL_RSCRL_L
BTN_R
USB20_N5<23>
USB20_P5<23>
Scroll RightScroll Left
SW3
EVQPLHA15_4P
3
4
5
6
SW6
EVQPLHA15_4P
3
4
5
6
BTN_R
C591 100P_0402_50V8J
SCRL_R
C592 100P_0402_50V8J
SCRL_U
C593 100P_0402_50V8J
SCRL_L
C594 100P_0402_50V8J
SCRL_D
C595 100P_0402_50V8J
BTN_L
C596 100P_0402_50V8J
TP_DATA
C597 100P_0402_50V8J
TP_CLK
C598 100P_0402_50V8J
USB20_N5
WLAN_BT_DATA<36>
WLAN_BT_CLK<36>
1
2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
3
WCM2012F2S-900T04_0805
USB20_P5_R
USB20_N5_R
2
3
+BT_VCC
L76
1
1
4
4
SCRL_R
BTN_R
2
3
D19
@
PSOT24C_SOT23
1
SCRL_L
SCRL_U
2
3
D20
@
PSOT24C_SOT23
1
SCRL_D
BTN_L
2
3
D21
@
PSOT24C_SOT23
1
USB20_N5_R
USB20_P5_RUSB20_P5
JP18
1
2
3
4
5
6
7
8
ACES_87212-0800
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M /B LA-3151P
401412
星期四
09, 2006
三月
of
34 55,
B
Page 35
http://hobi-elektronika.net
KBA[0..19]<33>
ADB[0..7]<33>
U26
KBA18
1
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2
A18
2
A16
3
A15
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14
DQ1
15
DQ2
16
VSS
SST39VF040-70-4C-NH_PLCC32@
1MB Flash ROM
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
INT_FSEL#
FRD#
FWE#
U28
21
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
40
A17
13
A18
37
A19
22
CE#
24
OE#
9
WE#
SST39VF080-70_TSOP40
KBA[0..19]
ADB[0..7]
(CL55)
VCC0
VCC1
RP#
READY/BUSY#
NC0
NC1
GND0
GND1
NC
VDD
WE#
D0
D1
D2
D3
D4
D5
D6
D7
A17
A14
A13
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
0.1U_0402_16V4Z@
C627
1 2
INT_FLASH_EN#
+3VALW
1
+3VALW
2
C626
0.1U_0402_16V4Z@
32
FWE#
31
KBA17
30
KBA14
29
KBA13
28
KBA8
27
A8
KBA9
26
A9
KBA11
25
FRD#
24
KBA10
23
FSEL#
22
ADB7
21
ADB6
20
ADB5
19
ADB4
18
ADB3
17
1
0.1U_0402_16V4Z
FWE#
C628
1 2
+3VALW
4
O
5
U27
2
P
I0
1
I1
G
TC7SH32FU_SSOP5
3
+3VALW
12
R489
100K_0402_5%
2
G
1 3
D
Q17
2N7002_SOT23
FWR# <33>
S
SN74AHCT1G125DCKR_SC70-5@
SUSP# <33,39,46,51,53>
EC_FLASH# <23>
5
P
OE#
A2Y
G
3
U61
1 2
R829 0_0402_5%
4
1 2
+3VALW
R490
100K_0402_5%@
1 2
R491 22_0402_5%@
R488
10K_0402_5%
@
1 2
INT_FSEL#FSEL#
FOR DEBUG ONLY
+3VALW
1
5
P
SUS_STAT#<23>
SN74AHCT1G125DCKR_SC70-5@
+3VALW
31
30
ADB0
25
ADB1
26
ADB2
27
ADB3
28
ADB4
32
ADB5
33
ADB6
34
ADB7
35
RESET#
10
11
12
29
38
23
39
1 2
R493
100K_0402_5%
1
C629
0.1U_0402_16V4Z
2
+3VALW
1MB Flash ROM
KBA16 KBA17
KBA15
KBA14
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
JP19
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
SUYIN_80065AR-040G2T
@
KBA19KBA13
KBA10
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
FRD#
FSEL#
KBA0
+3VALW
FRD# <33>
FSEL# <33>
EC_SMB_CK1<33,50>
EC_SMB_DA1<33,50>
U62
+5VALW
C630 0.1U_0402_16V4Z
1 2
U29
8
VCC
7
WP
6
SCL
5
SDA
AT24C16AN-10SU-2.7_SO8
A2Y
G
3
OE#
GND
4
A0
A1
A2
INT_FLASH_SEL
+5VALW
1
2
3
4
12
12
SB_INT_FLASH_SEL# <23>
R492
100K_0402_5%
R494
100K_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/08 2006/03/08
Compal Secret Data
Deciphered Date
Title
SCHEMATIC, M /B LA-3151P
Size Document Number Rev
Custom
401412
Date: Sheet
星期四
09, 2006
三月
of
35 55,
B
Page 36
A
B
C
D
E
http://hobi-elektronika.net
+3VALW
1
1
C640
C641
0.1U_0402_16V4Z
2
2
+5VS
+3VALW
PCI_RST# <22,31,37,39,40>
+3VS
PCI_GNT#1 <22>
WLAN_BT_CLK <34>
PCI_PIRQG# <22>
MINI_PME# <33>
PCI_AD18
+3VALW+3VS +1.5VS
1
C642
4.7U_0805_10V4Z
2
SB_PCIE_WAKE#<23,39>
MINI1_CLKREQ#<15>
CLK_PCIE_MINI1#<15>
CLK_PCIE_MINI1<15>
PCIE_MRX_PTX_N1<12>
PCIE_MRX_PTX_P1<12>
PCIE_MTX_C_PRX_N1<12>
PCIE_MTX_C_PRX_P1<12>
1
2
SB_PCIE_WAKE#
WLAN_BT_DATA
WLAN_BT_CLK
MINI1_CLKREQ#
C643
0.1U_0402_16V4Z
1
C644
4.7U_0805_10V4Z
2
JP21
1
1
3
3
5
5
7
7
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
G153G254G355G3
+3VS
JP43
GND1
GND2
ACES_88266-05001
1
2
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
(MINI1_LED#)
44
46
48
50
52
FOX_AS0B226-S99N-7F
56
W=30mils
R851
+CAM_VDD
1 2
0_0805_5%
1
1
2
2
3
3
4
4
5
5
6
7
C645
0.1U_0402_16V4Z
1
C952
0.1U_0402_16V4Z
2
1
C646
0.1U_0402_16V4Z
2
MINI1_OFF#
NB_RST#
ICH_SMBCLK
ICH_SMBDATA
USB20_N4 <23>
USB20_P4 <23>
+3VALW
1
C647
0.1U_0402_16V4Z
2
+3VS
+1.5VS
MINI1_OFF# <33>
NB_RST# <13,16,22,27,33,41>
ICH_SMBCLK <15,39>
ICH_SMBDATA <15,39>
1
C637
2
RINGTIP
+3VS
1
C638
4.7U_0805_10V4Z
2
W=40mils
W=40mils
W=40mils
PCI_GNT#1
WLAN_BT_CLK
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL1
PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
AUDIO_INR
W=40mils
1
C639
0.1U_0402_16V4Z
2
1000P_0402_50V7K
R495
1 2
100_0402_5%
PCI_PAR <22,31,37,40>
PCI_FRAME# <22,31,37,40>
PCI_T RDY# <22,31,37,40>
PCI_STOP# <22,31,37,40>
PCI_DEVSEL# <22 ,3 1,37,40>PCI_PERR#<22,31,37,40>
PCI_CBE#0 <22,31,37,40>
TV_THERM# <33>
AUDIO_INR <43>
+3VALW
0.1U_0402_16V4Z
1
C631
1 1
2 2
3 3
2
1000P_0402_50V7K
PCI_PIRQH#<22,37>
CLK_PCI_MINI
12
R496
10_0402_5%@
1
C648
10P_0402_50V8K@
2
+5VS
1
2
1
C632
WLAN_BT_DATA<34>
C633
10U_0805_10V4Z
2
1000P_0402_50V7K
WL_OFF#<33>
+3VS
S_YIN<43> S_CIN <43>
CLK_PCI_MINI<22>
PCI_REQ#1<22>
PCI_CBE#3<22,31,37,40>
PCI_CBE#2<22,31,37,40>
PCI_IRDY#<22,31,37,40>
PM_CLKRUN#<22,31,41>
PCI_SERR#<22,31,37>
PCI_CBE#1<22,31,37,40>
CVBS_IN<43>
AUDIO_INL<43>
WL_OFF#
RB751V_SOD323
W=40mils
S_YIN S_CIN
CLK_PCI_MINI
PCI_REQ#1
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
WLAN_BT_DATA
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_CBE#2
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_CBE#1
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
CVBS_IN
PCI_AD3
+5VS
PCI_AD1
AUDIO_INL
+5VS
W=30mils W=20mils
1
2
W=40mils
1000P_0402_50V7K
C634
D22
1
C635
2
0.1U_0402_16V4Z
PCI_AD[0..31]
JP20
112
KEY KEY
334
556
778
9910
111112
21
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980
818182
838384
858586
878788
898990
919192
939394
959596
979798
9999100
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
P-TWO_A53921-A0G16-P
0.1U_0402_16V4Z
1
C636
2
PCI_AD[0..31] <22,26,31,37,40>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
(Change to SP070003200)
4 4
Power
+3VS
+3VALW
+1.5VS
A
Mini Card Power Rating
Primary Power (mA)
Peak Normal
1000
330
500
750
250
375
B
Auxiliary Power (mA)
Normal
250 (wake enable)
5 (Not wake enable)
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
D
2006/02/20 modify
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
E
of
36 55, 09, 2006
B
Page 37
A
+3VS
40mil
0.1U_0402_16V4Z
1
1
C650
C649
0.1U_0402_16V4Z
1 1
2 2
3 3
+3VS
1 2
R499 43K_0402_5%61@
SM_CD#
2
2
0.1U_0402_16V4Z
1
1
C652
C651
2
2
0.1U_0402_16V4Z
MFUNC5[3:0] = (0 1 0 1)
MFUNC5[4] = 1
0.1U_0402_16V4Z
PCI_CBE#[0..3]<22,31,36,40>
MS_PWREN#<38>
SDCK_XDWE#<38>
B
0.1U_0402_16V4Z
1
1
C654
C653
2
2
PCI_AD[0..31]<22,26,31,36,40>
CLK_PCI_PCM
12
R497
10_0402_5%@
1
C660
15P_0402_50V8J@
2
1 2
+3VS
R501 10K_0402_5%
0_0402_5%@
1
C655
2
0.1U_0402_16V4Z
PCI_AD[0..31]
PCI_CBE#[0..3]
12
R498
1
C661
2
R503
1 2
R505 33_0402_5%61@
1 2
SDCM_XDALE<38>
SDDA0_XDD7<38>
SDDA1_XDD0<38>
SDDA2_XDCL<38>
SDDA3_XDD4<38>
CLK_SD_48M
10_0402_5%@
15P_0402_50V8J@
PCI_RST#<22,31,36,39,40>
PCI_FRAME#<22,31,36,40>
PCI_IRDY#<22,31,36,40>
PCI_TRDY#<22,31,36,40>
PCI_DEVSEL#<22,31,36,40>
PCI_STOP#<22,31,36,40>
PCI_PERR#<22,31,36,40>
PCI_SERR#<22,31,36>
PCI_PAR<22,31,36,40>
PCI_REQ#2<22>
PCI_GNT#2<22>
CLK_PCI_PCM<22>
PCI_AD20
PCI_PIRQE#<22,40>
PCI_PIRQH#<22,36>
5IN1_LED#<33>
SDOC#<38>
SD_CD#<38>
SD_WP#<38>
SD_PWREN#<38>
CLK_SD_48M<15>
C
+3VS
http://hobi-elektronika.net
VPPD0<38>
VPPD1<38>
VCCD0#<38>
VCCD1#<38>
1 2
R502 100_0402_5%
SERIRQ<22,33,41>
+VCC_SD
VPPD0
VPPD1
VCCD0#
VCCD1#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
PCI_RST#
PCI_REQ#2
CLK_PCI_PCM
SD_PULLHIGH
SM_CD#
5IN1_LED#
SDOC#
PCI_RST#
SD_CD#
SD_WP#
SD_PWREN#
CLK_SD_48M
SD_CLK
SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4
U30
C2
AD31
C1
AD30
D4
AD29
D2
AD28
D1
AD27
E4
AD26
E3
AD25
E2
AD24
F2
AD23
F1
AD22
G2
AD21
G3
AD20
H3
AD19
H4
AD18
J1
AD17
J2
AD16
N2
AD15
M3
AD14
N3
AD13
K4
AD12
M4
AD11
K5
AD10
L5
AD9
M5
AD8
K6
AD7
M6
AD6
N6
AD5
M7
AD4
N7
AD3
L7
AD2
K7
AD1
N8
AD0
E1
CBE3#
J3
CBE2#
N1
CBE1#
N5
CBE0#
G4
PCIRST#
J4
FRAME#
K1
IRDY#
K3
TRDY#
L1
DEVSEL#
L2
STOP#
L3
PERR#
M1
SERR#
M2
PAR
A1
PCIREQ#
B1
PCIGNT#
H1
PCICLK
L8
RIOUT#_PME#
L11
SUSPEND#
F4
IDSEL
K8
MFUNC0
N9
MFUNC1
K9
MFUNC2
N10
MFUNC3
L10
MFUNC4
N11
MFUNC5
M11
MFUNC6
J9
MFUNC7
M10
GRST#
E7
VCC_SD
E8
SDCD#
F8
SDWP/SMWPD#
G7
SDPWREN33#
H5
SDCLKI
F6
SDCLK/SMWE#
E5
SDCMD/SMALE
E6
SDDAT0/SMDATA7
F7
SDDAT1/SMDATA0
F5
SDDAT2/SMCLE
G6
SDDAT3/SMDATA4
G5
GND_SD
+S1_VCC
N12
M12
N13
M13
VPPD0
VPPD1
VCCD0#
VCCD1#
PCI Interface
SD/MMC/MS/SM
G13
A7
VCCA1
VCCA2
GND1D3GND2H2GND3L4GND4M8GND5
G1
K2
N4
L6
C8
L9
H11
D12
B4
VCC3
VCC4
VCC5
VCC9
VCC6
VCC7
VCC8
VCC10
CAD15/IOWR#
CAD13/IORD#
CAD10/CE2#
CCBE3#/REG#
CCBE2#/A12
CCBE0#/CE1#
CARDBUS
CRST#/RESET
CFRAME#/A23
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19
CINT#/READY_IREQ#
CAUDIO/BVD2_SPKR#
CCD2#/CD2#
CCD1#/CD1#
MSPWREN#/SMPWREN#
MSBS/SMDATA1
MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3
GND6
GND7
GND8
CB714_LFBGA169
B6
61@
F12
K11
C10
CIRDY#/A15
CGNT#/WE#
F3
VCC2
VCC1
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD14/A9
CAD12/A11
CAD11/OE#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CCBE1#/A8
CPAR/A13
CCLK/A16
SPKROUT
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14
MSINS#
SMBSY#
SMCD#
SMWP#
SMCE#
D
S1_A[0..25]
S1_D[0..15]
S1_D10
B2
S1_D9
C3
S1_D1
B3
S1_D8
A3
S1_D0
C4
S1_A0
A6
S1_A1
D7
S1_A2
C7
S1_A3
A8
S1_A4
D8
S1_A5
A9
S1_A6
C9
S1_A25
A10
S1_A7
B10
S1_A24
D10
S1_A17
E12
S1_IOWR#
F10
S1_A9
E13
S1_IORD#
F13
S1_A11
F11
S1_OE#
G10
S1_CE2#
G11
S1_A10
G12
S1_D15
H12
S1_D7
H10
S1_D13
J11
S1_D6
J12
S1_D12
K13
S1_D5
J10
S1_D11
K10
S1_D4
K12
S1_D3
L13
S1_REG#
B7
S1_A12
A11
S1_A8
E11
S1_CE1#
H13
S1_RST
B9
S1_A23
B11
S1_A15
A12
S1_A22
A13
S1_A21
B13
S1_A20
C12
S1_A14
C13
S1_WAIT#
A5
S1_A13
D13
S1_INPACK#
B8
S1_WE#
C11
B12
S1_BVD1
C5
S1_WP
D5
S1_A19
D11
S1_RDY#
D6
PCM_SPK#
M9
S1_BVD2
B5
S1_CD2#
A4
S1_CD1#
L12
S1_VS2
D9
S1_VS1
C6
S1_D2
A2
S1_A18
E10
S1_D14
J13
H7
XD_PWREN#
J8
MSBS_XDD1
H8
MS_CLK
E9
MSD0_XDD2
G9
MSD1_XDD6
H9
MSD2_XDD5
G8
MSD3_XDD3
F9
H6
XD_CD#
J7
XD_WP#
J6
J5
1 2
S1_IOWR# <38>
S1_IORD# <38>
S1_OE# <38>
S1_CE2# <38>
S1_REG# <38>
S1_CE1# <38>
S1_RST <38>
S1_WAIT# <38>
S1_INPACK# <38>
S1_WE# <38>
S1_BVD1 <38>
S1_WP <38>
S1_RDY# <38>
PCM_SPK# <44>
S1_BVD2 <38>
S1_CD2# <38>
S1_CD1# <38>
S1_VS2 <38>
S1_VS1 <38>
1 2
XD_BSY# <38>
XD_CD# <38>
XD_WP# <38>
XD_CE# <38>
S1_A16
33_0402_5%61@
1 2
R500 33_0402_5%
R504
R506
2.2K_0402_5%
61@
MS_INS# <38>
XD_PWREN# <38>
MSBS_XDD1 <38>
MSCLK_XDRE# <38>
MSD0_XDD2 <38>
MSD1_XDD6 <38>
MSD2_XDD5 <38>
MSD3_XDD3 <38>
S1_A[0..25] <38>
S1_D[0..15] <38>
+3VS
1
C656
4.7U_0805_10V4Z
2
+S1_VCC
1
C658
0.1U_0402_16V4Z
2
S1_CD2# S1_CD1#
C662
10P_0402_50V8K
2
1
E
1
C657
0.1U_0402_16V4Z
2
1
C659
0.1U_0402_16V4Z
2
C663
10P_0402_50V8K
2
1
**CB714 use B0 version
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
401412
星期四 三月
E
B
of
37 55, 09, 2006
Page 38
A
PCMCIA Power Control
+S1_VCC
1 1
W=40mil
1
C667
10U_0805_10V4Z
2
1
C668
2
0.1U_0402_16V4Z
W=40mil
1
C671
10U_0805_10V4Z
2
2 2
1
C672
2
0.1U_0402_16V4Z
+5VS
+3VS
9
5
6
3
4
12
R508
10K_0402_5%
U31
12V
5V
5V
3.3V
3.3V
7
VCCD0#
R513 10K_0402_5%
VCCD1#
R514 10K_0402_5%
VCC
VCC
VCC
VPP
VCCD0
VCCD1
VPPD0
VPPD1
OC
GND
SHDN
CP2211FD3_SSOP16
16
1 2
1 2
40mil
13
12
11
10
1
2
15
14
8
VCCD0#
VCCD1#
VPPD0
VPPD1
SD/MS Power Control
XD Power Control
+3VS
3 3
SD_PWREN#<37>
MS_PWREN#<37>
10K_0402_5%61@
XD_PWREN#
SD_PWREN#
R518
1 2
12
R523
0_0402_5%
61@
U32
1
GND
OUT
2
IN
OUT
3
OUT
IN
4
FLG
EN#
G528_SO8
61@
XD_PWREN#
1 2
R524 0_0603_5%
61@
40mil
+VCC_XD+3VS
8
7
6
SDOC#
5
12
13
D
2
G
S
+VCC_SD+VCC_XD
R522
300_0402_5%61@
Q18
40mil
+3VS
2N7002_SOT2361@
+S1_VPP
1 2
B
1
C666
0.1U_0402_16V4Z
2
VCCD0# <37>
VCCD1# <37>
VPPD0 <37>
VPPD1 <37>
R517
10K_0402_5%61@
SDOC# <37>XD_PWREN#<37>
http://hobi-elektronika.net
+S1_VCC
1
C664
10U_0805_10V4Z
2
+S1_VPP
1
C669
2
10U_0805_10V4Z
S1_OE#
1 2
R507 43K_0402_5%
S1_WP
R509 43K_0402_5%
S1_RST
1 2
R510 43K_0402_5%
S1_CE1#
1 2
R511 43K_0402_5%
S1_CE2#
1 2
R512 43K_0402_5%
xD PU and PD. Close to Socket
+3VS
R515 43K_0402_5%@
+VCC_XD
1 2
R516 2.2K_0402_5%61@
1 2
R519 2.2K_0402_5%61@
1 2
R520 2.2K_0402_5%61@
1 2
R521 2.2K_0402_5%61@
Reserve for SD,MS CLK.
Close to Socket
SDCK_XDWE#
C678 10P_0402_50V8K
MSCLK_XDRE#
C679 10P_0402_50V8K
C670
12
XD_CD#
12
MSCLK_XDRE#
1 2
1 2
1
C665
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
SDCK_XDWE#
XD_CE#
XD_BSY#
61@
61@
+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC
+S1_VCC
C
+VCC_SD
1
2
SDDA1_XDD0<37>
MSBS_XDD1<37>
MSD0_XDD2<37>
MSD3_XDD3<37>
SDDA3_XDD4<37>
MSD2_XDD5<37>
MSD1_XDD6<37>
SDDA0_XDD7<37>
SDCK_XDWE#<37>
SDCM_XDALE<37>
MSCLK_XDRE#<37>
SDDA2_XDCL<37>
S1_A[0..25]
S1_D[0..15]
C674
0.1U_0402_16V4Z
61@
+VCC_XD
C676
10U_0805_10V4Z
61@
+VCC_XD
XD_WP#<37>
XD_CD#<37>
XD_BSY#<37>
XD_CE#<37>
1
2
1
2
1
C675
0.1U_0402_16V4Z
2
61@
1
C677
0.1U_0402_16V4Z
2
61@
SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7
SDCK_XDWE#
XD_WP#
SDCM_XDALE
XD_CD#
XD_BSY#
MSCLK_XDRE#
XD_CE#
SDDA2_XDCL
41
33
34
35
36
37
38
39
40
30
31
29
23
25
26
27
28
32
24
42
18
S1_A[0..25]<37>
S1_D[0..15]<37>
C673
10U_0805_10V4Z61@
D
PCMCIA Socket
S1_CD1#<37>
S1_CE1#<37>
S1_CE2#<37>
S1_OE#<37>
S1_VS1<37>
S1_IORD#<37>
S1_IOWR#<37>
S1_WE#<37>
S1_RDY#<37>
+S1_VCC
+S1_VCC
+S1_VPP
+S1_VPP
S1_VS2<37>
S1_RST<37>
S1_WAIT#<37>
S1_INPACK#<37>
S1_REG#<37>
S1_BVD2<37>
S1_BVD1<37>
S1_WP<37>
S1_CD2#<37>
4 IN 1 Socket
(HDQ70)
JP23
XD-VCC
XD-D0
4 IN 1 CONN
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-GND
XD-GND
N.C.
N.C.
TAITW_R007-530-L3
61@
S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
S1_A16
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-CMD
SD-CD-SW
SD-CD-COM
SD-WP-SW
SD-WP-COM
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-GND
MS-GND
SD-VCC
MS-VCC
SD_CLK
MS-INS
MS-BS
SD-GND
SD-GND
1
GND
35
GND
2
DATA3
36
CD1#
3
DATA4
37
DATA11
4
DATA5
38
DATA12
5
DATA6
39
DATA13
6
DATA7
40
DATA14
7
CE1#
41
DATA15
8
ADD10
42
CE2#
9
OE#
43
VS1#
10
ADD11
44
IORD#
11
ADD9
45
IOWR#
12
ADD8
46
ADD17
13
ADD13
47
ADD18
14
ADD14
48
ADD19
15
WE#
49
ADD20
16
READY
50
ADD21
17
VCC
51
VCC
18
VPP
52
VPP
19
ADD16
53
ADD22
20
ADD15
54
ADD23
21
ADD12
55
ADD24
22
ADD7
56
ADD25
23
ADD6
57
VS2#
24
ADD5
58
RESET
25
ADD4
59
WAIT#
26
ADD3
60
INPACK#
27
ADD2
61
REG#
28
ADD1
62
BVD2
29
ADD0
63
BVD1
30
DATA0
64
DATA8
31
DATA1
65
DATA9
32
DATA2
66
DATA10
33
WP
67
CD2#
34
GND
68
GND
SANTA_130601-7_LT
15
9
SDCK_XDWE#
16
SDDA0_XDD7
19
SDDA1_XDD0
20
SDDA2_XDCL
11
SDDA3_XDD4
12
SDCM_XDALE
13
SD_CD#
21
22
SD_WP#
43
44
MSCLK_XDRE#
8
MSD0_XDD2
4
MSD1_XDD6
3
MSD2_XDD5
5
MSD3_XDD3
7
MS_INS#
6
MSBS_XDD1
2
14
17
1
10
GND
GND
JP22
(NEW)
69
70
+VCC_SD
E
SD_CD# <37>
SD_WP# <37>
MS_INS# <37>
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
B
of
38 55, 09, 2006
E
Page 39
A
B
C
D
E
http://hobi-elektronika.net
New Card Power Switch
U63
CP_USB#
CP_PE#
SUSP#
SYSON
PCI_RST#
5
3.3Vin1
6
3.3Vin2
21
3.3Vaux_in
18
1.5Vin1
19
1.5Vin2
14
CPUSB#
15
CPPE#
4
STBY#
SHDN#3RCLKEN
2
SYSRST#
GND
11
1
C689
10U_0805_10V4Z
2
NC@
3.3Vout1
3.3Vout2
1.5Vout1
1.5Vout2
PERST#
NC11NC210NC312NC413NC5
24
+3VS
1 1
R525 100K_0402_5%NC@
+3VALW
2 2
10U_0805_10V4Z
NC@
1 2
R526 100K_0402_5%NC@
1 2
SUSP#<33,35,46,51,53>
SYSON<33,46>
PCI_RST#<22,31,36,37,40>
+3VS +1.5VS+3VALW
1
C687
2
1
C688
10U_0805_10V4Z
2
NC@
+3VALW
+1.5VS
7
8
20
Aux_out
16
17
23
OC#
22
9
TPS2231PWPR_PWP24
NC@
60mils
40mil
40mil
RCLKEN1
PERST1#
+3VS_CARD1
+3VALW_CARD1
+1.5VS_CARD1
USB20_P1<23>
+3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1
1
C680
10U_0805_10V4Z
NC@
10K_0402_5%
NC@
RCLKEN1
USB20_P1
USB20_N1
R528
2
G
1
2
+3VS
12
13
D
Q42
2N7002_SOT23
NC@
S
C681
2
0.1U_0402_16V4Z
NC@
R527
10K_0402_5%
NC@
CLKREQ1#
2
3
WCM2012F2S-900T04_0805@
2
3
C682
10U_0805_10V4Z
NC@
+3VS +3VS
12
2
B
1
A
1 2
R821 0_0402_5%USB@
1 2
R823 0_0402_5%USB@
Imax = 1.35A Imax = 0.75AImax = 0.275A
1
1
2
2
0.1U_0402_16V4Z
NC@
1
C686
0.1U_0402_16V4Z
2
NC@
5
U64
4
Vcc
Y
G
NC7SZ32P5X_NL_SC70-5
3
NC@
L65
1
1
USB20_P1_R
USB20_N1_R
4
4
C683
USB Component co-layout
1
C684
10U_0805_10V4Z
2
NC@
EXP_CLKREQ# <15>
1
C685
2
0.1U_0402_16V4Z
NC@
USB20_N2<23>
USB20_P2<23>USB20_N1<23>
USB20_N2
USB20_P2
New Card Socket (Left)
USB20_N0<23>
ICH_SMBDATA<15,36>
+1.5VS_CARD1
SB_PCIE_WAKE#<23,36>
+3VALW_CARD1
+3VS_CARD1
CLK_PCIE_CARD#<15>
CLK_PCIE_CARD<15>
PCIE_MRX_PTX_N0<12>
PCIE_MRX_PTX_P0<12>
PCIE_MTX_C_PRX_N0<12>
PCIE_MTX_C_PRX_P0<12>
2
3
WCM2012F2S-900T04_0805@
USB20_P0<23>
ICH_SMBCLK<15,36>
CP_PE#<23>
1 2
R822 0_0402_5%
2
3
1 2
R824 0_0402_5%
CP_USB#
PERST1#
CLKREQ1#
CP_PE#
L66
1
1
USB20_N2_R
USB20_P2_R
4
4
JP24
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
TYCO_1759056-1
NC@
(NEW)
USB CONN. 1 & 2
+USB_VCCA+USB_VCCA
+USB_VCCA
1
+
3 3
+5VALW
1
C694
4.7U_0805_10V4Z
2
USB_EN#<33,43>
4 4
USB_EN#
A
U35
1
GND
2
IN
3
IN
4
EN#
G528_SO8
OUT
OUT
OUT
FLG
+USB_VCCA
8
7
6
5
R530
0_0402_5%
1 2
B
1
C695
0.1U_0402_16V4Z
2
@
USB_OC#0 <23>
C690
150U_D_6.3VM
2
USB@
1
C692
470P_0402_50V7K
2
USB@
USB20_P1_R
2005/09/06 2005/09/06
JP25
1
2
3
4
SUYIN_020173MR004S312ZL
USB@
ECQ60 ECQ60
D23
1
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
4
VCC
GND
I/O
I/O
PRTR5V0U2X_SOT143@
+USB_VCCA
3
SUYIN_020173MR004G533ZR_4P
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
+USB_VCCA
1
+
C691
150U_D_6.3VM
2
D
USB20_P2 USB20_N2USB20_P1 USB20_N1
W=80milsW=80mils
1
C693
470P_0402_50V7K
2
USB20_N2_RUSB20_N1_R
USB20_P2_R
D24
1
GND
2
I/O
PRTR5V0U2X_SOT143@
SUYIN_020173MR004G533ZR_4P
Title
Size Document Number Rev
B
Date: Sheet
JP26
1
2
3
4
SUYIN_020173MR004S312ZL
4
VCC
I/O
+USB_VCCA
3
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
星期四 三月
401412
E
B
of
39 55, 09, 2006
Page 40
A
B
C
D
E
C699
0.1U_0402_16V4Z
1394@
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_STOP#
PCI_PERR#
PCI_PAR
PCI_PIRQE#
CLK_PCI_1394
PCI_GNT#0
PCI_REQ#0
1394_IDSEL
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_FRAME#
12
R541
10_0402_5%@
1
C714
10P_0402_50V8K@
2
+2.5VS_1394
1
2
C700
0.1U_0402_16V4Z
1394@
+2.5VS_1394
U37
94
AD31
95
AD30
96
AD29
97
AD28
98
AD27
101
AD26
102
AD25
103
AD24
106
AD23
107
AD22
109
AD21
113
AD20
114
AD19
115
AD18
116
AD17
117
AD16
2
AD15
3
AD14
4
AD13
7
AD12
8
AD11
9
AD10
10
AD9
11
AD8
14
AD7
PCI I/F
15
AD6
16
AD5
18
AD4
19
AD3
20
AD2
24
AD1
25
AD0
104
CBE3#
119
CBE2#
1
CBE1#
12
CBE0#
125
STOP#
127
PERR#
128
PAR
88
INTA#
89
PCIRST#
90
PCICLK
92
GNT#
93
REQ#
105
IDSEL
34
PME#
121
IRDY#
123
TRDY#
124
DEVSEL#
120
FRAME#
1
C701
0.1U_0402_16V4Z
2
1394@
+3VS
111
122
VDD446VDD330VDD221VDD1
VCC699VCC536VCC417VCC35VCC2
VT6311S
OSCILLATOR
PHY PORT0
PHY PORT1
GNDATX166GNDARX165GNDATX280GNDARX279GND19
GND18
GND17
GND16
GND1591GND1061GND956GND847GND738GND633GND531GND423GND322GND26GND113GND0
118
112
108
100
1
C702
0.1U_0402_16V4Z
2
1394@
110
VCC1
EEPROM
others
+3VS
1
C696
0.1U_0402_16V4Z
2
1394@
1 1
2 2
3 3
4 4
1
C697
0.1U_0402_16V4Z
2
1394@
PCI_AD[0..31]<22,26,31,36,37>
PCI_AD16 1394_IDSEL
PCI_AD[0..31]
IDSEL:PCI_AD16
1 2
R538 100_0402_5%1394@
1
C698
0.1U_0402_16V4Z
2
1394@
PCI_CBE#3<22,31,36,37>
PCI_CBE#2<22,31,36,37>
PCI_CBE#1<22,31,36,37>
PCI_CBE#0<22,31,36,37>
PCI_STOP#<22,31,36,37>
PCI_PERR#<22,31,36,37>
PCI_PAR<22,31,36,37>
PCI_PIRQE#<22,37>
PCI_RST#<22,31,36,37,39>
CLK_PCI_1394<22>
PCI_GNT#0<22>
PCI_REQ#0<22>
PCI_IRDY#<22,31,36,37>
PCI_TRDY#<22,31,36,37>
PCI_DEVSEL#<22,31,36,37>
PCI_FRAME#<22,31,36,37>
CLK_PCI_1394
1
2
http://hobi-elektronika.net
1
C703
0.1U_0402_16V4Z
2
1394@
20mils
+1394_PLLVDD
59
PVA587PVA486PVA373PVA272PVA162PVA0
SDA/EEDI
SCL/EECK
PHYRST#
BJT_CTL
PWRDET
REG_FB
REG_OUT
XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0
XTPB1M
XTPB1P
XTPA1M
XTPA1P
XTPBIAS1
126
EECS
EEDO
I2CEN
XCPS
XREXT
XI
XO
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0
VT6311S_LQFP128
1394@
0.1U_0402_16V4Z1394@
1
C704
2
EECS
EEDI
EECK
I2CEEN
REG_FB
REG_OUT
XREXT
10mils
1394_XI
1394_XO
TPB0-
TPB0+
TPA0TPA0+
TPBIAS0
R532
R533 4.7K_0402_5%@
R534 4.7K_0402_5%@
R535 4.7K_0402_5%1394@
R536 1K_0402_5%1394@
R537 6.19K_0603_1%1394@
26
27
28
29
55
81
43
32
84
85
60
63
57
58
67
68
69
70
71
74
75
76
77
78
83
82
64
54
53
52
51
50
49
48
45
44
42
41
40
39
37
35
0.1U_0402_16V4Z1394@
1
1
C705
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
0.1U_0402_16V4Z1394@
C708 1U_0402_6.3V4Z1394@
C709 0.1U_0402_16V4Z1394@
C711 47P_0402_50V8J1394@
C706
1 2
1
C707
4.7U_0805_10V4Z1394@
2
+3VS
4.7K_0402_5%1394@
VCC
WP
SCL
SDA
40mil
8
7
6
5
2
B
+3VS
EECK
EEDI
+3VS
31
E
Q43
2SB1197K_SOT23@
C
+2.5VS_1394
When use external BJT
Populate Q35, R279
12
R531
510_0402_5%
@
U36
1
A0
2
A1
3
A2
4
GND
AT24C02N-10SU-2.7_SO8
@
EECK and EEDI is pull high internal
L59
MBK1608301YZF_06031394@
+3VS
+3VS
C710
10P_0402_50V8K1394@
1 2
Y5
1394@
24.576MHZ_16P_X8A024576FG1H
1 2
1 2
C712
10P_0402_50V8K1394@
External pull h ig h ci rcuit is unnecessary
When use exte r n a l EEPROM
Populate U14, R246, R253
Un-populate R261
REG_OUT
REG_FB
15mils
1
C713
0.33U_0603_10V7K1394@
2
JP27
4
4
3
6
3
6
5
2
5
2
1
1
FOX_UV31413-4R1-TR
54.9_0402_1%1394@
4.99K_0402_1%1394@
1394@
(ECQ60)
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-
12
R539
54.9_0402_1%
1394@
12
R542
54.9_0402_1%
1394@
1
C715
270P_0402_50V7K
1394@
2
12
R540
54.9_0402_1%
1394@
12
R543
12
R544
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
401412
星期四 三月
E
B
of
40 55, 09, 2006
Page 41
LPC_AD0<22,33>
LPC_AD1<22,33>
LPC_AD2<22,33>
LPC_AD3<22,33>
LPC_DRQ#0<22>
LPC_FRAME#<22,26,33>
PM_CLKRUN#<22,31,36>
SERIRQ<22,33,37>
CLK_PCI_SIO<22>
NB_RST#<13,16,22,27,33,36>
CLK_14M_SIO<15>
+3VS
+3VS
1 2
R547 10K_0402_5%
1 2
R548 10K_0402_5%@
CLK_14M_SIO
R552
10_0402_5%@
1 2
2
C719
15P_0402_50V8J@
1
CLK_PCI_SIO
Place on the BOT side(near MINIPCI conn.)
+5VS
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_FRAME#
PM_CLKRUN#
SERIRQ
CLK_PCI_SIO
NB_RST#
CLK_14M_SIO
SIO_PD#
SIO_PME#
1 2
2
1
JP28
1
2
3
4
5
6
7
8
9
10
ACES_85201-10051@
U38
64
LAD0
2
LAD1
4
LAD2
7
LAD3
10
LPC_CLK_33
12
LDRQ1#
24
LDRQ0#
14
LFRAME#
16
CLKRUN#
19
SERIRQ
21
PCI_CLK
22
PCIRST#
23
SIO_14M
25
LPCPD#
47
IO_PME#
63
DLAD0
1
DLAD1
3
DLAD2
6
DLAD3
9
DLPC_CLK_33
11
DLDRQ1#
13
DLFRAME#
15
DCLKRUN#
18
DSER_IRQ
26
DSIO_14M
LPC47N207-JN_STQFP64
@
RTS#1
Base I/O Address
*
R553
33_0402_5%@
C720
22P_0402_50V8J@
SUPER I/O SMsC LPC47N207
+3VS
0.1U_0402_16V4Z
0 = 02Eh
1 = 04Eh
1
C716
FIR@
2
0.1U_0402_16V4Z
+3VS
3.3V53.3V173.3V313.3V423.3V
LPC I/F
DLPC I/F
1
2
60
48
GPIO
DTR1#/SYSOPT1
SERIAL I/F
IR
GND08GND120GND229GND337GND445GND5
C717
FIR@
VTR
GPIO10
GPIO11
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO15
GPIO16
GPIO17
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
RXD1
TXD1
DRSR1#
RTS1#/SYSOPT0
CTS1#
RI1#
DCD1#
IRTX2
IRRX2
IRMODE/IRRX3
62
1
C718
FIR@
0.1U_0402_16V4Z
2
27
28
30
32
33
34
35
36
38
39
40
41
43
44
46
61
52
53
54
55
56
57
58
59
49
50
51
DCD#1
RI#1
CTS#1
DSR#1
RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
IRTXOUT
IRRX
IRMODE
1 8
2 7
3 6
4 5
RP10
4.7K_1206_8P4R_5%
FIR@
http://hobi-elektronika.net
+3VS
1 2
R545 10K_0402_5%@
1 2
R546 10K_0402_5%@
1 2
R549 10K_0402_5%@
1 2
R550 10K_0402_5%@
1 2
R551
FIR@
10K_0402_5%
+3VS
+3VS
+3VS
FIR Module
FIR@
1 2
R556
47_1206_5%
1 2
R802 10K_0402_5%@
1 2
R803 10K_0402_5%
+IR_3VS
1
1
C722
FIR@
10U_0805_10V4Z
2
2
SIO2@
W=40mil
C723
FIR@
0.1U_0402_16V4Z
+3VS
LPC_FRAME#
LPC_DRQ#0
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
NB_RST#
SIO_PD#
PM_CLKRUN#
SERIRQ
CLK_PCI_SIO
CLK_14M_SIO
BASE_ADDRESS
+3VS
C721
FIR@
4.7U_0805_10V4Z
+IR_3VS
U65
3
VCC
14
VCC
22
VCC
7
LFRAME#
8
LDRQ#
2
LAD0
4
LAD1
5
LAD2
6
LAD3
9
PCI_RESET#
10
LPCPD#
11
CLKRUN#
13
SER_IRQ
12
PCI_CLK
1
CLOCKI
18
GPIO/SYSOPT1
Base I/O Address
0 = 004Eh*
FIR@
1 2
R554 0_1206_5%
FIR@
1 2
1
R555 0_1206_5%
2
IR1
2
IRED_C
4
RXD
6
VCC
8
GND
TFDU6102-TR3_8P
FIR@
LPC I/F
IRED_A
TXD
SD/MODE
MODE
FIR
IRMODE/ALT_IRRX
SLCTIN#
PARALLEL I/F
BUSY
ERROR#
STROBE#
GROUND PAD
SIO1036-AEZG_QFN36
SIO2@
+IR_ANODE
W=60mil
1
T = 12mil
3
5
T = 12mil
7
IRRX
IRTX
INIT#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
ACK#
ALF#
VSS
IRRX
15
IRTXOUT
16
IRMODE
17
19
20
21
23
24
25
26
27
28
29
30
31
PE
32
33
34
35
36
37
IRTXOUT
IRMODEIRRX
For SW debug use when no seial port
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
of
41 55, 09, 2006
B
Page 42
A
B
C
D
E
http://hobi-elektronika.net
+3VALW
Power ON Circuit
2
C724
0.1U_0402_16V4Z
1 1
VLDT_EN<33,46> SB_PWRGD <7,23>
VLDT_EN
R560
10K_0402_5%
R557
470K_0402_5%
1 2
12
0.1U_0402_16V4Z
1
C725
2
14
1
7
1
P
O2I
G
U39A
SN74LVC14APWLE_TSSOP14
+3VALW +3VALW +3VALW
14
P
3
O4I
G
U39B
SN74LVC14APWLE_TSSOP14
7
R558
200K_0402_5%
1 2
0.47U_0603_16V7K
C726
R561
10_0402_5%
1 2
1
2
14
P
5
O
I
G
U39C
SN74LVC14APWLE_TSSOP14
7
NB_PWRGD <13>
6
14
P
9
O
I
G
U39D
SN74LVC14APWLE_TSSOP14
7
R559
8
10_0402_5%
1 2
note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,
SUSP# goes to low after SB_PWRGD goes to low for power
down.
T1
VLDT_EN
NB_PWRGD
SB_PWRGD
2 2
SUSP#
T2
+1.8VS
ON/OFF switch
TOP Side
12
J2 JOPEN@
12
J3 JOPEN@
EC_ON<33>
Bottom Side
ON/OFFBTN#
EC_ON
10K_0402_5%
DAN202U_SC70
R564
1 2
3 3
ON/OFFBTN#<43>
4 4
A
+3VALW
Power Button
R562
100K_0402_5%
2
G
1 2
2
3
13
D
S
2N7002_SOT23
51ON#
2
C727
1000P_0402_50V7K
1
Q44
B
ON/OFF <33>
51ON# <47>
12
D27
RLZ20A_LL34
Lid Switch
Change P/N : SN111000207
SW7
3
4
MPU-101-81_4P
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/08 2006/03/08
C
Compal Secret Data
Deciphered Date
1
2
2005/09/04
D
D25
1
2
1
+3VALW
12
3
D26
@
PSOT24C_SOT23
R563
100K_0402_5%
LID_SW# <33>
Compal Electronics, inc.
Title
SCHEMATIC, M /B LA-3151P
Size Document Number Rev
B
401412
Date: Sheet
星期四
09, 2006
三月
42 55,
E
B
of
Page 43
http://hobi-elektronika.net
PWR_LED#
13
D
PWR_LED<33>
12
R568
300_0402_5%
21
3
2
G
Q45
S
2N7002_SOT23
+5VS+5VS
12
R569
300_0402_5%
21
LED4
HT-110UD_1204
WL_LED# <33> BT_LED# <33>
3
LED5
HT-110NBQA_BULE_1204
BT_LED#WL_LED#
BT_SW
5
2005/09/12 2005/09/12
1
5
1
2
2
3
3
4
4
6
SW8
6
HSS110_4P
5
5
1
2
3
4
6
SW9
6
HSS110_4P
WL_SW
1
2
3
4
R565
300_0402_5%
1 2
+5VS
R566
300_0402_5%
R571
100_0805_5%
CIR@
C730
CIR@
1 2
R567
300_0402_5%
1 2
R570
300_0402_5%
1 2
+3VALW
12
1
2
+5VALW
+5VALW
+5VALW
WLSW_EN#BTSW_EN#
WLSW _EN# <33>BTSW_EN# <33>
4.7U_0805_10V4Z
LED1
2 1
3
HT-110UYG_1204
LED2
2 1
3
HT-110UD_1204
LED3
2 1
3
HT-110UYG_1204
LED6
2 1
3
HT-110UD_1204
PWR_LED#
PWR_SUSP_LED#
BATT_GRN_LED#
BATT_AMB_LED#
Update Part N u m ber to SCR36236000
CIR
IR2
4
Vs3OUT
1
2
GND
GND
TSOP36236TR_4PCIR@
PWR_SUSP_LED# <33>
BATT_GRN_LED# <33>
BATT_AMB_LED# <33>
RCIRRX
1
C731
CIR@
1000P_0402_50V7K
2
RCIRRX <33>
To LED/B Conn.
MEDIA_LED#<33>
CAPS_LED#<33>
NUM_LED#<33>
E-MAIL_LED#<33>
ON/OFFBTN#<42>
E-MAIL_BTN#<33>
IE_BTN#<33>
USER_BTN#<33>
EMPWR_BTN#<33>
CVBS_IN<36>
S_YIN<36>
S_CIN<36>
+5VS
PWR_LED#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
JP29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
GND31GND32GND33GND34GND35GND
+5VALW
C728
0.1U_0402_16V4Z
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
ACES_88018-304G
36
USB20_N3
USB20_P3
USB20_N6
USB20_P6
1
+
C729
150U_D_6.3VM
2
+5VALW
USB20_N3 <23>
USB20_P3 <23>
USB20_N6 <23>
USB20_P6 <23>
USB_EN# <33,39>
AUDIO_INL <36>
AUDIO_INR <36>
Geneva Grapevine
2005/09/04
KSO16 KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
VOL_UP
RIGHT
PLAY
STOP
NEXT
REV
LEFT
VOL_DOWN
ENTER
RECORD
KSI2
KSI3
KSI4
KSI5
KSO16
PLAY
STOP
NEXT
REV
KSO17
VOL_UP
VOL_DOWN
ARCADE_TV
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/06/20 2006/06/20
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
of
43 55, 09, 2006
B
Page 44
A
1 1
BEEP#<33>
PCM_SPK#<37>
SB_SPKR<23>
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C527
C528
C533
1 2
1 2
1 2
B
R430
1 2
560_0402_5%
R433
1 2
560_0402_5%
R438
1 2
560_0402_5%
10K_0402_5%
R442
12
2
B
+VDDA
C
E
2 1
12
12
1
3
C
R689
10K_0402_5%
1 2
C542 1U_0603_10V4Z
R688
10K_0402_5%
C535
1 2
1U_0402_6.3V4Z
Q19
2SC2411K_SC59
D16
RB751V_SOD323
1 2
R687
2.4K_0402_5%
D
E
http://hobi-elektronika.net
+5VAMP
L32
+5VS
MONO_IN
1 2
KC FBM-L11-201209-221LMAT_0805
L33
1 2
KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z
1
C550
2
1
C553
2
0.1U_0402_16V4Z
60mil
F
U34
4
VIN
2
DELAY
ERROR7CNOISE
8
SD
SI9182DH-AD_MSOP8
G
28.7K for Module Design (VDDA = 4.702)
(output = 250 mA)
40mil
VOUT
SENSE or ADJ
GND
5
6
1
3
1
2
0.1U_0402_16V4Z
C548
30K_0402_1%
1 2
12
1
R452
2
R451
10K_0402_1%
+VDDA
4.85V
C558
10U_0805_10V4Z
H
HD Audio Codec
+AVDD_AC97
1
2
0.1U_0402_16V4Z
LINE_C_L
LINE_C_R
CD_L_RC
CD_R_RC
CD_AGND_RC
MIC1_C_L
MONO_IN
40mil
1
C559
2
DGND
U33
AVDD125AVDD2
14
LINE2_L
15
LINE2_R
16
MIC2_L
17
MIC2_R
23
LINE1_L
24
LINE1_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1_L
22
MIC1_R
12
PCBEEP
11
RESET#
10
SYNC
5
SDATA_OUT
2
GPIO0
3
GPIO1
13
SENSE A
34
SENSE B
47
SPDIFI/EAPD
48
SPDIFO
4
DVSS1
7
DVSS2
ALC883-LF_LQFP48
L34
+VDDA
2 2
Modify 11/07 for EMI
3 3
1 2
R826 0_0603_5%
1 2
R827 0_0603_5%
1 2
R589 0_0603_5%
1 2
R590 0_0603_5%
1 2
R592 0_0603_5%
1 2
FBM-L11-160808-800LMT_0603
10U_0805_10V4Z
LINE_L<45>
LINE_R<45>
MIC1_L<45>
MIC1_R<45>
MIC1_L
MIC1_R MIC1_C_R
2005/09/12
SPDIF<45>
0.1U_0402_16V4Z
1
C545
C549
2
LINE_L
LINE_R
1 2
C556 1U_0603_10V4Z
1 2
C557 1U_0603_10V4Z
1 2
C543 1U_0603_10V4Z@
1 2
C546 1U_0603_10V4Z@
1 2
C544 1U_0603_10V4Z@
1 2
C547 1U_0603_10V4Z
1 2
C554 1U_0603_10V4Z
ICH_RST_AUDIO#<23>
ICH_SYNC_AUDIO<23>
ICH_SDOUT_AUDIO<23>
NBA_PLUG<45>
EAPD<33>
L75
1 2
FBM-L11-160808-800LMT_0603
GND GNDA
38
FRONT_OUT_L
FRONT_OUT_R
SIDESURR_OUT_L
SIDESURR_OUT_R
MIC1_VREFO_L
MIC1_VREFO_R
20mil
DVDD11DVDD2
SURR_OUT_L
SURR_OUT_R
CEN_OUT
LFE_OUT
BIT_CLK
SDATA_IN
PIN37_VREFO
LINE1_VREFO
LINE2_VREFO
MIC2_VREFO
VREF
JDREF
VAUX
AVSS1
AVSS2
0.1U_0402_16V4Z
1
C537
2
9
AMP_LEFT
35
AMP_RIGHT
36
39
41
45
46
43
44
6
R443 33_0402_5%
8
37
29
31
10mil
28
32
30
27
40
33
26
42
AGND
1
C539
2
0.1U_0402_16V4Z
C538 22P_0402_50V8J
1 2
1 2
MIC1_VREFO_L
MIC1_VREFO_R
AC97_VREF
12
R445
20K_0402_1%
@
Modify 11/07 for EMI
L74
1 2
FBM-L11-160808-800LMT_0603
1
C532
10U_0805_10V4Z
2
10mil
1
C561
10U_0805_10V4Z
2
+3VS
AMP_LEFT <45>
AMP_RIGHT <45>
ICH_BITCLK_AUDIO <23>
ICH_AC_SDIN0 <23>
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2005/06/20 2006/06/20
E
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
F
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
G
B
of
44 55, 09, 2006
H
Page 45
A
B
C
D
E
http://hobi-elektronika.net
JP12
1
2
3
4
ACES_85204-0400
+5VAMP
S
D
1 3
SPK_L+
SPK_LSPK_R+
SPK_R-
G
SPDIF_PLUG#
2
Q22
SI2301BDS_SOT23
20mil
SPKL+
NBA_PLUG
2
C562
330P_0402_50V7K
1
SPDIF_PLUG#
SPDIF
SPKLSPKR+
SPKR-
+5VAMP
12
R458
1 1
12
R455
@
5.1K_0402_1%
13
SPDIF_PLUG#
2N7002_SOT23 @
2 2
D
2
Q20
G
S
AMP_LEFT<44>
AMP_RIGHT<44>
10K_0402_5%
VOL_AMP
(0.65V -> 10dB )
12
R457
1.5K_0402_1%
C882 0.1U_0402_16V4Z
R690 0_0402_5%
1 2
C566 1U_0402_6.3V4Z
1 2
C568 1U_0402_6.3V4Z
0.1U_0402_16V4Z
12
VOL_AMP
VOLMAX
12
NBA_PLUG
AMP_LEFT_C
AMP_RIGHT_C
BYPASS
1
2
+5VAMP
C881
20mil
C886
4.7U_0805_10V4Z
W=40mil
1
1
C892
4.7U_0805_10V4Z
2
2
U56
10
VDD
15
SHUTDOWN#
VDD
7
VOLUME
8
VOLMAX
13
SE/BTL#
6
LIN-
3
RIN-
4
BYPASS
APA2068KAI-TRL_SOP16
+5VAMP
1
MUTE
2
9
LOUT-
16
ROUT-
11
LOUT+
14
ROUT+
5
GND
12
GND
SPKL+
1 2
C891 150U_D_6.3VM
SPKR+
1 2
C888 150U_D_6.3VM
R651
1K_0402_1%@
12
R467
100K_0402_5%
100K_0402_5%
SPKLSPKRSPKL+
SPKR+
+
+
HPOUT_R_1
R468
1 2
EC_MUTE
HPOUT_L_1
12
EC_MUTE <33>
1 2
R702 47_0603_5%
1 2
R699 47_0603_5%
12
R652
1K_0402_1%@
HPOUT_L_2
HPOUT_R_2
NBA_PLUG<44>
2
C563
330P_0402_50V7K
1 2
L51 FBM-11-160808-700T_0603
1 2
L50 FBM-11-160808-700T_0603
+5VAMP
1
HPOUT_L_3
HPOUT_R_3
SPDIF<44>
+5VSPDIF
12
R456 100K_0402_5%
R462 0_0603_5%
1 2
R464 0_0603_5%
1 2
R466 0_0603_5%
1 2
R469 0_0603_5%
1 2
20mil
Speaker Conn.
+5VAMP
12
R698
100K_0402_5%
13
D
SPDIF_PLUG#
2
G
Q21
2N7002_SOT23
S
S/PDIF Out JACK
JP40
1
2
6
3
5
4
7
8
10
9
ACES_20234-0101
+5VSPDIF
LINE-IN JACK
JP41
5
3 3
LINE_R<44>
LINE_L<44>
Int MIC Conn.
JP13
15mil
1
2
ACES_85204-0200
4 4
A
INT_MIC_L
B
MIC1_R<44>
MIC1_L<44>
L48 FBM-11-160808-700T_0603
LINE_R
1 2
LINE_L LINE_L_R
1 2
L49 FBM-11-160808-700T_0603
220P_0402_50V7K
2.2K_0402_5%
1 2
L54
1 2
L35
220P_0402_50V7K
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1
C885
2
12
R775
FBM-11-160808-700T_0603
FBM-11-160808-700T_0603
1
C569
2
2005/06/20 2006/06/20
1
C884
220P_0402_50V7K
2
MIC1_VREFO_RMIC1_VREFO_L
R776
2.2K_0402_5%
C876
220P_0402_50V7K
LINE_R_R
12
MIC1_R_1
MIC1_L_1
1
2
Compal Secret Data
Deciphered Date
4
3
6
2
1
SUYIN_010164FR006G118ZL
MIC JACK
JP42
5
4
3
6
2
1
SUYIN_010164FR006G118ZL
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATI C, M/B LA-3151P
401412
星期四 三月
E
of
45 55, 09, 2006
B
Page 46
A
B
C
D
E
http://hobi-elektronika.net
+VDD_CORE
+5VS
R614
D
S
+3VS
D
S
1 2
13
1 2
13
Q27
470_0402_5%
SUSP
2
G
Q32
2N7002_SOT23
R609
470_0402_5%
SUSP
2
G
2N7002_SOT23
+1.8VALW
+1.8VALW
1
2
+1.8VALW TO +1.8V
U44
8
7
6
5
1
2
1
S
D
2
S
D
3
S
D
4
G
D
SI4800DY_SO8
C775
4.7U_0805_10V4Z
5VS_GATE3
+1.8VALW TO +1.8VS
D29
CH751H-40_SC76
2 1
+3VS
U45
8
D
7
D
6
D
5
D
SI4800DY_SO8
C782
4.7U_0805_10V4Z
S
S
S
G
1
2
3
4
D30
CH751H-40_SC76
2 1
5VS_GATE4
4.7U_0805_10V4Z
1
2
1
C772
4.7U_0805_10V4Z
2
2
C777
0.1U_0603_25V7K
1
D31
2 1
1
C780
2
R618
1 2
47K_0402_5%
C785
0.22U_0603_16V7K
1
C773
1U_0402_6.3V4Z
2
D
S
CH751H-40_SC76
1
C781
1U_0402_6.3V4Z
2
13
D
S
+1.8V
R612
100K_0402_5%
1 2
13
2
G
Q30
2N7002_SOT23
+1.8VS
R619
100K_0402_5%
1 2
2
G
Q34
2N7002_SOT23
+VSB
SYSON#
+VSB
SUSP
1 1
2 2
3 3
+5VALW
8
7
6
5
1
2
+3VALW
8
7
6
5
1
C783
10U_0805_10V4Z
2
+5VS
U43
1
S
D
2
S
D
3
S
D
4
G
D
SI4800DY_SO8
C774
4.7U_0805_10V4Z
+3VALW TO +3VS
U46
1
S
D
2
S
D
3
S
D
4
G
D
SI4800DY_SO8
1
2
+5VALW TO +5VS
1
C770
4.7U_0805_10V4Z
2
5VS_GATE0
2
C776
0.1U_0603_25V7K
1
+3VS
1
C778
10U_0805_10V4Z
2
5VS_GATE1
C784
0.22U_0603_16V7K
1
2
12
R617
1M_0402_1%@
C779
1U_0402_6.3V4Z
1
C771
1U_0603_10V4Z
2
R611
100K_0402_5%
1 2
13
D
2
G
Q29
S
2N7002_SOT23
D
S
SUSP
R615
100K_0402_5%
1 2
13
2
G
Q33
2N7002_SOT23
+VSB
+VSB
SUSP
R843
470_0402_5%
1 2
13
D
2
G
Q46
S
11/17 modify
+1.8V
R613
470_0402_5%
1 2
13
D
2
G
Q31
S
+0.9VS
R620
470_0402_5%
1 2
13
D
2
G
Q36
S
SUSP
2N7002_SOT23
SYSON#
2N7002_SOT23
SUSP
2N7002_SOT23
SUSP<52>
SUSP#<33,35,39,51,53>
+1.8VS
R610
470_0402_5%
1 2
13
D
G
Q28
S
DTC115EKA_SOT23
Q35
SUSP
2
2N7002_SOT23
SUSP
2
100K
100K
+5VALW
1 2
13
R616
10K_0402_5%
+1.2VS
8
7
6
5
SI4800DY_SO8
1
C788
4.7U_0805_10V4Z
2
4 4
+1.2VS TO +1.2V_HT
U47
1
S
D
2
S
D
3
S
D
4
G
D
4.7U_0805_10V4Z
2
1
A
1
C786
2
5VS_GATE2
C789
0.1U_0603_25V7K
1
C787
1U_0402_6.3V4Z
2
D
S
VLDT_EN<33,42>
+1.2V_HT
R624
100K_0402_5%
1 2
13
2
G
Q40
2N7002_SOT23
+VSB
VLDT_EN#
VLDT_EN
DTC115EKA_SOT23
Q37
+0.9V TO +0.9VS
+0.9V
U48
8
S
D
7
S
+5VALW
R621
10K_0402_5%
1 2
13
100K
2
100K
D
6
S
D
5
G
D
SI4800DY_SO8
1
C793
10U_0805_10V4Z
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C791
10U_0805_10V4Z
2
1
2
3
5VS_GATE5
4
1
C794
0.22U_0603_16V7K@
2
+0.9VS
1
C792
1U_0402_6.3V4Z
2
12
R628
1M_0402_1%@
2005/03/08 2006/03/08
C
R627
100K_0402_5%
1 2
13
D
S
SUSP
2
G
Q41
2N7002_SOT23
Compal Secret Data
Deciphered Date
+VSB
+1.2V_HT
1 2
13
D
S
D
R623
470_0402_5%
VLDT_EN#
2
G
Q39
2N7002_SOT23
+5VALW
R622
10K_0402_5%
1 2
SYSON
SYSON#
100K
2
E
100K
13
of
46 55,
SYSON#<52>
SYSON<33,39>
DTC115EKA_SOT23
Q38
Compal Electronics, inc.
Title
SCHEMATIC, M /B LA-3151P
Size Document Number Rev
Custom
401412
Date: Sheet
星期四
09, 2006
三月
B
Page 47
A
B
C
D
http://hobi-elektronika.net
PJP1
SINGA_2DC-G756-I06
1
2
G
G
1 1
3
ADPIN VIN
12
PC1
560P_0402_50V7K
PL1
FBMA-L18-453215-900LMA90T_1812
1 2
12
PC2
12P_0402_50V8J
PC3
VIN
12
PR1
10_1206_5%
12
12
PC4
12P_0402_50V8J
560P_0402_50V7K
RLZ24B_LL34
PD1
12
VIN
PD2
12
RLS4148_LLDS2
PR2
1K_1206_5%
1 2
PR3
1K_1206_5%
1 2
PR4
1K_1206_5%
1 2
PR7
1K_1206_5%
1 2
12
PR5
12
PR6
100K_0402_5%
PQ1
TP0610K-T1-E3_SOT23
2
100K_0402_5%
13
B+
12
PR8
100K_0402_5%
13
2
12
PR18
191K_0402_1%
PRG++
PQ5
MF2N7002W-G_SOT323-3
13
D
2
G
S
PQ3
DTC115EUA_SC70
B+
PR19
499K_0402_1%
PR21
47K_0402_5%
13
PQ6
DTC115EUA_SC70
2
12
PR13
499K_0402_1%
12
12
12
PC9
0.01U_0402_25V7K
PACIN <49,50>
+5VALW
PR9
13
PD3
RLS4148_LLDS2
1 2
12
12
PC6
0.1U_0603_25V7K
VS
MAINPWON<7,48,50>
ACIN
Precharge detector
Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
13
VS
1
O
34K_0402_1%
PQ2
2
PR12
2.2M_0402_5%
PU2A
LM393DR_SO8
8
P
+
-
G
4
PR20
12
3
2
12
12
PC11
1000P_0402_50V7K
32.3
12
PR22
@
66.5K_0402_1%
DTC115EUA_SC70
ACOFF<33,49>
VL
12
PR14
100K_0402_1%
PD5
2
1
ACON<49>
3
RB715F_SOT323
12
PC10
0.1U_0603_25V7K
RTCVREF
PD4
RB751V_SOD323
CHGRTCP
PR10
100K_0402_5%
PR11
22K_0402_5%
1 2
RTCVREF
12
PC8
12
12
G920AT24U_SOT89
3
4.7U_0805_6.3V6K
12
PC5
0.22U_1206_25V7K
PU1
OUT
TP0610K-T1-E3_SOT23
2
IN
GND
1
PQ4
33_1206_5%
2
12
PR15
200_0805_5%
12
PC7
1U_0805_25V4Z
2 2
3 3
+CHGRTC
BATT+
PR16
560_0603_5%
1 2
51ON#<42>
3.3V
PR17
1 2
560_0603_5%
BATT ONLY
Precharge detector
Min. typ. Max.
4 4
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRIE TARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFOR MATIO N. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY O R DISCL OSED T O ANY TH IRD PAR TY WIT HOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2005/0926 2006/0926
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四
09, 2006
三月
D
of
47 55,
B
Page 48
A
B+
PL2
1 2
1 1
FBM-L11-322513-151LMAT_1210
2 2
3 3
B+++
12
PC14
2200P_0402_50V7K
12
PC15
4.7U_1206_25V6K
+5VALWP
1
+
PC23
2
150U_D_6.3VM
PR34
@
5HG
PL3
10UH_SIL104R-100PF_4.4A_30%
1 2
1 2
10.2K_0402_1%
PR36
0_0402_5%
1 2
PQ7
8
G2
7
D1/S2/K
6
D1/S2/K
5
D1/S2/K
AO4916_SO8
VS
D2
D2
G1
S1/A
PZD1
RLZ5.1B_LL34
1 2
0.1U_0603_25V7K
1
2
3
4
PR37
47K_0402_5%
1 2
PC12
1 2
0_0603_5%
1 2
PR40
30.6
DL5
PR27
LX5
1 2
100K_0402_5%
DH5
12
Imax=3.5A
Ipeak=4.5A
+5V Iocp = 5.35A ~8.65 A
PC24
0.047U_0603_16V7K
B
http://hobi-elektronika.net
2
3
PD6
PR23
0_0603_5%
1 2
PR43
47K_0402_5%
1 2
BST5A
1 2
1 2
0_0402_5%
12
PC28
0.047U_0603_16V7K
PC21
PR35
0_0402_5%
2VREF_1999
PR38
12
CHP202UPT_SOT323-3
1
B+++
12
PR25
4.7_1206_5%
12
VL
PC19
12
4.7U_0805_10V4Z
14
BST5
16
DH5
15
LX5
19
DL5
21
OUT5
9
FB5
1
N.C.
MAX8734AEEI+_QSOP28
6
SHDN#
4
ON5
3
ON3
12
SKIP#
8
REF
PC26
0.22U_0603_16V7K
18
1U_1206_25V7K
LD05
@
23
PR26
GND
4.7_1206_5%
20
V+
PU3
PC27
12
PC22
12
25
12
VL
PR24
1 2
0.1U_0603_25V7K
13
17
ILIM3
TON
VCC
ILIM5
BST3
DH3
DL3
OUT3
FB3
PGOOD
PRO#
LDO3
10
4.7U_0805_10V4Z
1 2
47_0402_5%
12
PC20
5
11
28
26
24
27
LX3
22
7
2
PR41
0_0402_5%
1U_0805_16V7K
BST3BBST5B
12
PC16
0.1U_0603_25V7K
2VREF_1999
PR29
1 2
100K_0402_1%
PR32
1 2
499K_0402_1%
SPOK<50>
C
PR30
1 2
100K_0402_1%
PR33
1 2
499K_0402_1%
0.1U_0603_25V7K
1 2
PR28
0_0603_5%
1 2
BST3A
PC13
DH3
B+++
12
PC17
0_0603_5%
12
PC18
2200P_0402_50V7K
4.7U_1206_25V6K
PR31
1 2
D
DL3
PQ8
1
D2
2
D2
3
G1
4
S1/A
AO4916_SO8
3HG
LX3
D1/S2/K
D1/S2/K
D1/S2/K
8
G2
7
6
5
PL4
10UH_SIL104R-100PF_4.4A_30%
1 2
+3VALWP
PR42
0_0402_5%
1 2
1 2
PR39
@
3.57K_0402_1%
1
+
PC25
2
150U_D_6.3VM
+3.3V Iocp =5.36A ~ 9.03A
Imax=3.5A
Ipeak=4.5A
MAINPW O N <7,4 7,50>
12
PC29
1U_0603_16V6K
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRIE TARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFOR MATIO N. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY O R DISCL OSED T O ANY TH IRD PAR TY WIT HOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2005/09/26 2006/09/26
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
09, 2006
三月
401412
D
星期四
of
48 55,
B
Page 49
A
Iadp=0~4.5A(90W)
PQ9
AO4407L_SO8~N
PQ13
2
13
ACOFF#
8
7
5
47K
47K
1 3
PQ16
DTC115EUA_SC70
PD11
1N4148_SOD80
1 2
PR61
22K_0402_5%
1 2
VIN
1 1
12
PR47
47K_0402_5%
DTA144EUA_SC70
2
13
D
PQ18
2
2 2
3 3
G
S
MF2N7002W-G_SOT323-3
PACIN<47,50>
ACON<47>
P2
1
2
36
4
12
12
PC36
0.1U_0603_25V7K
12
PR51
150K_0402_5%
13
D
2
G
S
CP Point:
Iinput=(90.0K/100.9K)*(75/15)=4.504A
LI-4S :17.8V--BATT-OVP=1.9758V
BATT-OVP=0.111*BATT+
IREF=0.832*Icharge
IREF=0.73~3.3V
PQ10
AO4407L_SO8~N
1
2
3 6
4
PR46
200K_0402_1%
PC38
1U_0603_10V6K
10K_0402_0.1%
PR50
12
12
PR55
PQ19
MF2N7002W-G_SOT323-3
0.1U_0402_16V7K
90.9K_0402_0.1%
12
PC40
2P4S:4800mAH/cell
0.8C=3.84A
4 4
OVP voltage :
8
7
5
1908LDO
12
IREF<33>
B
0.1U_0603_25V7K
1SS355_SOD323
VIN
0.1U_0603_25V7K
PR53
9.31K_0402_1%
24.9K_0402_1%
100K_0402_1%
FSTCHG<33>
12
P3
PR58
PC34
PC37
PR59
PD9
12
12
12
15K_0402_1%
12
12
C
http://hobi-elektronika.net
12
0.1U_0603_25V7K
CSSN
G
2
S
PR49
@
0_0402_5%
PR64
1 2
10K_0402_5%
7
PC35
13
D
PC50
VS
0
B+
FBMA-L18-453215-900LMA90T_1812
PU4
1
DCIN
17
12
CELLS
4
REF
3
CLS
12
REFIN
15
VCTL
13
ICTL
11
ACOK#
8
SHDN#
10
ACIN
9
ICHG
28
IINP
7
CCV
PR60
10K_0402_1%
1 2
12
PC48
0.1U_0402_16V7K
0.01U_0402_25V7K
12
PC51
0.1U_0402_16V7K
8
PU5B
5
P
+
6
-
G
LM358ADR_SO8
4
PL5
1 2
CCI
CCS
6
5
MAX1908-CCS
12
1 2
12
PC30
PC31
4.7U_1206_25V6K
CSSP
TP
CSSN
DHI
LX
DLO
BST
DLOV
LDO
CSIP
CSIN
BATT
PGND
GND
14
PC49
0.01U_0402_25V7K
20
MAX1908ETI+T_QFN28
BATT_OVP<33>
PR44
0.015_2512_1%
1
2
CSSP
6C/8C#<50>
SI2301DS_SOT23~D
12
PR54
12
PC45
PR62
0_0402_5%
1 2
PR63
100K_0402_5%
4
3
PQ15
0.01U_0402_25V7K
1 2
12
4.7U_1206_25V6K
27
29
26
25
23
21
24
22
2
19
18
16
PC32
0.1U_0603_25V7K
charger_DHI
charger_LX
charger_DLO
charger_BST
charger_DLOV
1908LDO
1 2
CSIP
CSIN
BATT+
12
PC33
2200P_0402_25V7K
PC46
1U_0603_10V6K
1
0
12
5
4
5
4
PR56
0_0402_5%
1 2
PR57
33_1206_5%
8
PU5A
P
+
-
G
LM358ADR_SO8
4
D
CHG_B+
D8D7D6D
S1S2S3G
D8D7D6D
S1S2S3G
12
VS
12
3
2
PC52
PQ12
SI4810BDY-T1-E3_SO8
12
PC39
@
1000P_0402_50V7K
PQ17
SI4810BDY-T1-E3_SO8
10UH_SIL104R-100PF_4.4A_30%
1 2
12
PC47
1U_0805_25V4Z
1 2
BATT+
12
PR65
845K_0603_1%
12
PR66
300K_0603_0.1%
0.01U_0402_25V7Z
12
PR69
200K_0402_1%
1
2
3 6
1 2
PC41
0.1U_0603_25V7K
PD10
1SS355_SOD323
PQ11
AO4407L_SO8~N
4
PR48
10K_0402_1%
1 2
13
PL6
PR68
511K_0402_1%
1 2
12
PC53
0.01U_0402_25V7Z
E
8
7
5
PR45
47K_0402_1%
1 2
ACOFF#
PQ14
DTC115EUA_SC70
ACOFF
2
PR52
0.015_2512_1%
1
2
VIN
ACOFF <33,47>
4
3
12
PC43
PC42
4.7U_1206_25V6K
Charge voltage
4S CC-CV MODE : 16.8V
+3VALW
12
13
D
PQ20
MF2N7002W-G_SOT323-3
2
G
S
13
D
S
Charger
12
12
PC44
4.7U_1206_25V6K
4.7U_1206_25V6K
PR67
10K_0402_5%
2
6C/8C# <50>
G
PQ21
MF2N7002W-G_SOT323-3
BATT+
LI-3S :17.8V----BATT-OVP=1.9758V
BATT-OVP=0.111*BATT+
A
B
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/09/26 2006/09/26
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四 三月
of
49 55, 09, 2006
E
B
Page 50
A
SM AR T
Ba t te r y:
1 . G N D
2. SMC
3.S M D
4 .TS
5. B / I
6 . I D
7. B A TT+
B
C
D
PR70
100K_0402_5%
BATT++BATT+
PL7
FBMA-L18-453215-900LMA90T_1812
1 1
BATT+
12
1 2
PC54
0.01U_0402_25V7Z
PC55
1000P_0402_50V7K
PJP2 battery connector
2 2
SUYIN_200275MR007G161ZL
12
PJP2
7
6
5
4
3
2
1
BATT++
1 2
PR71
1K_0402_5%
PR78
1K_0402_5%
1 2
12
12
PR72
@
1K_0402_5%
1 2
100_0402_5%
1 2
+3VALWP
6C/8C# <49>
PR75
1K_0402_5%
1 2
6.49K_0402_1%
1 2
PR81
100_0402_5%
PR83
http://hobi-elektronika.net
BATT_TEMP
PR79
BATT_TEMP <33>
+3VALWP
EC_SMB_DA1 <33,35>
EC_SMB_CK1 <33,35>
1000P_0402_50V7K
PC57
PH1 under CPU botten side :
CPU thermal protection at 90 degree C
Recovery at 70 degree C
PR74
9.76K_0402_1%
12
VL
12
PR77
82.5K_0603_1%
1 2
12
PH1
PC58
1U_0805_16V7K
100K_0603_1%_TH11-4H104FT
12
PC56
0.1U_0603_25V7K
TM_REF1
12
12
5
+
6
-
PR80
150K_0402_1%
PR82
150K_0402_1%
VS
PR76
442K_0603_1%
1 2
8
PU2B
P
7
O
G
LM393DR_SO8
4
12
VL
VL
PR73
150K_0402_1%
1 2
MAINPW ON <7,47,48>
Vin Detector
Min. typ. Max.
H-->L 16.976V 17.257V 17.728V
PQ22
TP0610K-T1-E3_SOT23
B+
12
PR85
100K_0402_5%
PR88
13
D
2
G
S
22K_0402_5%
1 2
PQ23
MF2N7002W-G_SOT323-3
VL
3 3
SPOK<48>
PR90
100K_0402_5%
PR93
1 2
0_0402_5%
1 2
PC63
@
0.1U_0402_16V7K
12
12
PC59
0.22U_1206_25V7K
13
12
2
+VSBP
PC60
0.1U_0603_25V7K
L-->H 17.430V 17.901V 18.384V
VIN
12
PR86
84.5K_0402_1%
PR91
22K_0402_5%
1 2
PC61
1000P_0402_50V7K
12
12
PR92
20K_0402_1%
12
PC62
0.1U_0603_25V7K
1M_0402_1%
3
2
PR95
10K_0402_5%
PR84
1 2
VS
8
PU6A
P
+
O
-
G
LM393DR_SO8
4
12
1
RTCVREF
PZD2
RLZ4.3B_LL34
VIN
12
PR87
10K_0402_5%
12
PR89
10K_0402_5%
1 2
12
PR94
10K_0402_5%
ACIN
PACIN
ACIN <33>
PACIN <47,49>
8
PU6B
5
P
+
7
O
6
-
G
LM393DR_SO8
4
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEE RING DR AWING IS THE P ROPRIE TARY P ROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFOR MATIO N. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY O R DISCL OSED T O ANY TH IRD PAR TY WIT HOUT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2005/09/26 2006/09/26
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
401412
星期四
09, 2006
三月
D
of
50 55,
B
Page 51
5
4
3
2
1
http://hobi-elektronika.net
D D
PL8
FBM-L11-322513-151LMAT_1210
1 2
B+
12
PC64
10U_1206_25VAK
C C
6269_VCC
12
PR101
100K_0402_5%
SUSP#<33,35,39,46,53>
1 2
12
PC69
0.22U_0603_16V7K
PC67
2.2U_0603_6.3V6K
6269_VCC PHASE_6269
PR96
1K_0402_1%
17
GND
1
VIN
2
PR100
0_0402_5%
1 2
VCC
3
FCCM
4
EN
ISL6269CRZ-T_QFN16
COMP5FB6FSET
1 2
16
PGOOD
PU7
PR97
1 2
0_0603_5%
BOOT_6269
PHASE
13
14
UG
BOOT
12
PVCC
PGND
VO
8
7
LG
ISEN
2.2U_0603_6.3V6K
11
10
9
15
1 2
PC65 0.1U_0603_25V7K
12
PR98
@
4.7_0603_5%
PR99
4.7_0603_5%
1 2
PC66
1 2
LG_6269
ISEN_6269
1 2
PR102
15.4K_0402_1%
UG_6269
+5VS
6269_VCC
5
D8D7D6D
S1S2S3G
SI4800BDY-T1-E3_SO8
4
5
D8D7D6D
S1S2S3G
4
PQ24
1.8UH_SIL104R-1R8PF_9.5A_30%
1 2
PL9
PQ25
SI4810BDY-T1-E3_SO8
1
+
PC68
330U_D2E_2.5VM
2
+1.2VSP
PR106
PR104
57.6K_0402_1%
12
12
12
PC70
0.01U_0402_25V7K
PR105
3K_0402_1%
1 2
12
12
B B
PC71
22P_0402_50V8J
PR103
49.9K_0402_1%
12
PC72
6800P_0402_25V7K
3K_0402_1%
Ipeak=VGA_1.2V+(+1.2V_HT)=2.1A+6.067A=8.167A
Imax=5.7A
Iocmin=9.23A
Iocmax=19.23A
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/26 2006/09/26
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
星期四
401412
09, 2006
三月
B
of
51 55,
1
Page 52
5
4
3
2
1
+3VALW
http://hobi-elektronika.net
1
PJP3
1
+1.8VALW
1
PJP4
PC74
PJP13
JUMP_43X113
1
2
2
12
2
G
PJP5
2
JUMP_43X113
PJP8
2
JUMP_43X113
PJP10
2
JUMP_43X113
PJP12
2
JUMP_43X113
112
JUMP_43X79
PR107
1K_0402_1%
13
D
PQ26
S
@
112
112
112
112
+1.8V
PR111
MF2N7002W-G_SOT323-3
+VDD_CORE+VGA_CORE_P
12
12
1K_0402_1%
+5VALW
+1.2VS
+0.9V
PU8
VIN1VCNTL
2
GND
3
VREF
4
VOUT
APL5331KAC-TRL_SO8
12
PC79
22U_1206_10V6M
+0.9VSP
12
PC78
0.1U_0402_16V7K
+1.8VALWP
+2.5VSP
+1.5VSP
+VSBP +VSB
6
5
NC
7
NC
8
NC
9
TP
+3VALW
12
PC75
1U_0603_6.3V6M
PJP6
2
JUMP_43X113
PJP9
2
JUMP_43X113
PJP11
2
JUMP_43X113
PJP14
2
JUMP_43X113
PJP15
2
JUMP_43X113
+2.5VSP
PC77
4.7U_1206_25V6K
112
112
112
112
112
+1.8VALW
+2.5VS
+1.5VS
+VDD_CORE+VGA_CORE_P
D D
10U_1206_25VAK
PR110
@
0_0402_5%
SYSON#<46>
C C
1 2
+3VALWP +3VALW
+5VALWP
+1.2VSP
B B
+0.9VSP
2
JUMP_43X79
2
2
12
PR108
1 2
1 2
+1.5VSP
PC84
4.7U_1206_25V6K
1 2
PC73
4.7U_1206_25V6K
10_0603_1%
PC81
0.1U_0603_25V7K
+1.8VALW
1 2
CM8562IS_PSOP8
1
VIN
2
VFB
3
VTT
VTT4REFEN
1
PJP7
1
JUMP_43X79
2
2
PC82
12
10_0603_1%
PR114
1 2
PC86
PU9
AGND
9
1 2
4.7U_1206_25V6K
0.1U_0603_25V7K
8
PGND
7
AGND
6
VCCA
5
CM8562IS_PSOP8
1
VIN
2
VFB
3
VTT
VTT4REFEN
PU10
9
+5VALW
12
PGND
AGND
VCCA
AGND
PR112
200K_0402_1%
PC80
0.047U_0402_16V7K
13
D
S
8
7
6
5
12
RTCVREF
1 2
PC76
1U_0603_16V6K
12
PR109
60.4K_0402_1%
PQ27
MF2N7002W-G_SOT323-3
2
G
12
+5VALW
PC85
PR116
51K_0402_1%
0.047U_0402_16V7K
D
S
PR113
100K_0402_5%
1 2
PC135
0.047U_0603_16V7K
RTCVREF
1 2
PC83
1U_0603_16V6K
12
PR115
60.4K_0402_1%
PQ28
13
MF2N7002W-G_SOT323-3
2
G
12
1 2
PR117
100K_0402_5%
PC136
0.047U_0603_16V7K
SUSP <46>
SUSP <46>
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/09/26 2006/09/26
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
SCHEMATIC, M /B LA-3151P
Size Document Number Rev
Custom
401412
星
|, 09, 2006
薔三月
2
Date: Sheet
1
52 55
B
of
Page 53
5
4
3
2
1
http://hobi-elektronika.net
PL10
D D
5
4
PQ31
SUSP#<33,35,39,46,51>
4.7U_0805_6.3V6K
3 5
241
5
D8D7D6D
S1S2S3G
4
FDS6676AS_SO8
PR129 10K_0402_1%@
PR123=1K
PR135=8.87K
PR132=8.87K
L=1.102V
H=1.001V
PQ29
SI7840DP-T1-E3_SO8
+VGA_CORE_P
C C
330U_D2E_2.5VM
B B
POWER_SEL <16>
PC100
10K_0402_5%
PR141
10K_0402_5%
1
2
12
12
+
PR131
2
G
PC107
@
+5VALW
0.01U_0402_25V7Z
1 2
PR182
10K_0402_5%
1 2
13
D
S
PC134
PQ34
MF2N7002W-G_SOT323-3
0.01U_0402_25V7Z
1.4U_SSF-13056-1R4_15.5A_20%
12
12
PR123
1K_0402_1%
12
12
PR132
5.9K_0402_1%
13
D
2
G
S
12
PQ33
MF2N7002W-G_SOT323-3
Ipeak=16.40A
Imax=12.25A
Iocpmin=22.07A
Iocpmax=38.67A
A A
PL11
1 2
3
12
D8D7D6D
S1S2S3G
PR122
4.7_1206_5%
@
12
PR124
0_0402_5%@
PC101
0.01U_0402_25V7Z
12
PC102
@
680P_0603_50V7K
+3VS +3VALW
12
PR136
PR135
0_0402_5%
18.2K_0402_1%
For VGA chipset type, that should be dynamic change by everytime load BOM.
M52PG
PR123=1K
PR135=18.2K
PR132=17.8K
L=1.000V
H=0.949V
PC87
10U_1206_25VAK
PC93
DAP202U_SOT323
0.1U_0402_16V7K
LX_VGA
PQ44
FDS6676AS_SO8
1 2
PR137
100K_0402_5%
1 2
M54P
12
PC88
12
PC98
12
10U_1206_25VAK
PD12
BST_VGA
12
1 2
PR125
1.5K_0402_1%
1 2
VSE_VGA
PC106
0.1U_0402_16V7K
12
PC89
10U_1206_25VAK
1
0.1U_0603_25V7K
2
3
PC96
12
0.01U_0402_25V7Z
PR120
0_0603_5%
DH_VGA
ISE_VGA
DL_VGA
12
12
M56P
PR123=1K
PR135=18.2K
PR132=5.9K
L=1.102V
H=0.949V
12
51_1206_5%
PC90
2200P_0402_25V7K
PC94
12
6
5
4
7
2
3
9
10
8
15
11
PR139
110K_0402_1%
PR118
12
SOFT1
BOOT1
UGATE1
PHASE1
ISL6227CA-T_SSOP28
ISEN1
LGATE1
PGND1
VOUT1
VSEN1
EN1
PG1
OCSET1
12
14
1
VIN
GND
PU11
+5VALW
1 2
28
VCC
DDR
13
PR119
2.2_0603_5%
SOFT2
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PGND2
VOUT2
VSEN2
EN2
PG2/REF
OCSET2
12
PC95
2.2U_0805_10V6K
BST_1.8V
PC97
4700P_0402_25V7K
17
12
0_0603_5%
BST_1.8V-1BST_VGA-1
23
1 2
DH_1.8V
24
LX_1.8V
25
ISE_1.8V
22
DL_1.8V
27
26
20
VSE_1.8V
19
21
16
18
12
56.2K_0402_1%
PR121
PR126
1.5K_0402_1%
1 2
PR138
PC99
0.1U_0402_16V7K
12
12
PC105
0.1U_0402_16V7K
PR130
@
1 2
10K_0402_1%
PR140
10K_0402_5%
1 2
ISL6227B+
5
PQ30
D8D7D6D
SI4800BDY-T1-E3_SO8
S1S2S3G
4
PL12
1.8U_SIL104R-1R8_9.5A_30%
1 2
5
PQ32
SI4810BDY-T1-E3_SO8
D8D7D6D
S1S2S3G
4
+5VALW
PC91
12
PR127
0_0402_5%
12
10U_1206_25VAK
0_0402_5%
FBM-L11-322513-151LMAT_1210
1 2
12
12
PC92
2200P_0402_25V7K
12
PC104
0.01U_0402_25V7Z
PR134
@
Ipeak=8.5A
Imax=6A
Iocpmin=8.76A
Iocpmax=13.46A
+1.8VALWP
12
PR128
10K_0402_1%
12
PR133
10K_0402_1%
1
+
PC103
220U_D2_4VM_R15
2
B+
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/26 2006/09/26
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P
, 09, 2006
三月
401412
1
53 55
星期四
B
of
Page 54
5
4
3
2
1
http://hobi-elektronika.net
+5VS
+3VS
12
D D
PR143
10K_0402_5%
@
VID0<7>
VID1<7>
VID2<7>
VID3<7>
VID4<7>
VID5<7>
VGATE<33>
+3VS
C C
VR_ON<33>
B B
PSI#<7>
A A
0_0402_5%
1 2
POUT<33>
0.1U_0402_16V7K
MAX8774_REF
31.6K_0402_1%
PR158
1 2
PC123
1 2
PR168
169K_0603_1%
2
AGND
PR169
2
G
200K_0402_1%
PR180
0_0603_5%
1 2
PR155 100K_0402_1%
PR159
@
1 2
100K_0402_5%
PR165 10K_0402_1%
1 2
CPU_B+
1 2
200K_0402_1%
12
PQ38
13
D
S
MF2N7002W-G_SOT323-3
12
PR174
13
PQ41
FDV301N_NL 1N SOT23-3
12
PR144 0_0402_5%
12
PR145 0_0402_5%
PR152 0_0402_5%
PR153 0_0402_5%
1 2
PR167
200K_0402_1%
12
PR147 0_0402_5%
12
PR149 0_0402_5%
12
PR150 0_0402_5%
12
1 2
+3VS
12
PR172
13
D
2
G
S
PR160 71.5K_0402_1%
1 2
PC124 0.1U_0603_16V7K
PQ40
MF2N7002W-G_SOT323-3
PR142 10_0402_5%
12
PC114
2.2U_0603_10V6K
1 2
MAX8774_VCC
J1 SHORT PADS
1 2
For EC ATE
MAX8774_VCC
12
150P_0402_50V8J
MAX8774_REF
PR170
0_0402_5%
PC121
12
PU12
19
31
32
33
34
35
36
1
17
37
38
6
8
12
3
10
7
2
4
39
4700P_0603_50V7K
VCC
D0
D1
D2
D3
D4
D5
PWRGD
PHASEGD
TWO-PH
SHDN#
TIME
CCV
POUT
REF
TON
OFS
VRHOT#
SKIP#
EP
41
PC129
PR178
10_0402_5%
PC113
1 2
2.2U_0603_6.3V6K
25
VDD
5
THRM
30
BST1
29
DH1
28
LX1
26
DL1
27
PGND1
16
CSP1
15
CSN1
18
GND
40
IC
FB
11
FB
9
CCI
20
BST2
21
DH2
22
LX2
24
DL2
23
PGND2
13
CSP2
14
CSN2
GNDS
12
MAX8774GTL+_TQFN40
12
12
12
CPU_VSS_SENSE<7>
PC115
PR146
0_0603_5%
1 2
DH1
LX1
DL1
AGND
PR161
2.55K_0603_1%
1 2
1 2
PC122 470P_0402_50V8J
DH2
LX2
DL2
CSP2
PR173
10_0402_1%
4700P_0402_25V7K
1 2
PR163 20K_0402_1%
12
PC116
0.01U_0402_25V7K
PC119
1 2
12
0.22U_0603_16V7K
1 2
PR171
0_0603_5%
1 2
12
PC130
0.22U_0603_16V7K
PR148
0_0603_5%
1 2
PR162
10_0402_1%
1 2
4700P_0402_25V7K
12
PC117
@
4700P_0402_25V7K
PR175
0_0603_5%
PC132
@
1 2
3 5
241
5
D8D7D6D
PQ36
S1S2S3G
4
PR164 0_0402_5%
1 2
3 5
241
5
PQ42
4
FDS6676AS_SO8
PR181
1 2
0_0402_5%
CPU_B+
PQ35
SI7840DP-T1-E3_SO8
5
D8D7D6D
PQ37
S1S2S3G
4
FDS6676AS_SO8
PQ39
SI7840DP-T1-E3_SO8
5
PQ43
4
FDS6676AS_SO8
D8D7D6D
S1S2S3G
D8D7D6D
S1S2S3G
PR151
@
1 2
4.7_1206_5%
12
FDS6676AS_SO8
PC118
@
680P_0603_50V8J
CPU_B+
12
PC125
PR176
4.7_1206_5%
@
PC131
@
680P_0603_50V8J
FBMA-L18-453215-900LMA90T_1812
12
12
4.7U_1206_25V6K
1 2
12
PR154
15K_0402_1%
15K_0402_1%
1 2
12
PC127
4.7U_1206_25V6K
2 1
12
PC110
PC111
0.01U_0402_25V7K
PL14
PR156
1 2
PC120
0.033U_0603_25V7K
12
PC128
0.01U_0402_25V7K
PD14
1 2
15K_0402_1%
1 2
SKS30-04AT_TSMA
CSP2
12
PC109
PC108
4.7U_1206_25V6K
0.56UH_ETQP4LR56WFC_21A_20%
PD13
2 1
SKS30-04AT_TSMA
12
PC126
4.7U_1206_25V6K
2200P_0402_50V7K
1 2
12
PL13
1 2
2200P_0402_50V7K
PH2
10KB_0603_ERTJ1VR103J
1 2
PL15
0.56UH_ETQP4LR56WFC_21A_20%
1 2
PR177
15K_0402_1%
PR179
0.033U_0603_25V7K
1 2
PC133
1 2
PH3
10KB_0603_ERTJ1VR103J
1
2
+
PC112
100U_25V_M
12
PR157
10_0402_5%
0_0402_5%
1 2
CPU_VCC_SENSE<7>
B+
+CPU_CORE
PR166
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/09/26 2006/09/26
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P
星期四
401412
09, 2006
三月
54 55,
1
B
of
Page 55
5
4
3
2
1
http://hobi-elektronika.net
Version change list (P.I.R. List) Page 1 of 1
for PWR
Reason for change Rev. PG# Modify List VER PhaseFixed IssueItem
1
D D
2
3
4
5
6
C C
7
8
9
10
11
B B
8
9
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P
星
|, 09, 2006
薔三月
401412
1
of
55 55
B
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