Acer Aspire 4410 Schematic

Dr-Bios.com

JM41 Block

D D

Diagram

CLK GEN.

ICS9LPRS365B

DDR3

800/1066 MHz

C C

DDR3

800/1066 MHz

Int MIC

Line Out

MIC In

B B

A A

INT.SPKR

1.5W

Codec

Realtek ALC269Q

17,18

AZALIA

HDD SATA

ODD SATA

SSD SATA

Intel CPU

Penryn SFF

HOST BUS 667/800/1066MHz@1.05V

Cantiga-GS SFF

AGTL+ CPU I/F

DDR Memory I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

X4 DMI 400MHz

ICH9M SFF

6 PCIe ports

PCI/PCI BRIDGE

ACPI 2.0

4 SATA

12 USB 2.0/1.1 ports

ETHERNET (10/100/1000MbE)

High Definition Audio

LPC I/F

Serial Peripheral I/F

Matrix Storage Technology(DO)

Active Managemnet Technology(DO)

SATA

Mini USB Blue Tooth

Cardreader

RTS5159

4,5,6

7,8,9,10,11,12

C-Link0

13,14,15,16

USB

Thermal Sensor

SMSC

EMC2103

LVDS

RGB CRT

PCIex16

PCIe

USB

LPC BUS

Camera

USB 4 Port

LCD

CRT

HDMI

LAN

Giga LAN

Atheros AR8131

Mini 1 Card WLAN

Mini 2 Card 3G

BIOS

SPI

KBC

Winbond

WPCE773LA0DG

Touch Pad

INT. KB

35 33

(2MB)

TXFM RJ45

3128

MEDIA KEY

MS/MS Pro/xD /MMC/SD

Project code: 91.4CQ01.001 PCB P/N : 48.4CQ01.011 REVISION : 08266-1

PCB STACKUP

TOP

VCC/GND

GND/VCC

BOTTOM

27 27

LPC

DEBUG CONN.

Title

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet

Date: Sheet of

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT

RT8202

INPUTS OUTPUTS

DCBATOUT 1D05V_S0(10A)

RT8202

INPUTS OUTPUTS

DCBATOUT

1D5V_S3(11A)

RT9026

INPUTS OUTPUTS

5V_S5

CHARGER

MAX8731A

DCBATOUT

CPU DC/DC

ADP3207A

INPUTS

DCBATOUT

INPUTS

DCBATOUT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

JM41_UMA

OUTPUTS

VCC_CORE

0~1.3V 64A

VGA

ISL6263A

OUTPUTS

VCC_GFXCORE

1 40Monday, March 09, 2009

OUTPUTS

5V_S5(6A)

3D3V_S5(5A)

5V_AUX_S5

3D3V_AUX_S5

DDR_VREF_S3 (1.2A)

OUTPUTSINPUTS

CHG_PWR

18V 6.0A

(7A)

-1

Dr-Bios.com

ICH9M Functional Strap Definitions

Signal

HDA_SDOUT

HDA_SYNC

4 4

GNT2#/ GPIO53

GPIO20

GNT1#/ GPIO51

GNT3#/ GPIO55

GNT0#: SPI_CS1#/ GPIO58

SPI_MOSI

3 3

GPIO49

SATALED#

SPKR

TP3

GPIO33/ HDA_DOCK _EN#

Usage/When Sampled

XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK

PCIE config1 bit0, Rising Edge of PWROK.

PCIE config2 bit2, Rising Edge of PWROK.

Reserved

ESI Strap (Server Only) Rising Edge of PWROK

Top-Block Swap Override. Rising Edge of PWROK.

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.

Integrated TPM Enable, Rising Edge of CLPWROK

DMI Termination Voltage, Rising Edge of PWROK.

PCI Express Lane Reversal. Rising Edge of PWROK.

No Reboot. Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

Flash Descriptor Security Override Strap Rising Edge of PWROK

Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down

This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)

This signal should not be pulled high.

ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

The signal is required to be low for desktop applications and required to be high for mobile applications.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)

If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

This signal should not be pull low unless using XOR Chain testing.

Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.

ICH9 EDS 642879 Rev.1.5

Comment

2 2

ICH9M Integrated Pull-up

page 92

and Pull-down Resistors

SIGNAL Resistor Type/Value

CL_CLK[1:0]

CL_DATA[1:0]

CL_RST0#

DPRSLPVR/GPIO16

ENERGY_DETECT

HDA_BIT_CLK

HDA_DOCK_EN#/GPIO33

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT

HDA_SYNC

GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO[20]

GPIO[49]

LDA[3:0]#/FHW[3:0]#

LAN_RXD[2:0]

LDRQ[0]

LDRQ[1]/GPIO23

PME#

PWRBTN#

SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI

SPI_MISO

SPKR

TACH_[3:0]

TP[3]

USB[11:0][P,N]

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

ICH9 EDS 642879 Rev.1.5

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-UP 15K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 15K

SDVO_CTRLDATA

Montevina Platform Design guide 22339 0.5

Pin Name

CFG[2:0]

CFG[4:3] CFG8 CFG[15:14] CFG[18:17]

CFG5

CFG6

CFG7

CFG9

CFG10 PCIE Loopback enable

CFG[13:12]

CFG16

CFG19

CFG20

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.

2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

Strap Description

FSB Frequency Select

Reserved

DMI x2 Select

iTPM Host Interface

Intel Management engine Crypto strap

PCIE Graphics Lane

XOR/ALL

FSB Dynamic ODT

DMI Lane Reversal

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

SDVO Present

Local Flat Panel (LFP) Present

Configuration

000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved

0 = DMI x2

1 = DMI x4

0= The iTPM Host Interface is enabled(Note2)

1=The iTPM Host Interface is disalbed(default)

0 = Transport Layer Security (TLS) cipher suite with no confidentiality

1 = TLS cipher suite with confidentiality (default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane Numbered in order

0 = Enable (Note 3)

1= Disabled (default)

00 = Reserve 10 = XOR mode Enabled 01 = ALLZ mode Enabled (Note 3)

11 = Disabled (default)

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = Normal operation(Default): Lane Numbered in Order

1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1)

0 = Only Digital Display Port or PCIE is operational (Default)

1 =Digital display Port and PCIe are operting simulataneously via the PEG port

0 =No SDVO Card Present (Default)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1= LFP Card Present; PCIE disabledL_DDC_DATA

page 218

(Default)

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

Date: Sheet

Date: Sheet of

Reference

JM41_UMA

2 40Sunday, March 01, 2009

-1

3D3V_S0

Dr-Bios.com

R195

1 2

0R0603-PAD

3D3V_48MPWR_S0

C407

C405

SC4D7U6D3V3KX-GP

1D05V_S0

R61

1 2

0R0603-PAD

SCD1U16V2KX-3GP

C420

SC1U10V3KX-3GP

0R0603-PAD

C404

1D05V_CLK_S0

SCD1U16V2KX-3GP

C401

SCD1U16V2KX-3GP

C394

C397

C400

SCD1U16V2KX-3GP

C412

SCD1U16V2KX-3GP

3D3V_CLK_S0

SCD1U16V2KX-3GP

C226

SCD1U16V2KX-3GP

C411

C417

C393

SC4D7U10V5ZY-3GP

C417

C406

SCD1U16V2KX-3GP

C418

SCD1U16V2KX-3GP

R197

1 2

0R0603-PAD

3D3V_S0

4 4

CL=20pF±0.2pF

C416 SC10P50V2JN-4GPC416 SC10P50V2JN-4GP

1 2

PCLKCLK4

R207

10KR2J-3-GP

3 3

PCLK_KBC28 PCLK_ICH14

CLK_ICH14

PCLK_ICH

PCLK_KBC

CLK48_ICH

2 2

C419 SC10P50V2JN-4GPC419 SC10P50V2JN-4GP

1 2

3D3V_S0

RN30

RN30 SRN10KJ-5-GP

SRN10KJ-5-GP

RN29

1 2 3

SRN33J-5-GP-U

EC48 SC22P50V2JN-4GP

EC49 SC22P50V2JN-4GP

EC52 SC22P50V2JN-4GP

EC47 SC22P50V2JN-4GP

EMI capacitor for Antenna team suggestion

1 2

23 1

GEN_XTAL_IN

X2 X-14D31818M-50GP

X-14D31818M-50GP

82.30005.A51

PCLKCLK2 PCLKCLK5

SB_20090205

PCLKCLK4 PCLKCLK5

CLK48_ICH14

CPU_SEL04,8

3D3V_S0

PCLK_FWH29

CPU_SEL14,8 CPU_SEL24,8

CLK_ICH1414

R201 2K2R2J-2-GPR201 2K2R2J-2-GP

CLK_PWRGD14

10KR2J-3-GP

R204 22R2J-2-GPR204 22R2J-2-GP

R205

R205 R206 33R2J-2-GPR206 33R2J-2-GP

PM_STPPCI#14

PM_STPCPU#14

SMBC_ICH16,17,18

SMBD_ICH16,17,18

R200

10KR2J-3-GP

ICS9LPRS365YGLFT setting table

PIN NAME DESCRIPTION

Byte 5, bit 7 0 = PCI0 enabled (default)

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

PCI3

1 1

PCI4/27M_SEL

PCI_F5/ITP_EN

SRCT3/CR#_C

1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair

Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair

0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#

0 =SRC8/SRC8# 1 = ITP/ITP#

Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair

PIN NAME DESCRIPTION

SRCC3/CR#_D

SRCC7/CR#_E

SRCT7/CR#_F

SRCC11/CR#_G

SRCT11/CR#_H

3D3V_CLK_S0 1D05V_CLK_S0

GEN_XTAL_OUT

33R2J-2-GP

CLK_48

R203

PCLKCLK2

PCLKCLK4 PCLKCLK5

CPU_SEL2_R

3D3V_48MPWR_S0

U27

USB_48MHZ/FSLA

PCI_STOP#

CPU_STOP#

SCLK

SDATA

CK_PWRGD/PD#

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/27_SELECT

PCI_F5/ITP_EN

FSLB/TEST_MODE

REF0/FSLC/TEST_SEL

NC#55

ICS9LPRS365BKLFT-GP-U

71.09365.A03

2nd = 71.08513.003

3RD = 71.00875.C03

Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair

Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6

Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8

Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9

Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10

VDDREF

GND48

VDD48

VDDPCI

GNDREF

GNDPCI

CLK_MCH_OE#8 SATACLKREQ#14 LAN_CLKREQ#25 WLAN_CLKREQ#25

VDDSRC

VDDCPU

VDDPLL3

GND

GNDSRC

VDD96_IO

VDDSRC_IO

VDDCPU_IO

VDDPLL3_IO

27MHZ_NONSS/SRCT1/SE1

27MHZ_SS/SRCC1/SE2

GND

GNDSRC

GNDCPU

GND

CPUT0 CPUC0

CPUT1_F CPUC1_F

CPUT2_ITP/SRCT8

CPUC2_ITP/SRCC8

SRCT7/CR#_F

SRCC7/CR#_E

SRCT6 SRCC6

SRCT10

SRCC10

SRCT11/CR#_H

SRCC11/CR#_G

SRCT9 SRCC9

SRCT4 SRCC4

SRCT3/CR#_C

SRCC3/CR#_D

SRCT2/SATAT

SRCC2/SATAC

SRCT0/DOTT_96 SRCC0/DOTC_96

RN22

4 5

SRN470J-3-GP

CR#_D CR#_C CR#_H CR#_E

61 60

58 57

54 53

CR#_E

48 47

41 42

CR#_H

40 39

37 38

34 35

CR#_C

CR#_D

28 29

24 25

20 21

3D3V_S0

123

RN23

RN23 SRN10KJ-6-GP

SRN10KJ-6-GP

678

SEL2 FSC

SEL1 FSB

1 0

0101

00 0

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Clock Generator

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7

CLK_PCIE_ICH 14 CLK_PCIE_ICH# 14

CLK_PCIE_MINI1 25 CLK_PCIE_MINI1# 25

CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25

CLK_MCH_3GPLL 8 CLK_MCH_3GPLL# 8

CLK_PCIE_SATA 13 CLK_PCIE_SATA# 13

DREFSSCLK 8 DREFSSCLK# 8

DREFCLK 8 DREFCLK# 8

SEL0 FSA

CPU

100M 133M 166M

JM41_UMA

200M

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3 40Thursday, March 05, 2009

CPU

SB DMI

Wireless

LAN

NB CLK

SB SATA

FSB

X 533M 667M 800M

1067M266M

-1

Dr-Bios.com

H_A#[35..3]7

4 4

H_ADSTB#07 H_REQ#[4..0]7

3 3

H_ADSTB#17

H_A20M#13

H_FERR#13

H_IGNNE#13

H_STPCLK#13

2 2

H_FERR# H_STPCLK# H_IGNNE# H_INTR H_DPSLP# H_PWRGD H_A20M# H_SMI# H_NMI H_INIT#

1 1

H_A#[35..3]

H_DINV#[3..0]

1 OF 6

ADDR GROUP 0

CONTROL

ADDR GROUP 1

XDP/ITP SIGNALS

THERMAL

PROCHOT#

ICH

THERMTRIP#

H CLK

1 OF 6

ADS# BNR# BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0# BPM1# BPM2#

BPM3# PRDY# PREQ#

TDO TMS

TRST#

DBR#

THRMDA

THRMDC

BCLK0

BCLK1

M4 J5 L5

N5 F38 J1

B40 D8

G5 K2 H4 K4 L1

H2 F2

AY8 BA7 BA5 AY2 AV10 AV2 AV4

TCK

AW7

TDI

AU1 AW5 AV8 J7

D38 BB34 BD34

B10

A35 C35

RESERVED

CPU1A

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_INTR13 H_NMI13 H_SMI#13

1 2

C329 SC100P50V2JN-3GP

1 2

C113 SC100P50V2JN-3GP

1 2

C323 SC100P50V2JN-3GP

1 2

C327 SC100P50V2JN-3GP

1 2

C324 SC100P50V2JN-3GP

1 2

C92 SC100P50V2JN-3GP

1 2

C322 SC100P50V2JN-3GP

1 2

C317 SC100P50V2JN-3GP

1 2

C318 SC100P50V2JN-3GP

1 2

C316 SC100P50V2JN-3GP

CPU1A

A3#

A4#

A5#

A6#

AA1

A7#

AB4

A8#

A9#

AC5

A10#

AD2

A11#

AD4

A12#

AA5

A13#

AE5

A14#

AB2

A15#

AC1

A16#

ADSTB0#

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

AN1

A17#

AK4

A18#

AG1

A19#

AT4

A20#

AK2

A21#

AT2

A22#

AH2

A23#

AF4

A24#

AJ5

A25#

AH4

A26#

AM4

A27#

AP4

A28#

AR5

A29#

AJ1

A30#

AL1

A31#

AM2

A32#

AU5

A33#

AP2

A34#

AR1

A35#

AN5

ADSTB1#

A20M#

FERR#

F10

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD#V2

RSVD#Y2

AG5

RSVD#AG5

AL5

RSVD#AL5

RSVD#J9

RSVD#F4

RSVD#H8

PENRYN-SFF-GP-U1-NF

TP5 TPAD14-GPTP5 TPAD14-GP

H_ADS# 7 H_BNR# 7

H_BPRI# 7

H_DEFER# 7 H_DRDY# 7 H_DBSY# 7

H_BREQ#0 7

H_IERR#

H_INIT# 13

H_LOCK# 7

H_RS#0 H_RS#1 H_RS#2

XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_CPURST# 7

H_TRDY# 7

H_HIT# 7 H_HITM# 7

CPU_PROCHOT#_1

XDP_TMS

XDP_TDI

XDP_BPM#5

XDP_TDO

H_THERMDA 27 H_THERMDC 27

SB_20090205

XDP_DBRESET#

XDP_TCK

XDP_TRST#

All place within 2" to CPU

1D05V_S0

R157

R157 56R2J-4-GP

56R2J-4-GP

H_RS#[2..0] 7

1D05V_S0

R160

R160 56R2J-4-GP

56R2J-4-GP

PM_THRMTRIP-A# 8,13,32

PH @ page48

Layout Note: "CPU_GTLREF0"

0.5" max length.

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

R119 51R2F-2-GPR119 51R2F-2-GP

1 2

R120 51R2F-2-GPR120 51R2F-2-GP

1 2

R122 51R2F-2-GPR122 51R2F-2-GP

1 2

R121 51R2F-2-GP

1 2

R39 1KR2J-1-GP

1 2

R124 51R2F-2-GPR124 51R2F-2-GP

1 2

R123 51R2F-2-GPR123 51R2F-2-GP

1 2

Place testpoint on H_IERR# with a GND

0.1" away

H_THERMDA

H_THERMDC

Close to NB

should connect toPM_THRMTRIP# without T-ingICH9 and MCH

2KR2F-3-GP

1D05V_S0

3D3V_S0

C307

C307 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

1D05V_S0

1KR2F-3-GP

1KR2F-3-GP R133

R133

1 2 12

R134

1 2

R162 1KR2J-1-GP

1 2

R153 1KR2J-1-GP

C314

SCD1U10V2KX-4GP

C311

SC1KP50V2KX-1GP

TEST1

TEST2

TEST4

CPU_GTLREF0

CPU1B

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9

H_D#10 H_D#11 H_D#12 H_D#13 H_D#14

H_DSTBN#07 H_DSTBP#07 H_DINV#07

H_DSTBN#17 H_DSTBP#17 H_DINV#17

TP42TPAD14-GP TP42TPAD14-GP

TP2TPAD14-GP TP2TPAD14-GP TP31TPAD14-GP TP31TPAD14-GP

CPU_SEL03,8 CPU_SEL13,8 CPU_SEL23,8

Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals

Place these TP on button-side, easy to measure.

H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

TEST1 TEST2

RSVD_CPU_12

TEST4 RSVD_CPU_13

RSVD_CPU_14

H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# H_INIT# H_CPURST#

CPU1B

F40

D0#

G43

D1#

E43

D2#

J43

D3#

H40

D4#

H44

D5#

G39

D6#

E41

D7#

L41

D8#

K44

D9#

N41

D10#

T40

D11#

M40

D12#

G41

D13#

M44

D14#

L43

D15#

K40

DSTBN0#

J41

DSTBP0#

P40

DINV0#

P44

D16#

V40

D17#

V44

D18#

AB44

D19#

R41

D20#

W41

D21#

N43

D22#

U41

D23#

AA41

D24#

AB40

D25#

AD40

D26#

AC41

D27#

AA43

D28#

Y40

D29#

Y44

D30#

T44

D31#

U43

DSTBN1#

W43

DSTBP1#

R43

DINV1#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL0

C37

BSEL1

B38

BSEL2

PENRYN-SFF-GP-U1-NF

TP10 TPAD14-GPTP10 TPAD14-GP

TP46 TPAD14-GPTP46 TPAD14-GP

TP41 TPAD14-GPTP41 TPAD14-GP

TP13 TPAD14-GPTP13 TPAD14-GP

TP45 TPAD14-GPTP45 TPAD14-GP

TP14 TPAD14-GPTP14 TPAD14-GP

TP9 TPAD14-GPTP9 TPAD14-GP

2 OF 6

D32# D33# D34#

DATA GROUP 0

D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46#

DATA GROUP 2DATA GROUP 3

D47# DSTBN2# DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

DATA GROUP 1

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63# DSTBN3# DSTBP3#

DINV3#

COMP0

MISC

COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_D#[63..0]

H_D#32

AP44

H_D#33

AR43

H_D#34

AH40

H_D#35

AF40

H_D#36

AJ43

H_D#37

AG41

H_D#38

AF44

H_D#39

AH44

H_D#40

AM44

H_D#41

AN43

H_D#42

AM40

H_D#43

AK40

H_D#44

AG43

H_D#45

AP40

H_D#46

AN41

H_D#47

AL41 AK44 AL43 AJ41

H_D#48

AV38

H_D#49

AT44

H_D#50

AV40

H_D#51

AU41

H_D#52

AW41

H_D#53

AR41

H_D#54

BA37

H_D#55

BB38

H_D#56

AY36

H_D#57

AT40

H_D#58

BC35

H_D#59

BC39

H_D#60

BA41

H_D#61

BB40

H_D#62

BA35

H_D#63

AU43 AY40 AY38 BC37

COMP0

AE43

COMP1

AD44

COMP2

AE1

COMP3

AF2

G7 B8 C41 E7 D10

PSI#

BD10

Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

TP3 TPAD14-GPTP3 TPAD14-GP

Layout Note:

Title

Size Document Number Rev

Date: Sheet of

H_DINV#[3..0] 7

H_DSTBN#[3..0] 7

H_DSTBP#[3..0] 7

H_D#[63..0] 7

H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7

H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7

R139 27D4R2F-L1-GPR139 27D4R2F-L1-GP

1 2

R141 54D9R2F-L1-GPR141 54D9R2F-L1-GP

1 2

R143 27D4R2F-L1-GPR143 27D4R2F-L1-GP

1 2

R142 54D9R2F-L1-GPR142 54D9R2F-L1-GP

1 2

H_DPRSTP# 8,13,34 H_DPSLP# 13 H_DPWR# 7

H_CPUSLP# 7

C118

SC100P50V2JN-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 3)

JM41_UMA

H_PWRGD 13,32

4 40Thursday, March 05, 2009

-1

Dr-Bios.com

VCC_CORE

4 4

3 3

2 2

1 1

CPU1C

F32

VCC

G33

VCC

H32

VCC

J33

VCC

K32

VCC

L33

VCC

M32

VCC

N33

VCC

P32

VCC

R33

VCC

T32

VCC

U33

VCC

V32

VCC

W33

VCC

Y32

VCC

AA33

VCC

AB32

VCC

AC33

VCC

AD32

VCC

AE33

VCC

AF32

VCC

AG33

VCC

AH32

VCC

AJ33

VCC

AK32

VCC

AL33

VCC

AM32

VCC

AN33

VCC

AP32

VCC

AR33

VCC

AT34

VCC

AT32

VCC

AU33

VCC

AV32

VCC

AY32

VCC

BB32

VCC

BD32

VCC

B28

VCC

B30

VCC

B26

VCC

D28

VCC

D30

VCC

F30

VCC

F28

VCC

H30

VCC

H28

VCC

D26

VCC

F26

VCC

H26

VCC

K30

VCC

K28

VCC

M30

VCC

M28

VCC

K26

VCC

M26

VCC

P30

VCC

P28

VCC

T30

VCC

T28

VCC

V30

VCC

V28

VCC

P26

VCC

T26

VCC

V26

VCC

Y30

VCC

Y28

VCC

AB30

VCC

PENRYN-SFF-GP-U1-NF

3 OF 6

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

VCCA VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

J11 E11 G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

BD12

BC13

VCC_CORE

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

C35

SCD1U10V2KX-4GP

RN11

2 3 1

SRN100J-3-GP

C46

SCD1U10V2KX-4GP

H_VID[6..0] 34

TC7

ST330U2D5VDM-13GP

VCC_CORE

1D05V_S0

2ND = 80.3371V.12L

77.C3371.10L

layout note: "1D5V_VCCA_S0" as short as possible

1D5V_VCCA_S0

C339

Layout Note:

VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

L10

1 2

C347

SCD01U16V2KX-3GP

SC10U6D3V5MX-3GP

1D5V_S0

0R0805-PAD

VCORE_VCCSENSE 34

VCORE_VSSSENSE 34

CPU1D

B42

VSS

F44

VSS

D42

VSS

F42

VSS

H42

VSS

K42

VSS

M42

VSS

P42

VSS

T42

VSS

V42

VSS

Y42

VSS

AB42

VSS

AD42

VSS

AF42

VSS

AH42

VSS

AK42

VSS

AM42

VSS

AP42

VSS

AV44

VSS

AT42

VSS

AV42

VSS

AY42

VSS

BA43

VSS

BB42

VSS

C39

VSS

E39

VSS

G37

VSS

H38

VSS

J39

VSS

L39

VSS

M38

VSS

N39

VSS

R39

VSS

T38

VSS

U39

VSS

W39

VSS

Y38

VSS

AA39

VSS

AC39

VSS

AD38

VSS

AE39

VSS

AG39

VSS

AH38

VSS

AJ39

VSS

AL39

VSS

AM38

VSS

AN39

VSS

AR39

VSS

AR37

VSS

AT38

VSS

AU39

VSS

AU37

VSS

AW39

VSS

AW37

VSS

BA39

VSS

BC41

VSS

BD38

VSS

B36

VSS

H34

VSS

D36

VSS

K34

VSS

M34

VSS

M36

VSS

P34

VSS

T34

VSS

V34

VSS

T36

VSS

Y34

VSS

AB34

VSS

AD34

VSS

Y36

VSS

AD36

VSS

AF34

VSS

AH34

VSS

AH36

VSS

AK34

VSS

AM34

VSS

AM36

VSS

AP34

VSS

AR35

VSS

PENRYN-SFF-GP-U1-NF

4 OF 6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

CPU (2 of 3)

JM41_UMA

-1

5 40Thursday, March 05, 2009

-1

Dr-Bios.com

AL37 AN37 AP38 B32 C33 D32 E35 E33 F34 G35 F36 H36 J35 L35 N35 K36 R35 U35 P36 V36 W35 AA35 AC35 AB36 AE35 AG35 AJ35 AF36 AL35 AN35 AK36 AP36 B12 B14 C13 D12 D14 E13 F14 F12 G13 H14 H12 J13 K14 K12 L13 L11 M14 N13 N11 K10 P14 P12 R13 R11 T14 U13 U11 V14 V12 W13 W11 P10 V10 Y14 AA13 AA11 AB14 AB12 AC13 AC11 AD14 AB10 AE13 AE11 AF14 AF12 AG13 AG11 AH14 AJ13 AJ11 AF10 AK14 AK12 AL13 AL11 AN13 AN11 AP12 AR13 AR11 AK10 AP10 AU13 AU11 L9 L7 N9 N7 R9 R7 U9 U7 W9 W7 AA9 AA7 AC9 AC7 AE9 AE7 AG9 AG7 AJ9 AJ7 AL9 AL7 AN9 AN7 AR9 AR7 A33 A13

1D05V_S0

TP62 TPAD14-GPTP62 TPAD14-GP TP63 TPAD14-GPTP63 TPAD14-GP TP64 TPAD14-GPTP64 TPAD14-GP TP65 TPAD14-GPTP65 TPAD14-GP TP66 TPAD14-GPTP66 TPAD14-GP TP67 TPAD14-GPTP67 TPAD14-GP TP68 TPAD14-GPTP68 TPAD14-GP TP69 TPAD14-GPTP69 TPAD14-GP

VCC_CORE

1D05V_S0

CPU1F

BD28

VCC

BB26

VCC

BD26

VCC

B22

VCC

B24

VCC

D22

VCC

D24

VCC

F24

VCC

F22

VCC

H24

VCC

H22

VCC

K24

VCC

K22

VCC

M24

VCC

M22

VCC

P24

VCC

P22

VCC

T24

VCC

T22

VCC

V24

VCC

V22

VCC

Y24

VCC

Y22

VCC

AB24

VCC

AB22

VCC

AD24

VCC

AD22

VCC

AF24

VCC

AF22

VCC

AH24

VCC

AH22

VCC

AK24

VCC

AK22

VCC

AM24

VCC

AM22

VCC

AP24

VCC

AP22

VCC

AT24

VCC

AT22

VCC

AV24

VCC

AV22

VCC

AY24

VCC

AY22

VCC

BB24

VCC

BB22

VCC

BD24

VCC

BD22

VCC

B16

VCC

B18

VCC

B20

VCC

D16

VCC

D18

VCC

F18

VCC

F16

VCC

H18

VCC

H16

VCC

D20

VCC

F20

VCC

H20

VCC

K18

VCC

K16

VCC

M18

VCC

M16

VCC

K20

VCC

M20

VCC

P18

VCC

P16

VCC

T18

VCC

T16

VCC

V18

VCC

V16

VCC

P20

VCC

T20

VCC

V20

VCC

Y18

VCC

Y16

VCC

AB18

VCC

AB16

VCC

AD18

VCC

AD16

VCC

Y20

VCC

AB20

VCC

AD20

VCC

AF18

VCC

AF16

VCC

AH18

VCC

AH16

VCC

AF20

VCC

AH20

VCC

AK18

VCC

AK16

VCC

AM18

VCC

AM16

VCC

AP18

VCC

AP16

VCC

AK20

VCC

AM20

VCC

AP20

VCC

AT18

VCC

AT16

VCC

AV18

VCC

AV16

VCC

AY18

VCC

AY16

VCC

AT20

VCC

AV20

VCC

AY20

VCC

BB18

VCC

BB16

VCC

BD18

VCC

BD16

VCC

BB20

VCC

BD20

VCC

AM14

VCC

AP14

VCC

AT14

VCC

AV14

VCC

AY14

VCC

BB14

VCC

BD14

VCC

AF38

VCCP

AG37

VCCP

AJ37

VCCP

AK38

VCCP

PENRYN-SFF-GP-U1-NF

6 OF 6

VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP

CPU1E

5 OF 6

Place these inside socket cavity on L8(North side Secondary)

VCC_CORE

D D

C C

B B

A A

C298

SC10U6D3V3MX-GP

VCC_CORE

C58

SC10U6D3V3MX-GP

VCC_CORE

C76

SCD1U10V2KX-4GP

C80

SCD1U10V2KX-4GP

Place these inside socket cavity on L8(North side Secondary)

1D05V_S0

C82

SC10U6D3V3MX-GPC8SC10U6D3V3MX-GP

SC10U6D3V3MX-GPC1SC10U6D3V3MX-GP

SC10U6D3V3MX-GPC5SC10U6D3V3MX-GP

C52

C41

SC10U6D3V3MX-GP

SC10U6D3V3MX-GPC4SC10U6D3V3MX-GP

C84

C91

C102

SCD1U10V2KX-4GP

C71

C66

C59

SCD1U10V2KX-4GP

C114

C81

C63

SCD1U10V2KX-4GP

C297

SC10U6D3V3MX-GP

SC10U6D3V3MX-GPC7SC10U6D3V3MX-GP

C26

C22

SC10U6D3V3MX-GP

C105

C112

SCD1U10V2KX-4GP

C78

C73

SCD1U10V2KX-4GP

C49

C56

SCD1U10V2KX-4GP

VCC_CORE

C25

SC10U6D3V3MX-GP

C23

SC10U6D3V3MX-GP

C101

SCD1U10V2KX-4GP

C69

SCD1U10V2KX-4GP

C17

SC10U6D3V3MX-GPC6SC10U6D3V3MX-GP

C65

C83

C87

SC10U6D3V3MX-GP

SCD1U10V2KX-4GP

VCC_CORE

VCC_COREVCC_CORE

SC10U6D3V3MX-GP

C42

SC10U6D3V3MX-GP

C64

SCD1U10V2KX-4GP

C75

SCD1U10V2KX-4GP

C300

SC10U6D3V3MX-GP

C47

SC10U6D3V3MX-GP

C57

SCD1U10V2KX-4GP

C67

SCD1U10V2KX-4GP

C31

C37

C45

SC10U6D3V3MX-GP

C301

C33

SC10U6D3V3MX-GP

SC10U6D3V3MX-GPC3SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

C53

C44

C40

SCD1U10V2KX-4GP

C116

C55

C51

SCD1U10V2KX-4GP

C50

C36

C28

SC10U6D3V3MX-GP

C299

C39

SC10U6D3V3MX-GP

SC10U6D3V3MX-GPC2SC10U6D3V3MX-GP

C100

C103

C107

SCD1U10V2KX-4GP

C99

C32

C115

SCD1U10V2KX-4GP

AA25 AA23 AA21 AC25 AC23 AC21 AE25 AE23 AE21 AG25 AG23 AG21

AN25 AN23 AN21 AR25 AR23 AR21 AU25 AU23 AU21 AW25 AW23 AW21 BA25 BA23 BA21 BC25 BC23 BC21

AA19 AA17 AC19 AC17 AE19 AE17 AG19 AG17

AN19 AN17 AR19 AR17 AU19 AU17 AW19 AW17 BA19 BA17 BC19 BC17

AA15 AC15 AD12

G25 G23 G21 J25 J23 J21 L25 L23 L21 N25 N23 N21 R25 R23 R21 U25 U23

U21 W25 W23 W21

AJ25 AJ23 AJ21 AL25 AL23 AL21

C17

C19

E19

E17 G19 G17

J19

J17

L19

L17

N19

N17

R19

R17

U19

U17 W19 W17

AJ19 AJ17 AL19 AL17

C11

C15

E15 G15

H10 M12

J15

L15

N15 M10

T12

R15

U15 W15

T10

Y10

Y12

5 OF 6

NCTF_VSS#A5

VSS

NCTF_VSS#A41

VSS

NCTF_VSS#AY44

VSS

NCTF_VSS#BA1 NCTF_VSS#BD4

VSS VSS

NCTF_VSS#BD40

NCTF_VSS#D44

VSS

NCTF_VSS#E1

VSS VSS

PENRYN-SFF-GP-U1-NF

NCTF TEST PIN:

A5,A41,AY44,BA1,BD4,BD40,D44,E1

NCTF TEST PIN:

A5,A41,AY44,BA1,BD4,BD40,D44,E1

AD10

VSS

AH12

VSS

AE15

VSS

AG15

VSS

AJ15

VSS

AH10

VSS

AM12

VSS

AL15

VSS

AN15

VSS

AR15

VSS

AM10

VSS

AT12

VSS

AV12

VSS

AW13

VSS

AW11

VSS

AY12

VSS

AU15

VSS

AW15

VSS

AT10

VSS

BA13

VSS

BA11

VSS

BB12

VSS

BC11

VSS

BA15

VSS

BC15

VSS

AB8

VSS

AB6

VSS

AD8

VSS

AD6

VSS

AF8

VSS

AF6

VSS

AH8

VSS

AH6

VSS

AK8

VSS

AK6

VSS

AM8

VSS

AM6

VSS

AP8

VSS

AP6

VSS

AT8

VSS

AT6

VSS

AU9

VSS

AV6

VSS

AU7

VSS

AW9

VSS

AY6

VSS

BA9

VSS

BB6

VSS

BC9

VSS

BD6

VSS

AA3

VSS

AC3

VSS

AE3

VSS

AG3

VSS

AJ3

VSS

AL3

VSS

AN3

VSS

AR3

VSS

AU3

VSS

AW3

VSS

BA3

VSS

BC3

VSS

AW1

VSS

BB2

VSS

A39

VSS

A29

VSS

A27

VSS

A31

VSS

A25

VSS

A23

VSS

A21

VSS

A19

VSS

A17

VSS

A11

VSS

A15

VSS

NCTF_VSS#A5

A5 A41 AY44 BA1 BD4 BD40 D44 E1

NCTF_VSS#A41 NCTF_VSS#AY44 NCTF_VSS#BA1 NCTF_VSS#BD4 NCTF_VSS#BD40 NCTF_VSS#D44 NCTF_VSS#E1

1 1 1 1 1 1 1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (3 of 3)

JM41_UMA

-1

6 40Sunday, March 01, 2009

Dr-Bios.com

1 OF 10

NB1A

H_D#_0

H_D#_1

L11

H_D#_2

H_D#_3

H_D#_4

H_D#_5

K10

H_D#_6

K12

H_D#_7

H_D#_8

M10

H_D#_9

H_D#_10

N11

H_D#_11

H_D#_12

H_D#_13

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

P10

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

H_D#_27

V10

H_D#_28

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

H_SWING

H_RCOMP

J11

H_CPURST#

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA-GS-GP-NF

H_AVREF

H_D#[63..0]

SC1KP50V2KX-1GP

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_CPURST#4

H_CPUSLP#4

C177

H_D#[63..0]4

H_SWING

C385

SCD1U10V2KX-4GP

H_RCOMP

1D05V_S0

R172

R172 221R2F-2-GP

221R2F-2-GP

R173

R173 100R2F-L1-GP-U

100R2F-L1-GP-U

D D

H_SWING routing Trace width and Spacing use 10 / 20 mil

H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )

C C

H_RCOMP routing Trace width and Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

R170

Place them near to the chip ( < 0.5")

B B

1D05V_S0

R58

R58 1KR2F-3-GP

1KR2F-3-GP

1 2

R59

R59 2KR2F-3-GP

2KR2F-3-GP

1 OF 10

HOST

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN_0 H_DSTBN_1 H_DSTBN_2 H_DSTBN_3

H_DSTBP_0 H_DSTBP_1 H_DSTBP_2 H_DSTBP_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

L15 B14 C15 D12 F14 G17 B12 J15 D16 C17 D14 K16 F16 B16 C21 D18 J19 J21 B18 D22 G19 J17 L21 L19 G21 D20 K22 F18 K20 F20 F22 B20 A19

F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[35..3]

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_DEFER# 4

H_DBSY# 4

CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3

H_DPWR# 4

H_DRDY# 4 H_HIT# 4 H_HITM# 4

H_LOCK# 4 H_TRDY# 4

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_A#[35..3] 4

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (1 of 6)

Size Document Number Rev

Date: Sheet of

Cantiga (1 of 6)

JM41_UMA

7 40Thursday, March 05, 2009

-1

Dr-Bios.com

D D

SB_20090205

CPU_SEL03,4

PM_DPRSLPVR14,34

M_RCOMPP

M_RCOMPN

PLT_RST1#14,24,25,28,29

PM_EXTTS#0 PM_EXTTS#1

LCTLA_CLK LCTLB_DATA

CPU_SEL13,4 CPU_SEL23,4

CFG9

CFG16

TP52TPAD14-GP TP52TPAD14-GP

CFG20

PM_SYNC#14

H_DPRSTP#4,13,34

PM_EXTTS#017,18

PWROK14,32

150R2J-L1-GP-U

SC100P50V2JN-3GP

SRN10KJ-5-GP

RN27

RN7

SRN10KJ-5-GP

R57

1 2

0R0402-PAD

3D3V_S0

23 1

3D3V_S0

1 23

C175

R186

PM_EXTTS#0 PM_EXTTS#1

PLT_RST1#_Cantiga PM_THRMTRIP-A#_R

C C

1D5V_S3

R187

R187 80D6R2F-L-GP

80D6R2F-L-GP

3D3V_S0

R67 4K02R2F-GP

1 2

R60 2K21R2F-GP

1 2

CFG20

CFG9

R190

80D6R2F-L-GP

SB_20090205

B B

A A

PM_THRMTRIP-A#4,13,32

NB1B

J43 L43 J41

L41 AN11 AM10 AK10 AL11

F12 AN45 AP44 AT44 AN47

C27 D30

AW42

BB20 BE19 BF20 BF18

K26

G23 G25

J25

L25

L27

F24

D24 D26

J23

B26

A23

C23

B24

B22

K24

C25

L23

L33

K32

K34

J35

F6 J39 L39

AY39 BB18

K28 K36

A7 A49 A52 A54 B54

D55

G55 BE55 BH55 BK55 BK54 BL54 BL52 BL49

BL7 BL4

BL2 BK2 BK1 BH1 BE1

CANTIGA-GS-GP-NF

RSVD#J43 RSVD#L43 RSVD#J41 RSVD#L41 RSVD#AN11 RSVD#AM10 RSVD#AK10 RSVD#AL11 RSVD#F12 RSVD#AN45 RSVD#AP44 RSVD#AT44 RSVD#AN47 RSVD#C27 RSVD#D30

RSVD#J9

RSVD#AW42

RSVD#BB20 RSVD#BE19 RSVD#BF20 RSVD#BF18

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC#A7 NC#A49 NC#A52 NC#A54 NC#B54 NC#D55 NC#G55 NC#BE55 NC#BH55 NC#BK55 NC#BK54 NC#BL54 NC#BL52 NC#BL49 NC#BL7 NC#BL4 NC#BL2 NC#BK2 NC#BK1 NC#BH1 NC#BE1 NC#G1

MCH_TSATN#

2 OF 10

BB32 BA25 BA33 BA23

BA31 BC25 BC33 BB24

BC35 BE33 BE37 BC37

BK18 BK16 BE23 BC19

BJ17 BJ19 BC17 BE17

M_RCOMPP

BL25

M_RCOMPN

BK26

SM_RCOMP_VOH

BK32

SM_RCOMP_VOL

BL31

BC51

DDR2 : connect to GND

AY37

SM_REXT

BH20 BA37

B42 D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

GFXVR_EN

G39

AK52 AK54 AW40 AL53

MCH_CLVREF

AL55

for HDMI port C

F34 F32 B38 A37 C31 K42

MCH_TSATN#

D10

C29 B30

HDA_SDI

D28 A27 B28

M_CLK_DDR0 17 M_CLK_DDR1 17 M_CLK_DDR2 18 M_CLK_DDR3 18

M_CLK_DDR#0 17 M_CLK_DDR#1 17 M_CLK_DDR#2 18 M_CLK_DDR#3 18

M_CKE0 17 M_CKE1 17 M_CKE2 18 M_CKE3 18

M_CS0# 17 M_CS1# 17 M_CS2# 18 M_CS3# 18

M_ODT0 17 M_ODT1 17 M_ODT2 18 M_ODT3 18

R180 499R2F-2-GPR180 499R2F-2-GP

1 2

DDR3_DRAMRST# 17,18

CLK_MCH_3GPLL 3

CLK_MCH_3GPLL# 3

DMI_TXN0 14 DMI_TXN1 14 DMI_TXN2 14 DMI_TXN3 14

DMI_TXP0 14 DMI_TXP1 14 DMI_TXP2 14 DMI_TXP3 14

DMI_RXN0 14 DMI_RXN1 14 DMI_RXN2 14 DMI_RXN3 14

DMI_RXP0 14 DMI_RXP1 14 DMI_RXP2 14 DMI_RXP3 14

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4

GFXVR_EN 38

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DDR CLK/ CONTROL/COMPENSATION

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1

CLK

DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2

CFGRSVD

1D05V_S0

DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

DMI

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

MISC

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

R179

56R2J-4-GP

DREFCLK 3

DREFCLK# 3

DREFSSCLK 3

DREFSSCLK# 3

CL_CLK0 14

CL_DATA0 14 PWROK 14,32 CL_RST#0 14

GMCH_HDMI_CLK 20

GMCH_HDMI_DATA 20 CLK_MCH_OE# 3 MCH_ICH_SYNC# 14

HDA_BCLK_NB 13 HDA_RST#_NB 13

HDA_SDO_NB 13 HDA_SYNC_NB 13

R196 1KR2F-3-GPR196 1KR2F-3-GP

R194

R194 3K01R2F-3-GP

3K01R2F-3-GP

R193

R193 1KR2F-3-GP

1KR2F-3-GP

1 2

SM_PWROK 32

DDR_VREF_S3_1

GMCH_DDCCLK20 GMCH_DDCDATA20

GMCH_HSYNC20 GMCH_VSYNC20

GFX_VID[4..0] 38

1D05V_S0

1 2

C422

FOR Cantiga:500 ohm Teenah: 392 ohm

SCD1U10V2KX-4GP

1 2

1D5V_S3

C402

SCD01U16V2KX-3GP

C399

SCD01U16V2KX-3GP

0.75V

C241

SCD1U10V2KX-4GP

RN24

SRN2K2J-1-GP

R210

R210 1KR2F-3-GP

1KR2F-3-GP

Cantiga

R211

R211 511R2F-2-GP

511R2F-2-GP

33R2J-2-GP

R185

SM_RCOMP_VOH

C403

SC2D2U6D3V3MX-1-GP

SM_RCOMP_VOL

C398

SC2D2U6D3V3MX-1-GP

layout take note

GMCH_LCDVDD_ON19

3D3V_S0

2 3

ACZ_SDIN3 13

L_BKLTCTL19 GMCH_BL_ON28

CLK_DDC_EDID19 DAT_DDC_EDID19

TP27TPAD14-GP TP27TPAD14-GP

GMCH_TXACLK-19 GMCH_TXACLK+19

GMCH_TXAOUT0-19 GMCH_TXAOUT1-19 GMCH_TXAOUT2-19

GMCH_TXAOUT0+19 GMCH_TXAOUT1+19 GMCH_TXAOUT2+19

GMCH_BLUE20

GMCH_GREEN20

GMCH_RED20

GMCH_DDCCLK GMCH_DDCDATA

GMCH_HSYNC_C

GMCH_VSYNC_C

2 3

RN8

RN8 SRN33J-5-GP-U

SRN33J-5-GP-U

1 2

R188 976R2F-3-GPR188 976R2F-3-GP

FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm

CRT_IREF routing Trace width use 20 mil

GMCH_HDMI_DATA GMCH_HDMI_CLK

LCTLA_CLK

LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID

GMCH_LCDVDD_ON

LIBG L_LVBG

TV_DACA TV_DACB TV_DACC

GMCH_BLUE

GMCH_GREEN

GMCH_RED

CRT_IREF

3D3V_S0

2 3

D38 C37 K38

L37 J37 L35

B36

F50 H46 P44 K46 D46 B46 D44 B44

G45

F46 G41 C45

F44 G47

F40 A45

B40 A41

F42 D48

D40 C41 G43 B48

J27 E27 G27

F26

B34 D34

J29

G29

F30

E29

D36 C35

J33 D32 G31

RN26

SRN1K5J-GP

NB1C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CANTIGA-GS-GP-NF

3 OF 10

PEG_CMP

U45

PEG_COMPI

T44

PEG_COMPO

D52

PEG_RX#_0

G49

PEG_RX#_1

K54

PEG_RX#_2

H50

PEG_RX#_3

M52

PEG_RX#_4

N49

PEG_RX#_5

P54

PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

SRN150F-1-GP

1 2 3 4 5

V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54

E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52

L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54

J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52

SRN150F-1-GP

1 2 3 4 5

DIS = 66.R0036.A8L

RN18

8 7 6

DIS = 66.R0036.A8L

PEG_RXP3

GTXN0 GTXN1 GTXN2 GTXN3

GTXP0 GTXP1 GTXP2 GTXP3

RN20

TV_DACC TV_DACB

TV_DACA

LVDS

PCI-EXPRESS GRAPHICS

VGA

GMCH_BLUE GMCH_GREEN GMCH_RED

FOR Discrete change RN to 0 ohm (66.R0036.A8L)

FOR Discrete,change to 0 ohm (66.R0036.A8L)

1D05V_S0

Close to GMCH as 500 mils.

R70 49D9R2F-GPR70 49D9R2F-GP

R72

1 2

0R0402-PAD

C235 SCD1U10V2KX-5GPC235 SCD1U10V2KX-5GP

1 2

C243 SCD1U10V2KX-5GPC243 SCD1U10V2KX-5GP

1 2

C237 SCD1U10V2KX-5GPC237 SCD1U10V2KX-5GP

1 2

C248 SCD1U10V2KX-5GPC248 SCD1U10V2KX-5GP

1 2

C234 SCD1U10V2KX-5GPC234 SCD1U10V2KX-5GP

1 2

C245 SCD1U10V2KX-5GPC245 SCD1U10V2KX-5GP

1 2

C236 SCD1U10V2KX-5GPC236 SCD1U10V2KX-5GP

1 2

C247 SCD1U10V2KX-5GPC247 SCD1U10V2KX-5GP

1 2

8 7 6

Title

Size Document Number Rev

Date: Sheet

GMCH_LCDVDD_ON GMCH_BL_ON

LIBG

Cantiga (2 of 6)

HDMI_DETECT# 20

HDMI_DATA2- 20 HDMI_DATA1- 20 HDMI_DATA0- 20 HDMI_CLK- 20

HDMI_DATA2+ 20 HDMI_DATA1+ 20 HDMI_DATA0+ 20 HDMI_CLK+ 20

RN25

2 3

SRN100KJ-6-GP

1 2

R199 2K4R2F-GPR199 2K4R2F-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

JM41_UMA

8 40Thursday, March 05, 2009

-1

Dr-Bios.com

M_A_DQ[63..0]17

D D

C C

B B

M_A_DQ[63..0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

NB1D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA-GS-GP-NF

4 OF 10

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BC21 BJ21 BJ41

BH22 BK20 BL15

AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7

AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8

M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_RAS# 17

M_A_WE# 17

M_A_DQS[7..0] 17

M_A_BS#0 17 M_A_BS#1 17 M_A_BS#2 17

M_A_CAS# 17

M_A_DM[7..0] 17

M_A_DQS#[7..0] 17

M_A_A[14..0] 17

M_B_DQ[63..0]18

M_B_DQ[63..0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

NB1E

AP54 AM52 AR55 AV54 AM54 AN53

AT52

AU53

AW53

AY52 BB52 BC53 AV52

AW55

BD52 BC55

BF54 BE51 BH48 BK48 BE53 BH52 BK46

BJ47

BL45

BJ45

BL41 BH44 BH46 BK44 BK40

BJ39 BK10 BH10

BK6 BH6

BJ9

BL11

BG5

BJ5

BG3

BF4 BD4 BA3 BE5

BF2 BB4

AY4 BA1 AP2 AU1

AT2

AT4 AV4 AU3 AR3 AN1 AP4

AL3

AJ1 AK4 AM4 AH2 AK2

CANTIGA-GS-GP-NF

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

5 OF 10

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

DDR SYSTEM MEMORY B

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS# SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

BJ13 BK12 BK38

BE21 BH14 BK14

AP52 AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2

AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8

M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

M_B_RAS# 18 M_B_CAS# 18 M_B_WE# 18

M_B_BS#0 18 M_B_BS#1 18 M_B_BS#2 18

M_B_DM[7..0] 18

M_B_DQS[7..0] 18

M_B_DQS#[7..0] 18

M_B_A[14..0] 18

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Cantiga (3 of 6)

JM41_UMA

9 40Thursday, March 05, 2009

-1

Dr-Bios.com

NB1G

AW34 AW32

AW30

AW26

AM22

AM21

AM16

BB36 BE35

BK30

BG29 BE29 BC29 BA29 AY29 BK28 BH28

BD28 BB28

BG27 BE27 BC27 BA27 AY27

BF24

BB16

AG31 AE31 AD31 AC31 AA31

AH29 AG29 AE29 AD29 AC29 AA29

AH28 AG28 AE28 AA28 AH27 AG27 AE27 AD27 AC27 AA27

AH25 AD25 AC25

AH24 AG24 AE24 AD24 AC24 AA24

AH22 AG22 AE22 AD22 AC22 AA22

AH21 AD21 AC21 AA21

AG13 AE13

BH30 BF30 BD30 BB30

BL29 BJ29

BF28

BL27 BJ27

BL19

W32

Y31

W31

Y29

W29

Y27

W27

W25

AJ24

Y24

W24

AL22 AJ22

AL21 AJ21

Y21

W21

AL16

NB1G

VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC_AXG_SENSE VSS_AXG_SENSE

CANTIGA-GS-GP-NF

1D5V_S3

D D

VCC_GFXCORE

C C

B B

VCC_AXG_SENSE38

VSS_AXG_SENSE38

VCC_AXG_SENSE VSS_AXG_SENSE

U60(ISL6263ACRZ-T-GP) place near Cantiga

7 OF 10

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC GFX

VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF

VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG

VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF

VCC SM LF

T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18

VCC_GFXCORE

AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15

SM_LF1_GMCH

AU45

SM_LF2_GMCH

BF52

SM_LF3_GMCH

BB38

SM_LF4_GMCH

BA19

SM_LF5_GMCH

BE9

SM_LF6_GMCH

AU9

SM_LF7_GMCH

AL9

VCC_GFXCORE

C153

C155

SCD1U10V2KX-4GP

place near Cantiga

C182

C156

-1_20090301

VCC_GFXCORE 1D05V_S0

C199

C176

C172

SCD1U16V2KX-3GP

Place on the Edge

Place CAP where LVDS and DDR3 taps

C183

C217

C421

SCD22U10V2KX-1GP

SCD47U16V3ZY-3GP

C184

SCD1U16V2KX-3GP

C240

SC1U10V3KX-3GP

R268

1 2

0R3-0-U-GP

R269

1 2

0R3-0-U-GP

R270

1 2

0R3-0-U-GP

C178

SCD1U16V2KX-3GP

C195

SCD1U10V2KX-4GP

SC1U10V3KX-3GP

C191

SC10U6D3V5MX-3GP

FOR VCC SM

C186

C169

SCD47U6D3V2KX-GP

Coupling CAP

TC9

ST330U2D5VBM-GP

Place on the Edge

1D05V_S0

C219

C223

SCD1U16V2KX-3GP

Coupling CAP 370 mils from the Edge

C180

C171

BC1

C181

SC1U10V3KX-3GP

SC10U10V5KX-2GP

SC1U10V3KX-3GP

SC10U10V5KX-2GP

C198

SC22U6D3V5MX-2GP

SCD1U10V2KX-4GP

1D5V_S3

C194

SC22U6D3V5MX-2GP

FOR VCC CORE

C213

C239

SC22U6D3V5MX-2GP

C238

SC10U6D3V5MX-3GP

Coupling CAP

C212

SCD22U10V2KX-1GP

C211

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

C218

SCD1U10V2KX-4GP

1 2

0R0402-PAD

6 OF 10

NB1F

AT41

VCC

AR41

VCC

AN41

C207

SCD1U10V2KX-4GP

VCC_GMCH_35

R66

AH41 AD41 AC41

AM40

AH40 AG40

AD40 AC40

AN35 AM35

AH35 AD35 AC35

AM34

AH34 AG34

AD34

AC34

AM32

AH32

AD32

AM31

AH31 AM29

AM28

AM27

AM25

AM24

AJ41

Y41

W41

AT40

AL40

AJ40

AE40

AA40

Y40

AJ35

W35

AL34 AJ34

AE34

AA34

Y34

W34

AL32 AJ32

AE32

AA32

AL31 AJ31

AL29

AL28 AJ28

AL27

AL25 AJ25

N36

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

CANTIGA-GS-GP-NF

6 OF 10

VCC CORE

POWER

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

VCC NCTF

VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF

AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34

1D05V_S0

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga (4 of 6)

JM41_UMA

10 40Tuesday, March 17, 2009

-1

Title

Size Document Number Rev

Date: Sheet

Dr-Bios.com

5V_S0

SC1U16V3ZY-GP

D D

1D05V_S0

1 2

0R0603-PAD

1 2

0R0603-PAD

1D05V_S0

C C

1 2

FCM1608KF-1-GP

Imax = 300 mA

U26

VIN

GND EN3NC#4

G9091-330T11U-GP

BC3

74.09091.J3F

2ND = 74.09198.G7F

65mA

R198

SCD1U16V2KX-3GP

65mA

R202

SCD1U16V2KX-3GP

R166

R166 0R0603-PAD

0R0603-PAD

1D05V_SUS_MCH_PLL2

FCM1608KF-1-GP

1 2

68.00217.161

2ND = 68.00248.061

1 2

L11

68.00217.161

2ND = 68.00248.061

3D3V_S0_DAC

VOUT

BC2

SC1U16V3ZY-GP

M_VCCA_DPLLA

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

C410

C414

C409

C408

M_VCCA_DPLLB

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

C413

C415

SB_20090205

24mA

M_VCCA_HPLL

SC4D7U6D3V3KX-GP

C161

C154

SCD1U10V2KX-4GP

M_VCCA_MPLL

SC10U6D3V5MX-3GP

C368

C396

C396 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

139.2mA

C369

C369 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3D3V_S0_DAC

1 2

0R0603-PAD

1D05V_S0

480mA

R62

120ohm 100MHz

1D05V_S01D05V_S0

B B

A A

1 2

FCM1608CF-221T02-GP

220ohm 100MHz

68.00217.521

2ND = 68.00119.111

1D5V_S0

1 2

0R0603-PAD

HCB1608K-181T20GP

2ND = 68.00206.041

180ohm 100MHz

R64

1 2

68.00214.101

C246

1D05V_RUN_PEGPLL

C249

C249 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

1D5VRUN_TVDAC

C221

SCD022U16V2KX-3GP

1D5VRUN_QDAC

C203

C204

SCD01U16V2KX-3GP

SCD1U10V2KX-4GP

58.7mA

C220

SCD1U10V2KX-4GP

1 2

0R0603-PAD

24mA

1D05V_SUS_MCH_PLL2

C162

R65

1 2

0R0603-PAD

10mA

C209

SC1KP50V2KX-1GP

1D5V_S0

R53

1 2

0R0603-PAD

R63

SCD1U10V2KX-4GP

157.2mA

1D8V_NB_S0

60.3mA

80mA

C215

SCD01U16V2KX-3GP

1D8V_TXLVDS_S0

R74

1 2

0R0603-PAD

C188

SC10U6D3V5MX-3GP

1 2

0R0603-PAD

C208

C225

R68

SCD01U16V2KX-3GP

C216

SCD1U10V2KX-4GP

VCCA_PEG_BG

C244

C244 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C158

SC10U6D3V5MX-3GP

SC2D2U6D3V3MX-1-GP

C190

C242

50mA

3D3V_CRTDAC_S0

SCD1U10V2KX-4GP

M_VCCA_DAC_BG

13.2mA

1D05V_RUN_PEGPLL

1D05V_SM

C173

SC4D7U6D3V3KX-GP

1D05V_SM_CK

SCD1U10V2KX-4GP

C205

1D05V_RUN_PEGPLL

SCD1U10V2KX-4GP

1D8V_SUS_DLVDS

C231

SCD1U10V2KX-4GP

M_VCCA_DPLLA

M_VCCA_DPLLB

M_VCCA_HPLL

M_VCCA_MPLL

50mA

C163

SC1U10V3KX-3GP

NB1H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS

U41

VCCA_LVDS

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM

AU24

VCCA_SM

AW22

VCCA_SM

AU22

VCCA_SM

AU21

VCCA_SM

AW20

VCCA_SM

AU19

VCCA_SM

AW18

VCCA_SM

AU18

VCCA_SM

AW16

VCCA_SM

AU16

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AU15

VCCA_SM

AT15

VCCA_SM

AR15

VCCA_SM

AW14

VCCA_SM

AT24

VCCA_SM_NCTF

AR24

VCCA_SM_NCTF

AT22

VCCA_SM_NCTF

AR22

VCCA_SM_NCTF

AT21

VCCA_SM_NCTF

AR21

VCCA_SM_NCTF

AT19

VCCA_SM_NCTF

AR19

VCCA_SM_NCTF

AT18

VCCA_SM_NCTF

AR18

VCCA_SM_NCTF

AU27

VCCA_SM_CK

AU28

VCCA_SM_CK

AU29

VCCA_SM_CK

AU31

VCCA_SM_CK

AT31

VCCA_SM_CK_NCTF

AR31

VCCA_SM_CK_NCTF

AT29

VCCA_SM_CK_NCTF

AR29

VCCA_SM_CK_NCTF

AT28

VCCA_SM_CK_NCTF

AR28

VCCA_SM_CK_NCTF

AT27

VCCA_SM_CK_NCTF

AR27

VCCA_SM_CK_NCTF

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS

L45

VCCD_LVDS

CANTIGA-GS-GP-NF

8 OF 10

VTT VTT VTT VTT VTT VTT VTT VTT

VTT

VCCA_TV_DAC

VCC_HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF VCC_AXF VCC_AXF

AXF

VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK

SM CK

VCC_TX_LVDS

VCC_HV VCC_HV

VCC_PEG VCC_PEG VCC_PEG VCC_PEG

PEG

VCC_DMI VCC_DMI VCC_DMI

VTTLF VTTLF VTTLF

VTTLF

VTT VTT VTT VTT VTT

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

TVD TV/CRT

HDA

DMI

SB_20090205

3D3V_S0 3D3V_HV_S0

R192

1 2

0R0603-PAD

C395

R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1

K30

A31

N34

N32

M25 N24 M23

BK24 BL23 BJ23 BK22

T41

C33 A33

AB44 Y44 AC43 AA43

AM44 AN43 AL43

K14 Y12 P2

SCD1U10V2KX-4GP

VCC_HDA

1D5VRUN_TVDAC

1D5VRUN_QDAC

106mA

VTTLF1 VTTLF2 VTTLF3

C233

3D3VTVDAC 3D3V_S0_DAC

350mA

SC1U10V3KX-3GP

C210

1D8V_TXLVDS_S0

3D3V_HV_S0

1782mA

C197

456mA

C160

C364

SCD47U6D3V2KX-GP

C222

SCD47U6D3V2KX-GP

C201

SCD1U10V2KX-4GP

1D05V_S0

SC10U6D3V5MX-3GP

C229

SCD1U10V2KX-4GP

C390

SC4D7U6D3V3KX-GP

C164

SCD47U6D3V2KX-GP

C187

SC2D2U6D3V3MX-1-GP

SC4D7U6D3V3KX-GP

1 2

0R0603-PAD

1 2

0R0603-PAD

C391

SCD1U10V2KX-4GP

3D3V_S0

VCC_SM_CK

C451

SC10U6D3V5MX-3GP

C224

SC1KP50V2KX-1GP

C224

SC1KP50V2KX-1GP

1D05V_S0

SCD1U10V2KX-4GP

C192

Title

Size Document Number Rev

Date: Sheet of

C200

SCD47U6D3V2KX-GP

180ohm 100MHz

R189

C450

SC1U10V2ZY-GP

1 2

200mA

R184

1 2

1R2F-GP

100mA

C196

SC10U6D3V5MX-3GP

852mA

TC11

ST220U2D5VDM-13GP

1D5V_S0

I=300mA

U11

VIN

GND EN/EN#3NC#4

RT9198-18PBR-GP

74.09198.C7F

R182

1 2

0R0603-PAD

1D5V_SM_CK_R

C227

SC10U6D3V5MX-3GP

C214

SC10U6D3V5MX-3GP

Cantiga (5 of 6)

JM41_UMA

1D05V_S0

SB_20090205

SB_20090203

NB:180mA

VOUT

C449

SC1U10V2ZY-GP

1 2

74.09091.G3F

1D5V_S3

C189

SC10U6D3V5MX-3GP

1D8V_NB_S0

R69

1 2

0R0603-PAD

1D05V_S0

TC10

ST150U6D3VBM-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

11 40Sunday, March 01, 2009

1D8V_NB_S0

-1

Dr-Bios.com

9 OF 10

NB1I

BA55

VSS

AU55

VSS

AN55

VSS

AJ55

VSS

AE55

VSS

AA55

VSS

U55

VSS

N55

VSS

BD54

VSS

BG53

VSS

D D

C C

B B

A A

AJ53

VSS

AE53

VSS

AA53

VSS

U53

VSS

N53

VSS

J53

VSS

G53

VSS

E53

VSS

K52

VSS

BG51

VSS

BA51

VSS

AW51

VSS

AU51

VSS

AR51

VSS

AN51

VSS

AL51

VSS

AJ51

VSS

AG51

VSS

AE51

VSS

AC51

VSS

AA51

VSS

W51

VSS

U51

VSS

R51

VSS

N51

VSS

L51

VSS

J51

VSS

G51

VSS

C51

VSS

BK50

VSS

AM50

VSS

K50

VSS

BG49

VSS

E49

VSS

C49

VSS

BD48

VSS

BB48

VSS

AY48

VSS

AV48

VSS

AT48

VSS

AP48

VSS

AM48

VSS

AK48

VSS

AH48

VSS

AF48

VSS

AD48

VSS

AB48

VSS

Y48

VSS

V48

VSS

T48

VSS

P48

VSS

M48

VSS

K48

VSS

H48

VSS

BL47

VSS

BG47

VSS

E47

VSS

C47

VSS

A47

VSS

BD46

VSS

AY46

VSS

AM46

VSS

AK46

VSS

AH46

VSS

BG45

VSS

AE45

VSS

AC45

VSS

AA45

VSS

W45

VSS

R45

VSS

N45

VSS

E45

VSS

BD44

VSS

BB44

VSS

AV44

VSS

AK44

VSS

AH44

VSS

AF44

VSS

AD44

VSS

K44

VSS

H44

VSS

BL43

VSS

BG43

VSS

AY43

VSS

AR43

VSS

W43

VSS

R43

VSS

M43

VSS

E43

VSS

CANTIGA-GS-GP-NF

9 OF 10

VSS

C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25

NB1J

AN25

VSS

AG25

VSS

AE25

VSS

AA25

VSS

Y25

VSS

E25

VSS

A25

VSS

BD24

VSS

AN24

VSS

AL24

VSS

H24

VSS

BG23

VSS

AY23

VSS

E23

VSS

BD22

VSS

BB22

VSS

AN22

VSS

Y22

VSS

W22

VSS

H22

VSS

BL21

VSS

BG21

VSS

AY21

VSS

AN21

VSS

AG21

VSS

AE21

VSS

M21

VSS

E21

VSS

A21

VSS

BD20

VSS

H20

VSS

BG19

VSS

AY19

VSS

M19

VSS

E19

VSS

BD18

VSS

N18

VSS

H18

VSS

BL17

VSS

BG17

VSS

AY17

VSS

M17

VSS

E17

VSS

A17

VSS

BD16

VSS

AN16

VSS

AG16

VSS

AE16

VSS

Y16

VSS

W16

VSS

N16

VSS

H16

VSS

BG15

VSS

AY15

VSS

AN15

VSS

AD15

VSS

AC15

VSS

R15

VSS

M15

VSS

E15

VSS

BD14

VSS

H14

VSS

BL13

VSS

BG13

VSS

AY13

VSS

AU13

VSS

AR13

VSS

AJ13

VSS

AC13

VSS

AA13

VSS

W13

VSS

U13

VSS

M13

VSS

E13

VSS

A13

VSS

BD12

VSS

AV12

VSS

AP12

VSS

AM12

VSS

AK12

VSS

AB12

VSS

V12

VSS

P12

VSS

H12

VSS

BG11

VSS

AG11

VSS

E11

VSS

BD10

VSS

AY10

VSS

AP10

VSS

H10

VSS

BL9

VSS

BG9

VSS

BD8

VSS

BB8

VSS

AY8

VSS

AV8

VSS

AT8

VSS

AP8

VSS

CANTIGA-GS-GP-NF

VSS

VSS SCB

NCTF TEST PIN:

BL55,BL1,A55,D1,A4

10 OF 10

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

RSVD#B55

VSS_SCB

NCTF_VSS_SCB#BL55

NCTF_VSS_SCB#BL1 NCTF_VSS_SCB#A55

NCTF_VSS_SCB#D1

NCTF_VSS_SCB#A4

VSS VSS VSS VSS

AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13

N42 N40 N38 M39

AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18

B55 B2

BL55 BL1 A55 D1 A4

VSS_SCB#B2

NCTF_VSS_SCB#BL55 NCTF_VSS_SCB#BL1 NCTF_VSS_SCB#A55 NCTF_VSS_SCB#D1 NCTF_VSS_SCB#A4

1 1 1 1 1

TP50 TPAD14-GPTP50 TPAD14-GP

TP55 TPAD14-GPTP55 TPAD14-GP TP49 TPAD14-GPTP49 TPAD14-GP TP53 TPAD14-GPTP53 TPAD14-GP TP48 TPAD14-GPTP48 TPAD14-GP TP51 TPAD14-GPTP51 TPAD14-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

Cantiga (6 of 6)

JM41_UMA

12 40Sunday, March 01, 2009

-1

+ 28 hidden pages

Acer Aspire 4410 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual