Acer Aspire 1620, Aspire1622, TravelMate 2000, TravelMate2100, TravelMate5F2500 Schematics
...
A
YUHINA2&3 Block Diagram
4 4
DDR*2
3 3
Line In
Mic In
2 2
Line Out
INT.SPKR
1 1
31
31
31
11,12
A
Thermal &
2x FAN
CLK GEN.
ICS951402AGT
266/333/400MHz
G768D
AC'97
CODEC
ALC655
20
30
OP AMP
G1421
31
MODEM/BT
MDC Card
22
3
FSB
400/533/800MHz
AC-Link
USB
2.0
PIDE
HDD
ATA100
21
B
Intel CPU
Mobile P4
/Northwood
/Prescott
ATI
RC300M
ALIK I/F
66MHz
ATI
IXP150
SIDE
CD ROM
B
USB
21
X 4
4, 5
6,7,8,9,10
16,17,18,19
USB
2.0
22
PCI BUS
33MHz
LPC BUS 33MHz
NS SIO
PC87392
FDD PRN
Port
21
C
Realtek
RTL8100C
26/A/4
CARDBUS
PCI 1520
GHK
25/B/1
FIR
29
C
23
26
KBC
M38857
28
Project code: 91.40I01.001
PCB P/N : 48.40I01.0SB
REVISION : 03245-2
10/100Mb
PWR SW
TPS2224A
27 27
Mini-PCI
802.11A/B/G
21/B/2
LPC
4MB
SST49LF040
Touch
Pad
33 33
RJ45
25
32 323334
INT KB
D
CRT
TV OUT
LCD
XGA/SXGA+
14
24
CARDBUS
TWO SLOT
LPC
DEBUG
CONN.
D
13
21
PS/2
Debug
con
E
SYSTEM DC/DC
TPS51020DBT
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS5110
INPUTS OUTPUTS
DCBATOUT
APL5331
CPU DC/DC
MAX1546AETL
CM2843ACIM25
Micro-P
ATTINY12L-4SI
BAT CONN
AD CONN
INVERTER
Power
Button
42
43
43
14
35
EMI
45
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom
33
Date: Sheet of
INPUTS OUTPUTS
DCBATOUT
MAXIM CHARGER
MAX1909
DCBATOUT
PCB LAYER
L1:
Signal 1
L2:
VCC/GND
L3:
Signal 2
L4:
Signal 3
L5:
GND
L6:
Signal 4
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
1 46Tuesday, March 23, 2004
E
38
OUTPUTS
5V_S5
5V_S3
5V_S0
3D3V_S5
3D3V_S3
3D3V_S0
37
2D5V_S5
1D5V_S0
36
1D25V_S02D5V_S3
39,40
39
+VCC_CORE
1.3V 44A
+VID
1.2V 0.3A
41
OUTPUTSINPUTS
BT+
18V 4.0A
UP+5V
5V 100mA
-2
1D2V_VID
1D5V_S0
1D2V_VID 4,5,39
1D5V_S0 6,9,15,36,45
2D5V_S0
2D5V_S3
3D3V_S0
3D3V_S3
3D3V_S5
3D3V_LAN_S5
5V_USB1_S0
5V_USB3_S0
5V_CRT_S0
5VA_AUD_S0
5V_S0
5V_S5
+5V_UP_S5
5V_AUX_S5
LCDVDD
DCBATOUT
2D5V_S0 7,15,18,44,45
2D5V_S3 8,9,11,12,18,36,37,44,45
3D3V_S0 3,4,6,7,9,11,13,14,15,16,17,18,19,20,21,22,23,25,26,27,28,30,32,33,34,35,39,44,45,46
3D3V_S3 8,14,16,17,18,19,30,33,44,45
3D3V_S5 4,8,17,18,19,22,30,35,36,38,44,45
3D3V_LAN_S5 22,23,24,44
5V_USB1_S0 22
5V_USB3_S0 22
5V_CRT_S0 13
5VA_AUD_S0 30,31,46
5V_S0 6,9,13,14,15,18,20,21,22,25,27,29,30,31,32,33,34,36,39,40,42,44,45
5V_S5 15,37,38,42,44
+5V_UP_S5 14,42,45
5V_AUX_S5 16,20,35,38,39,41,42,43,45,46
LCDVDD 14
AD+
AD+ 41,43,45
DCBATOUT 14,15,18,20,35,37,38,40,41,42,44,45,46
PCI DEVICE RESOURCE ASSIGNMENT
BUS DEVICE
LAN
CardBus
MiniPCI
1
1
1
5
9
6
IDSEL PCI_REQ# PCI_GNT# INT_IRQ#
PCI_AD26
PCI_AD20
PCI_AD21
REQ#4
REQ#1
REQ#2
GNT#4
GNT#1
GNT#2
IRQD#
IRQB#/IRQA#
IRQE#
VCC_FAN
A_SKT_VCC_S0
A_SKT_VPP_S0
VCC_FAN 20
A_SKT_VCC_S0 26,27
A_SKT_VPP_S0 27
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Table of Content / HISTORY
Size Document Number Rev
A3
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
2 46Thursday, March 25, 2004
-2
R367
1 2
0R5J-1
SCD1U16V
C374
DUMMY-SC4D7U10V5ZY
1- PLACE ALL THE SERIES TERMINATION
RESISTORS AS CLOSE AS U300 AS
POSSIB LE
2- ROUTE ALL CPUCLK/#, NBCLK/# AND
ITPCLK/# AS DIFFERENT PAIR RULE
3- PUT DECOUPLING CAPS C LOSE TO U300
POWER P IN
VID_PWRGD4,35,39
C371
SCD1U16V
SCD1U16V
C354
**
CPU & MEMORY Freq. Selection
R417 1KR3
CKG_FS0
CKG_FS1
1 2
R419 1KR3
1 2
DUMMY-SCD1U16V
C356
C357
-2
R421
1 2
0R0603-PAD
12
SCD1U16V
3D3V_S03D3V_S0
R482
4K7R3
SCD1U16V
C372
12
R481
4K7R3
SCD1U16V
C373
1 2
1 2
CLK_VDD3D3V_S0
SCD1U16V
C386
BC66
1 2
SC10P50V2JN-1
BC61
CK-408_GEN_X2
SC10P50V2JN-1
EXT_CLKEN
R420
DUMMY-10KR3
C355
-2
CK-408_GEN_X1
400M Hz
533M Hz00
800M Hz 1 0
BSEL0 4,10
BSEL1 4,10
12
X4
1 2
XTAL-14D3 18M
SMBC_SB11,17
SMBD_SB11,17
PM_STPCPU#4,16,19,39
Ioh = 5 * I ref
(2.32mA )
Voh = 0.71V @ 60 ohm
CPU BSEL1 BSEL0
R351
1MR3
CLK_VDD
1 2
R423 10KR3
R331
475R3F
0
1
VDDA
VSSA
CLK_VDDA
36
37
40
CPUCLK_EXT_R
39
CPUCLK#_EXT_R
NBCLK_EXT_R
44
43
NBCLK#_EXT_R
47
NB_DDRCLK_EXT_R
AGPCLK0_EXT_R
32
31
AGPCLK1_EXT_R
16
17
20
21
22
23
11
PCI_SEL66/33#
14
15
FS4
26
28
USB_48M_2
27
CKG_FS0
2
CKG_FS1
3
CKG_FS2
4
C341
SCD1U16V
R395 DUMMY-0R3-0-U1 2
12
U40
9
VDDXTAL
1
VDDREF
13
VDDPCI
19
VDDPCI#19
29
VDD48M
30
VDDAGP
48
VDDSD
42
VDDCPU
8
GNDXTAL
5
GNDREF
18
GNDPCI
24
GNDPCI#24
25
GND48M
33
GNDAGP
46
GNDSD
41
GNDCPU
6
XIN
7
XOUT
35
SCLK
34
SDATA
10
VTTPWRGD/PD#
45
CPU_STP#
12
PCI_STOP#
38
IREF
ICS951402AGT
@
@
@
CPUT0
CPUC0
CPUT1
CPUC1
SDRAMOUT
AGPCLK0
AGPCLK1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCI66/33#SEL
FS3/PCICLK_F0
FS4/PCICLK_F1
24/48#SEL
@@
48MHz_0
48MHz_1
FS0/REF0
FS1/REF1
FS2/REF2
@These inputs have 120K internal pull-up resistor to VDD
@@ Internal pull-down res istors to GND
R323
1 2
0R5J-1
DUMMY-SC4D7U10V5ZY
C334
RN10 SRN33-2-U2
**
1
**
2 3
RN9 SRN33-2-U2
**
1
**
2 3
**
R344 33R21 2
**
R345 33R21 2
**
R346 33R2
R422 10KR3
1 2
**
R424 22R2
1 2
R425 10KR31 2
R483 10KR3
1 2
R347 33R2
1 2
12
R396
10KR3
SB
3D3V_S0
4
4
1 2
SB
USB_48M 17
TP54
TPAD30
12
R182
DUMMY-1K2R3F
12
R180
DUMMY-1KR3F
CLOSE TO NB
R319 49D9R3F
R322 49D9R3F1 2
AGPCLK_66
3D3V_S0
ALINK_CLKFS3
R418 DUMMY-33R21 2
**
R397 33R2
NB_X1_1 7
**
1 2
R320 DUMMY-0R3-0-U
**
1 2
R321 DUMMY-0R3-0-U
1 2
R317 49D9R3F
1 2
R318 49D9R3F1 2
NB_DDRCLK 7
AGPCLK0 7
AGPCLK_66 15
ALINK
66MHz
SB
1 2
EXT CLK FREQUENCY SELECT TABLE(MHZ)
FS4 FS3 FS2 FS1 FS0 CPU MEM AGP PCI
0
0
0
0
0
0
0
0
ITP_CPUCLK
ITP_CPUCLK#
CPUCLK
CPUCLK#
NBCLK 7
NBCLK# 7
ALINK_CLK 16
CODEC_14M
SB_OSC
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
ITP_CPUCLK 4,5
ITP_CPUCLK# 4,5
CPUCLK 4
CPUCLK# 4
CODEC_14M 30
SB_OSC 17
100.01 100.01
133.33 133.33
200.01 200.01
166.64 166.64
100.01
133.34
100.01133.34
133.16
166.45
133.16
166.45
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Clock Generator -ICS951402
Size Document Number Rev
A3
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
3 46Thursday, April 08, 2004
-2
GTL_A#[16:3]8
GTL_ADSTB#08
GTL_REQ#[4:0]8
TP47 TPAD30
TP46 TPAD30
TP42 TPAD30
GTL_ADSTB#18
3D3V_S0
12
3
Q31
1
MMBT3904-U1
2
R293 470R3
1D2V_VID
12
R426
470R3
D
Q39
2N7002
S
2 3
TP41 TPAD30
R368
470R3
1
1 2
THERMDP20
THERMDN20
1
GTL_A#[31:17]8
ROUTE H_THRMDA AND HW_AGND
TRACES AS DIFF PAIRS TO SIO
1
G
U22D
N5
GTL_A#16
GTL_A#15
GTL_A#14 AP#1
GTL_A#13
GTL_A#12
GTL_A#11
GTL_A#10
GTL_A#9
GTL_A#8
GTL_A#7
GTL_A#6
GTL_A#5
GTL_A#4
GTL_A#3
GTL_REQ#4
GTL_REQ#3 TESTHI8
GTL_REQ#2
GTL_REQ#1
GTL_REQ#0
GTL_A#35
GTL_A#34
GTL_A#33
GTL_A#32
GTL_A#31
GTL_A#30
GTL_A#29
GTL_A#28
GTL_A#27
GTL_A#26
GTL_A#25
GTL_A#24
GTL_A#23
GTL_A#22
GTL_A#21
GTL_A#20
GTL_A#19
GTL_A#18
GTL_A#17
12
R352
300R3
3
Q32
MMBT3904-U1
2
12
3
Q38
MMBT3904-U1
2
VID_PWRGD
SC1000P50V
R398
1KR2
VID_PWRGD_1
12
C243
THERMTRIP#17
VCC_CORE
A#16
N4
A#15
N2
A#14
M1
A#13
N1
A#12
M4
A#11
M3
A#10
L2
A#9
M6
A#8
L3
A#7
K1
A#6
L6
A#5
K4
A#4
K2
A#3
L5
ADSTB#0
H3
REQ#4
J3
REQ#3
J4
REQ#2
K5
REQ#1
J1
REQ#0
AB1
A#35
Y1
A#34
W2
A#33
V3
A#32
U4
A#31
T5
A#30
W1
A#29
R6
A#28
V2
A#27
T4
A#26
U3
A#25
P6
A#24
U1
A#23
T2
A#22
R3
A#21
P4
A#20
P3
A#19
R2
A#18
T1
A#17
R5
ADSTB#1
PZ47803-U1
CC_FERR# 16
CPUCLK3
CPUCLK#3
ITP_CPUCLK3,5
R225
ITP_CPUCLK#3,5
10KR2
CC_A20M#16
CC_IGNNE#16
CC_INTR16
CC_SMI#16
CC_STPCLK#16
R121 56R31 2
R122 56R3
1 2
R129 56R31 2
R127 56R3
1 2
R260 56R31 2
R124 56R3
1 2
-2
R242 0R0603-PAD
1 2
H_VID539
VID_PWRGD 3,35,39
ADDR GROUP 0ADDR GROUP 1
Note:Host Clock
terminations are at the
source(CK408)
CC_NMI16
1D2V_VID
CONTROL
CC_A20M#
FERR#
FERR#
CC_IGNNE#
CC_INTR
CC_NMI
CC_SMI#
CC_STPCLK#
PROCHOT_S#
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
VID_PWRGD_CPU
R280 0R0603-PAD1 2
R226 0R0603-PAD1 2
C233
DUMMY-SCD1U16V
ADS#
AP#0
AP#1
BINIT#
BNR#
BPRI#
DP#3
DP#2
DP#1
DP#0
DEFER#
DRDY#
DBSY#
TESTHI8
TESTHI9
TESTHI10
BR#0
IERR#
INIT#
LOCK#
MCERR#
RESET#
RS#2
RS#1
RS#0
RSP#
TRDY#
HIT#
HITM#
AF22
AF23
AC26
AD26
AC23
AC24
AC20
AC21
AA2
AD24
AD2
AD3
AE21
AF3
AF24
AF25
A22
G1
AC1
V5
AA3
G2
D2
L25
K26
K25
J26
E2
H2
H5
U6
W4
Y3
H6
AC3
W5
G4
V6
AB25
F4
G5
F1
AB2
J6
F3
E3
C6
B6
B2
D1
E5
B5
Y4
B3
C4
A2
C3
A7
DP#0
TESTHI9
TESTHI10
IERR
CC_INIT#
MCERR#
RSP#
U22C
BCLK0
BCLK1
ITP_CLK0
ITP_CLK1
A20M#
FERR#
IGNNE#
/INT R
LINT0
/NMI
LINT1
SMI#
STPCLK#
THERMDA
THERMDC
THERMTRIP#
PROCHOT#
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
NC
NC
NC
NC
NC
NC
NC
NC
PZ47803-U1
AP#0
BINIT#
DP#3
DP#2
DP#1
R255 56R31 2
R257 56R3
R259 56R31 2
R294 56R31 2
TP44
TPAD30
HOST CLKLEGACY CPUTHERM
GTL_ADS# 8
GTL_BNR# 8
GTL_BPRI# 8
GTL_DEFER# 8
GTL_DRDY# 8
GTL_DBSY# 8
1 2
CC_INIT# 16,32
GTL_LOCK# 8
TP31TPAD30
GTL_RS#2 8
GTL_RS#1 8
GTL_RS#0 8
GTL_TRDY# 8
GTL_HIT# 8
GTL_HITM# 8
BSEL0
FSBSE1
DPSLP#
COMP0
COMP1
GTLREF3
GTLREF2
GTLREF1
GTLREF0
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
ITPCLKOUT0
ITPCLKOUT1
TAP/ITP REF&COMP
TRST#
SKTOCC#
TP48TPAD30
TP35TPAD30
TP43TPAD30
TP4TPAD30
TP3TPAD30
TP2TPAD30
TP1TPAD30
R207
220R3F
1 2
1 2
VCC_CORE
R120
1 2
51R3F
VCC_CORE
12
AD6
AD5
BSEL1
A6
GHI#
DPSLP#
AD25
CC_CPUSLP#
AB26
SLP#
Trace 25 mils Mini.
L24
COMP0
P1
COMP1
GTLREF_3
GTLREF_1
GTLREF_0
ITPCLK0
ITPCLK1
CPU_AF26
R128
DUMMY-R2
1 2
12
DBR#
TCK
TDO
TMS
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
AA20
AB22
AE25
D4
C1
TDI
D5
F7
E6
AF26
VCC_CORE
12
R66
470R3
D
Q6
1
2N7002
G
VCC_CORE
R217
0R0603-PAD
VCC_CORE
DUMMY-470R3
R218
300R3
BSEL1 3,10
R185 61D9R3F1 2
R254 61D9R3F
1 2
R192
C160
DUMMY-SC220P50V2JN
12
S
2 3
GTL_BR0# 8
-2
GTL_CPURST# 5,8
3D3V_S0
12
R316
3
Q29
1
DUMMY-MMBT3904-U1
2
R315 DUMMY-470R3
1 2
BSEL0 3,10
PM_CPUPERF# 17
CC_CPUSLP# 16
DUMMY-0R2-0
TP10TPAD30
TP29TPAD30
Near
proce ssor
H_BPM5_PREQ# 5
H_BPM4_PRDY# 5
H_BPM3_ITP# 5
H_BPM2_ITP# 5
H_BPM1_ITP# 5
H_BPM0_ITP# 5
R117 56R3
1 2
R119 56R31 2
H_TCK 5
H_TDI 5
H_TDO 5
H_TMS 5
H_TRST# 5
12
R253
680R3
12
R146
1KR2
DPSLP#
3
Q7
1
MMBT3904-U1
2
12
R314
1KR2
3
Q28
1
DUMMY-MMBT3904-U1
2
Trace length:Less
than 1.5 inch
SB
1) PLACE THOSE CIRCUITS
< 1.5" FROM THE BALL
2) THE 220PF CAPS HAS TO
BE CLOSED TO THE BALL
AS POSSIBLE.
GTLREF_2
12
C222
SC220P50V2JN
VCC_CORE
1) ADDR. GROUP 0: H_ REQ#[4..0], H_A#[16..3], H_ADSTB#0
2) ADDR. GROUP 1: H_A#[31..17], H_ADSTB#1
3) DATA GROUP 0: H_D#[15..0], H_DBI#0, H_DSTBP#0, H_DSTBN#0
4) DATA GROUP 1: H_D#[31..16], H_DBI#1, H_DSTBP#1, H_DSTBN#1
5) DATA GROUP 2: H_D#[47..32], H_DBI#2, H_DSTBP#2, H_DSTBN#2
6) DATA GROUP 3: H_D#[63..48], H_DBI#3, H_DSTBP#3, H_DSTBN#3
CHECK LAYOUT GUIDELINE FOR ROUTING THOSE GROUPS
GTL_D#[15:0]8
GTL_D#[31:16]8
CC_PROCHOT_S# 17
VCC_CORE
Near
resis tor
3D3V_S5
PM_STPCPU# 3,16,19,39
GTL_DINV#08
GTL_DSTBN#08
GTL_DSTBP#08
GTL_DINV#18
GTL_DSTBN#18
GTL_DSTBP#18
12
R306
51R3
PROCHOT_S#
VCC_CORE
12
12
C208
SC1U10V3ZY
12
R126
150R3
DBRESET#_ITP 5
R197
51D1R3F
R198
86D6R3
GTL_D#15
GTL_D#14
GTL_D#13
GTL_D#12
GTL_D#11
GTL_D#10
GTL_D#9
GTL_D#8
GTL_D#7
GTL_D#6
GTL_D#5
GTL_D#4
GTL_D#3
GTL_D#2
GTL_D#1
GTL_D#0
GTL_D#31
GTL_D#30
GTL_D#29
GTL_D#28
GTL_D#27
GTL_D#26
GTL_D#25
GTL_D#24
GTL_D#23
GTL_D#22
GTL_D#21
GTL_D#20
GTL_D#19
GTL_D#18
GTL_D#17
GTL_D#16
U22B
D25
D#15
J21
D#14
D23
D#13
C26
D#12
H21
D#11
G22
D#10
B25
D#9
C24
D#8
C23
D#7
B24
D#6
D22
D#5
C21
D#4
A25
D#3
A23
D#2
B22
B21
E21
E22
F21
H25
K23
J24
L22
M21
H24
G26
L21
D26
F26
E25
F24
F23
G23
E24
H22
G25
K22
J23
CC_INIT#
CC_A20M#
CC_CPUSLP#
CC_INTR
CC_NMI
CC_SMI#
CC_STPCLK#
CC_IGNNE#
DATA GR P2DATA GR P3
D#1
D#0
DBI#0
DSTBN#0
DSTBP#0
D#31
D#30
D#29
D#28
D#27
D#26
D#25
D#24
D#23
D#22
D#21
D#20
D#19
D#18
D#17
D#16
DBI#1
DSTBN#1
DSTBP#1
PZ47803-U1
12
C296
DUMMY-SC180P-N4
H_BPM5_PREQ#
H_BPM4_PRDY#
H_BPM3_ITP#
H_BPM2_ITP#
H_BPM1_ITP#
H_BPM0_ITP#
H_TDI
Title
Size Document Number Rev
A3
Date: Sheet of
T23
D#47
D#46
D#45
D#44
D#43
D#42
D#41
D#40
D#39
D#38
D#37
D#36
D#35
DATA GR P0
D#34
D#33
D#32
DBI#2
DSTBN#2
DSTBP#2
D#63
D#62
D#61
D#60
D#59
D#58
D#57
D#56
D#55
D#54
D#53
D#52
D#51
D#50
DATA GR P1
D#49
D#48
DBI#3
DSTBN#3
DSTBP#3
VCC_CORE
12
GTL_D#47
T22
GTL_D#46
T25
GTL_D#45
T26
GTL_D#44
R24
GTL_D#43
R25
GTL_D#42
P24
GTL_D#41
R21
GTL_D#40
N25
GTL_D#39
N26
GTL_D#38
M26
GTL_D#37
N23
GTL_D#36
M24
GTL_D#35
P21
GTL_D#34
N22
GTL_D#33
M23
GTL_D#32
P26
R22
P23
AA24
GTL_D#63
AA22
GTL_D#62
AA25
GTL_D#61
Y21
GTL_D#60
Y24
GTL_D#59
Y23
GTL_D#58
W25
GTL_D#57
Y26
GTL_D#56
W26
GTL_D#55
V24
GTL_D#54
V22
GTL_D#53
U21
GTL_D#52
V25
GTL_D#51
U23
GTL_D#50
U24
GTL_D#49
U26
GTL_D#48
V21
W22
W23
R256 91R3
1 2
R279 200R31 2
R118 200R3
1 2
R251 200R31 2
R252 200R3
1 2
R262 200R31 2
R258 200R3
1 2
R292 200R31 2
12
C295
DUMMY-SC180P-N4
12
R264
51R3F
12
R281
51R3F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R295
51R3F
P4- SOCKET 478 1/2
YUHINA2&3
12
R263
51R3F
GTL_D#[47:32] 8
GTL_DINV#2 8
GTL_DSTBN#2 8
GTL_DSTBP#2 8
GTL_D#[63:48] 8
GTL_DINV#3 8
GTL_DSTBN#3 8
GTL_DSTBP#3 8
VCC_COREVCC_CORE
PLACE WITH IN
1.5" FROM C PU
12
12
R282
51R3F
4 46Thursday, April 08, 2004
R241
51R3F
12
R249
150R3
-2
VCC_CORE
A10
A12
VCC
VSS
A11
A13
VCC_CORE
12
Layout Note:
C3D7 should be placed within 600 mils of the
VCCA and VSSA pins
VCCA should be routed in parallel and next to
VSSA
R235 0R3-U
1 2
A14
A16
A18
A20
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
VCC
VCC
VCC
VCC
VCC
VCCA8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA3VSSA9VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A15
A17
A19
A21
A24
A26
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
VCC_CORE_L
AE16
AE18
AE20
AE6
AE8
AF11
AF13
E14
E16
E18
E20
F11
F13
F15
F17
F19
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCE8VCC
VCC
VCC
VCC
VCC
VCCF9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC19
AC2
AC5
AC7
AC9
AC22
AC25
AD1
BOOTSELECT
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
H_VID[4:0]39
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
VCC
VCC
VCC
VCC
VCC
VCC
VCCB7VCCB9VCC
VCC
VCC
VCC
VCC
VCC
VCCC8VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF1
AF6
AF8
B10
B12
B14
B16
B18
B20
AE9
AF10
AF12
AF14
AF16
AF18
AF20
B23
L3
IND-4D7UH
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
D17
D19
E10
E12
AE1
AE2
VCC
VCC
VCC
VCCD7VCCD9VCC
VCC
VID4
VSS
VSS
VSSB4VSSB8VSS
VSS
VSS
VSS
VSS
B26
C11
C13
C15
C17
C19
12
L4
IND-4D7UH
TC6 ST33U10VBM
1 2
C161 DUMMY-SC1U10V3ZY
H_VCCIOPLL
H_VCCA
H_VSSA
AE3
AE4
AE5
AD20
A5
AE23
AD22
A4
VID3
VID2
VID1
VID0
VSSA
VCCA
VCCIOPLL
VSSSENSE
VCCSENSE
VSSC2VSS
VSS
VSSC5VSSC7VSSC9VSS
VSS
VSS
VSS
C22
C25
D10
D12
D14
D16
D18
SB
12
TC27
ST33U10VBM
VCCSENSE 39
VSSSENSE 39
1D2V_VID
AF4
AB23
VCCVID
PWRGOOD
VSS
VSS
VSS
VSS
VSSD3VSSD6VSSD8VSSE1VSS
VSS
VSS
VSS
VSS
VSS
E11
E13
E15
E17
E19
E23
D20
D21
D24
E26
VSS
VSSE4VSSE7VSSE9VSS
VCC_CORE
VSS
VSS
VSS
F10
F12
F14
F16
F18
CC_CPUPWRGD 16
12
R123
300R3
U22A
PZ47803-U1
T6
VSS
K3
VSS
Y5
VSS
Y25
VSS
Y22
VSS
Y2
VSS
W6
VSS
W3
VSS
W24
VSS
W21
VSS
V4
VSS
V26
VSS
V23
VSS
V1
VSS
U5
VSS
U25
VSS
U22
VSS
U2
P25
VSS
VSSP5VSSR1VSS
R23
VSS
VSS
VSS
R4
R26
VSS
VSSF2VSS
VSS
VSSF5VSSF8VSS
VSS
VSSG3VSSG6VSSH1VSS
VSS
VSSH4VSSJ2VSS
VSS
VSSJ5VSS
VSS
VSS
VSS
VSS
VSSK6VSSL1VSS
VSS
VSSL4VSSM2VSS
VSS
VSSM5VSS
VSS
T3
J22
F22
F25
G21
G24
J25
T21
T24
L23
K21
H23
H26
L26
K24
VSSN3VSSN6VSSP2VSS
P22
N21
N24
M22
M25
10U/X5R 1206 DECOUPLING CAPS
8X IN SOCKET CAVITY
10X IN CRB
VCC_CORE
12
VCC_CORE
12
C220
SC10U6D3V5MX
C185
SC10U6D3V5MX
BOOTSELECT39
Dummy for
Pre-scott CPU
12
12
C186
SC10U6D3V5MX
C146
SC10U6D3V5MX
12
12
C173
SC10U6D3V5MX
C147
SC10U6D3V5MX
12
12
12
C207
SC10U6D3V5MX
C188
SC10U6D3V5MX
R353
DUMMY-0R2-0
12
C174
SC10U6D3V5MX
12
C221
SC10U6D3V5MX
GDN: 50 ohm platform
NC: 60 ohm platform
TP_PSC_50_60_BUFFER
R125
1 2
DUMMY-0R2-0
12
C216
SC10U6D3V5MX
12
C175
SC10U6D3V5MX
12
Dummy for
Pre-scott CPU
12
C205
SC10U6D3V5MX
12
C189
SC10U6D3V5MX
12
C187
SC10U6D3V5MX
C198
SC10U6D3V5MX
DUMMY-SC10U6D3V5MX
12
C159
12
C215
DUMMY-SC10U6D3V5MX
ITP Debug Pad
H_TDI4
H_TMS4
H_TRST#4
H_TCK4
H_TDO4
ITP_CPUCLK#3,4
ITP_CPUCLK3,4
GTL_CPURST#4,8
Should place near conn.
R250
27D4R3F
VCC_CORE
VCC_CORE
12
12
R216
R261
75R3F
39D2R3F
H_TDO
ITP_CPUCLK#
ITP_CPUCLK
GTL_CPURST#
H_BPM5_PREQ#4
12
H_BPM4_PRDY#4
H_BPM3_ITP#4
H_BPM2_ITP#4
H_BPM1_ITP#4
H_BPM0_ITP#4
DBRESET#_ITP4
DUMMY-SCD1U10V2MX-1
Title
Size Document Number Rev
Custom
Date: Sheet of
H_TCK
VCC_CORE
12
C69
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
P4- SOCKET 478 2/2
YUHINA2&3
TP11TPAD30
TP45TPAD30
TP30TPAD30
TP28TPAD30
TP40TPAD30
TP34TPAD30
TP7TPAD30
TP6TPAD30
TP50TPAD30
TP5TPAD30
TP38TPAD30
TP36TPAD30
TP32TPAD30
TP39TPAD30
TP37TPAD30
TP33TPAD30
TP8TPAD30
TP20TPAD30
TP15TPAD30
TP14TPAD30
5 46Thursday, April 08, 2004
-2
A
B
C
D
E
U27B
AK5
A_C/BE#0
A_C/BE#1
A_C/BE#2
A_C/BE#3
A_PAR
A_FRAME#
A_IRDY#
A_TRDY#
A_INTA#
A_DEVSEL#
A_STOP#
A_SBREQ#
A_SBGNT#
R240
1 2
DUMMY-8K2R3
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGP_VREF_VGA
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
AJ5
AJ4
AH4
AJ3
AJ2
AH2
AH1
AG2
AG1
AG3
AF3
AF1
AF2
AF4
AE3
AE4
AE5
AE6
AC2
AC4
AB3
AB2
AB5
AB6
AA2
AA4
AA5
AA6
AG4
AE2
AC3
AA3
AD5
AC6
AC5
AD2
W4
AD3
AD6
W5
W6
M5
AGP_CO MP
R223
1 2
169R2F
R187
1 2
71D5R2F
Y3
Y5
Y6
V5
V6
K5
K6
J5
J6
RC300M
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE0#
A_CBE1#
A_CBE2#
A_CBE3#
A_PAR
A_FRAME#
A_IRDY#
A_TRDY#
A_INTA#
A_DEVSEL#
A_STOP#
A_SBREQ#
A_SBGNT#
A_REQ0#
A_GNT0#
AGP_GNT#
AGP_REQ#
AGP_COMP
AGP8X_DET#
AGP_VREF4X
FOR AG P
1D5V_S0
D
S
2 3
A_AD[31..0]10,16
4 4
3D3V_S0
AGP_GNT#15
A_C/BE#[3..0]16
1D5V_S0
A_PAR10,16
A_FRAME#16
A_IRDY#16
A_TRDY#16
A_INTA#16,23,26,28
A_DEVSEL#16
A_STOP#16
A_SBREQ#16
A_SBGNT#16
R230 10KR3
1 2
AGP_REQ#15
3 3
2 2
SC
1 1
A
G
A_LI NK
Q17
2N7002
1
I/F
2/6
A_LINK/AGP I/F
AGP_MBDET#
AGP8X
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
AGP_DEVSEL#
AGP_FRAME#
AGP_PIPE#DBI_HI
AGP_DBI_LO
AGP_STOP#
AGP_TRDY#
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
I/F
AGP_IRDY#
AGP_PAR
AGP_RBF#
AGP_WBF#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
B
Y2
AGP_AD0
W3
AGP_AD1
W2
AGP_AD2
V3
AGP_AD3
V2
AGP_AD4
V1
AGP_AD5
U1
AGP_AD6
U3
AGP_AD7
T2
AGP_AD8
R2
AGP_AD9
P3
AGP_AD10
P2
AGP_AD11
N3
AGP_AD12
N2
AGP_AD13
M3
AGP_AD14
M2
AGP_AD15
L1
AGP_AD16
L2
AGP_AD17
K3
AGP_AD18
K2
AGP_AD19
J3
AGP_AD20
J2
AGP_AD21
J1
AGP_AD22
H3
AGP_AD23
F3
AGP_AD24
G2
AGP_AD25
F2
AGP_AD26
F1
AGP_AD27
E2
AGP_AD28
E1
AGP_AD29
D2
AGP_AD30
D1
AGP_AD31
E5
AGP_SBSTB
E6
AGP_SBSTB#
T3
AGP_ADSTB0
U2
AGP_ADSTB0#
G3
AGP_ADSTB1
H2
AGP_ADSTB1#
R3
AGP_C/BE#0
M1
AGP_C/BE#1
L3
AGP_C/BE#2
H1
AGP_C/BE#3
R5
P6
P5
T5
C1
D3
N6
T6
R6
N5
C3
AGP_SBA0
C2
AGP_SBA1
D4
AGP_SBA2
E4
AGP_SBA3
F6
AGP_SBA4
F5
AGP_SBA5
G6
AGP_SBA6
G5
AGP_SBA7
L6
AGP_ST0
M6
AGP_ST1
L5
AGP_ST2
AGP_MBDET#9,15
AGP8X_DET#
AGP_MBDET#
4K53R3
10KR3
AGP_SBSTB 15
AGP_SBSTB# 15
AGP_ADSTB0 15
AGP_ADSTB0# 15
AGP_ADSTB1 15
AGP_ADSTB1# 15
AGP_DEVSEL# 15
AGP_FRAME# 15
AGP_IRDY# 15
AGP_PAR 15
AGP_ADBIH 15
AGP_ADBIL 15
AGP_RBF# 15
AGP_STOP# 15
AGP_TRDY# 15
AGP_WBF# 15
R173
470R2
R179
R188
5V_S0
12
1
12
12
AGP_AD[0..31] 15
AGP_C/BE#[0..3] 15
AGP_SBA[0..7] 15
AGP_ST[0..2] 15
D
Q15
2N7002
G
S
2 3
R214
1 2
147R2F
C
1D5V_S0
12
12
R224
324R3F
R215
110R2F
C237
SCD01U50V3KX
SB
SC
AGP_VREF_VGA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
NB-A_LINK+AGP I/F
Size Document Number Rev
A3
D
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3 -2
6 46Thursday, April 08, 2004
E
A
B
C
D
E
2D5V_S0
12
1 2
3D3V_S0
C195
SCD1U10V2KX
DAC_RED
DAC_GREEN
DAC_BLUE
DAC_VSYNC
DAC_HSYNC
715R3F
TP18
TPAD30TP17
TPAD30
TP22
TPAD30
TP21
TPAD30
TP12
TPAD30
TPAD30
12
C227
SC1U10V3KX
NB_X1_1
NB_X2_1
U27D
G9
+3.3V
H9
+3.3V#H9
A14
AVDD
B13
AVSSN
B14
AVDDDI
C13
AVSSDI
A15
AVDDQ
B15
AVSSQ
H11
PLLVDD
G11
PLLVSS
F14
RED
F15
GREEN
E14
BLUE
D9
DACVSYNC
C8
DACHSYNC
C14
RSET
A4
XTLIN
B4
XTLOUT
A5
HCLKIN
B5
HCLKIN#
B6
SYS_FBCLKOUT
A6
SYS_FBCLKOUT#
D8
ALINK_CLK
B2
AGPCLKOUT
B3
AGPCLKIN
A3
EXT_MEM_CLK
D7
USBCLK
B7
REF27
C5
OSC
RC300M
4/6
CRT
CLK. GEN.
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LVDS
LVDDR#C12
LVSSR#C11
SVID
CPUSTOP#
SYSCLK#
LPVDD
LPVSS
LVDDR
LVSSR
COMP_B
DACSCL
DACSDA
SYSCLK
C_R
Y_G
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
E15
C15
D15
D6
C6
D5
A8
B8
LVDS_TXU0N
LVDS_TXU0P
LVDS_TXU1N
LVDS_TXU1P
LVDS_TXU2N
LVDS_TXU2P
LVDS_TXUCKN
LVDS_TXUCKP
LVDS_TXL0N
LVDS_TXL0P
LVDS_TXL1N
LVDS_TXL1P
LVDS_TXL2N
LVDS_TXL2P
LVDS_TXLCKN
LVDS_TXLCKP
TV_C/R
TV_Y/G
TV_COMP
DAC_SCL
DAC_SDAT
TP13
TPAD30
TP19
TPAD30TP16
LVDS_TXU0N 15
LVDS_TXU0P 15
LVDS_TXU1N 15
LVDS_TXU1P 15
LVDS_TXU2N 15
LVDS_TXU2P 15
LVDS_TXUCKN 15
LVDS_TXUCKP 15
LVDS_TXL0N 15
LVDS_TXL0P 15
LVDS_TXL1N 15
LVDS_TXL1P 15
LVDS_TXL2N 15
LVDS_TXL2P 15
LVDS_TXLCKN 15
LVDS_TXLCKP 15
12
C196
SC1U10V3KX
TV_C/R 15
TV_Y/G 15
TV_COMP 15
DAC_SCL 15
DAC_SDAT 15
12
C197
SC1U10V3KX
LVDDR
12
C181
SCD1U10V2KX
3D3V_S0
12
R203
4K7R3
Bead Spec:
200ohm at 100MHZ
DCR=0.4ohm
Current Rating: 200mA
L7
1 2
MLB-160808-15
C171
SC10U6D3V5MX
L8
1 2
MLB-160808-15
C172
SC10U6D3V5MX
1D8V_S0
1D8V_S0
12
C182
SCD1U10V2KX
12
C180
SCD1U10V2KX
LPVDD
12
12
PUT AVDD,AVDDI,AV DDQ,PLVDD
DECOUPLING CAPS ON THE
BOTTOM,CLOSE T O BALLS
AVDD DAC VDD (2.5V)
AVDDI DIGITAL V DD (1.8V)
4 4
3 3
2 2
AVDDQ DAC2 BANDGAP REF (1.8V)
PLLVDD PLL VDD (1.8V)
1D8V_S0
L10
1 2
MLB-160808-15
SC1U16V3KX
C179
12
3D3V_S0
12
R181
10KR3
SB
PLL_VDD
12
REF_27M
1D8V_S0
C228
SCD1U10V2KX
12
C183
SCD1U10V2KX
AGPCLK03
NB_DDRCLK3
1D8V_S0
12
NBCLK3
NBCLK#3
C203
SCD1U10V2KX
DAC_RED15
DAC_GREEN15
DAC_BLUE15
DAC_VSYNC15
DAC_HSYNC15
R184
NB_X1_13
C157
SC20P
C156
SC20P
1 1
A
X2
XTAL-14D318M
1 2
-2
12
R195
1MR3
NB_X1
NB_X2
R196
1 2
0R0603-PAD
R194
1 2
0R0603-PAD
B
NB_X1_1
NB_X2_1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
NB-VIDEO I/F &CLK_GEN
Size Document Number Rev
A3
YUHINA2&3 -2
C
D
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
7 46Thursday, April 08, 2004
E
A
B
C
D
E
PM_SUS_STAT#
3D3V_S3
12
D
S
2 3
U83D
TSLCX14-U
GTL Data
Group 0
Group 1
Group 2
Group 3
A_RST#
Q27
2N7002
PM_SUS_STAT#
VCC_CORE
12
12
DELAY 15ms
R774 15KR3
1 2
C662
SC1U16V3KX
GTL_D#[15..0] 4
GTL_DINV#0 4
GTL_DSTBN#0 4
GTL_DSTBP#0 4
GTL_D#[31..16] 4
GTL_DINV#1 4
GTL_DSTBN#1 4
GTL_DSTBP#1 4
GTL_D#[47..32] 4
GTL_DINV#2 4
GTL_DSTBN#2 4
GTL_DSTBP#2 4
GTL_D#[63..48] 4
GTL_DINV#3 4
GTL_DSTBN#3 4
GTL_DSTBP#3 4
D55
DUMMY-BAT54-U1
D56
DUMMY-BAT54-U1
R232
49D9R2F
NB_GTLREF
12
R233
100R2F
12
To CPU
12
12
2D5V_S3
12
12
C279
SC1U16V3KX
3D3V_S5
147
11 10
1D8V_S0
12
12
R328
2K2R3
R884 0R3-0-U
1 2
R327
5K6R3
VCC_CORE
1D8V_S0
U83E
TSLCX14-U
SC
R882
DUMMY-27KR3
PM_SUS_STAT_IN#
R883
DUMMY-330KR3
SC
A_RST#15,16,18,33
R248 49D9R3F
R234 24D9R3F
SC1U10V3KX
3D3V_S5
147
13 12
B
GTL_A#3
GTL_A#4
GTL_A#5
GTL_A#6
GTL_A#7
GTL_A#8
GTL_A#9
GTL_A#10
GTL_A#11
GTL_A#12
GTL_A#13
GTL_A#14
GTL_A#15
GTL_A#16
GTL_ADSTB#0
GTL_A#17
GTL_A#18
GTL_A#20
GTL_A#21
GTL_A#22
GTL_A#23
GTL_A#24
GTL_A#25
GTL_A#26
GTL_A#27
GTL_A#28
GTL_A#29
GTL_A#30
GTL_A#31
GTL_ADSTB#1
GTL_ADS#
GTL_BNR#
GTL_BPRI#
GTL_DEFER#
GTL_DRDY#
GTL_DBSY#
GTL_BR0#
GTL_LOCK#
GTL_CPURST#
GTL_RS#2
GTL_RS#1
GTL_RS#0
GTL_TRDY#
GTL_HIT#
GTL_HITM#
PM_SUS_STAT_IN#
R289
1 2
33R2
NB_PWROK
1 2
1 2
1 2
R189 412R2F
1 2
C280 SC220P
1 2
C231
TP51
TPAD30
TP52 TPAD30
U83F
TSLCX14-U
NB_PWROK
R781
10KR3
GTL_REQ#0
GTL_REQ#1
GTL_REQ#2
GTL_REQ#3
GTL_REQ#4
A_RST#_NB
12
SB
M28
P25
M25
N29
N30
M26
N28
P29
P26
R29
P30
P28
N26
N27
M29
N25
R26
L28
L29
R27
U30
T30
R28
R25
U25
T28
V29
T26
U29
U26
V26
T25
V25
U27
U28
T29
L27
K25
H26
J27
L26
G27
F25
K26
A17
G25
G26
J25
F26
J26
H25
AH5
AG5
C7
W29
V28
A9
W28
H23
J23
Y28
Y29
B17
U27A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB1#
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
LOCK#
CPURST#
RS2#
RS1#
RS0#
TRDY#
HIT#
HITM#
SUS_STAT#
SYSRST#
POWERGOOD
COMP_P
COMP_N
RSET
GTLVREF
CPVDD
CPVSS
THERMAL_D_P
THERMAL_D_N
TESTMODE
RC300M
VCC_CORE
R1
R2
12
R191
DUMMY-4K7R2
12
R190
10R2
ADDR. GROUP 1 ADDR. GROUP 0CONTROLMISC.
1/6
AGTL+ I/F
CPU
RESISTOR
R1
R2
C
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
D12#
D13#
D14#
D15#
DBI0#
DSTBN0#
DSTBP0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DBI1#
DSTBN1#
DSTBP1#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DBI2#
DSTBN2#
DSTBP2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBI3#
DSTBN3#
DSTBP3#
GTL_D#0
L30
GTL_D#1
K29
GTL_D#2
J29
GTL_D#3
H28
GTL_D#4
K28
GTL_D#5
K30
GTL_D#6
H29
GTL_D#7
J28
GTL_D#8
F28
GTL_D#9
H30
GTL_D#10
E30
GTL_D#11
D29
GTL_D#12
G28
GTL_D#13
E29
GTL_D#14
D30
GTL_D#15
F29
GTL_DINV#0
E28
GTL_DSTBN#0
G30
GTL_DSTBP#0
G29
GTL_D#16
B26
GTL_D#17
C30
GTL_D#18
A27
GTL_D#19GTL_A#19
B29
GTL_D#20
C28
GTL_D#21
C29
GTL_D#22
B28
GTL_D#23
D28
GTL_D#24
D26
GTL_D#25
B27
GTL_D#26
C26
GTL_D#27
E25
GTL_D#28
E26
GTL_D#29
A26
GTL_D#30
B25
GTL_D#31
C25
GTL_DINV#1
A28
GTL_DSTBN#1
D27
GTL_DSTBP#1
E27
GTL_D#32
F24
GTL_D#33
D24
GTL_D#34
E23
GTL_D#35
E24
GTL_D#36
F23
GTL_D#37
C24
GTL_D#38
B24
GTL_D#39
A24
GTL_D#40
F21
GTL_D#41
A23
GTL_D#42
B23
GTL_D#43
C22
GTL_D#44
B22
GTL_D#45
C21
GTL_D#46
E21
GTL_D#47
D22
GTL_DINV#2
D23
GTL_DSTBN#2
E22
GTL_DSTBP#2
F22
GTL_D#48
B21
GTL_D#49
F20
GTL_D#50
A21
GTL_D#51
C20
GTL_D#52
E20
GTL_D#53
D20
GTL_D#54
A20
GTL_D#55
D19
GTL_D#56
C18
GTL_D#57
B20
GTL_D#58
E18
GTL_D#59
B19
GTL_D#60
D18
GTL_D#61
B18
GTL_D#62
C17
GTL_D#63
A18
GTL_DINV#3
F19
GTL_DSTBN#3
E19
GTL_DSTBP#3
F18
RC300M MODE
TEST MODE
NORMAL MODE
AE12
AF12
AE11
AF11
AJ12
AH12
AH14
AH15
AH11
AJ13
AJ15
AJ16
AF18
AG20
AG21
AF22
AF19
AF20
AE22
AF23
AJ21
AJ22
AJ24
AK25
AH21
AH22
AH24
AJ25
AK26
AK27
AJ28
AH29
AH25
AJ26
AJ29
AH30
AF29
AE29
AB28
AA28
AE28
AD28
AC29
AB29
AC26
AB25
AE26
AD26
AA26
AA29
AK19
AK20
AJ10
W26
U27C
AG6
MEM_DQ0
AJ7
MEM_DQ1
AJ9
MEM_DQ2
MEM_DQ3
AJ6
MEM_DQ4
AH6
MEM_DQ5
AH8
MEM_DQ6
AH9
MEM_DQ7
AE7
MEM_DQ8
AE8
MEM_DQ9
MEM_DQ10
MEM_DQ11
AF7
MEM_DQ12
AF8
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
Y26
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
Y27
MEM_DQ63
MEM_CAP2
AF6
MEM_CAP1
DDR_COMP
DDR_VREF
RC300M
DDR_A0
3/6
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_A15
MEM_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7
DDR_RAS#
DDR_CAS#
DDR_WE#
MEM I/F
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_CK0#
DDR_CK0
DDR_CK1#
DDR_CK1
DDR_CK2#
DDR_CK2
DDR_CK3#
DDR_CK3
DDR_CK4#
DDR_CK4
DDR_CK5#
DDR_CK5
DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3
DDR_CS0#
DDR_CS1#
DDR_CS2#
DDR_CS3#
MPVDD
MPVSS
AH19
AJ17
AK17
AH16
AK16
AF17
AE18
AF16
AE17
AE16
AJ20
AG15
AF15
AE23
AH20
AE25
AH7
AF10
AJ14
AF21
AH23
AK28
AD29
AB26
AF24
AF25
AE24
AJ8
AF9
AH13
AE21
AJ23
AJ27
AC28
AA25
AH10
AK10
AJ19
AH18
AG29
AG30
AJ11
AK11
AJ18
AH17
AG28
AF28
AF13
AE13
AG14
AF14
AH26
AH27
AF26
AG27
AC18
AD18
M_A0
M_A1
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15
M_SDM_R0
M_SDM_R1
M_SDM_R2
M_SDM_R3
M_SDM_R4
M_SDM_R5
M_SDM_R6
M_SDM_R7
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7
M_A[15..0] 11
M_SDM_R[7..0] 11,12
M_RAS# 11
M_CAS# 11
M_WE# 11
M_DQS_R[7..0] 11,12
CLK_DDR0# 11
CLK_DDR0 11
CLK_DDR1# 11
CLK_DDR1 11
CLK_DDR2# 11
CLK_DDR2 11
CLK_DDR3# 11
CLK_DDR3 11
CLK_DDR4# 11
CLK_DDR4 11
CLK_DDR5# 11
CLK_DDR5 11
M_CKE0_R# 11,12
M_CKE1_R# 11,12
M_CKE2_R# 11,12
M_CKE3_R# 11,12
M_CS0_R# 11,12
M_CS1_R# 11,12
M_CS2_R# 11,12
M_CS3_R# 11,12
12
1D8V_S0DDR_VREF_S3
C285
SC1U16V3KX
M_DATA_R_[0..63]11,12
12
SCD1U16 V
C339
C685
C310 SCD47U16V
1 2
C348 SCD47U16V
1 2
1 2
R330 49D9R2F
2D5V_S3
12
SCD1U16 V
R329 DUMMY-0R3-0-U
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
1 2
SB
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
ATI RC300M (2/3)
Size Document Number Rev
Custom
D
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
8 46Thursday, April 08, 2004
E
-2
GTL Commnad
GTL_ADS# 4
GTL_BNR# 4
GTL_BPRI# 4
GTL_DBSY# 4
GTL_DEFER# 4
GTL_DRDY# 4
GTL_HIT# 4
GTL_HITM# 4
4 4
GTL_LOCK# 4
GTL_TRDY# 4
GTL_RS#2 4
GTL_RS#1 4
GTL_RS#0 4
GTL_BR0# 4
GTL_REQ#[4..0] 4
To CPU
GTL Address
Group 0
Group 1
CPU Reset
3 3
PM_SUS_STAT#_KBC15,33
2 2
1 1
PM_SUS_STAT#17
3D3V_S5
147
5 6
To CPU
GTL_A#[16..3] 4
GTL_ADSTB#0 4
GTL_A#[31..17] 4
GTL_ADSTB#1 4
To CPU
GTL_CPURST# 4,5
R326
10KR3
3D3V_S3
1
VCORE_PWROK 17,39
3D3V_S5
U83C
TSLCX14-U
9 8
A
G
147
A
CLOSE TO NB
1D5V_S0
U27E
F9
VDD_CORE#F9
F10
VDD_CORE
G12
VDD_CORE#G12
H12
VDD_CORE#H12
H13
VDD_CORE#H13
M12
VDD_CORE#M12
4 4
3 3
VCC_CORE
2 2
3D3V_S0
1 1
M13
M14
M17
M18
M19
W12
W13
W14
W17
W18
W19
M23
W30
N12
N13
N14
N17
N18
N19
P12
P13
P14
P17
P18
P19
U12
U13
U14
U17
U18
U19
V13
V14
V18
C16
D16
D17
E17
F16
F17
G17
G21
G23
G24
H16
H17
H19
H21
H24
K23
K24
P23
P24
T23
T24
U23
U24
AA1
AA7
AA8
AC7
AC8
AD1
AD7
AD8
AK3
V12
V17
V19
E16
W8
VDD_CORE#M13
VDD_CORE#M14
VDD_CORE#M17
VDD_CORE#M18
VDD_CORE#M19
VDD_CORE#N12
VDD_CORE#N13
VDD_CORE#N14
VDD_CORE#N17
VDD_CORE#N18
VDD_CORE#N19
VDD_CORE#P12
VDD_CORE#P13
VDD_CORE#P14
VDD_CORE#P17
VDD_CORE#P18
VDD_CORE#P19
VDD_CORE#U12
VDD_CORE#U13
VDD_CORE#U14
VDD_CORE#U17
VDD_CORE#U18
VDD_CORE#U19
VDD_CORE#V12
VDD_CORE#V13
VDD_CORE#V14
VDD_CORE#V17
VDD_CORE#V18
VDD_CORE#V19
VDD_CORE#W12
VDD_CORE#W13
VDD_CORE#W14
VDD_CORE#W17
VDD_CORE#W18
VDD_CORE#W19
VDD_CPU#C16
VDD_CPU#D16
VDD_CPU#D17
VDD_CPU
VDD_CPU#E17
VDD_CPU#F16
VDD_CPU#F17
VDD_CPU#G17
VDD_CPU#G21
VDD_CPU#G23
VDD_CPU#G24
VDD_CPU#H16
VDD_CPU#H17
VDD_CPU#H19
VDD_CPU#H21
VDD_CPU#H24
VDD_CPU#K23
VDD_CPU#K24
VDD_CPU#M23
VDD_CPU#P23
VDD_CPU#P24
VDD_CPU#T23
VDD_CPU#T24
VDD_CPU#U23
VDD_CPU#U24
VDD_CPU#W30
VDD_A#W8
VDD_A
VDD_A#AA7
VDD_A#AA8
VDD_A#AC7
VDD_A#AC8
VDD_A#AD1
VDD_A#AD7
VDD_A#AD8
VDD_A#AK3
A
CORE
CPU I/F
ALINK
PWR
PWR
PWR
5/6
VDD_MEM#V23
VDD_MEM#W23
VDD_MEM#W24
VDD_MEM#W25
VDD_MEM#Y25
VDD_MEM#AA23
VDD_MEM#AA27
VDD_MEM#AB30
VDD_MEM#AC10
VDD_MEM#AC12
VDD_MEM#AC13
VDD_MEM#AC15
VDD_MEM#AC17
VDD_MEM#AC19
VDD_MEM#AC21
VDD_MEM#AC23
VDD_MEM#AC24
VDD_MEM#AC25
VDD_MEM#AC27
VDD_MEM#AD10
VDD_MEM#AD12
VDD_MEM#AD13
VDD_MEM#AD15
VDD_MEM#AD17
VDD_MEM#AD19
VDD_MEM#AD21
VDD_MEM#AD23
VDD_MEM#AD24
VDD_MEM#AD25
VDD_MEM#AD27
VDD_MEM#AE9
VDD_MEM#AE10
VDD_MEM#AE14
VDD_MEM#AE19
VDD_MEM#AE20
VDD_MEM#AE30
POWER
VDD_MEM#AF27
VDD_MEM#AG8
VDD_MEM#AG9
VDD_MEM#AG11
VDD_MEM#AG12
VDD_MEM#AG17
VDD_MEM#AG18
VDD_MEM#AG23
VDD_MEM#AG24
VDD_MEM#AG26
VDD_MEM#AJ30
VDD_MEM#AK8
VDD_MEM#AK14
VDD_MEM#AK23
VDD_AGP3.3#F7
VDD_AGP3.3#G8
VDD_AGP#G4
VDD_AGP#H5
VDD_AGP#H6
VDD_AGP#H7
VDD_AGP#J4
VDD_AGP#K8
VDD_AGP#L4
VDD_AGP#M7
VDD_AGP#M8
VDD_AGP#N4
AGP PWR
VDD_AGP#P1
VDD_AGP#P7
VDD_AGP#P8
VDD_AGP#R4
VDD_AGP#T8
VDD_AGP#U4
VDD_AGP#U5
VDD_AGP#U6
VDD_AGP3.3
VDD_18#AC22
VDD_18#AC9
VDD_18#H22
MEM I/F
PWR
VDD_MEM
VDD_AGP
VDD_18
RC300M
V23
W23
W24
W25
Y25
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE9
AE10
AE14
AE15
AE19
AE20
AE30
AF27
AG8
AG9
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AJ30
AK8
AK14
AK23
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H22
H10
B
2D5V_S3
SB
1D5V_S0
VCC_GPIO VCC_GPIO
1D8V_S0
C275
1 2
SC10U6D3V5MX
SB
C271
1 2
SCD01U16V2KX
C272
1 2
SCD1U10V2KX
C80
1 2
SCD1U10V2KX
C283
1 2
DUMMY-SCD1U10V2KX
C249
DUMMY-SC22U10V-1
C239
1 2
SCD01U16V2KX
1D8V_S0
1 2
SCD1U10V2KX
1 2
SCD1U10V2KX
1 2
DUMMY-SCD1U10V2KX
1 2
SCD1U10V2KX
3D3V_S0 for UMA
1D5V_S0 for Discrete
C274
1 2
DUMMY-SCD01U16V2KX
C273
1 2
SCD01U16V2KX
C251
1 2
SCD01U16V2KX
C289
1 2
SCD01U16V2KX
C250
1 2
DUMMY-SCD01U16V2KX
C240
1 2
SCD01U16V2KX
C229
1 2
SCD01U16V2KX
C238
1 2
SCD01U16V2KX
SB
C291
C170
C489
C346
SCD1U10V2KX
SCD1U10V2KX
DUMMY-SCD1U10V2KX
SCD1U10V2KX
SCD1U10V2KX
SCD1U10V2KX
DUMMY-SCD1U10V2KX
-2
3D3V_S0
B
3
1 2
U33
BAV99-1
3
1 2
U34
BAV99-1
C260
1 2
C246
1 2
C261
1 2
C217
1 2
C236
1 2
C202
1 2
C262
1 2
R313
1 2
0R0603-PAD
R325
1 2
0R0603-PAD
3D3V_S0
AGP_MBDET#6,15
C
SB
C226
1 2
SCD01U16V2KX
C86
1 2
SCD01U16V2KX
C270
1 2
SCD01U16V2KX
C259
1 2
SCD01U16V2KX
C248
1 2
SCD1U10V2KX
C247
1 2
SCD1U10V2KX
C347
1 2
DUMMY-SC10U6D3V5MX
C269
1 2
SCD1U10V2KX
C284
1 2
SCD1U10V2KX
C268
1 2
SCD1U10V2KX
C395
1 2
SCD1U10V2KX
C300
1 2
SCD1U10V2KX
1D8V_S0
C
C288
1 2
SC10U6D3V5MX
C293
1 2
DUMMY-SCD1U10V2KX
C290
1 2
SCD1U10V2KX
SB
C302
1 2
SCD1U10V2KX
C309
1 2
SCD1U10V2KX
C287
1 2
DUMMY-SCD1U10V2KX
C338
1 2
DUMMY-SCD1U10V2KX
C292
1 2
SCD1U10V2KX
C286
1 2
SCD1U10V2KX
C304
1 2
SCD1U10V2KX
1D5V_S0
C688
SCD01U50V3KX
C690
SCD01U50V3KX
C692
SCD01U50V3KX
C689
SCD01U50V3KX
C691
SCD01U50V3KX
C693
SCD01U50V3KX
5V_S0
12
R183
DUMMY-4K7R3
D
Q16
1
DUMMY-2N7002
G
S
2 3
-2
VCC_CORE2D5V_S31D5V_S01D5V_S0
C277
1 2
DUMMY-SCD1U10V2KX
C308
1 2
DUMMY-SCD1U10V2KX
C294
1 2
SCD1U10V2KX
C324
1 2
SCD1U10V2KX
C303
1 2
SCD1U10V2KX
C337
1 2
SCD1U10V2KX
C340
1 2
SCD1U10V2KX
C333
1 2
SCD1U10V2KX
C301
1 2
SCD1U10V2KX
SB
3D3V_S0 1D5V_S0
4 5
3
2
1
FET1: N-CH G1=G2=1 CH1 ON
FET2: P-CH G1=G2=0 CH2 ON
UMA R175
DISCRETE R174
D
C230
1 2
SC10U6D3V5MX
C242
1 2
SCD1U10V2KX
C264
1 2
DUMMY-SCD1U10V2KX
C204
1 2
SCD1U10V2KX
C278
1 2
SCD1U10V2KX
C241
1 2
DUMMY-SCD1U10V2KX
C232
1 2
SCD01U16V2KX
R175 0R3-0-U1 2
R174 DUMMY-0R3-0-U
1 2
G2
S2
G1
S1
U17
DUMMY-FDS8928A
D
1 2
SCD01U16V2KX
1 2
SCD01U16V2KX
1 2
SCD01U16V2KX
1 2
SCD01U16V2KX
1 2
SCD01U16V2KX
1 2
SCD01U16V2KX
1 2
SCD01U16V2KX
D2
D2
6
D1
8
D1
7
U27F
A29
VSS
B1
VSS#B1
B16
VSS#B16
C219
C184
C276
SB
C263
C214
C252
C218
Title
Size Document Number Rev
A3
Date: Sheet of
B30
VSS#B30
C4
VSS#C4
C19
VSS#C19
C23
VSS#C23
C27
VSS#C27
D21
VSS#D21
D25
VSS#D25
E3
VSS#E3
E8
VSS#E8
E9
VSS#E9
F4
VSS#F4
F8
VSS#F8
F27
VSS#F27
G14
VSS#G14
G15
VSS#G15
G18
VSS#G18
G20
VSS#G20
H4
VSS#H4
H8
VSS#H8
H14
VSS#H14
H15
VSS#H15
H18
VSS#H18
H20
VSS#H20
H27
VSS#H27
J7
VSS#J7
J8
VSS#J8
K4
VSS#K4
K27
VSS#K27
L7
VSS#L7
L8
VSS#L8
L23
VSS#L23
L24
VSS#L24
L25
VSS#L25
M4
VSS#M4
M15
VSS#M15
M16
VSS#M16
M27
VSS#M27
N8
VSS#N8
N15
VSS#N15
N16
VSS#N16
N23
VSS#N23
N24
VSS#N24
P4
VSS#P4
P15
VSS#P15
P16
VSS#P16
P27
VSS#P27
R1
VSS#R1
R7
VSS#R7
R8
VSS#R8
R12
VSS#R12
R13
VSS#R13
R14
VSS#R14
R15
VSS#R15
R16
VSS#R16
R17
VSS#R17
R18
VSS#R18
R19
VSS#R19
R23
VSS#R23
T4
VSS#T4
T12
VSS#T12
RC300M
C158
SCD1U16V
ATI-RC300M-Power/Gnd(3/3)
YUHINA2&3
E
T13
VSS#T13
VSS#T14
VSS#T15
VSS#T16
VSS#T17
VSS#T18
VSS#T19
VSS#T27
VSS#U7
VSS#U8
VSS#U15
VSS#U16
VSS#V4
VSS#V7
VSS#V8
VSS#V15
VSS#V16
VSS#V27
VSS#W15
VSS#W16
VSS#W27
VSS#Y1
VSS#Y4
VSS#Y7
VSS#Y8
VSS#Y23
VSS#Y24
VSS#Y30
VSS#AB4
VSS#AB8
VSS#AB23
VSS#AB24
VSS#AB27
VSS#AC1
VSS#AC11
VSS#AC14
VSS#AC16
VSS#AC20
VSS#AC30
VSS#AD4
VSS#AD11
VSS#AD14
VSS#AD16
VSS#AD20
VSS#AE27
VSS#AF5
VSS#AF30
VSS#AG7
VSS#AG10
VSS#AG13
VSS#AG16
VSS#AG19
VSS#AG22
VSS#AG25
VSS#AH3
VSS#AH28
VSS#AJ1
VSS#AK2
VSS#AK4
VSS#AK7
VSS#AK13
VSS#AK22
VSS#AK29
9 46Thursday, April 08, 2004
T14
T15
T16
T17
T18
T19
T27
U7
U8
U15
U16
V4
V7
V8
V15
V16
V27
W15
W16
W27
Y1
Y4
Y7
Y8
Y23
Y24
Y30
AB4
AB8
AB23
AB24
AB27
AC1
AC11
AC14
AC16
AC20
AC30
AD4
AD11
AD14
AD16
AD20
AE27
AF5
AF30
AG7
AG10
AG13
AG16
AG19
AG22
AG25
AH3
AH28
AJ1
AK2
AK4
AK7
AK13
AK22
AK29
6/6
GND
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
E
-2
A
4 4
3 3
B
C
D
E
RC300M STRAPPING
R272
1 2
4K7R2
DUMMY-4K7R2
R271
A_AD31
2 2
A_AD30
A_AD29
A_AD28
1 1
A_AD27
A_AD26
1 2
R273
1 2
4K7R2
DUMMY-4K7R2
R274
1 2
R268
1 2
DUMMY-4K7R2
R267
1 2
4K7R2
R303 DUMMY-4K7R2
1 2
DUMMY-4K7R2
R301
1 2
A
BSEL1 3,4
A_AD[31..30] : FSB CLK SPEED
Default: 00
00: 100MHZ
01: 133MHZ
BSEL0 3,4
10: 200MHZ
11: 166MHZ
A_AD29 : STRAP CONFIGURATION
Default : 1
0: REDUCEDE SET
1: FULL SET
A_AD28 :SPREAD SPECTRUM ENABLE
Default : 0
0: DISABLE SS
1: ENABLE SS
A_AD27 :FrcShortTReset#
Default : 1
0: TESTE MODE
1: NORMAL MODE
A_AD26 :ENABLE IOQ
Default : 1
0: IOQ=1
1: IOQ=12
A_AD25,A_AD17 :CPU VOLTAGE[1..0]
A_AD25
A_AD17
A_AD24
A_AD23
A_AD22
A_AD21
B
R270
1 2
4K7R2
R305
1 2
DUMMY-4K7R2
R269 DUMMY-4K7R2
1 2
DUMMY-4K7R2
R324
1 2
DUMMY-4K7R2
R302
1 2
DUMMY-4K7R2
R304
1 2
Default : 01
00: 1.05V (MOBILE CPU)
01: 1.35V (MOBILE CPU)
10: 1.45V (DESKTOP CPU)
11: 1.75V (DESKTOP CPU)
A_AD24 :MOBILE CPU SELECT
Default : 1
0: BANIAS CPU
1: NOT BANIAS CPU
A_AD23 :CLOCK BYPASS DISABLE
Default : 1
0: TEST MODE
1: NORMAL OPERATION
A_AD22 :OSC PAD OUTPUT PCICLK
Default : 1
0: OSC PIN DRIVES PCICLK
1: OSC PIN DRIVES OSC CLK
A_AD21 :AUTO_CAL ENABLE
Default : 1
0: DISABLE AUTO_CAL
1: ENABLE AUTO_CAL
C
A_AD20
A_AD19
A_AD18
A_PAR6,16
A_PAR
D
A_AD[31..0] 6,16
A_AD20 :INTERNAL CLK GEN ENABLE
Default : 1
R276
1 2
4K7R2
DUMMY-4K7R2
R275
1 2
R343
1 2
4K7R2
DUMMY-4K7R2
R342
1 2
Title
NB_STRAPPING
Size Document Number Rev
A3
YUHINA2&3 -2
Date: Sheet of
0: EXTERNAL CLOCK GENERATOR
1: INTERNAL CLOCK GENERATOR
A_AD19 :MEMORY IO VOLTAGE SELECTION
Default : 1
0: 1.8V
1: 2.5V
A_AD18 :ENABLE PHASE CALIBRATION
Default : 0
0: DISABLE
1: ENABLE
PAR :EXTENDED DEBUG MODE
Default : 1
0: DEBUG MODE
1: NORMAL OPERATION
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
E
10 46Thursday, April 08, 2004
M_A[15..0]8
R643 10R3
M_A0 M_R_A0
1 2
R579 10R3
M_A3 M_R_A3
1 2
R640 10R3
1 2
R576 10R3
M_A7 M_R_A7
1 2
R639 10R3
M_A8 M_R_A8
1 2
R574 10R3
1 2
R581 10R3
M_A10 M_R_A10
1 2
R638 10R3
1 2
R575 10R3
M_A12 M_R_A12
1 2
R584 10R3
M_A15 M_R_A15
1 2
M_A1
R580 10R3
1 2
R642 10R3
M_A2 M_R_A2
1 2
R641 10R3
M_A4 M_R_A4
1 2
R577 10R3
M_A5 M_R_A5
1 2
DDR_VREF_S3 DDR_VREF_S3
M_R_A6M_A6
M_R_A9M_A9
M_R_A11M_A11
M_R_A1
C686
SCD1U16 V
SB SB
12
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
M_A15
12
C540
SCD1U16 V
M_A0
M_A1
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_RAS#
M_CAS#
M_WE#
3D3V_S0
DM1
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
202
GND
DDR-SODIMM-R-U2
121
/CS0
122
/CS1
96
CKE0
95
CKE1
11
DQS0
25
DQS1
47
DQS2
61
DQS3
133
DQS4
147
DQS5
169
DQS6
183
DQS7
77
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
REVERSE TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
M_SDM_R0
12
M_SDM_R1
26
M_SDM_R2
48
M_SDM_R3
62
M_SDM_R4
134
M_SDM_R5
148
M_SDM_R6
170
M_SDM_R7
184
78
35
37
160
158
89
91
SMBC_SB
195
SMBD_SB
193
DM1_SA0
194
196
198
9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
201
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7
M_CS0_R# 8,12
M_CS1_R# 8,12
M_CKE0_R# 8,12
M_CKE1_R# 8,12
CLK_DDR0 8
CLK_DDR0# 8
CLK_DDR1 8
CLK_DDR1# 8
CLK_DDR2 8
CLK_DDR2# 8
2D5V_S3
M_RAS#8
M_CAS#8
M_WE#8
M_A13
M_A14
-2
R648
0R0603-PAD
R582 10R3
R644 10R3
1 2
1 2
10R3
1 2
1 2
12
1 2
1 2
R64610R3
R583
R647
DUMMY-R3
R64510R3
M_DATA_R_[63..0]8,12
M_R_RAS#
M_R_CAS#
M_R_WE#
M_R_A012
M_R_A112
M_R_A212
M_R_A312
M_R_A412
M_R_A512
M_R_A612
M_R_A712
M_R_A812
M_R_A912
M_R_A1012
M_R_A1112
M_R_A1212
M_BS_FR#_0 12
M_BS_FR#_1 12
M_R_RAS#12
M_R_CAS#12
M_R_WE#12
C687
SCD1U16 V
12
M_R_A0
M_R_A1
M_R_A2
M_R_A3
M_R_A4
M_R_A5
M_R_A6
M_R_A7
M_R_A8
M_R_A9
M_R_A10
M_R_A11
M_R_A12
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
M_R_A15
M_R_RAS#
M_R_CAS#
M_R_WE#
3D3V_S0
12
C462
SCD1U16 V
M_BS_FR#_0
M_BS_FR#_1
DM2
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
201
GND
DDR-SODIMM-N-U1
121
/CS0
122
/CS1
96
CKE0
95
CKE1
11
DQS0
25
DQS1
47
DQS2
61
DQS3
133
DQS4
147
DQS5
169
DQS6
183
DQS7
77
DQS8
12
DM0
26
DM1
48
DM2
62
DM3
134
DM4
148
DM5
170
DM6
184
DM7
78
DM8
35
CK0
37
/CK0
160
CK1
158
/CK1
89
CK2
91
/CK2
195
SCL
193
SDA
DM2_SA0
194
SA0
196
SA1
198
SA2
9
VDD
10
VDD
21
VDD
22
VDD
33
VDD
34
VDD
36
VDD
45
VDD
46
VDD
57
VDD
58
VDD
69
VDD
70
VDD
81
VDD
82
VDD
92
VDD
93
VDD
94
VDD
113
VDD
114
VDD
131
VDD
132
VDD
143
VDD
144
VDD
155
VDD
156
VDD
157
VDD
167
VDD
168
VDD
179
VDD
180
VDD
191
VDD
192
VDD
NORMAL TYPE
3
VSS
4
VSS
15
VSS
16
VSS
27
VSS
28
VSS
38
VSS
39
VSS
40
VSS
51
VSS
52
VSS
63
VSS
64
VSS
75
VSS
76
VSS
87
VSS
88
VSS
90
VSS
103
VSS
104
VSS
125
VSS
126
VSS
137
VSS
138
VSS
149
VSS
150
VSS
159
VSS
161
VSS
162
VSS
173
VSS
174
VSS
185
VSS
186
VSS
202
GND
M_CS2_R# 8,12
M_CS3_R# 8,12
M_CKE2_R# 8,12
M_CKE3_R# 8,12
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7
M_SDM_R0
M_SDM_R1
M_SDM_R2
M_SDM_R3
M_SDM_R4
M_SDM_R5
M_SDM_R6
M_SDM_R7
CLK_DDR3 8
CLK_DDR3# 8
CLK_DDR4 8
CLK_DDR4# 8
CLK_DDR5 8
CLK_DDR5# 8
SMBC_SB 3,17
SMBD_SB 3,17
2D5V_S3
Title
DDR Socket
Size Document Number Rev
Custom
Date: Sheet of
M_DQS_R[7..0] 8,12
M_SDM_R[7..0] 8,12
-2
R737
1 2
12
0R0603-PAD
R738
DUMMY-R3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
3D3V_S03D3V_S0
11 46Thursday, April 08, 2004
-2
PLACE CAPS BETWEEN AND NEAR DDR SKTS
PLACE EACH 0.1UF CAP CLOSE TO POWER
2D5V_S3
PIN
C607
SCD1U16V
C525
SCD1U16V
C522
SCD1U16V
C524
SCD1U16V
C466
SCD1U16V
12
C515
DUMMY-SC10U6D3V5MX
C469
SCD1U16V
C465
SCD1U16V
12
C518
SC10U6D3V5MX
C467
SCD1U16V
C519
SCD1U16V
C464
SCD1U16V
C523
SCD1U16V
C608
SCD1U16V
C463
SCD1U16V
C606
SCD1U16V
C609
SCD1U16V
C470
SCD1U16V
C471
SCD1U16V
C526
SCD1U16V
C520
SCD1U16V
C560
SCD1U16V
C521
SCD1U16V
M_DATA_R_6
M_SDM_R0
M_DATA_R_4
M_DATA_R_5
M_SDM_R1
M_DATA_R_13
M_DATA_R_12
M_DATA_R_7
M_DATA_R_2
M_DQS_R0
M_DATA_R_1
M_DATA_R_0
M_DQS_R1
M_DATA_R_9
M_DATA_R_8
M_DATA_R_3
M_DATA_R_24
M_DATA_R_19
M_DATA_R_18
M_DQS_R2
M_DATA_R_27
M_DATA_R_26
M_DQS_R3
M_DATA_R_25
M_DATA_R_20
M_DATA_R_21
M_DATA_R_15
M_DATA_R_14
M_DATA_R_16
M_DATA_R_17
M_DATA_R_11
M_DATA_R_10
M_DATA_R_28
M_DATA_R_23
M_DATA_R_22
M_SDM_R2
M_DATA_R_31
M_DATA_R_30
M_SDM_R3
M_DATA_R_29
M_DATA_R_53
M_DATA_R_52
M_DATA_R_46
M_DATA_R_47
M_DATA_R_49
M_DATA_R_48
M_DATA_R_43
M_DATA_R_42
M_DATA_R_38
M_SDM_R4
M_DATA_R_37
M_DATA_R_36
M_SDM_R5
M_DATA_R_45
M_DATA_R_44
M_DATA_R_39
M_DATA_R_34
M_DQS_R4
M_DATA_R_33
M_DATA_R_32
M_DATA_R_41
M_DQS_R5
M_DATA_R_40
M_DATA_R_35
M_DATA_R_60
M_DATA_R_55
M_DATA_R_54
M_SDM_R6
M_DATA_R_63
M_DATA_R_62
M_SDM_R7
M_DATA_R_61
M_DATA_R_56
M_DATA_R_50
M_DATA_R_51
M_DQS_R6
M_DATA_R_59
M_DATA_R_58
M_DQS_R7
M_DATA_R_57
RN46
RN47
RN28
RN29
RN31
RN32
RN48
RN30
RN49
RN50
RN56
RN37
RN54
RN55
RN35
RN36
RN57
RN58
RN38
RN39
1
2
3
4 5
2
3
4 5
2
3
4 5
1
2
3
4 5
1
2
3
4 5
2
3
4 5
2
3
4 5
1
2
3
4 5
1
2
3
4 5
2
3
4 5
2
3
4 5
1
2
3
4 5
1
2
3
4 5
2
3
4 5
2
3
4 5
1
2
3
4 5
1
2
3
4 5
2
3
4 5
2
3
4 5
1
2
3
4 5
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
1D25V_S0
SRN56
SRN561
SRN561
SRN56
SRN56
SRN561
SRN561
SRN56
SRN56
SRN561
SRN561
SRN56
SRN56
SRN561
SRN561
SRN56
SRN56
SRN561
SRN561
SRN56
C619 SCD1U16V
C603 SCD1U16V
C620
DUMMY-SCD1U16V
C570 SCD1U16V
C559 SCD1U16V
C571
DUMMY-SCD1U16V
C561 SCD1U16V
C573 SCD1U16V
C574
DUMMY-SCD1U16V
C621 SCD1U16V
C604 SCD1U16V
C572
DUMMY-SCD1U16V
C623 SCD1U16V
C624 SCD1U16V
C605
DUMMY-SCD1U16V
C562 SCD1U16V
C586 SCD1U16V
C636
DUMMY-SCD1U16V
C633 SCD1U16V
C634 SCD1U16V
C635
DUMMY-SCD1U16V
C583 SCD1U16V
C585 SCD1U16V
C584
DUMMY-SCD1U16V
C637 SCD1U16V
C638 SCD1U16V
C639
DUMMY-SCD1U16V
C589 SCD1U16V
C587 SCD1U16V
C588
DUMMY-SCD1U16V
2D5V_S3
PARALLEL TERMINATION
PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO DM2
NO EQUAL LENGTH LIMITATION
M_DATA_R_[63..0] 8,11
M_DQS_R[7..0] 8,11
M_SDM_R[7..0] 8,11
CPC Address
M_R_WE#11
M_CS2_R#8,11
M_BS_FR#_011
M_CS0_R#8,11
M_R_A011
M_CS1_R#8,11
M_R_A211
M_R_A0
Address / Command
M_R_A411
M_R_A611
M_R_A811
M_CS3_R#8,11
M_R_CAS#11
M_BS_FR#_111
M_R_RAS#11
M_R_A6
M_R_A8
M_R_A311
M_R_A1211
M_R_A1111
M_R_A1011
M_R_A111
M_R_A511
M_R_A3
M_R_A12
M_R_A11
M_R_A10
Control
M_CKE2_R#8,11
M_CKE3_R#8,11
M_CKE1_R#8,11
M_CKE0_R#8,11
M_R_A711
M_R_A911
M_R_A7
M_R_A9
Title
DDR Serial/Terminator Resistor
Size Document Number Rev
A3
Date: Sheet of
1D25V_S0
RN34
1
8
2
7
3
6
4 5
SRN33
RN52
1
8
2
7
3
6
4 5
SRN33
1D25V_S0
RN51
1
2
3
4 5
SRN33
RN53
1
2
3
4 5
SRN33
1 2
1 2
RN33
1
2
3
4 5
SRN33
1 2
1 2
1 2
1 2
1 2
C627 SCD1U16V
8
7
6
C626 SCD1U16V
C630 SCD1U16V
8
7
6
C631 SCD1U16V
R68433R2
R68233R2 1 2
R73633R2
8
7
6
1D25V_S0
R73533R2
R68033R2
R57333R2
R63733R2
R68333R2
R68133R2 1 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
C581 SCD1U16V
C582 SCD1U16V
C629 SCD1U16V
C632 SCD1U16V
C580 SCD1U16V
C576 SCD1U16V
C578 SCD1U16V
C579 SCD1U16V
C625 SCD1U16V
C628 SCD1U16V
C622 SCD1U16V
C468 SCD1U16V
C577 SCD1U16V
C575 SCD1U16V
12 46Thursday, April 08, 2004
2D5V_S3
2D5V_S3
-2
CRT I/F & CONNECTOR
AGP_CRT_R15
AGP_CRT_G15
AGP_CRT_B15
12
R10
75R3F
Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
* 37.4_1% resistors must be placed at the same place as the RGB 75 Ohm
pull-down resistors.
Pi-filter & 75 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
Hsync & Vsync level shift
AGP_JVGA_HS15
AGP_JVGA_VS15
F1
1 2
EMC3
12
12
R12
2K2R3
SC100P50V 2JN
FUSE-1A6V
12
EMC7
Ferrite bead impedance: 75ohm@100MHz
EML2
1 2
MLB-160808-10
EML3
1 2
MLB-160808-10
EML4
12
12
R13
R11
75R3F
75R3F
EMC4
DUMMY-SC3P50V3KN
EMC5
DUMMY-SC3P50V3KN
1 2
MLB-160808-10
EMC9
DUMMY-SC3P50V3KN
EMC1
DY-SC18P50V3JN-L1
12
DUMMY-SC3P50V3KN
EMC6
DUMMY-SC3P50V3KN
CRT_R
CRT_G
CRT_B
EMC2
CRT_R
DAT_DDC1_5
CRT_G
JVGA_HS
CRT_B
JVGA_VS
CLK_DDC1_5
2 1
12
12
EMC10
D1
CH751H-40
R14
2K2R3
SC100P50V2JN
SB check value??
5V_CRT_S05V_S0
C20
SCD01U50V3KX
CRT1
16
6
11
1
7
12
2
8
13
3
9
14
4
10
15
SC1000P50V3JN
5
17
FOX-CONN15-1-U
12
EMC8
SC1000P50V 3JN
RDDP 1.0
DDC_CLK & DATA level shift
EMR1
14
4
5 6
7
5V_S0
14
2 3
U2B
7
TSAHCT125
C21
SCD1U16V
1
U2A
TSAHCT125
SB
3
D47
BAV99-2
5V_S0
2
1
1 2
33R3
EMR2
1 2
33R3
HSYNC_5
VSYNC_5
2
3
D48
1
BAV99-2
2
3
D49
1
BAV99-2
CRT_GCRT_R
CRT_B
JVGA_HS
JVGA_VS
3D3V_S03D3V_S0
12
R152
10KR3
AGP_DAT_DDC1_515
AGP_CLK_DDC1_515
3D3V_S0
12
12
R172
10KR3
G
2 3
S
Q12
2N7002
Title
Size Document Number Rev
A3
Date: Sheet of
SB
R165
2K2R3
1
G
1
2 3
S
Q14
2N7002
D
DAT_DDC1_5
CLK_DDC1_5
D
CRT Connector
YUHINA2&3
5V @ ext. CRT side
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
13 46Thursday, April 08, 2004
-2
STBY_LED_EN33
BLINKING_LED17
MAIL_LED_EN34
BACKLT_OFF#17
80211_LED#
3D3V_S3
12
SB
1
2
4
5
3D3V_S0
147
R62
33R2
3D3V_S3
147
3D3V_S3
147
U56B
TSLCX08-U
6
COVERUP33
80211_LED
U77A
3
TSLCX08-U
U77B
6
TSLCX08-U
LCD_ON
3D3V_S0
10
R47 0R0603-PAD
1 2
U86
5
VCC
4
Y
DUMMY-NC7SZ32-U
1
G
3D3V_S0
147
9
A
B
GND
R792
10KR2
D
1
G
S
2 3
Q76
2N7002
BL_ON15
4
5
Q2
D
1 2
1
G
S
2 3
2N7002
LCD / INVERTER INTERFACE
3D3V_S3
12
R768
10KR3
FPBACK
SB
12
R46
DUMMY-100KR3
STBY_LED# 33
MAIL_LED# 33
802.11_ACT 25
CHG_LED#42
MEDIA_LED#21
3D3V_S0
147
U38A
TSLCX14-U
12
NUM_LED#33
CAP_LED#33
1 2
FPBACK
R61 10KR3
BRIGHTNESS33
WLANONLED#_KBC 34
MEDIA_LED#
FPBACK_2
BC26
SCD1U16V
SC100P50V2JN
12
BC21
SC100P50V2JN
12
BC22
SC100P50V2JN
+5V_UP_S5
BC18
SCD1U16V
12
BC23
12
BC25
SC100P50V2JN
D
Q68
2N7002
S
2 3
3D3V_S0
12
R733
10KR3
D
Q66
1
2N7002
G
S
2 3
U56C
8
TSLCX08-U
-2
1
2
3
12
BC24
SC100P50V2JN
INV1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
ETY-CONN30D-U
20.F0322.030
DCBATOUT
31
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
32
SCD1U50V5KX
(LED USE)
BC20
BC3
SCD1U16V
DCBATOUT TRA CE
add thic k
12
BC19
SC10U35V0ZY-U
5V_S0
BC14
SC1U10V3ZY
3D3V_S3
1 2
R2 0R0603-PAD
3D3V_S0
BC15
SCD1U16V
BC4
DUMMY-SC100P50V2JN
TOP VIEW
2 40
INV CONN
1
-2
80211_LED#
PWR_LED#
STBY_LED#
12
12
BC1
SC100P50V2JN
12
BC2
SC100P50V2JN
39
PWR_LED# 33
3D3V_S0
U3
SI3445DV-U
4
S
12
-2
R64
G
100KR3
12
C58
DUMMY-C3
3
LCDVDD_ENR#
C52
SC1U10V3ZY
R79
1 2
2KR3
C53
DUMMY-SC1U10V3ZY
3D3V_S0
U38B
147
R1000
4K7R2
12
3 4
TSLCX14-U
LCDVDD_ON15
-2
LCDVDD
6
D
5
2
1
R30
1 2
1KR3
C51
SC1U10V3ZY
2N7002
Q4
D
LCDVDD_ENR#
1
G
S
2 3
PANEL_ID034
PANEL_ID134
PANEL_ID234
SB
PCIRST1#18,23,26,27,28
D_TX134
D_RTS1#34
D_RX134
D_DTR1#34
D_CTS1#34
DUMMY-SC4700P50V2KX
BC32
12
12
BC31
DUMMY-SC4700P50V2KX
12
BC30
DUMMY-SC4700P50V2KX
12
BC29
DUMMY-SC4700P50V2KX
DUMMY-SC4700P50V2KX
LCD CONN
12
BC28
12
BC27
DUMMY-SC4700P50V2KX
LCD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
SYN-CONN40A-U
20.F0312.040
42
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
41
AGP_TXBCLK+
AGP_TXBCLKAGP_TXBOUT2+
AGP_TXBOUT2AGP_TXBOUT1+
AGP_TXBOUT1AGP_TXBOUT0+
AGP_TXBOUT0AGP_TXACLK+
AGP_TXACLKAGP_TXAOUT2+
AGP_TXAOUT2AGP_TXAOUT1+
AGP_TXAOUT1AGP_TXAOUT0+
AGP_TXAOUT0-
LCDVDD
12
C50
DUMMY-SC10U6D3V5MX
AGP_TXBCLK+ 15PANEL_ID334
AGP_TXBCLK- 15
AGP_TXBOUT2+ 15
AGP_TXBOUT2- 15
AGP_TXBOUT1+ 15
AGP_TXBOUT1- 15
AGP_TXBOUT0+ 15
AGP_TXBOUT0- 15
AGP_TXACLK+ 15
AGP_TXACLK- 15
AGP_TXAOUT2+ 15
AGP_TXAOUT2- 15
AGP_TXAOUT1+ 15
AGP_TXAOUT1- 15
AGP_TXAOUT0+ 15
AGP_TXAOUT0- 15
TOP VIEW
2 40
LCD CONN
1
C30
C31
DUMMY-SCD1U16V
SCD1U16V
3D3V_S0
C32
SCD1U16V
Title
LCD/Inverter Connector
Size Document Number Rev
Custom
Date: Sheet of
39
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
YUHINA2&3
14 46Thursday, April 08, 2004
-2
Loading...